TOSHIBA TMP86C420FG

8 Bit Microcontroller
TLCS-870/C Series
TMP86C420FG
TMP86C420FG
The information contained herein is subject to change without notice. 021023 _ D
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless,
semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and
vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards
of safety in making a safe design for the entire system, and to avoid situations in which a malfunction
or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating
ranges as set forth in the most recent TOSHIBA products specifications.
Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for
Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A
The Toshiba products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic
appliances, etc.).
These Toshiba products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of
human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, medical instruments, all types of safety devices, etc. Unintended
Usage of Toshiba products listed in this document shall be made at the customer's own risk. 021023_B
The products described in this document shall not be used or embedded to any downstream products
of which manufacture, use and/or sale are prohibited under any applicable laws and regulations.
060106_Q
The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of TOSHIBA or others. 021023_C
The products described in this document may include products subject to the foreign exchange and
foreign trade laws. 021023_F
For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3
of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S
© 2007 TOSHIBA CORPORATION
All Rights Reserved
TMP86C420FG
The Functional Differences on Products basis: TMP86CM29L, TMP86Cx29B, TMP86CH21
and TMP86Cx20
Products name
TMP86CM29L
TMP86C829B
TMP86CH29B
TMP86CM29B
TMP86CH21
TMP86CH21A
TMP86C420
TMP86C820
ROM
32 K bytes
C829: 8K bytes
CH29: 16K bytes
CM29: 32K bytes
16K bytes
C420: 4K bytes
C820: 8K bytes
RAM
1.5K bytes
C829: 512bytes
CH29: 1.5K bytes
CM29: 1.5K bytes
512bytes
256bytes
I/O port
39 pins
Minumum command
execution time
0.25µsec at 16MHz
Supply Voltage
1.8V to 3.6V at 8.0MHz/
32.768kHz
2.7V to 3.6V at 16MHz/
32.768kHz
(Note4)
1.8V to 5.5V at 4.2MHz/32.768kHz
2.7V to 5.5V at 8.0MHz/32.768kHz
4.5V to 5.5V at 16MHz/32.768kHz
18-bit Timer counter
1ch
(ECIN input is both edge or single edge)
1ch
(ECIN input is single edge)
8-bit Timer counter
4ch
2ch
Time base timer
1ch
Watch dog timer
1ch
UART/SIO
1ch (Note1)
N.A.
SIO
N.A
1ch
4ch
Key-on wakeup
A/D converter
10-bit A/D: 8ch
8-bit A/D: 8ch
LCD driver
32SEG x 4COM
Operating Temperature
-40 to 85 ℃
-40 to 85 ℃ (Note2)
-40 to 85 ℃
QFP64(14x14mm)
LQFP64(10x10mm)
Package(Body size)
LQFP64(10x10mm)
Package
(P-QFP64-1010-0.80C)
N.A
TMP86C829BFG
TMP86CH29BFG
TMP86CM29BFG
TMP86CH21FG
TMP86C420FG
TMP86C820FG
Package
(P-LQFP64-1010-0.50E)
N.A
TMP86C829BUG
TMP86CH29BUG
TMP86CM29BUG
TMP86CH21UG
TMP86C420UG
TMP86C820UG
Package
(P-LQFP64-1010-0.50D)
TMP86CM29LUG
N.A.
TMP86CH21AUG
N.A.
Note 1: UART and SIO can not use function synchronously because each function pins are shared.
Note 2: With TMP86CH21AUG the operating temperature (Topr) is -20 ℃ to 85 ℃ when the supply voltage VDD is less than 2.0V.
Note 3: TMP86C820/420 don’t have the timer/counter-6 input/output and UART input/output.
Note 4: The electrial characteristics of TMP86CM29LUG are different from that of TMP86C829/CH29/CM29B, TMP86CH21/
CH21A and TMP86C420/C820. For details, please refer to "Electrical Characteristics" in data sheet of TMP86CM29LUG.
Note 5: The operating temperature (Topr) of AD characteristics of all products (TMP86C420/C820/CH21/CH21A/C829B/CH29B/
CM29B/CM29L) is -10 ℃ to 85 ℃ when the supply voltage VDD is less than 2.0V. For details, please refer to "AD Conversion Characteristics" in data sheet of each product.
Note 6: The characteristic of power supply current differs in each product. For details, please refer to "Electirical Characteristics"
in data sheet of each product.
TMP86C420FG
The Functional Differences on Products basis:
PM29B/FM29/CM29L.
TMP86C829B/CH29B/CM29B/PM29A/
Products name
TMP86C829B
TMP86CH29B
TMP86CM29B
TMP86PM29A
TMP86PM29B
TMP86FM29
TMP86CM29L
ROM
8K bytes
(MASK)
16K bytes
(MASK)
32K bytes
(MASK)
32K bytes
(OTP)
32K bytes
(FLASH)
32K bytes
(MASK)
RAM
512 bytes
DBR
128 bytes
(Flash memory control/status registers <EEPCR, EEPSR> are non-available.)
1.5K bytes
I/O port
Large current output
(Nch) port
39 pins
4 pins (Sink-open-drain output)
20 mA (Typ)
4 pins (Sink-open-drain output)
6 mA (Typ)
Interrupt sources
External: 5 Internal: 14
Timer/Counter
18bit Timer/Counter: 1ch
8bit Timer/Counter: 4ch
UART/SIO
1ch (Note1)
Key-on wakeup
4ch
AD converter
10bit x 8ch (Note3)
LCD driver
32SEG x 4COM
VDD
Circuitry of TEST pin
128 bytes
(Flash memory control/status registers
<EEPCR, EEPSR> are available.)
R
R
RIN
No Protection
Diode (VDD side)
VDD
R
RIN
No Pull down
Resistor
Feedback resistor in
High- frequency circuit
(Note4)
Rf = 1.2 M Ω(Typ)
Rf = 3 M Ω(Typ)
Feedback resistor in
Low- frequency circuit
(Note4)
Rf = 6 M Ω(Typ)
Rf = 20 M Ω(Typ)
Emulation Chip
(Note2)
Package
Operating voltage
(Note 5)
TMP86C929AXB
P-QFP64-1414-0.80C
P-LQFP64-1010-0.50E
1.8V to 5.5V at 4.2MHz/32.768kHz
2.7V to 5.5V at 8.0MHz/32.768kHz
4.5V to 5.5V at 16MHz/32.768kHz
P-LQFP64-10100.50D
1.8V to 3.6V at 8.0MHz/32.768kHz
2.7V to 3.6V at 16MHz/32.768kHz
(Note 6)
Note 1: UART and SIO can not use function synchronously because each function pins are shared.
Note 2: An emulation chip (TMP86C929AXB) can’t emulate the Flash memory functions, CPU wait and serial PROM mode.
Therefore, if the software which includes Flash memory function or CPU wait is executed in TMP86C929AXB, the operation might be different from TMP86FM29/CM29L.
Note 3: The operating temperature (Topr) of AD characteristics of all products (TMP86C829B/CH29B/CM29B/PM29A/PM29B/
FM29/CM29L) is -10℃ to 85℃ when the supply voltage VDD is less than 2.0V. For details, please refer to "AD Conversion
Characteristics" in data sheet of each product.
Note 4: The typical value of high and low frequency feedback resistor in TMP86FM29/CM29L are different from that of the other
products. For details, please refer to "Input/Output Circuitry" in data sheet of each product.
Note 5: The characteristic of power supply current differs in each product. For details, please refer to "Electirical Characteristics"
in data sheet of each product.
Note 6: The recommended operating condition of serial PROM mode in TMP86FM29 is different from MCU mode. Fore details,
please refer to "Electirical Characteristics" in data sheet of each product.
TMP86C420FG
Condition
Halt/Operate
Wait Time‘
CPU
Peripherals
10
After reset release
2 /fc [s]
Halt
Halt
Changing from STOP mode to NORMAL mode
(at EEPCR<MNPWDW>="1"
210/fc [s]
Halt
Operate
Changing from STOP mode to SLOW mode
(at EEPCR<MNPWDW>="1")
23/fc [s]
Halt
Operate
Changing from IDLE0/1/2 mode to NORMAL mode
(at EEPCR<MNPWDW>="0")
210/fc [s]
Halt
Operate
Changing from SLEEP0/1/2 mode to SLOW mode
(at EEPCR<MNPWDW>="0")
23/fc [s]
Halt
Operate
Note 1: TMP86FM29 has a CPU wait function which is a warming up (CPU halt) of CPU for stabilizing of power supply of
Flash memory. Even though TMP86CM29L doesn’t have a Flash memory, the CPU wait function is inserted to
keep the compatibility with Flash product (TMP86FM29). During the CPU wait period except RESET, CPU is
halted but peripheral functions are not halted. Therefore, if the interrupt occurs during the CPU wait period, the
interrupt latch (IL) is set and when IMF has been set to "1", the interrupt service routine might be executed after
CPU wait period . For details, please refer to "Flash Memory" in TMP86FM29 data sheet. TMP86FM29 (Flash
product) should be used as non-volatile product to confirm the software of TMP86CM29L because of the above
reason. And TMP86PM29A/PM29B (OTP product) should be used as non-volatile product to confirm the software
of TMP86C829B/CH29B/CM29B.
Type-1
(Reference pin =V1)
Type-2
(Reference pin =V1)
VDD
VDD
V3
V2
V2
V1
V1
C1
C0
VSS
VDD
V3
Reference
Voltage
C
Type-3
(Reference pin =V2)
V2
C
V1
C1
C
C0
VSS
C1
C
C0
VSS
V3
C
V2
C
C
Reference
Voltage
C
Type-5
(Reference pin =V3)
VDD
V3
C
Type-4
(Reference pin =V3)
V1
VDD
C
V2
C
Reference
Voltage
C1
C
C0
V3
C
Reference
Voltage
V1
C
C
C
C
C1
VSS
C0
VSS
Note 1: TMP86FM29/CM29L can't use LCD panel which is driven by 5V because the maximum recommended voltage is
3.6V. Therefore, the voltage level of V3 pin always should be under 3.6V.
Note 2: The operating temperature of TMP86FM29/CM29L in Type-1 and Type-2 is -10 ℃ to 85 ℃ . For details, please
refer to "LCD Driver" and "Electrical Characteristics" in data sheet.
Note 3: The operating temperature of TMP86C829B/CH29B/CM29B in all Types (Type 1 to 5) is -40 ℃ to 85 ℃ . However,
there is a voltage level limitation of V3 and VDD pin in each type. For details, please refer to "LCD Driver" and
"Electrical Characteristics" in data sheet.
C
TMP86C420FG
Revision History
Date
Revision
2006/12/6
1
First Release
2007/1/16
2
Contents Revised
2007/6/28
3
Contents Revised
Table of Contents
TMP86C420FG
1.1
1.2
1.3
1.4
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
3
4
5
2. Operational Description
2.1
CPU Core Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.1
2.1.2
2.1.3
Memory Address Map............................................................................................................................... 9
Program Memory (MaskROM).................................................................................................................. 9
Data Memory (RAM) ................................................................................................................................. 9
2.2.1
2.2.2
Clock Generator...................................................................................................................................... 10
Timing Generator .................................................................................................................................... 12
2.2
System Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.2.1
2.2.2.2
Configuration of timing generator
Machine cycle
2.2.3.1
2.2.3.2
2.2.3.3
Single-clock mode
Dual-clock mode
STOP mode
2.2.4.1
2.2.4.2
2.2.4.3
2.2.4.4
STOP mode
IDLE1/2 mode and SLEEP1/2 mode
IDLE0 and SLEEP0 modes (IDLE0, SLEEP0)
SLOW mode
2.2.3
2.2.4
2.3
Operation Mode Control Circuit .............................................................................................................. 13
Operating Mode Control ......................................................................................................................... 18
Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.3.1
2.3.2
2.3.3
2.3.4
External Reset Input ............................................................................................................................... 31
Address trap reset .................................................................................................................................. 32
Watchdog timer reset.............................................................................................................................. 32
System clock reset.................................................................................................................................. 32
3. Interrupt Control Circuit
3.1
3.2
Interrupt latches (IL15 to IL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Interrupt enable register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.2.1
3.2.2
Interrupt master enable flag (IMF) .......................................................................................................... 36
Individual interrupt enable flags (EF15 to EF4) ...................................................................................... 36
3.4.1
3.4.2
Interrupt acceptance processing is packaged as follows........................................................................ 39
Saving/restoring general-purpose registers ............................................................................................ 40
3.3
3.4
Interrupt Source Selector (INTSEL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.4.2.1
Using PUSH and POP instructions
i
3.4.2.2
Using data transfer instructions
3.4.3
Interrupt return ........................................................................................................................................ 41
3.5.1
3.5.2
Address error detection .......................................................................................................................... 42
Debugging .............................................................................................................................................. 42
3.5
3.6
3.7
3.8
Software Interrupt (INTSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Undefined Instruction Interrupt (INTUNDEF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Address Trap Interrupt (INTATRAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4. Special Function Register (SFR)
4.1
4.2
SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
DBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5. I/O Ports
5.1
5.2
5.3
5.4
5.5
5.6
Port P1 (P17 to P10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port P2 (P22 to P20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port P3 (P33 to P30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port P5 (P57 to P50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port P6 (P67 to P60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port P7 (P77 to P70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
52
53
54
55
56
57
6. Time Base Timer (TBT)
6.1
Time Base Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.1.1
6.1.2
6.1.3
Configuration .......................................................................................................................................... 59
Control .................................................................................................................................................... 59
Function .................................................................................................................................................. 60
6.2.1
6.2.2
Configuration .......................................................................................................................................... 61
Control .................................................................................................................................................... 61
6.2
Divider Output (DVO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7. Watchdog Timer (WDT)
7.1
7.2
Watchdog Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Watchdog Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
Malfunction Detection Methods Using the Watchdog Timer ...................................................................
Watchdog Timer Enable .........................................................................................................................
Watchdog Timer Disable ........................................................................................................................
Watchdog Timer Interrupt (INTWDT)......................................................................................................
Watchdog Timer Reset ...........................................................................................................................
64
65
66
66
67
7.3.1
7.3.2
7.3.3
7.3.4
Selection of Address Trap in Internal RAM (ATAS) ................................................................................
Selection of Operation at Address Trap (ATOUT) ..................................................................................
Address Trap Interrupt (INTATRAP).......................................................................................................
Address Trap Reset ................................................................................................................................
68
68
68
69
7.3
Address Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
8. 18-Bit Timer/Counter (TC1)
ii
8.1
8.2
8.3
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
8.3.1
8.3.2
8.3.3
8.3.4
Timer mode............................................................................................................................................. 75
Event Counter mode ............................................................................................................................... 75
Pulse Width Measurement mode............................................................................................................ 76
Frequency Measurement mode .............................................................................................................. 77
9. 8-Bit TimerCounter (TC3, TC4)
9.1
9.2
9.3
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
9.3.8
9.3.9
8-Bit Timer Mode (TC3 and 4) ................................................................................................................
8-Bit Event Counter Mode (TC3, 4) ........................................................................................................
8-Bit Programmable Divider Output (PDO) Mode (TC3, 4).....................................................................
8-Bit Pulse Width Modulation (PWM) Output Mode (TC3, 4)..................................................................
16-Bit Timer Mode (TC3 and 4) ..............................................................................................................
16-Bit Event Counter Mode (TC3 and 4) ................................................................................................
16-Bit Pulse Width Modulation (PWM) Output Mode (TC3 and 4)..........................................................
16-Bit Programmable Pulse Generate (PPG) Output Mode (TC3 and 4) ...............................................
Warm-Up Counter Mode.........................................................................................................................
9.3.9.1
9.3.9.2
85
86
86
89
91
92
92
95
97
Low-Frequency Warm-up Counter Mode
(NORMAL1 → NORMAL2 → SLOW2 → SLOW1)
High-Frequency Warm-Up Counter Mode
(SLOW1 → SLOW2 → NORMAL2 → NORMAL1)
10. Synchronous Serial Interface (SIO)
10.1
10.2
10.3
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
10.3.1
Internal clock
External clock
10.3.2.1
10.3.2.2
Leading edge
Trailing edge
10.3.2
10.4
10.5
10.6
Clock source ....................................................................................................................................... 101
10.3.1.1
10.3.1.2
Shift edge............................................................................................................................................ 103
Number of bits to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Number of words to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
10.6.1
10.6.2
10.6.3
4-bit and 8-bit transfer modes ............................................................................................................. 104
4-bit and 8-bit receive modes ............................................................................................................. 106
8-bit transfer / receive mode ............................................................................................................... 107
11. 8-Bit AD Converter (ADC)
11.1
11.2
11.3
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
11.3.1
11.3.2
11.3.3
11.3.4
AD Conveter Operation ......................................................................................................................
AD Converter Operation .....................................................................................................................
STOP and SLOW Mode during AD Conversion .................................................................................
Analog Input Voltage and AD Conversion Result ...............................................................................
11.4.1
Analog input pin voltage range ........................................................................................................... 115
11.4
112
112
113
114
Precautions about AD Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
iii
11.4.2
11.4.3
Analog input shared pins .................................................................................................................... 115
Noise countermeasure........................................................................................................................ 115
12. Key-on Wakeup (KWU)
12.1
12.2
12.3
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
13. LCD Driver
13.1
13.2
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
13.2.1
13.2.2
13.2.3
13.3
LCD driving methods .......................................................................................................................... 121
Frame frequency................................................................................................................................. 122
Driving method for LCD driver ............................................................................................................ 123
13.2.3.1
13.2.3.2
When using the booster circuit (LCDCR<BRES>="1")
When using an external resistor divider (LCDCR<BRES>="0")
LCD Display Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
13.3.1
13.3.2
Display data setting ............................................................................................................................ 125
Blanking .............................................................................................................................................. 126
13.4.1
13.4.2
13.4.3
Initial setting ........................................................................................................................................ 127
Store of display data ........................................................................................................................... 127
Example of LCD drive output .............................................................................................................. 130
13.4
Control Method of LCD Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
14. Input/Output Circuitry
14.1
14.2
Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
15. Electrical Characteristics
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AD Conversion Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Counter 1 input (ECIN) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Oscillating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Handling Precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
137
138
139
140
142
142
143
143
16. Package Dimensions
This is a technical document that describes the operating functions and electrical
specifications of the 8-bit microcontroller series TLCS-870/C (LSI).
iv
TMP86C420FG
CMOS 8-Bit Microcontroller
TMP86C420FG
Product No.
ROM
(MaskROM)
RAM
Package
OTP MCU
Emulation Chip
TMP86C420FG
4096
bytes
256
bytes
QFP64-P-1414-0.80C
TMP86P820FG
TMP86C929AXB
1.1 Features
1. 8-bit single chip microcomputer TLCS-870/C series
- Instruction execution time :
0.25 µs (at 16 MHz)
122 µs (at 32.768 kHz)
- 132 types & 731 basic instructions
2. 15interrupt sources (External : 5 Internal : 10)
3. Input / Output ports (39 pins)
Large current output: 4pins (Typ. 20mA), LED direct drive
4. Prescaler
- Time base timer
- Divider output function
5. Watchdog Timer
6. 18-bit Timer/Counter : 1ch
- Timer Mode
- Event Counter Mode
- Pulse Width Measurement Mode
- Frequency Measurement Mode
7. 8-bit timer counter : 2 ch
- Timer, Event counter, Programmable divider output (PDO),
Pulse width modulation (PWM) output,
060116EBP
• The information contained herein is subject to change without notice. 021023_D
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can
malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when
utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations
in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for
Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A
• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither
intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of
which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments,
airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's
own risk. 021023_B
• The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or
sale are prohibited under any applicable laws and regulations. 060106_Q
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C
• The products described in this document are subject to the foreign exchange and foreign trade laws. 021023_E
• For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and
Reliability Assurance/Handling Precautions. 030619_S
Page 1
1.1 Features
TMP86C420FG
Programmable pulse generation (PPG) modes
8. 8-bit SIO: 1 ch
9. 8-bit successive approximation type AD converter (with sample hold)
Analog inputs: 8ch
10. Key-on wakeup : 4 ch
11. LCD driver/controller
Built-in voltage booster for LCD driver With display memory
LCD direct drive capability (MAX 32 seg × 4 com)
1/4,1/3,1/2duties or static drive are programmably selectable
12. Clock operation
Single clock mode
Dual clock mode
13. Low power consumption operation
STOP mode: Oscillation stops. (Battery/Capacitor back-up.)
SLOW1 mode: Low power consumption operation using low-frequency clock.(High-frequency clock
stop.)
SLOW2 mode: Low power consumption operation using low-frequency clock.(High-frequency clock
oscillate.)
IDLE0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using high frequency clock. Release by falling edge of the source clock which is set by TBTCR<TBTCK>.
IDLE1 mode: CPU stops and peripherals operate using high frequency clock. Release by interruputs(CPU restarts).
IDLE2 mode: CPU stops and peripherals operate using high and low frequency clock. Release by interruputs. (CPU restarts).
SLEEP0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using low frequency clock.Release by falling edge of the source clock which is set by TBTCR<TBTCK>.
SLEEP1 mode: CPU stops, and peripherals operate using low frequency clock. Release by interruput.(CPU restarts).
SLEEP2 mode: CPU stops and peripherals operate using high and low frequency clock.
interruput.
14. Wide operation voltage:
4.5 V to 5.5 V at 16MHz /32.768 kHz
2.7 V to 5.5 V at 8 MHz /32.768 kHz
1.8 V to 5.5 V at 4.2MHz /32.768 kHz
Page 2
Release by
TMP86C420FG
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
RESET
(INT5/STOP) P20
(AIN0) P60
(ECIN/AIN1) P61
(ECNT/AIN2) P62
(INT0/AIN3) P63
(STOP2/AIN4) P64
(STOP3/AIN5) P65
(STOP4/AIN6) P66
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
VSS
XIN
XOUT
TEST
VDD
(XTIN) P21
(XTOUT) P22
SEG2
SEG1
SEG0
COM3
COM2
COM1
COM0
V3
V2
V1
C1
C0
(DVO) P30
(TC3/PDO3/PWM3) P31
(TC4/PDO4/PWM4/PPG4) P32
P33
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SEG3
SEG4
SEG5
SEG6
SEG7
P77 (SEG8)
P76 (SEG9)
P75 (SEG10)
P74 (SEG11)
P73 (SEG12)
P72 (SEG13)
P71 (SEG14)
P70 (SEG15)
P57 (SEG16)
P56 (SEG17)
P55 (SEG18)
1.2 Pin Assignment
Figure 1-1 Pin Assignment
Page 3
P54(SEG19)
P53(SEG20)
P52(SEG21)
P51(SEG22)
P50(SEG23)
P17(SEG24/SCK)
P16(SEG25/SO)
P15(SEG26/SI)
P14(SEG27/INT3)
P13(SEG28/INT2)
P12(SEG29/INT1)
P11(SEG30)
P10(SEG31)
AVDD
VAREF
P67(AIN7/STOP5)
1.3 Block Diagram
TMP86C420FG
1.3 Block Diagram
Figure 1-2 Block Diagram
Page 4
TMP86C420FG
1.4 Pin Names and Functions
Table 1-1 Pin Names and Functions(1/3)
Pin Name
Pin Number
Input/Output
Functions
27
IO
O
IO
PORT17
LCD segment output 24
Serial Clock I/O
P16
SEG25
SO
26
IO
O
O
PORT16
LCD segment output 25
Serial Data Output
P15
SEG26
SI
25
IO
O
I
PORT15
LCD segment output 26
Serial Data Input
P14
SEG27
INT3
24
IO
O
I
PORT14
LCD segment output 27
External interrupt 3 input
P13
SEG28
INT2
23
IO
O
I
PORT13
LCD segment output 28
External interrupt 2 input
P12
SEG29
INT1
22
IO
O
I
PORT12
LCD segment output 29
External interrupt 1 input
P11
SEG30
21
IO
O
PORT11
LCD segment output 30
P10
SEG31
20
IO
O
PORT10
LCD segment output 31
P22
XTOUT
7
IO
O
PORT22
Resonator connecting pins(32.768kHz) for inputting external
clock
P21
XTIN
6
IO
I
PORT21
Resonator connecting pins(32.768kHz) for inputting external
clock
9
IO
I
I
PORT20
STOP mode release signal input
External interrupt 5 input
64
IO
PORT33
63
IO
O
I
PORT32
PDO4/PWM4/PPG4 output
TC4 input
62
IO
O
I
PORT31
PDO3/PWM3 output
TC3 input
61
IO
O
PORT30
Divider Output
P57
SEG16
35
IO
O
PORT57
LCD segment output 16
P56
SEG17
34
IO
O
PORT56
LCD segment output 17
P55
SEG18
33
IO
O
PORT55
LCD segment output 18
P17
SEG24
SCK
P20
STOP
INT5
P33
P32
PDO4/PWM4/PPG4
TC4
P31
PDO3/PWM3
TC3
P30
DVO
Page 5
1.4 Pin Names and Functions
TMP86C420FG
Table 1-1 Pin Names and Functions(2/3)
Pin Name
Pin Number
Input/Output
Functions
P54
SEG19
32
IO
O
PORT54
LCD segment output 19
P53
SEG20
31
IO
O
PORT53
LCD segment output 20
P52
SEG21
30
IO
O
PORT52
LCD segment output 21
P51
SEG22
29
IO
O
PORT51
LCD segment output 22
P50
SEG23
28
IO
O
PORT50
LCD segment output 23
P67
AIN7
STOP5
17
IO
I
I
PORT67
Analog Input7
STOP5 input
P66
AIN6
STOP4
16
IO
I
I
PORT66
Analog Input6
STOP4 input
P65
AIN5
STOP3
15
IO
I
I
PORT65
Analog Input5
STOP3 input
P64
AIN4
STOP2
14
IO
I
I
PORT64
Analog Input4
STOP2 input
13
IO
I
I
PORT63
Analog Input3
External interrupt 0 input
P62
AIN2
ECNT
12
IO
I
I
PORT62
Analog Input2
ECNT input
P61
AIN1
ECIN
11
IO
I
I
PORT61
Analog Input1
ECIN input
P60
AIN0
10
IO
I
PORT60
Analog Input0
P77
SEG8
43
IO
O
PORT77
LCD segment output 8
P76
SEG9
42
IO
O
PORT76
LCD segment output 9
P75
SEG10
41
IO
O
PORT75
LCD segment output 10
P74
SEG11
40
IO
O
PORT74
LCD segment output 11
P73
SEG12
39
IO
O
PORT73
LCD segment output 12
P72
SEG13
38
IO
O
PORT72
LCD segment output 13
P71
SEG14
37
IO
O
PORT71
LCD segment output 14
P70
SEG15
36
IO
O
PORT70
LCD segment output 15
P63
AIN3
INT0
Page 6
TMP86C420FG
Table 1-1 Pin Names and Functions(3/3)
Pin Name
Pin Number
Input/Output
Functions
SEG7
44
O
LCD segment output 7
SEG6
45
O
LCD segment output 6
SEG5
46
O
LCD segment output 5
SEG4
47
O
LCD segment output 4
SEG3
48
O
LCD segment output 3
SEG2
49
O
LCD segment output 2
SEG1
50
O
LCD segment output 1
SEG0
51
O
LCD segment output 0
COM3
52
O
LCD common output 3
COM2
53
O
LCD common output 2
COM1
54
O
LCD common output 1
COM0
55
O
LCD common output 0
V3
56
I
LCD voltage booster pin
V2
57
I
LCD voltage booster pin
V1
58
I
LCD voltage booster pin
C1
59
I
LCD voltage booster pin
C0
60
I
LCD voltage booster pin
XIN
2
I
Resonator connecting pins for high-frequency clock
XOUT
3
O
Resonator connecting pins for high-frequency clock
RESET
8
IO
Reset signal
TEST
4
I
Test pin for out-going test. Normally, be fixed to low.
VAREF
18
I
Analog Base Voltage Input Pin for A/D Conversion
AVDD
19
I
Analog Power Supply
VDD
5
I
Power Supply
VSS
1
I
0(GND)
Page 7
1.4 Pin Names and Functions
TMP86C420FG
Page 8
TMP86C420FG
2. Operational Description
2.1 CPU Core Functions
The CPU core consists of a CPU, a system clock controller, and an interrupt controller.
This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit.
2.1.1
Memory Address Map
The TMP86C420FG memory is composed MaskROM, RAM, DBR(Data buffer register) and SFR(Special
function register). They are all mapped in 64-Kbyte address space. Figure 2-1 shows the
memory address map.
0000H
SFR
SFR:
64 bytes
003FH
0040H
256
bytes
RAM
RAM:
TMP86C420FG
Special function register includes:
I/O ports
Peripheral control registers
Peripheral status registers
System control registers
Program status word
Random access memory includes:
Data memory
Stack
013FH
0F80H
DBR:
128
bytes
DBR
0FFFH
F000H
MaskROM:
Data buffer register includes:
Peripheral control registers
Peripheral status registers
LCD display memory
Program memory
4096
bytes
MaskROM
FFC0H
Vector table for vector call instructions
(32 bytes)
FFDFH
FFE0H
Vector table for interrupts
FFFFH
(32 bytes)
Figure 2-1 Memory Address Map
2.1.2
Program Memory (MaskROM)
The TMP86C420FG has a 4096 bytes (Address F000H to FFFFH) of program memory (MaskROM ).
2.1.3
Data Memory (RAM)
The TMP86C420FG has 256bytes (Address 0040H to 013FH) of internal RAM. The first 192 bytes (0040H
to 00FFH) of the internal RAM are located in the direct area; instructions with shorten operations are available
against such an area.
Page 9
2. Operational Description
2.2 System Clock Controller
TMP86C420FG
The data memory contents become unstable when the power supply is turned on; therefore, the data memory
should be initialized by an initialization routine.
Example :Clears RAM to “00H”. (TMP86C420FG)
SRAMCLR:
LD
HL, 0040H
; Start address setup
LD
A, H
; Initial value (00H) setup
LD
BC, 00FFH
LD
(HL), A
INC
HL
DEC
BC
JRS
F, SRAMCLR
2.2 System Clock Controller
The system clock controller consists of a clock generator, a timing generator, and a standby controller.
Timing generator control register
TBTCR
0036H
Clock
generator
XIN
fc
High-frequency
clock oscillator
Timing
generator
XOUT
Standby controller
0038H
XTIN
Low-frequency
clock oscillator
SYSCR1
fs
System clocks
0039H
SYSCR2
System control registers
XTOUT
Clock generator control
Figure 2-2 System Colck Control
2.2.1
Clock Generator
The clock generator generates the basic clock which provides the system clocks supplied to the CPU core
and peripheral hardware. It contains two oscillation circuits: One for the high-frequency clock and one for the
low-frequency clock. Power consumption can be reduced by switching of the standby controller to low-power
operation based on the low-frequency clock.
The high-frequency (fc) clock and low-frequency (fs) clock can easily be obtained by connecting a resonator
between the XIN/XOUT and XTIN/XTOUT pins respectively. Clock input from an external oscillator is also
possible. In this case, external clock is applied to XIN/XTIN pin with XOUT/XTOUT pin not connected.
Page 10
TMP86C420FG
Low-frequency clock
High-frequency clock
XIN
XOUT
XIN
XOUT
XTIN
XTOUT
(Open)
(a) Crystal/Ceramic
resonator
XTIN
XTOUT
(Open)
(c) Crystal
(b) External oscillator
(d) External oscillator
Figure 2-3 Examples of Resonator Connection
Note:The function to monitor the basic clock directly at external is not provided for hardware, however, with disabling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse
which the fixed frequency is outputted to the port by the program.
The system to require the adjustment of the oscillation frequency should create the program for the adjustment in advance.
Page 11
2. Operational Description
2.2 System Clock Controller
2.2.2
TMP86C420FG
Timing Generator
The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware
from the basic clock (fc or fs). The timing generator provides the following functions.
1. Generation of main system clock
2. Generation of divider output (DVO) pulses
3. Generation of source clocks for time base timer
4. Generation of source clocks for watchdog timer
5. Generation of internal source clocks for timer/counters
6. Generation of warm-up clocks for releasing STOP mode
7. LCD
2.2.2.1
Configuration of timing generator
The timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator,
and machine cycle counters.
An input clock to the 7th stage of the divider depends on the operating mode, SYSCR2<SYSCK> and
TBTCR<DV7CK>, that is shown in Figure 2-4. As reset and STOP mode started/canceled, the prescaler
and the divider are cleared to “0”.
fc or fs
Main system clock generator
Machine cycle counters
SYSCK
DV7CK
High-frequency
clock fc
Low-frequency
clock fs
1 2
fc/4
S
A
Divider
Y
1 2 3 4 5 6
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
B
Multiplexer
S
B0
B1
A0 Y0
A1 Y1
Multiplexer
Warm-up
controller
Watchdog
timer
Timer counter, Serial interface, Time-base-timer, divider output, etc. (Peripheral functions)
Figure 2-4 Configuration of Timing Generator
Page 12
TMP86C420FG
Timing Generator Control Register
TBTCR
(0036H)
7
6
(DVOEN)
5
(DVOCK)
DV7CK
4
3
DV7CK
(TBTEN)
Selection of input to the 7th stage
of the divider
2
1
0
(TBTCK)
(Initial value: 0000 0000)
0: fc/28 [Hz]
1: fs
R/W
Note 1: In single clock mode, do not set DV7CK to “1”.
Note 2: Do not set “1” on DV7CK while the low-frequency clock is not operated stably.
Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care
Note 4: In SLOW1/2 and SLEEP1/2 modes, the DV7CK setting is ineffective, and fs is input to the 7th stage of the divider.
Note 5: When STOP mode is entered from NORMAL1/2 mode, the DV7CK setting is ineffective during the warm-up period after
release of STOP mode, and the 6th stage of the divider is input to the 7th stage during this period.
2.2.2.2
Machine cycle
Instruction execution and peripheral hardware operation are synchronized with the main system clock.
The minimum instruction execution unit is called an “machine cycle”. There are a total of 10 different
types of instructions for the TLCS-870/C Series: Ranging from 1-cycle instructions which require one
machine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. A
machine cycle consists of 4 states (S0 to S3), and each state consists of one main system clock.
1/fc or 1/fs [s]
Main system clock
State
S0
S1
S2
S3
S0
S1
S2
S3
Machine cycle
Figure 2-5 Machine Cycle
2.2.3
Operation Mode Control Circuit
The operation mode control circuit starts and stops the oscillation circuits for the high-frequency and lowfrequency clocks, and switches the main system clock. There are three operating modes: Single clock mode,
dual clock mode and STOP mode. These modes are controlled by the system control registers (SYSCR1 and
SYSCR2). Figure 2-6 shows the operating mode transition diagram.
2.2.3.1
Single-clock mode
Only the oscillation circuit for the high-frequency clock is used, and P21 (XTIN) and P22 (XTOUT)
pins are used as input/output ports. The main-system clock is obtained from the high-frequency clock. In
the single-clock mode, the machine cycle time is 4/fc [s].
(1)
NORMAL1 mode
In this mode, both the CPU core and on-chip peripherals operate using the high-frequency clock.
The TMP86C420FG is placed in this mode after reset.
Page 13
2. Operational Description
2.2 System Clock Controller
TMP86C420FG
(2)
IDLE1 mode
In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are
halted; however on-chip peripherals remain active (Operate using the high-frequency clock).
IDLE1 mode is started by SYSCR2<IDLE> = "1", and IDLE1 mode is released to NORMAL1
mode by an interrupt request from the on-chip peripherals or external interrupt inputs. When the IMF
(Interrupt master enable flag) is “1” (Interrupt enable), the execution will resume with the acceptance
of the interrupt, and the operation will return to normal after the interrupt service is completed. When
the IMF is “0” (Interrupt disable), the execution will resume with the instruction which follows the
IDLE1 mode start instruction.
(3)
IDLE0 mode
In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation.
This mode is enabled by SYSCR2<TGHALT> = "1".
When IDLE0 mode starts, the CPU stops and the timing generator stops feeding the clock to the
peripheral circuits other than TBT. Then, upon detecting the falling edge of the source clock selected
with TBTCR<TBTCK>, the timing generator starts feeding the clock to all peripheral circuits.
When returned from IDLE0 mode, the CPU restarts operating, entering NORMAL1 mode back
again. IDLE0 mode is entered and returned regardless of how TBTCR<TBTEN> is set. When IMF =
“1”, EF6 (TBT interrupt individual enable flag) = “1”, and TBTCR<TBTEN> = “1”, interrupt processing is performed. When IDLE0 mode is entered while TBTCR<TBTEN> = “1”, the INTTBT
interrupt latch is set after returning to NORMAL1 mode.
2.2.3.2
Dual-clock mode
Both the high-frequency and low-frequency oscillation circuits are used in this mode. P21 (XTIN) and
P22 (XTOUT) pins cannot be used as input/output ports. The main system clock is obtained from the
high-frequency clock in NORMAL2 and IDLE2 modes, and is obtained from the low-frequency clock in
SLOW and SLEEP modes. The machine cycle time is 4/fc [s] in the NORMAL2 and IDLE2 modes, and
4/fs [s] (122 µs at fs = 32.768 kHz) in the SLOW and SLEEP modes.
The TLCS-870/C is placed in the signal-clock mode during reset. To use the dual-clock mode, the lowfrequency oscillator should be turned on at the start of a program.
(1)
NORMAL2 mode
In this mode, the CPU core operates with the high-frequency clock. On-chip peripherals operate
using the high-frequency clock and/or low-frequency clock.
(2)
SLOW2 mode
In this mode, the CPU core operates with the low-frequency clock, while both the high-frequency
clock and the low-frequency clock are operated. As the SYSCR2<SYSCK> becomes "1", the hardware changes into SLOW2 mode. As the SYSCR2<SYSCK> becomes “0”, the hardware changes
into NORMAL2 mode. As the SYSCR2<XEN> becomes “0”, the hardware changes into SLOW1
mode. Do not clear SYSCR2<XTEN> to “0” during SLOW2 mode.
(3)
SLOW1 mode
This mode can be used to reduce power-consumption by turning off oscillation of the high-frequency clock. The CPU core and on-chip peripherals operate using the low-frequency clock.
Page 14
TMP86C420FG
Switching back and forth between SLOW1 and SLOW2 modes are performed by
SYSCR2<XEN>. In SLOW1 and SLEEP modes, the input clock to the 1st stage of the divider is
stopped; output from the 1st to 6th stages is also stopped.
(4)
IDLE2 mode
In this mode, the internal oscillation circuit remain active. The CPU and the watchdog timer are
halted; however, on-chip peripherals remain active (Operate using the high-frequency clock and/or
the low-frequency clock). Starting and releasing of IDLE2 mode are the same as for IDLE1 mode,
except that operation returns to NORMAL2 mode.
(5)
SLEEP1 mode
In this mode, the internal oscillation circuit of the low-frequency clock remains active. The CPU,
the watchdog timer, and the internal oscillation circuit of the high-frequency clock are halted; however, on-chip peripherals remain active (Operate using the low-frequency clock). Starting and releasing of SLEEP mode are the same as for IDLE1 mode, except that operation returns to SLOW1 mode.
In SLOW1 and SLEEP1 modes, the input clock to the 1st stage of the divider is stopped; output from
the 1st to 6th stages is also stopped.
(6)
SLEEP2 mode
The SLEEP2 mode is the idle mode corresponding to the SLOW2 mode. The status under the
SLEEP2 mode is same as that under the SLEEP1 mode, except for the oscillation circuit of the highfrequency clock.
(7)
SLEEP0 mode
In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation. This mode
is enabled by setting “1” on bit SYSCR2<TGHALT>.
When SLEEP0 mode starts, the CPU stops and the timing generator stops feeding the clock to the
peripheral circuits other than TBT. Then, upon detecting the falling edge of the source clock selected
with TBTCR<TBTCK>, the timing generator starts feeding the clock to all peripheral circuits.
When returned from SLEEP0 mode, the CPU restarts operating, entering SLOW1 mode back
again. SLEEP0 mode is entered and returned regardless of how TBTCR<TBTEN> is set. When IMF
= “1”, EF6 (TBT interrupt individual enable flag) = “1”, and TBTCR<TBTEN> = “1”, interrupt processing is performed. When SLEEP0 mode is entered while TBTCR<TBTEN> = “1”, the INTTBT
interrupt latch is set after returning to SLOW1 mode.
2.2.3.3
STOP mode
In this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. The
internal status immediately prior to the halt is held with a lowest power consumption during STOP mode.
STOP mode is started by the system control register 1 (SYSCR1), and STOP mode is released by a
inputting (Either level-sensitive or edge-sensitive can be programmably selected) to the STOP pin. After
the warm-up period is completed, the execution resumes with the instruction which follows the STOP
mode start instruction.
Page 15
2. Operational Description
2.2 System Clock Controller
TMP86C420FG
IDLE0
mode
RESET
Reset release
Note 2
SYSCR2<TGHALT> = "1"
SYSCR1<STOP> = "1"
SYSCR2<IDLE> = "1"
NORMAL1
mode
Interrupt
STOP pin input
IDLE1
mode
(a) Single-clock mode
SYSCR2<XTEN> = "0"
SYSCR2<XTEN> = "1"
SYSCR2<IDLE> = "1"
IDLE2
mode
NORMAL2
mode
Interrupt
SYSCR1<STOP> = "1"
STOP pin input
SYSCR2<SYSCK> = "0"
SYSCR2<SYSCK> = "1"
STOP
SYSCR2<IDLE> = "1"
SLEEP2
mode
SLOW2
mode
Interrupt
SYSCR2<XEN> = "0"
SYSCR2<XEN> = "1"
SYSCR2<IDLE> = "1"
SLEEP1
mode
Interrupt
(b) Dual-clock mode
SYSCR1<STOP> = "1"
SLOW1
mode
STOP pin input
SYSCR2<TGHALT> = "1"
Note 2
SLEEP0
mode
Note 1: NORMAL1 and NORMAL2 modes are generically called NORMAL; SLOW1 and SLOW2 are called SLOW; IDLE0, IDLE1
and IDLE2 are called IDLE; SLEEP0, SLEEP1 and SLEEP2 are called SLEEP.
Note 2: The mode is released by falling edge of TBTCR<TBTCK> setting.
Figure 2-6 Operating Mode Transition Diagram
Table 2-1 Operating Mode and Conditions
Oscillator
Operating Mode
High
Frequency
Low
Frequency
RESET
NORMAL1
Single clock
IDLE1
Oscillation
Reset
Operate
Halt
Operate
Halt
Operate with
high frequency
Machine Cycle
Time
4/fc [s]
–
4/fc [s]
Halt
Oscillation
Operate with
low frequency
Oscillation
Halt
Operate
Operate
Operate with
low frequency
SLOW1
4/fs [s]
Stop
SLEEP0
STOP
Reset
Stop
SLEEP2
SLEEP1
Reset
Halt
SLOW2
Dual clock
Other
Peripherals
Stop
NORMAL2
IDLE2
TBT
Operate
IDLE0
STOP
CPU Core
Halt
Stop
Halt
Page 16
Halt
–
TMP86C420FG
System Control Register 1
SYSCR1
7
6
5
4
(0038H)
STOP
RELM
RETM
OUTEN
3
2
1
0
WUT
(Initial value: 0000 00**)
STOP
STOP mode start
0: CPU core and peripherals remain active
1: CPU core and peripherals are halted (Start STOP mode)
R/W
RELM
Release method for STOP
mode
0: Edge-sensitive release
1: Level-sensitive release
R/W
RETM
Operating mode after STOP
mode
0: Return to NORMAL1/2 mode
1: Return to SLOW1 mode
R/W
Port output during STOP mode
0: High impedance
1: Output kept
R/W
OUTEN
WUT
Warm-up time at releasing
STOP mode
Return to NORMAL mode
Return to SLOW mode
00
3 x 216/fc
3 x 213/fs
01
216/fc
213/fs
10
3 x 214/fc
3 x 26/fs
11
214/fc
26/fs
R/W
Note 1: Always set RETM to “0” when transiting from NORMAL mode to STOP mode. Always set RETM to “1” when transiting
from SLOW mode to STOP mode.
Note 2: When STOP mode is released with RESET pin input, a return is made to NORMAL1 regardless of the RETM contents.
Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *; Don’t care
Note 4: Bits 1 and 0 in SYSCR1 are read as undefined data when a read instruction is executed.
Note 5: As the hardware becomes STOP mode under OUTEN = “0”, input value is fixed to “0”; therefore it may cause external
interrupt request on account of falling edge.
Note 6: When the key-on wakeup is used, RELM should be set to "1".
Note 7: Port P20 is used as STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes
High-Z mode.
Note 8: The warmig-up time should be set correctly for using oscillator.
System Control Register 2
SYSCR2
(0039H)
7
6
5
4
XEN
XTEN
SYSCK
IDLE
3
2
1
TGHALT
0
(Initial value: 1000 *0**)
XEN
High-frequency oscillator control
0: Turn off oscillation
1: Turn on oscillation
XTEN
Low-frequency oscillator control
0: Turn off oscillation
1: Turn on oscillation
SYSCK
Main system clock select
(Write)/main system clock monitor (Read)
0: High-frequency clock (NORMAL1/NORMAL2/IDLE1/IDLE2)
1: Low-frequency clock (SLOW1/SLOW2/SLEEP1/SLEEP2)
IDLE
CPU and watchdog timer control
(IDLE1/2 and SLEEP1/2 modes)
0: CPU and watchdog timer remain active
1: CPU and watchdog timer are stopped (Start IDLE1/2 and SLEEP1/2 modes)
TGHALT
TG control (IDLE0 and SLEEP0
modes)
0: Feeding clock to all peripherals from TG
1: Stop feeding clock to peripherals except TBT from TG.
(Start IDLE0 and SLEEP0 modes)
R/W
R/W
Note 1: A reset is applied if both XEN and XTEN are cleared to “0”, XEN is cleared to “0” when SYSCK = “0”, or XTEN is cleared
to “0” when SYSCK = “1”.
Note 2: *: Don’t care, TG: Timing generator, *; Don’t care
Note 3: Bits 3, 1 and 0 in SYSCR2 are always read as undefined value.
Note 4: Do not set IDLE and TGHALT to “1” simultaneously.
Note 5: Because returning from IDLE0/SLEEP0 to NORMAL1/SLOW1 is executed by the asynchronous internal clock, the period
of IDLE0/SLEEP0 mode might be shorter than the period setting by TBTCR<TBTCK>.
Note 6: When IDLE1/2 or SLEEP1/2 mode is released, IDLE is automatically cleared to “0”.
Note 7: When IDLE0 or SLEEP0 mode is released, TGHALT is automatically cleared to “0”.
Note 8: Before setting TGHALT to “1”, be sure to stop peripherals. If peripherals are not stopped, the interrupt latch of peripherals
may be set after IDLE0 or SLEEP0 mode is released.
Page 17
2. Operational Description
2.2 System Clock Controller
2.2.4
TMP86C420FG
Operating Mode Control
2.2.4.1
STOP mode
STOP mode is controlled by the system control register 1, the STOP pin input and key-on wakeup input
(STOP5 to STOP2) which is controlled by the STOP mode release control register (STOPCR).
The STOP pin is also used both as a port P20 and an INT5 (external interrupt input 5) pin. STOP mode is
started by setting SYSCR1<STOP> to “1”. During STOP mode, the following status is maintained.
1. Oscillations are turned off, and all internal operations are halted.
2. The data memory, registers, the program status word and port output latches are all held in the
status in effect before STOP mode was entered.
3. The prescaler and the divider of the timing generator are cleared to “0”.
4. The program counter holds the address 2 ahead of the instruction (e.g., [SET (SYSCR1).7])
which started STOP mode.
STOP mode includes a level-sensitive mode and an edge-sensitive mode, either of which can be
selected with the SYSCR1<RELM>. Do not use any key-on wakeup input (STOP5 to STOP2) for releasing STOP mode in edge-sensitive mode.
Note 1: The STOP mode can be released by either the STOP or key-on wakeup pin (STOP5 to STOP2).
However, because the STOP pin is different from the key-on wakeup and can not inhibit the release
input, the STOP pin must be used for releasing STOP mode.
Note 2: During STOP period (from start of STOP mode to end of warm up), due to changes in the external
interrupt pin signal, interrupt latches may be set to “1” and interrupts may be accepted immediately
after STOP mode is released. Before starting STOP mode, therefore, disable interrupts. Also, before
enabling interrupts after STOP mode is released, clear unnecessary interrupt latches.
(1)
Level-sensitive release mode (RELM = “1”)
In this mode, STOP mode is released by setting the STOP pin high or setting the STOP5 to STOP2
pin input which is enabled by STOPCR. This mode is used for capacitor backup when the main
power supply is cut off and long term battery backup.
Even if an instruction for starting STOP mode is executed while STOP pin input is high or STOP5
to STOP2 input is low, STOP mode does not start but instead the warm-up sequence starts immediately. Thus, to start STOP mode in the level-sensitive release mode, it is necessary for the program to
first confirm that the STOP pin input is low or STOP5 to STOP2 input is high. The following two
methods can be used for confirmation.
1. Testing a port.
2. Using an external interrupt input INT5 (INT5 is a falling edge-sensitive input).
Example 1 :Starting STOP mode from NORMAL mode by testing a port P20.
SSTOPH:
LD
(SYSCR1), 01010000B
; Sets up the level-sensitive release mode
TEST
(P2PRD). 0
; Wait until the STOP pin input goes low level
JRS
F, SSTOPH
; IMF ← 0
DI
SET
(SYSCR1). 7
; Starts STOP mode
Page 18
TMP86C420FG
Example 2 :Starting STOP mode from NORMAL mode with an INT5 interrupt.
PINT5:
TEST
(P2PRD). 0
; To reject noise, STOP mode does not start if
JRS
F, SINT5
LD
(SYSCR1), 01010000B
port P20 is at high
; Sets up the level-sensitive release mode.
; IMF ← 0
DI
SET
SINT5:
(SYSCR1). 7
; Starts STOP mode
RETI
VIH
STOP pin
XOUT pin
NORMAL
operation
STOP
operation
Warm up
Confirm by program that the
STOP pin input is low and start
STOP mode.
NORMAL
operation
STOP mode is released by the hardware.
Always released if the STOP
pin input is high.
Figure 2-7 Level-sensitive Release Mode
Note 1: Even if the STOP pin input is low after warm-up start, the STOP mode is not restarted.
Note 2: In this case of changing to the level-sensitive mode from the edge-sensitive mode, the release
mode is not switched until a rising edge of the STOP pin input is detected.
(2)
Edge-sensitive release mode (RELM = “0”)
In this mode, STOP mode is released by a rising edge of the STOP pin input. This is used in applications where a relatively short program is executed repeatedly at periodic intervals. This periodic
signal (for example, a clock from a low-power consumption oscillator) is input to the STOP pin. In
the edge-sensitive release mode, STOP mode is started even when the STOP pin input is high level.
Do not use any STOP5 to STOP2 pin input for releasing STOP mode in edge-sensitive release mode.
Example :Starting STOP mode from NORMAL mode
; IMF ← 0
DI
LD
(SYSCR1), 10010000B
; Starts after specified to the edge-sensitive release mode
VIH
STOP pin
XOUT pin
NORMAL
operation
STOP
operation
Warm up
NORMAL
operation
STOP mode started
by the program.
STOP
operation
STOP mode is released by the hardware at the rising
edge of STOP pin input.
Figure 2-8 Edge-sensitive Release Mode
Page 19
2. Operational Description
2.2 System Clock Controller
TMP86C420FG
STOP mode is released by the following sequence.
1. In the dual-clock mode, when returning to NORMAL2, both the high-frequency and lowfrequency clock oscillators are turned on; when returning to SLOW1 mode, only the lowfrequency clock oscillator is turned on. In the single-clock mode, only the high-frequency
clock oscillator is turned on.
2. A warm-up period is inserted to allow oscillation time to stabilize. During warm up, all
internal operations remain halted. Four different warm-up times can be selected with the
SYSCR1<WUT> in accordance with the resonator characteristics.
3. When the warm-up time has elapsed, normal operation resumes with the instruction following the STOP mode start instruction.
Note 1: When the STOP mode is released, the start is made after the prescaler and the divider of the
timing generator are cleared to "0".
Note 2: STOP mode can also be released by inputting low level on the RESET pin, which immediately
performs the normal reset operation.
Note 3: When STOP mode is released with a low hold voltage, the following cautions must be observed.
The power supply voltage must be at the operating voltage level before releasing STOP mode.
The RESET pin input must also be “H” level, rising together with the power supply voltage. In this
case, if an external time constant circuit has been connected, the RESET pin input voltage will
increase at a slower pace than the power supply voltage. At this time, there is a danger that a
reset may occur if input voltage level of the RESET pin drops below the non-inverting high-level
input voltage (Hysteresis input).
Table 2-2 Warm-up Time Example (at fc = 16.0 MHz, fs = 32.768 kHz)
Warm-up Time [ms]
WUT
00
01
10
11
Return to NORMAL Mode
Return to SLOW Mode
12.288
4.096
3.072
1.024
750
250
5.85
1.95
Note 1: The warm-up time is obtained by dividing the basic clock by the divider. Therefore, the warm-up
time may include a certain amount of error if there is any fluctuation of the oscillation frequency
when STOP mode is released. Thus, the warm-up time must be considered as an approximate
value.
Page 20
Page 21
Figure 2-9 STOP Mode Start/Release
Divider
Instruction
execution
Program
counter
Main
system
clock
Oscillator
circuit
STOP pin
input
Divider
Instruction
execution
Program
counter
Main
system
clock
Oscillator
circuit
0
Halt
Turn off
Turn on
Turn on
n
Count up
a+3
Warm up
a+2
n+2
n+3
n+4
0
(b) STOP mode release
1
Instruction address a + 2
a+4
2
Instruction address a + 3
a+5
(a) STOP mode start (Example: Start with SET (SYSCR1). 7 instruction located at address a)
n+1
SET (SYSCR1). 7
a+3
3
Instruction address a + 4
a+6
0
Halt
Turn off
TMP86C420FG
2. Operational Description
2.2 System Clock Controller
2.2.4.2
TMP86C420FG
IDLE1/2 mode and SLEEP1/2 mode
IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable
interrupts. The following status is maintained during these modes.
1. Operation of the CPU and watchdog timer (WDT) is halted. On-chip peripherals continue to
operate.
2. The data memory, CPU registers, program status word and port output latches are all held in the
status in effect before these modes were entered.
3. The program counter holds the address 2 ahead of the instruction which starts these modes.
Starting IDLE1/2 and
SLEEP1/2 modes by
instruction
CPU and WDT are halted
Yes
Reset input
Reset
No
No
Interrupt request
Yes
“0”
IMF
“1” (Interrupt release mode)
Normal
release mode
Interrupt processing
Execution of the instruction which follows the
IDLE1/2 and SLEEP1/2
modes start instruction
Figure 2-10 IDLE1/2 and SLEEP1/2 Modes
Page 22
TMP86C420FG
• Start the IDLE1/2 and SLEEP1/2 modes
After IMF is set to "0", set the individual interrupt enable flag (EF) which releases IDLE1/2
and SLEEP1/2 modes. To start IDLE1/2 and SLEEP1/2 modes, set SYSCR2<IDLE> to “1”.
• Release the IDLE1/2 and SLEEP1/2 modes
IDLE1/2 and SLEEP1/2 modes include a normal release mode and an interrupt release mode.
These modes are selected by interrupt master enable flag (IMF). After releasing IDLE1/2 and
SLEEP1/2 modes, the SYSCR2<IDLE> is automatically cleared to “0” and the operation mode
is returned to the mode preceding IDLE1/2 and SLEEP1/2 modes.
IDLE1/2 and SLEEP1/2 modes can also be released by inputting low level on the RESET pin.
After releasing reset, the operation mode is started from NORMAL1 mode.
(1)
Normal release mode (IMF = “0”)
IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled by the individual
interrupt enable flag (EF). After the interrupt is generated, the program operation is resumed from the
instruction following the IDLE1/2 and SLEEP1/2 modes start instruction. Normally, the interrupt
latches (IL) of the interrupt source used for releasing must be cleared to “0” by load instructions.
(2)
Interrupt release mode (IMF = “1”)
IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled with the individual
interrupt enable flag (EF) and the interrupt processing is started. After the interrupt is processed, the
program operation is resumed from the instruction following the instruction, which starts IDLE1/2
and SLEEP1/2 modes.
Note: When a watchdog timer interrupts is generated immediately before IDLE1/2 and SLEEP1/2
modes are started, the watchdog timer interrupt will be processed but IDLE1/2 and SLEEP1/2
modes will not be started.
Page 23
Page 24
Figure 2-11 IDLE1/2 and SLEEP1/2 Modes Start/Release
Watchdog
timer
Instruction
execution
Program
counter
Interrupt
request
Main
system
clock
Watchdog
timer
Instruction
execution
Program
counter
Interrupt
request
Main
system
clock
Watchdog
timer
Instruction
execution
Program
counter
Interrupt
request
Main
system
clock
Halt
Halt
Halt
Halt
Operate
Operate
Operate
Acceptance of interrupt
Instruction address a + 2
a+4
(b) IDLE1/2 and SLEEP1/2 modes release
㽳㩷Interrupt release mode
a+3
㽲㩷Normal release mode
a+3
(a) IDLE1/2 and SLEEP1/2 modes start (Example: Starting with the SET instruction located at address a)
Operate
SET (SYSCR2). 4
a+2
Halt
a+3
2.2 System Clock Controller
2. Operational Description
TMP86C420FG
TMP86C420FG
2.2.4.3
IDLE0 and SLEEP0 modes (IDLE0, SLEEP0)
IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base
timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0 modes.
1. Timing generator stops feeding clock to peripherals except TBT.
2. The data memory, CPU registers, program status word and port output latches are all held in the
status in effect before IDLE0 and SLEEP0 modes were entered.
3. The program counter holds the address 2 ahead of the instruction which starts IDLE0 and
SLEEP0 modes.
Note: Before starting IDLE0 or SLEEP0 mode, be sure to stop (Disable) peripherals.
Stopping peripherals
by instruction
Starting IDLE0, SLEEP0
modes by instruction
CPU and WDT are halted
Reset input
Yes
Reset
No
No
TBT
source clock
falling
edge
Yes
No
TBTCR<TBTEN>
= "1"
Yes
No
TBT interrupt
enable
Yes
(Normal release mode)
No
IMF = "1"
Yes (Interrupt release mode)
Interrupt processing
Execution of the instruction
which follows the IDLE0,
SLEEP0 modes start
instruction
Figure 2-12 IDLE0 and SLEEP0 Modes
Page 25
2. Operational Description
2.2 System Clock Controller
TMP86C420FG
• Start the IDLE0 and SLEEP0 modes
Stop (Disable) peripherals such as a timer counter.
To start IDLE0 and SLEEP0 modes, set SYSCR2<TGHALT> to “1”.
• Release the IDLE0 and SLEEP0 modes
IDLE0 and SLEEP0 modes include a normal release mode and an interrupt release mode.
These modes are selected by interrupt master flag (IMF), the individual interrupt enable flag
of TBT and TBTCR<TBTEN>.
After releasing IDLE0 and SLEEP0 modes, the SYSCR2<TGHALT> is automatically
cleared to “0” and the operation mode is returned to the mode preceding IDLE0 and SLEEP0
modes. Before starting the IDLE0 or SLEEP0 mode, when the TBTCR<TBTEN> is set to “1”,
INTTBT interrupt latch is set to “1”.
IDLE0 and SLEEP0 modes can also be released by inputting low level on the RESET pin.
After releasing reset, the operation mode is started from NORMAL1 mode.
Note: IDLE0 and SLEEP0 modes start/release without reference to TBTCR<TBTEN> setting.
(1)
Normal release mode (IMF•EF6•TBTCR<TBTEN> = “0”)
IDLE0 and SLEEP0 modes are released by the source clock falling edge, which is setting by the
TBTCR<TBTCK>. After the falling edge is detected, the program operation is resumed from the
instruction following the IDLE0 and SLEEP0 modes start instruction. Before starting the IDLE0 or
SLEEP0 mode, when the TBTCR<TBTEN> is set to “1”, INTTBT interrupt latch is set to “1”.
(2)
Interrupt release mode (IMF•EF6•TBTCR<TBTEN> = “1”)
IDLE0 and SLEEP0 modes are released by the source clock falling edge, which is setting by the
TBTCR<TBTCK> and INTTBT interrupt processing is started.
Note 1: Because returning from IDLE0, SLEEP0 to NORMAL1, SLOW1 is executed by the asynchronous internal clock, the period of IDLE0, SLEEP0 mode might be the shorter than the period setting by TBTCR<TBTCK>.
Note 2: When a watchdog timer interrupt is generated immediately before IDLE0/SLEEP0 mode is
started, the watchdog timer interrupt will be processed but IDLE0/SLEEP0 mode will not be
started.
Page 26
Page 27
Figure 2-13 IDLE0 and SLEEP0 Modes Start/Release
Watchdog
timer
Instruction
execution
Program
counter
TBT clock
Halt
Halt
Halt
Watchdog
timer
Main
system
clock
Halt
Instruction
execution
Program
counter
TBT clock
Main
system
clock
Watchdog
timer
Instruction
execution
Program
counter
Interrupt
request
Main
system
clock
a+3
Halt
Operate
Operate
(b) IDLE and SLEEP0 modes release
㽳㩷Interrupt release mode
a+3
㽲㩷Normal release mode
a+3
Acceptance of interrupt
Instruction address a + 2
a+4
(a) IDLE0 and SLEEP0 modes start (Example: Starting with the SET instruction located at address a
Operate
SET (SYSCR2). 2
a+2
TMP86C420FG
2. Operational Description
2.2 System Clock Controller
2.2.4.4
TMP86C420FG
SLOW mode
SLOW mode is controlled by the system control register 2 (SYSCR2).
The following is the methods to switch the mode with the warm-up counter.
(1)
Switching from NORMAL2 mode to SLOW1 mode
First, set SYSCR2<SYSCK> to switch the main system clock to the low-frequency clock for
SLOW2 mode. Next, clear SYSCR2<XEN> to turn off high-frequency oscillation.
Note: The high-frequency clock can be continued oscillation in order to return to NORMAL2 mode from
SLOW mode quickly. Always turn off oscillation of high-frequency clock when switching from
SLOW mode to stop mode.
Example 1 :Switching from NORMAL2 mode to SLOW1 mode.
SET
(SYSCR2). 5
; SYSCR2<SYSCK> ← 1
(Switches the main system clock to the low-frequency
clock for SLOW2)
CLR
(SYSCR2). 7
; SYSCR2<XEN> ← 0
(Turns off high-frequency oscillation)
Example 2 :Switching to the SLOW1 mode after low-frequency clock has stabilized.
SET
(SYSCR2). 6
; SYSCR2<XTEN> ← 1
LD
(TC3CR), 43H
; Sets mode for TC4, 3 (16-bit mode, fs for source)
LD
(TC4CR), 05H
; Sets warming-up counter mode
LDW
(TTREG3), 8000H
; Sets warm-up time (Depend on oscillator accompanied)
; IMF ← 0
DI
SET
(EIRH). 3
; IMF ← 1
EI
SET
; Enables INTTC4
(TC4CR). 3
; Starts TC4, 3
CLR
(TC4CR). 3
; Stops TC4, 3
SET
(SYSCR2). 5
; SYSCR2<SYSCK> ← 1
:
PINTTC4:
(Switches the main system clock to the low-frequency clock)
CLR
(SYSCR2). 7
; SYSCR2<XEN> ← 0
(Turns off high-frequency oscillation)
RETI
:
VINTTC4:
DW
PINTTC4
; INTTC4 vector table
Page 28
TMP86C420FG
(2)
Switching from SLOW1 mode to NORMAL2 mode
First, set SYSCR2<XEN> to turn on the high-frequency oscillation. When time for stabilization
(Warm up) has been taken by the timer/counter (TC4,TC3), clear SYSCR2<SYSCK> to switch the
main system clock to the high-frequency clock.
SLOW mode can also be released by inputting low level on the RESET pin. After releasing reset, the
operation mode is started from NORMAL1 mode.
Note: After SYSCK is cleared to “0”, executing the instructions is continiued by the low-frequency clock
for the period synchronized with low-frequency and high-frequency clocks.
High-frequency clock
Low-frequency clock
Main system clock
SYSCK
Example :Switching from the SLOW1 mode to the NORMAL2 mode (fc = 16 MHz, warm-up time is 4.0 ms).
SET
(SYSCR2). 7
; SYSCR2<XEN> ← 1 (Starts high-frequency oscillation)
LD
(TC3CR), 63H
; Sets mode for TC4, 3 (16-bit mode, fc for source)
LD
(TC4CR), 05H
; Sets warming-up counter mode
LD
(TTREG4), 0F8H
; Sets warm-up time
; IMF ← 0
DI
SET
(EIRH). 3
; IMF ← 1
EI
SET
; Enables INTTC4
(TC4CR). 3
; Starts TC4, 3
CLR
(TC4CR). 3
; Stops TC4, 3
CLR
(SYSCR2). 5
; SYSCR2<SYSCK> ← 0
:
PINTTC4:
(Switches the main system clock to the high-frequency clock)
RETI
:
VINTTC4:
DW
PINTTC4
; INTTC4 vector table
Page 29
Page 30
Figure 2-14 Switching between the NORMAL2 and SLOW Modes
SET (SYSCR2). 7
SET (SYSCR2). 5
SLOW1 mode
Instruction
execution
XEN
SYSCK
Highfrequency
clock
Lowfrequency
clock
Main
system
clock
NORMAL2
mode
Instruction
execution
XEN
SYSCK
Highfrequency
clock
Lowfrequency
clock
Main
system
clock
(b) Switching to the NORMAL2 mode
Warm up during SLOW2 mode
CLR (SYSCR2). 5
(a) Switching to the SLOW mode
SLOW2 mode
CLR (SYSCR2). 7
NORMAL2
mode
SLOW1 mode
Turn off
2.2 System Clock Controller
2. Operational Description
TMP86C420FG
TMP86C420FG
2.3 Reset Circuit
The TMP86C420FG has four types of reset generation procedures: An external reset input, an address trap reset, a
watchdog timer reset and a system clock reset. Of these reset, the address trap reset, the watchdog timer and the system clock reset are a malfunction reset. When the malfunction reset request is detected, reset occurs during the maximum 24/fc[s] (The RESET pin outputs "L" level).
The malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initialized when power is turned on. Therefore, reset may occur during maximum 24/fc[s] (1.5µs at 16.0 MHz) when
power is turned on. RESET pin outputs "L" level during maximum 24/fc[s] (1.5µs at 16.0MHz).
Table 2-3 shows on-chip hardware initialization by reset action.
Table 2-3 Initializing Internal Status by Reset Action
On-chip Hardware
Initial Value
Program counter
(PC)
(FFFEH)
Stack pointer
(SP)
Not initialized
General-purpose registers
(W, A, B, C, D, E, H, L, IX, IY)
(JF)
Not initialized
Zero flag
(ZF)
Not initialized
Carry flag
(CF)
Not initialized
Half carry flag
(HF)
Not initialized
Sign flag
(SF)
Not initialized
Overflow flag
(VF)
Not initialized
(IMF)
0
(EF)
0
(IL)
0
Interrupt individual enable flags
Interrupt latches
2.3.1
Initial Value
Prescaler and divider of timing generator
0
Not initialized
Jump status flag
Interrupt master enable flag
On-chip Hardware
Watchdog timer
Enable
Output latches of I/O ports
Refer to I/O port circuitry
Control registers
Refer to each of control
register
LCD data buffer
Not initialized
RAM
Not initialized
External Reset Input
The RESET pin contains a Schmitt trigger (Hysteresis) with an internal pull-up resistor.
When the RESET pin is held at “L” level for at least 3 machine cycles (12/fc [s]) with the power supply voltage within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized.
When the RESET pin input goes high, the reset operation is released and the program execution starts at the
vector address stored at addresses FFFEH to FFFFH.
VDD
RESET
Internal reset
Watchdog timer reset
Malfunction
reset output
circuit
Address trap reset
System clock reset
Figure 2-15 Reset Circuit
Page 31
2. Operational Description
2.3 Reset Circuit
TMP86C420FG
2.3.2
Address trap reset
If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction
from the on-chip RAM (when WDTCR1<ATAS> is set to “1”), DBR or the SFR area, address trap reset will be
generated. The reset time is maximum 24/fc[s] (1.5µs at 16.0 MHz). Then, the RESET pin outputs "L" level
during maximum 24/fc[s].
Note:The operating mode under address trapped is alternative of reset or interrupt. The address trap area is alternative.
Instruction
execution
JP a
RESET output
Reset release
Instruction at address r
Address trap is occurred
("L" output)
4/fc to 12/fc [s]
Maximum 24/fc [s]
16/fc [s]
Note 3
Internal reset
signal
Note 1: Address “a” is in the SFR, DBR or on-chip RAM (WDTCR1<ATAS> = “1”) space.
Note 2: During reset release, reset vector “r” is read out, and an instruction at address “r” is fetched and decoded.
Note 3: Varies on account of external condition: voltage or capacitance
Figure 2-16 Address Trap Reset
2.3.3
Watchdog timer reset
Refer to Section “Watchdog Timer”.
2.3.4
System clock reset
If the condition as follows is detected, the system clock reset occurs automatically to prevent dead lock of the
CPU. (The oscillation is continued without stopping.)
- In case of clearing SYSCR2<XEN> and SYSCR2<XTEN> simultaneously to “0”.
- In case of clearing SYSCR2<XEN> to “0”, when the SYSCR2<SYSCK> is “0”.
- In case of clearing SYSCR2<XTEN> to “0”, when the SYSCR2<SYSCK> is “1”.
The reset time is maximum 24/fc (1.5 µs at 16.0 MHz). Then, the RESET pin outputs "L" level during maximum 24/fc[s] (1.5µs at 16.0MHz).
Page 32
TMP86C420FG
Page 33
2. Operational Description
2.3 Reset Circuit
TMP86C420FG
Page 34
TMP86C420FG
3. Interrupt Control Circuit
The TMP86C420FG has a total of 15 interrupt sources excluding reset, of which 1 source levels are multiplexed.
Interrupts can be nested with priorities. Four of the internal interrupt sources are non-maskable while the rest are
maskable.
Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors.
The interrupt latch is set to “1” by the generation of its interrupt request which requests the CPU to accept its interrupts. Interrupts are enabled or disabled by software using the interrupt master enable flag (IMF) and interrupt enable
flag (EF). If more than one interrupts are generated simultaneously, interrupts are accepted in order which is dominated by hardware. However, there are no prioritized interrupt factors among non-maskable interrupts.
Interrupt Factors
Internal/External
Enable Condition
Interrupt
Latch
Vector
Address
Priority
(Reset)
Non-maskable
–
FFFE
1
Internal
INTSWI (Software interrupt)
Non-maskable
–
FFFC
2
Internal
INTUNDEF (Executed the undefined instruction
interrupt)
Non-maskable
–
FFFC
2
Internal
INTATRAP (Address trap interrupt)
Non-maskable
IL2
FFFA
2
Internal
INTWDT (Watchdog timer interrupt)
Non-maskable
IL3
FFF8
2
External
INT0
IMF• EF4 = 1, INT0EN = 1
IL4
FFF6
5
External
INT1
IMF• EF5 = 1
IL5
FFF4
6
Internal
INTTBT
IMF• EF6 = 1
IL6
FFF2
7
External
INT2
IMF• EF7 = 1
IL7
FFF0
8
Internal
INTTC1
IMF• EF8 = 1
IL8
FFEE
9
Internal
INTSIO
IMF• EF9 = 1
IL9
FFEC
10
Reserved
IMF• EF10 = 1
IL10
FFEA
11
INTTC4
IMF• EF11 = 1
IL11
FFE8
12
Internal
Internal
Reserved
IMF• EF12 = 1
IL12
FFE6
13
INTADC
IMF• EF13 = 1
IL13
FFE4
14
IL14
FFE2
15
IL15
FFE0
16
External
INT3
IMF• EF14 = 1, IL14ER = 0
Internal
INTTC3
IMF• EF14 = 1, IL14ER = 1
External
INT5
IMF• EF15 = 1
Note 1: The INTSEL register is used to select the interrupt source to be enabled for each multiplexed source level (see 3.3 Interrupt Source Selector (INTSEL)).
Note 2: To use the address trap interrupt (INTATRAP), clear WDTCR1<ATOUT> to “0” (It is set for the “reset request” after reset is
cancelled). For details, see “Address Trap”.
Note 3: To use the watchdog timer interrupt (INTWDT), clear WDTCR1<WDTOUT> to "0" (It is set for the "Reset request" after
reset is released). For details, see "Watchdog Timer".
3.1 Interrupt latches (IL15 to IL2)
An interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the undefined instruction interrupt. When interrupt request is generated, the latch is set to “1”, and the CPU is requested to
accept the interrupt if its interrupt is enabled. The interrupt latch is cleared to "0" immediately after accepting interrupt. All interrupt latches are initialized to “0” during reset.
The interrupt latches are located on address 003CH and 003DH in SFR area. Each latch can be cleared to "0" individually by instruction. However, IL2 and IL3 should not be cleared to "0" by software. For clearing the interrupt
latch, load instruction should be used and then IL2 and IL3 should be set to "1". If the read-modify-write instructions
such as bit manipulation or operation instructions are used, interrupt request would be cleared inadequately if interrupt is requested while such instructions are executed.
Interrupt latches are not set to “1” by an instruction.
Since interrupt latches can be read, the status for interrupt requests can be monitored by software.
Page 35
3. Interrupt Control Circuit
3.2 Interrupt enable register (EIR)
TMP86C420FG
Note: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to
"0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL
(Enable interrupt by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on
interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL
should be executed before setting IMF="1".
Example 1 :Clears interrupt latches
; IMF ← 0
DI
LDW
(ILL), 1110100000111111B
; IL12, IL10 to IL6 ← 0
; IMF ← 1
EI
Example 2 :Reads interrupt latchess
WA, (ILL)
; W ← ILH, A ← ILL
TEST
(ILL). 7
; if IL7 = 1 then jump
JR
F, SSET
LD
Example 3 :Tests interrupt latches
3.2 Interrupt enable register (EIR)
The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the non-maskable
interrupts (Software interrupt, undefined instruction interrupt, address trap interrupt and watchdog interrupt). Nonmaskable interrupt is accepted regardless of the contents of the EIR.
The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). These
registers are located on address 003AH and 003BH in SFR area, and they can be read and written by an instructions
(Including read-modify-write instructions such as bit manipulation or operation instructions).
3.2.1
Interrupt master enable flag (IMF)
The interrupt enable register (IMF) enables and disables the acceptance of the whole maskable interrupt.
While IMF = “0”, all maskable interrupts are not accepted regardless of the status on each individual interrupt
enable flag (EF). By setting IMF to “1”, the interrupt becomes acceptable if the individuals are enabled. When
an interrupt is accepted, IMF is cleared to “0” after the latest status on IMF is stacked. Thus the maskable interrupts which follow are disabled. By executing return interrupt instruction [RETI/RETN], the stacked data,
which was the status before interrupt acceptance, is loaded on IMF again.
The IMF is located on bit0 in EIRL (Address: 003AH in SFR), and can be read and written by an instruction.
The IMF is normally set and cleared by [EI] and [DI] instruction respectively. During reset, the IMF is initialized to “0”.
3.2.2
Individual interrupt enable flags (EF15 to EF4)
Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding
bit of an individual interrupt enable flag to “1” enables acceptance of its interrupt, and setting the bit to “0” disables acceptance. During reset, all the individual interrupt enable flags (EF15 to EF4) are initialized to “0” and
all maskable interrupts are not accepted until they are set to “1”.
Note:In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear
IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF
or IL (Enable interrupt by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1".
Page 36
TMP86C420FG
Example 1 :Enables interrupts individually and sets IMF
; IMF ← 0
DI
LDW
:
(EIRL), 1110100010100000B
; EF15 to EF13, EF11, EF7, EF5 ← 1
Note: IMF should not be set.
:
; IMF ← 1
EI
Example 2 :C compiler description example
unsigned int _io (3AH) EIRL;
/* 3AH shows EIRL address */
_DI();
EIRL = 10100000B;
:
_EI();
Page 37
3. Interrupt Control Circuit
3.2 Interrupt enable register (EIR)
TMP86C420FG
Interrupt Latches
(Initial value: 00000000 000000**)
ILH,ILL
(003DH, 003CH)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
IL15
IL14
IL13
IL12
IL11
IL10
IL9
IL8
IL7
IL6
IL5
IL4
IL3
IL2
ILH (003DH)
IL15 to IL2
1
0
ILL (003CH)
at RD
0: No interrupt request
Interrupt latches
at WR
0: Clears the interrupt request
1: (Interrupt latch is not set.)
1: Interrupt request
R/W
Note 1: To clear any one of bits IL7 to IL4, be sure to write "1" into IL2 and IL3.
Note 2: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0"
(Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt
by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1".
Note 3: Do not clear IL with read-modify-write instructions such as bit operations.
Interrupt Enable Registers
(Initial value: 00000000 0000***0)
EIRH,EIRL
(003BH, 003AH)
15
14
13
12
11
10
9
8
7
6
5
4
EF15
EF14
EF13
EF12
EF11
EF10
EF9
EF8
EF7
EF6
EF5
EF4
EIRH (003BH)
EF15 to EF4
IMF
3
2
1
0
IMF
EIRL (003AH)
Individual-interrupt enable flag
(Specified for each bit)
0:
1:
Disables the acceptance of each maskable interrupt.
Enables the acceptance of each maskable interrupt.
Interrupt master enable flag
0:
1:
Disables the acceptance of all maskable interrupts
Enables the acceptance of all maskable interrupts
R/W
Note 1: *: Don’t care
Note 2: Do not set IMF and the interrupt enable flag (EF15 to EF4) to “1” at the same time.
Note 3: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0"
(Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt
by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1".
Page 38
TMP86C420FG
3.3 Interrupt Source Selector (INTSEL)
Each interrupt source that shares the interrupt source level with another interrupt source is allowed to enable the
interrupt latch only when it is selected in the INTSEL register. The interrupt controller does not hold interrupt
requests corresponding to interrupt sources that are not selected in the INTSEL register. Therefore, the INTSEL register must be set appropriately before interrupt requests are generated.
The following interrupt sources share their interrupt source level; the source is selected onnthe register INTSEL.
1. INT3 and INTTC3 share the interrupt source level whose priority is 15.
Interrupt source selector
INTSEL
(003EH)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
IL14ER
-
IL14ER
(Initial value: **** **0*)
0: INT3
1: INTTC3
Selects INT3 or INTTC3
R/W
3.4 Interrupt Sequence
An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to
“0” by resetting or an instruction. Interrupt acceptance sequence requires 8 machine cycles (2 µs @16 MHz) after the
completion of the current instruction. The interrupt service task terminates upon execution of an interrupt return
instruction [RETI] (for maskable interrupts) or [RETN] (for non-maskable interrupts). Figure 3-1 shows the timing
chart of interrupt acceptance processing.
3.4.1
Interrupt acceptance processing is packaged as follows.
a. The interrupt master enable flag (IMF) is cleared to “0” in order to disable the acceptance of any following interrupt.
b. The interrupt latch (IL) for the interrupt source accepted is cleared to “0”.
c. The contents of the program counter (PC) and the program status word, including the interrupt master
enable flag (IMF), are saved (Pushed) on the stack in sequence of PSW + IMF, PCH, PCL. Meanwhile, the stack pointer (SP) is decremented by 3.
d. The entry address (Interrupt vector) of the corresponding interrupt service program, loaded on the vector table, is transferred to the program counter.
e. The instruction stored at the entry address of the interrupt service program is executed.
Note:When the contents of PSW are saved on the stack, the contents of IMF are also saved.
Interrupt service task
1-machine cycle
Interrupt
request
Interrupt
latch (IL)
IMF
Execute
instruction
PC
SP
Execute
instruction
a−1
a
Execute
instruction
Interrupt acceptance
a+1
b
a
n
b+1 b+2 b + 3
n−1 n−2
n-3
Page 39
Execute RETI instruction
c+1
c+2
n−2 n−1
a
a+1 a+2
n
3. Interrupt Control Circuit
3.4 Interrupt Sequence
TMP86C420FG
Note 1: a: Return address entry address, b: Entry address, c: Address which RETI instruction is stored
Note 2: On condition that interrupt is enabled, it takes 38/fc [s] or 38/fs [s] at maximum (If the interrupt latch is set at the first
machine cycle on 10 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set.
Figure 3-1 Timing Chart of Interrupt Acceptance/Return Interrupt Instruction
Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt
service program
Vector table address
FFF2H
03H
FFF3H
D2H
Entry address
Vector
D203H
0FH
D204H
06H
Interrupt
service
program
Figure 3-2 Vector table address,Entry address
A maskable interrupt is not accepted until the IMF is set to “1” even if the maskable interrupt higher than the
level of current servicing interrupt is requested.
In order to utilize nested interrupt service, the IMF is set to “1” in the interrupt service program. In this case,
acceptable interrupt sources are selectively enabled by the individual interrupt enable flags.
To avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced,
before setting IMF to “1”. As for non-maskable interrupt, keep interrupt service shorten compared with length
between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply
nested.
3.4.2
Saving/restoring general-purpose registers
During interrupt acceptance processing, the program counter (PC) and the program status word (PSW,
includes IMF) are automatically saved on the stack, but the accumulator and others are not. These registers are
saved by software if necessary. When multiple interrupt services are nested, it is also necessary to avoid using
the same data memory area for saving registers. The following methods are used to save/restore the generalpurpose registers.
3.4.2.1
Using PUSH and POP instructions
If only a specific register is saved or interrupts of the same source are nested, general-purpose registers
can be saved/restored using the PUSH/POP instructions.
Example :Save/store register using PUSH and POP instructions
PINTxx:
PUSH
WA
; Save WA register
(interrupt processing)
POP
WA
; Restore WA register
RETI
; RETURN
Page 40
TMP86C420FG
Address
(Example)
SP
b-5
A
SP
b-4
SP
b-3
PCL
W
PCL
PCH
PCH
PCH
PSW
PSW
PSW
At acceptance of
an interrupt
PCL
At execution of
PUSH instruction
At execution of
POP instruction
b-2
b-1
SP
b
At execution of
RETI instruction
Figure 3-3 Save/store register using PUSH and POP instructions
3.4.2.2
Using data transfer instructions
To save only a specific register without nested interrupts, data transfer instructions are available.
Example :Save/store register using data transfer instructions
PINTxx:
LD
(GSAVA), A
; Save A register
(interrupt processing)
LD
A, (GSAVA)
; Restore A register
RETI
; RETURN
Main task
Interrupt
acceptance
Interrupt
service task
Saving
registers
Restoring
registers
Interrupt return
Saving/Restoring general-purpose registers using PUSH/POP data transfer instruction
Figure 3-4 Saving/Restoring General-purpose Registers under Interrupt Processing
3.4.3
Interrupt return
Interrupt return instructions [RETI]/[RETN] perform as follows.
[RETI]/[RETN] Interrupt Return
1. Program counter (PC) and program status word
(PSW, includes IMF) are restored from the stack.
2. Stack pointer (SP) is incremented by 3.
Page 41
3. Interrupt Control Circuit
3.5 Software Interrupt (INTSW)
TMP86C420FG
As for address trap interrupt (INTATRAP), it is required to alter stacked data for program counter (PC) to
restarting address, during interrupt service program.
Note:If [RETN] is executed with the above data unaltered, the program returns to the address trap area and
INTATRAP occurs again.When interrupt acceptance processing has completed, stacked data for PCL and
PCH are located on address (SP + 1) and (SP + 2) respectively.
Example 1 :Returning from address trap interrupt (INTATRAP) service program
PINTxx:
POP
WA
; Recover SP by 2
LD
WA, Return Address
;
PUSH
WA
; Alter stacked data
(interrupt processing)
RETN
; RETURN
Example 2 :Restarting without returning interrupt
(In this case, PSW (Includes IMF) before interrupt acceptance is discarded.)
PINTxx:
INC
SP
; Recover SP by 3
INC
SP
;
INC
SP
;
(interrupt processing)
LD
EIRL, data
; Set IMF to “1” or clear it to “0”
JP
Restart Address
; Jump into restarting address
Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next interrupt can be accepted immediately after the interrupt return instruction is executed.
Note 1: It is recommended that stack pointer be return to rate before INTATRAP (Increment 3 times), if return interrupt instruction [RETN] is not utilized during interrupt service program under INTATRAP (such as Example
2).
Note 2: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service
task is performed but not the main task.
3.5 Software Interrupt (INTSW)
Executing the SWI instruction generates a software interrupt and immediately starts interrupt processing (INTSW
is highest prioritized interrupt).
Use the SWI instruction only for detection of the address error or for debugging.
3.5.1
Address error detection
FFH is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent
memory address during single chip mode. Code FFH is the SWI instruction, so a software interrupt is generated and an address error is detected. The address error detection range can be further expanded by writing
FFH to unused areas of the program memory. Address trap reset is generated in case that an instruction is
fetched from RAM, DBR or SFR areas.
3.5.2
Debugging
Debugging efficiency can be increased by placing the SWI instruction at the software break point setting
address.
Page 42
TMP86C420FG
3.6 Undefined Instruction Interrupt (INTUNDEF)
Taking code which is not defined as authorized instruction for instruction causes INTUNDEF. INTUNDEF is generated when the CPU fetches such a code and tries to execute it. INTUNDEF is accepted even if non-maskable interrupt is in process. Contemporary process is broken and INTUNDEF interrupt process starts, soon after it is
requested.
Note: The undefined instruction interrupt (INTUNDEF) forces CPU to jump into vector address, as software interrupt
(SWI) does.
3.7 Address Trap Interrupt (INTATRAP)
Fetching instruction from unauthorized area for instructions (Address trapped area) causes reset output or address
trap interrupt (INTATRAP). INTATRAP is accepted even if non-maskable interrupt is in process. Contemporary process is broken and INTATRAP interrupt process starts, soon after it is requested.
Note: The operating mode under address trapped, whether to be reset output or interrupt processing, is selected on
watchdog timer control register (WDTCR).
3.8 External Interrupts
The TMP86C420FG has 5 external interrupt inputs. These inputs are equipped with digital noise reject circuits
(Pulse inputs of less than a certain time are eliminated as noise).
Edge selection is also possible with INT1 to INT3. The INT0/P63 pin can be configured as either an external interrupt input pin or an input/output port, and is configured as an input port during reset.
Edge selection, noise reject control and INT0/P63 pin function selection are performed by the external interrupt
control register (EINTCR).
Source
INT0
INT1
INT2
INT3
INT5
Pin
INT0
INT1
INT2
INT3
INT5
Enable Conditions
Release Edge
Digital Noise Reject
IMF ΠEF4 ΠINT0EN=1
Falling edge
Pulses of less than 2/fc [s] are eliminated as
noise. Pulses of 7/fc [s] or more are considered
to be signals. In the SLOW or the SLEEP mode,
pulses of less than 1/fs [s] are eliminated as
noise. Pulses of 3.5/fs [s] or more are considered to be signals.
IMF ΠEF5 = 1
Falling edge
or
Rising edge
Pulses of less than 15/fc or 63/fc [s] are eliminated as noise. Pulses of 49/fc or 193/fc [s] or
more are considered to be signals. In the SLOW
or the SLEEP mode, pulses of less than 1/fs [s]
are eliminated as noise. Pulses of 3.5/fs [s] or
more are considered to be signals.
IMF ΠEF7 = 1
Falling edge
or
Rising edge
Pulses of less than 7/fc [s] are eliminated as
noise. Pulses of 25/fc [s] or more are considered
to be signals. In the SLOW or the SLEEP mode,
pulses of less than 1/fs [s] are eliminated as
noise. Pulses of 3.5/fs [s] or more are considered to be signals.
Falling edge
or
Rising edge
Pulses of less than 7/fc [s] are eliminated as
noise. Pulses of 25/fc [s] or more are considered
to be signals. In the SLOW or the SLEEP mode,
pulses of less than 1/fs [s] are eliminated as
noise. Pulses of 3.5/fs [s] or more are considered to be signals.
Falling edge
Pulses of less than 2/fc [s] are eliminated as
noise. Pulses of 7/fc [s] or more are considered
to be signals. In the SLOW or the SLEEP mode,
pulses of less than 1/fs [s] are eliminated as
noise. Pulses of 3.5/fs [s] or more are considered to be signals.
IMF ΠEF14 = 1
and
IL14ER=0
IMF ΠEF15 = 1
Page 43
3. Interrupt Control Circuit
3.8 External Interrupts
TMP86C420FG
Note 1: In NORMAL1/2 or IDLE1/2 mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "signal establishment time + 6/fs[s]" from the input signal's edge to set the interrupt latch.
Note 2: When INT0EN = "0", IL4 is not set even if a falling edge is detected on the INT0 pin input.
Note 3: When a pin with more than one function is used as an output and a change occurs in data or input/output status, an interrupt request signal is generated in a pseudo manner. In this case, it is necessary to perform appropriate processing such
as disabling the interrupt enable flag.
Page 44
TMP86C420FG
External Interrupt Control Register
EINTCR
7
6
5
4
3
2
1
(0037H)
INT1NC
INT0EN
-
-
INT3ES
INT2ES
INT1ES
0
(Initial value: 00** 000*)
INT1NC
Noise reject time select
0: Pulses of less than 63/fc [s] are eliminated as noise
1: Pulses of less than 15/fc [s] are eliminated as noise
R/W
INT0EN
P63/INT0 pin configuration
0: P63 input/output port
1: INT0 pin (Port P63 should be set to an input mode)
R/W
INT3 ES
INT3 edge select
0: Rising edge
1: Falling edge
R/W
INT2 ES
INT2 edge select
0: Rising edge
1: Falling edge
R/W
INT1 ES
INT1 edge select
0: Rising edge
1: Falling edge
R/W
Note 1: fc: High-frequency clock [Hz], *: Don’t care
Note 2: When the system clock frequency is switched between high and low or when the external interrupt control register
(EINTCR) is overwritten, the noise canceller may not operate normally. It is recommended that external interrupts are disabled using the interrupt enable register (EIR).
Note 3: The maximum time from modifying INT1NC until a noise reject time is changed is 26/fc.
Page 45
3. Interrupt Control Circuit
3.8 External Interrupts
TMP86C420FG
Page 46
TMP86C420FG
4. Special Function Register (SFR)
The TMP86C420FG adopts the memory mapped I/O system, and all peripheral control and data transfers are performed through the special function register (SFR) or the data buffer register (DBR). The SFR is mapped on address
0000H to 003FH, DBR is mapped on address 0F80H to 0FFFH.
This chapter shows the arrangement of the special function register (SFR) and data buffer register (DBR) for
TMP86C420FG.
4.1 SFR
Address
Read
Write
0000H
Reserved
0001H
P1DR
0002H
P2DR
0003H
P3DR
0004H
P3OUTCR
0005H
P5DR
0006H
P6DR
0007H
0008H
P7DR
P1PRD
-
0009H
P2PRD
-
000AH
P3PRD
-
000BH
P5PRD
000CH
000DH
P6CR
P7PRD
000EH
ADCCR1
000FH
ADCCR2
0010H
TREG1AL
0011H
TREG1AM
0012H
TREG1AH
0013H
TREG1B
0014H
TC1CR1
0015H
0016H
TC1CR2
TC1SR
-
0017H
Reserved
0018H
TC3CR
0019H
TC4CR
001AH
Reserved
001BH
Reserved
001CH
TTREG3
001DH
TTREG4
001EH
Reserved
001FH
Reserved
0020H
ADCDR1
0021H
ADCDR2
-
0022H
Reserved
0023H
Reserved
0024H
Reserved
0025H
Reserved
Page 47
4. Special Function Register (SFR)
4.1 SFR
TMP86C420FG
Address
Read
Write
0026H
Reserved
0027H
Reserved
0028H
LCDCR
0029H
P1LCR
002AH
P5LCR
002BH
P7LCR
002CH
PWREG3
002DH
PWREG4
002EH
Reserved
002FH
Reserved
0030H
Reserved
0031H
Reserved
0032H
Reserved
0033H
Reserved
0034H
-
WDTCR1
0035H
-
WDTCR2
0036H
TBTCR
0037H
EINTCR
0038H
SYSCR1
0039H
SYSCR2
003AH
EIRL
003BH
EIRH
003CH
ILL
003DH
ILH
003EH
INTSEL
003FH
PSW
Note 1: Do not access reserved areas by the program.
Note 2: − ; Cannot be accessed.
Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such
as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.).
Page 48
TMP86C420FG
4.2 DBR
Address
Read
Write
0F80H
SEG1/0
0F81H
SEG3/2
0F82H
SEG5/4
0F83H
SEG7/6
0F84H
SEG9/8
0F85H
SEG11/10
0F86H
SEG13/12
0F87H
SEG15/14
0F88H
SEG17/16
0F89H
SEG19/18
0F8AH
SEG21/20
0F8BH
SEG23/22
0F8CH
SEG25/24
0F8DH
SEG27/26
0F8EH
SEG29/28
0F8FH
SEG31/30
0F90H
SIOBR0
0F91H
SIOBR1
0F92H
SIOBR2
0F93H
SIOBR3
0F94H
SIOBR4
0F95H
SIOBR5
0F96H
SIOBR6
0F97H
SIOBR7
0F98H
-
SIOCR1
0F99H
SIOSR
SIOCR2
0F9AH
-
STOPCR
0F9BH
Reserved
0F9CH
Reserved
0F9DH
Reserved
0F9EH
Reserved
0F9FH
Reserved
Address
Read
0FA0H
Write
Reserved
: :
: :
0FBFH
Reserved
Address
Read
0FC0H
Write
Reserved
: :
: :
0FDFH
Reserved
Address
Read
0FE0H
Write
Reserved
: :
: :
0FFFH
Reserved
Note 1: Do not access reserved areas by the program.
Page 49
4. Special Function Register (SFR)
4.2 DBR
TMP86C420FG
Note 2: − ; Cannot be accessed.
Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such
as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.).
Page 50
TMP86C420FG
5. I/O Ports
The TMP86C420FG have 6 parallel input/output ports (39 pins) as follows.
Primary Function
Port P1
Secondary Functions
8-bit I/O port
External interrupt input, serial interface input/output, and segment output.
Port P2
3-bit I/O port
Low-frequency resonator connections, external interrupt input, STOP mode
release signal input.
Port P3
4-bit I/O port
Timer/counter input/output and divider output.
Port P5
8-bit I/O port
Segment output.
Port P6
8-bit I/O port
Analog input, external interrupt input, timer/counter input and STOP mode
release signal input.
Port P7
8-bit I/O port
Segment output.
Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external
input data should be externally held until the input data is read from outside or reading should be performed several
timer before processing. Figure 5-1 shows input/output timing examples.
External data is read from an I/O port in the S1 state of the read cycle during execution of the read instruction. This
timing cannot be recognized from outside, so that transient input such as chattering must be processed by the program.
Output data changes in the S2 state of the write cycle during execution of the instruction which writes to an I/O
port.
Fetch cycle
Fetch cycle
Read cycle
S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3
Ex: LD A, (x)
Instruction execution cycle
Input strobe
Data input
(a) Input timing
Fetch cycle
Fetch cycle
Write cycle
S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3
Instruction execution cycle
Ex: LD (x), A
Output strobe
Old
Data output
(b) Output timing
Note: The positions of the read and write cycles may vary, depending on the instruction.
Figure 5-1 Input/Output Timing (Example)
Page 51
New
5. I/O Ports
5.1 Port P1 (P17 to P10)
TMP86C420FG
5.1 Port P1 (P17 to P10)
Port P1 is an 8-bit input/output port which is also used as an external interrupt input, serial interface input/output,
and segment output of LCD. When used as a segment pins of LCD, the respective bit of P1LCR should be set to “1”.
When used as an input port or a secondary function (except for segment) pins, the respective output latch (P1DR)
should be set to “1” and its corresponding P1LCR bit should be set to “0”. When used as an output port, the respective P1LCR bit should be set to “0”. During reset, the output latch is initialized to “1”.
P1 port output latch (P1DR) and P1 port terminal input (P1PRD) are located on their respective address.
When read the output latch data, the P1DR register should be read and when read the terminal input data, the
P1PRD register should be read.
If the terminal input data which is configured as LCD segment output is read, unstable data is read.
Control input
Terminal input (P1PRD)
P1LCRi
D
Q
D
Q
P1LCRi input
Output latch data (P1DR)
Data output (P1DR)
Control output
P1i
Note: i = 7 to 0
Output latch
STOP
OUTEN
LCD data output
Figure 5-2 Port 1
P1DR
(0001H)
R/W
P1LCR
(0029H)
7
6
5
4
3
2
1
0
P17
SEG24
P15
SEG26
SI
P14
SEG27
INT3
P13
SEG28
INT2
P12
SEG29
INT1
P11
SEG30
P10
SEG31
SCK
P16
SEG25
SO
7
6
5
4
3
2
1
0
(Initial value: 0000 0000)
Port P1/segment output control
(set for each bit individually)
0: P1 input/output port or secondary function (expect for segment)
1: Segment output
7
6
5
4
3
2
1
0
P17
P16
P15
P14
P13
P12
P11
P10
P1LCR
P1PRD
(0008H)
Read only
(Initial value: 1111 1111)
Page 52
R/W
TMP86C420FG
5.2 Port P2 (P22 to P20)
Port P2 is a 3-bit input/output port.
It is also used as an external interrupt, a STOP mode release signal input, and low-frequency crystal oscillator connection pins. When used as an input port or a secondary function pins, respective output latch (P2DR) should be set
to “1”.
During reset, the output latch is initialized to “1”.
A low-frequency crystal oscillator (32.768 kHz) is connected to pins P21 (XTIN) and P22 (XTOUT) in the dualclock mode. In the single-clock mode, pins P21 and P22 can be used as normal input/output ports.
It is recommended that pin P20 should be used as an external interrupt input, a STOP mode release signal input, or
an input port. If it is used as an output port, the interrupt latch is set on the falling edge of the output pulse.
P2 port output latch (P2DR) and P2 port terminal input (P2PRD) are located on their respective address.
When read the output latch data, the P2DR register should be read and when read the terminal input data, the
P2PRD register should be read. If a read instruction is executed for port P2, read data of bits 7 to 3 are unstable.
Data input (P20PRD)
Data input (P20)
D
Data output (P20)
Q
P20 (INT5, STOP)
Output latch
Control input
Data input (P21PRD)
Osc. enable
Data input (P21)
Data output (P21)
D
Q
P21 (XTIN)
Output latch
Data input (P22PRD)
Data input (P22)
Data output (P22)
D
Q
P22 (XTOUT)
Output latch
STOP
OUTEN
XTEN
fs
Figure 5-3 Port 2
P2DR
(0002H)
R/W
7
6
5
4
3
2
1
0
P22
XTOUT
P21
XTIN
P20
INT5
(Initial value: **** *111)
STOP
P2PRD
(0009H)
Read only
7
6
5
4
3
2
1
0
P22
P21
P20
Note: Port P20 is used as STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes
High-Z mode.
Page 53
5. I/O Ports
5.3 Port P3 (P33 to P30)
TMP86C420FG
5.3 Port P3 (P33 to P30)
Port P3 is a 4-bit input/output port.
It is also used as a timer/counter input/output, divider output.
When used as a timer/counter output or divider output, respective output latch (P3DR) should be set to “1”.
It can be selected whether output circuit of P3 port is C-MOS output or a sink open drain individually, by setting
P3OUTCR. When a corresponding bit of P3OUTCR is “0”, the output circuit is selected to a sink open drain and
when a corresponding bit of P3OUTCR is “1”, the output circuit is selected to a C-MOS output. When used as an
input port or timer/counter input, respective output control (P3OUTCR) should be set to “0“ after P3DR is set to “1”.
During reset, the P3DR is initialized to “1”, and the P3OUTCR is initialized to “0”.
P3 port output latch (P3DR) and P3 port terminal input (P3PRD) are located on their respective address.
When read the output latch data, the P3DR should be read and when read the terminal input data, the P3PRD register should be read. If a read instruction is executed for port P3, read data of bits 7 to 4 are unstable.
STOP
OUTEN
P3OUTCRi
D
Q
D
Q
P3OUTCRi input
Data input (P3PRD)
Data input (P3DR)
Data output (P3DR)
P3i
Note: i = 3 to 0
Control output
Control input
Figure 5-4 Port 3
7
6
5
4
P3DR
(0003H)
R/W
3
2
1
0
P33
P32
P31
P30
PWM4
PWM3
DVO
PDO4
PDO3
PPG4
TC3
(Initial value: **** 1111)
TC4
P3OUTCR
(0004H)
7
5
4
3
2
1
0
(Initial value: **** 0000)
P3OUTCR
P3PRD
(000AH)
Read only
6
7
Port P3 output circuit control
(set for each bit individually)
6
5
4
0: Sink open-drain output
1: C-MOS output
R/W
3
2
1
0
P33
P32
P31
P30
Page 54
TMP86C420FG
5.4 Port P5 (P57 to P50)
Port P5 is an 8-bit input/output port which is also used as a segment pins of LCD.
When used as input port, the respective output latch (P5DR) should be set to “1”.
During reset, the output latch is initialized to “1”.
When used as a segment pins of LCD, the respective bit of P5LCR should be set to “1”. When used as an output
port, the respective P5LCR bit should be set to “0”.
P5 port output latch (P5DR) and P5 port terminal input (P5PRD) are located on their respective address.
When read the output latch data, the P5DR register should be read and when read the terminal input data, the
P5PRD register should be read. If the terminal input data which is configured as LCD segment output is read, unstable data is read.
STOP
OUTEN
P5LCRi
D
Q
D
Q
P5LCRi input
Data input (P5PRD)
Data input (P5DR)
Data output (P5DR)
P5i
Note: i = 7 to 0
Output latch
LCD data output
Figure 5-5 Port 5
P5DR
(0005H)
R/W
P5LCR
(002AH)
7
6
5
4
3
2
1
0
P57
SEG16
P56
SEG17
P55
SEG18
P54
SEG19
P53
SEG20
P52
SEG21
P51
SEG22
P50
SEG23
7
6
5
4
3
2
1
0
(Initial value: 0000 0000)
Port P5/segment output control
(set for each bit individually)
0: P5 input/output port
1: LCD segment output
7
6
5
4
3
2
1
0
P57
P56
P55
P54
P53
P52
P51
P50
P5LCR
P5PRD
(000BH)
Read only
(Initial value: 1111 1111)
Page 55
R/W
5. I/O Ports
5.5 Port P6 (P67 to P60)
TMP86C420FG
5.5 Port P6 (P67 to P60)
Port P6 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit. Port P6 is also
used as an analog input, Key-on Wake-up input, timer/counter input and external interrupt input. Input/output modes
is specified by the P6 control register (P6CR), the P6 output latch (P6DR), and ADCCR1<AINDS>. During reset,
P6CR and P6DR are initialized to “0” and ADCCR1<AINDS> is set to “1”. At the same time, the input data of pins
P67 to P60 are fixed to “0”. To use port P6 as an input port, external interrupt input, timer/counter input or key on
wake up input, set data of P6DR to “1” and P6CR to “0”. To use it as an output port, set data of P6CR to “1”. To use
it as an analog input, set data of P6DR to “0” and P6CR to “0”, and start the AD. It is the penetration electric current
measures by the analog voltage.
Pins not used for analog input can be used as I/O ports. During AD conversion, output instructions should not be
executed to keep a precision. In addition, a variable signal should not be input to a port adjacent to the analog input
during AD conversion.
When the AD converter is in use (P6DR = 0), bits mentioned above are read as “0” by executing input instructions.
STOPj
Key on Wake up
Analog input
AINDS
SAIN
P6CRi
D
Q
D
Q
P6CRi input
Data input (P6DR)
Data output (P6DR)
P6i
Control input
STOP
Note 1:
Note 2:
Note 3:
Note 4:
i = 7 to 0, j = 7 to 4
STOP is bit7 in SYSCR1
SAIN is bit 0 to 3 in ADCCRA
STOPj is bit 4 to 7 is STOPCR.
Figure 5-6 Port 6
P6DR
(0006H)
R/W
7
6
5
4
3
2
1
0
P67
AIN7
STOP5
P66
AIN6
STOP4
P65
AIN5
STOP3
P64
AIN4
STOP2
P63
AIN3
P61
AIN1
ECIN
P60
AIN0
INT0
P62
AIN2
ECNT
7
6
5
4
3
2
1
0
(Initial value: 0000 0000)
(Initial value: 0000 0000)
P6CR
(000CH)
AINDS = 1 (AD unused)
P6CR
I/O control for port P6
(specified for each bit)
0
AINDS = 0 (AD used)
P6DR = “0”
P6DR = “1”
P6DR = “0”
P6DR = “1”
Input “0” fixed
Input mode
AD input
Input mode
1
Output mode
R/W
Output mode
Note 1: Do not set output mode to pin which is used for an analog input.
Note 2: When used as an INT0, ECNT and ECIN pins of a secondary function, the respective bit of P6CR should be set to “0” and
the P6 should set to “1”.
Note 3: When used as an STOP2 to STOP5 pins of Key on Wake up, the respective bit of P6CR should be set to “0”.
Note 4: When a read instruction for port P6 is executed, the bit of Analog input mode becomes read data “0”.
Note 5: Although P6DR is a read/writer register, because it is also used as an input mode control function, read-modify-write
instructions such as bit manipulate instructions cannot be used.
Page 56
TMP86C420FG
Read-modify-write instruction writes the all data of 8-bit after data is read and modified. Because a bit setting Input mode
read data of terminal, the output latch is changed by these instruction. So P6 port can not input data.
5.6 Port P7 (P77 to P70)
Port P7 is an 8-bit input/output port which is also used as a segment pins of LCD.
When used as input port, the respective output latch (P7DR) should be set to “1”.
During reset, the output latch is initialized to “1”.
When used as a segment pins of LCD, the respective bit of P7LCR should be set to “1” and its corresponding
P7LCR bit should be set to “0”. When used as an output port, the respective P7LCR bit should be set to “0”.
P7 port output latch (P7DR) and P7 port terminal input (P7PRD) are located on their respective address.
When read the output latch data, the P7DR register should be read and when read the terminal input data, the
P7PRD register should be read. If the terminal input data which is configured as LCD segment output is read, unstable data is read.
STOP
OUTEN
P7LCRi
D
Q
D
Q
P7LCRi input
P7LCRi
Data input (P7PRD)
Data input (P7DR)
Data output (P7DR)
P7i
Note: i = 7 to 0
Output latch
LCD data output
Figure 5-7 Port 7
P7DR
(0007H)
R/W
P7LCR
(002BH)
7
6
5
4
3
2
1
0
P77
SEG8
P76
SEG9
P75
SEG10
P74
SEG11
P73
SEG12
P72
SEG13
P71
SEG14
P70
SEG15
7
6
5
4
3
2
1
0
(Initial value: 0000 0000)
P7LCR
P7PRD
(000DH)
Read only
(Initial value: 1111 1111)
Port P7/segment output control
(set for each bit individually)
0: P7 input/output port
1: Segment output
R/W
7
6
5
4
3
2
1
0
P77
P76
P75
P74
P73
P72
P71
P70
Page 57
5. I/O Ports
5.6 Port P7 (P77 to P70)
TMP86C420FG
Page 58
TMP86C420FG
6. Time Base Timer (TBT)
The time base timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base
timer interrupt (INTTBT).
6.1 Time Base Timer
6.1.1
Configuration
MPX
fc/223 or fs/215
fc/221 or fs/213
fc/216 or fs/28
fc/214 or fs/26
fc/213 or fs/25
fc/212 or fs/24
fc/211 or fs/23
fc/29 or fs/2
Source clock
IDLE0, SLEEP0
release request
Falling edge
detector
INTTBT
interrupt request
3
TBTCK
TBTEN
TBTCR
Time base timer control register
Figure 6-1 Time Base Timer configuration
6.1.2
Control
Time Base Timer is controlled by Time Base Timer control register (TBTCR).
Time Base Timer Control Register
7
TBTCR
(0036H)
6
(DVOEN)
TBTEN
5
(DVOCK)
Time Base Timer
enable / disable
4
3
(DV7CK)
TBTEN
2
1
0
TBTCK
(Initial Value: 0000 0000)
0: Disable
1: Enable
NORMAL1/2, IDLE1/2 Mode
TBTCK
Time Base Timer interrupt
Frequency select : [Hz]
DV7CK = 0
DV7CK = 1
SLOW1/2
SLEEP1/2
Mode
000
fc/223
fs/215
fs/215
001
fc/221
fs/213
fs/213
010
fc/216
fs/28
–
011
fc/2
14
6
–
100
fc/213
fs/25
–
101
fc/2
12
4
–
110
fc/211
fs/23
–
111
9
fs/2
–
fc/2
Note 1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz], *; Don't care
Page 59
fs/2
fs/2
R/W
6. Time Base Timer (TBT)
6.1 Time Base Timer
TMP86C420FG
Note 2: The interrupt frequency (TBTCK) must be selected with the time base timer disabled (TBTEN="0"). (The interrupt frequency must not be changed with the disable from the enable state.) Both frequency selection and enabling can be performed simultaneously.
Example :Set the time base timer frequency to fc/216 [Hz] and enable an INTTBT interrupt.
LD
(TBTCR) , 00000010B
; TBTCK ← 010
LD
(TBTCR) , 00001010B
; TBTEN ← 1
; IMF ← 0
DI
SET
(EIRL) . 6
Table 6-1 Time Base Timer Interrupt Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz )
Time Base Timer Interrupt Frequency [Hz]
TBTCK
6.1.3
NORMAL1/2, IDLE1/2 Mode
NORMAL1/2, IDLE1/2 Mode
SLOW1/2, SLEEP1/2 Mode
DV7CK = 0
DV7CK = 1
000
1.91
1
1
001
7.63
4
4
010
244.14
128
–
011
976.56
512
–
100
1953.13
1024
–
101
3906.25
2048
–
110
7812.5
4096
–
111
31250
16384
–
Function
An INTTBT ( Time Base Timer Interrupt ) is generated on the first falling edge of source clock ( The divider
output of the timing generator which is selected by TBTCK. ) after time base timer has been enabled.
The divider is not cleared by the program; therefore, only the first interrupt may be generated ahead of the set
interrupt period ( Figure 6-2 ).
Source clock
TBTCR<TBTEN>
INTTBT
Interrupt period
Enable TBT
Figure 6-2 Time Base Timer Interrupt
Page 60
TMP86C420FG
6.2 Divider Output (DVO)
Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric
buzzer drive. Divider output is from DVO pin.
6.2.1
Configuration
Output latch
D
Data output
Q
DVO pin
MPX
A
B
C Y
D
S
2
fc/213 or fs/25
fc/212 or fs/24
fc/211 or fs/23
fc/210 or fs/22
Port output latch
TBTCR<DVOEN>
DVOCK
DVOEN
TBTCR
DVO pin output
Divider output control register
(a) configuration
(b) Timing chart
Figure 6-3 Divider Output
6.2.2
Control
The Divider Output is controlled by the Time Base Timer Control Register.
Time Base Timer Control Register
7
TBTCR
(0036H)
DVOEN
DVOEN
6
5
DVOCK
4
3
(DV7CK)
(TBTEN)
Divider output
enable / disable
2
1
0
(TBTCK)
(Initial value: 0000 0000)
0: Disable
1: Enable
R/W
DV7CK = 0
DV7CK = 1
SLOW1/2
SLEEP1/2
Mode
00
fc/213
fs/25
fs/25
01
fc/212
fs/24
fs/24
10
fc/211
fs/23
fs/23
11
fc/210
fs/22
fs/22
NORMAL1/2, IDLE1/2 Mode
DVOCK
Divider Output (DVO)
frequency selection: [Hz]
R/W
Note: Selection of divider output frequency (DVOCK) must be made while divider output is disabled (DVOEN="0"). Also, in other
words, when changing the state of the divider output frequency from enabled (DVOEN="1") to disable(DVOEN="0"), do not
change the setting of the divider output frequency.
Page 61
6. Time Base Timer (TBT)
6.2 Divider Output (DVO)
TMP86C420FG
Example :1.95 kHz pulse output (fc = 16.0 MHz)
LD
(TBTCR) , 00000000B
; DVOCK ← "00"
LD
(TBTCR) , 10000000B
; DVOEN ← "1"
Table 6-2 Divider Output Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz )
Divider Output Frequency [Hz]
DVOCK
NORMAL1/2, IDLE1/2 Mode
DV7CK = 0
DV7CK = 1
SLOW1/2, SLEEP1/2
Mode
00
1.953 k
1.024 k
1.024 k
01
3.906 k
2.048 k
2.048 k
10
7.813 k
4.096 k
4.096 k
11
15.625 k
8.192 k
8.192 k
Page 62
TMP86C420FG
7. Watchdog Timer (WDT)
The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spurious noises or the deadlock conditions, and return the CPU to a system recovery routine.
The watchdog timer signal for detecting malfunctions can be programmed only once as “reset request” or “interrupt request”. Upon the reset release, this signal is initialized to “reset request”.
When the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic interrupt.
Note: Care must be taken in system design since the watchdog timer functions are not be operated completely due to
effect of disturbing noise.
7.1 Watchdog Timer Configuration
Reset release
23
15
Binary counters
Selector
fc/2 or fs/2
fc/221 or fs/213
fc/219 or fs/211
fc/217 or fs/29
Clock
Clear
R
Overflow
1
WDT output
2
S
2
Q
Interrupt request
Internal reset
Q
S R
WDTEN
WDTT
Writing
disable code
Writing
clear code
WDTOUT
Controller
0034H
WDTCR1
0035H
WDTCR2
Watchdog timer control registers
Figure 7-1 Watchdog Timer Configuration
Page 63
Reset
request
INTWDT
interrupt
request
7. Watchdog Timer (WDT)
7.2 Watchdog Timer Control
TMP86C420FG
7.2 Watchdog Timer Control
The watchdog timer is controlled by the watchdog timer control registers (WDTCR1 and WDTCR2). The watchdog timer is automatically enabled after the reset release.
7.2.1
Malfunction Detection Methods Using the Watchdog Timer
The CPU malfunction is detected, as shown below.
1. Set the detection time, select the output, and clear the binary counter.
2. Clear the binary counter repeatedly within the specified detection time.
If the CPU malfunctions such as endless loops or the deadlock conditions occur for some reason, the watchdog timer output is activated by the binary-counter overflow unless the binary counters are cleared. When
WDTCR1<WDTOUT> is set to “1” at this time, the reset request is generated and the RESET pin outputs a
low-level signal, then internal hardware is initialized. When WDTCR1<WDTOUT> is set to “0”, a watchdog
timer interrupt (INTWDT) is generated.
The watchdog timer temporarily stops counting in the STOP mode including the warm-up or IDLE/SLEEP
mode, and automatically restarts (continues counting) when the STOP/IDLE/SLEEP mode is inactivated.
Note:The watchdog timer consists of an internal divider and a two-stage binary counter. When the clear code 4EH
is written, only the binary counter is cleared, but not the internal divider. The minimum binary-counter overflow
time, that depends on the timing at which the clear code (4EH) is written to the WDTCR2 register, may be 3/
4 of the time set in WDTCR1<WDTT>. Therefore, write the clear code using a cycle shorter than 3/4 of the
time set to WDTCR1<WDTT>.
Example :Setting the watchdog timer detection time to 221/fc [s], and resetting the CPU malfunction detection
Within 3/4 of WDT
detection time
LD
(WDTCR2), 4EH
: Clears the binary counters.
LD
(WDTCR1), 00001101B
: WDTT ← 10, WDTOUT ← 1
LD
(WDTCR2), 4EH
: Clears the binary counters (always clears immediately before and
after changing WDTT).
(WDTCR2), 4EH
: Clears the binary counters.
(WDTCR2), 4EH
: Clears the binary counters.
:
:
LD
Within 3/4 of WDT
detection time
:
:
LD
Page 64
TMP86C420FG
Watchdog Timer Control Register 1
WDTCR1
(0034H)
7
WDTEN
6
5
4
3
(ATAS)
(ATOUT)
WDTEN
Watchdog timer enable/disable
2
1
0
WDTT
WDTOUT
(Initial value: **11 1001)
0: Disable (Writing the disable code to WDTCR2 is required.)
1: Enable
NORMAL1/2 mode
WDTT
WDTOUT
Watchdog timer detection time
[s]
Watchdog timer output select
DV7CK = 0
DV7CK = 1
SLOW1/2
mode
00
225/fc
217/fs
217/fs
01
223/fc
215/fs
215fs
10
221fc
213/fs
213fs
11
219/fc
211/fs
211/fs
0: Interrupt request
1: Reset request
Write
only
Write
only
Write
only
Note 1: After clearing WDTOUT to “0”, the program cannot set it to “1”.
Note 2: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care
Note 3: WDTCR1 is a write-only register and must not be used with any of read-modify-write instructions. If WDTCR1 is read, a
don’t care is read.
Note 4: To activate the STOP mode, disable the watchdog timer or clear the counter immediately before entering the STOP mode.
After clearing the counter, clear the counter again immediately after the STOP mode is inactivated.
Note 5: To clear WDTEN, set the register in accordance with the procedures shown in “7.2.3 Watchdog Timer Disable”.
Watchdog Timer Control Register 2
WDTCR2
(0035H)
7
6
5
4
3
2
1
0
(Initial value: **** ****)
WDTCR2
Write
Watchdog timer control code
4EH: Clear the watchdog timer binary counter (Clear code)
B1H: Disable the watchdog timer (Disable code)
D2H: Enable assigning address trap area
Others: Invalid
Write
only
Note 1: The disable code is valid only when WDTCR1<WDTEN> = 0.
Note 2: *: Don’t care
Note 3: The binary counter of the watchdog timer must not be cleared by the interrupt task.
Note 4: Write the clear code 4EH using a cycle shorter than 3/4 of the time set in WDTCR1<WDTT>.
7.2.2
Watchdog Timer Enable
Setting WDTCR1<WDTEN> to “1” enables the watchdog timer. Since WDTCR1<WDTEN> is initialized
to “1” during reset, the watchdog timer is enabled automatically after the reset release.
Page 65
7. Watchdog Timer (WDT)
7.2 Watchdog Timer Control
7.2.3
TMP86C420FG
Watchdog Timer Disable
To disable the watchdog timer, set the register in accordance with the following procedures. Setting the register in other procedures causes a malfunction of the microcontroller.
1. Set the interrupt master flag (IMF) to “0”.
2. Set WDTCR2 to the clear code (4EH).
3. Set WDTCR1<WDTEN> to “0”.
4. Set WDTCR2 to the disable code (B1H).
Note:While the watchdog timer is disabled, the binary counters of the watchdog timer are cleared.
Example :Disabling the watchdog timer
: IMF ← 0
DI
LD
(WDTCR2), 04EH
: Clears the binary counter
LDW
(WDTCR1), 0B101H
: WDTEN ← 0, WDTCR2 ← Disable code
Table 7-1 Watchdog Timer Detection Time (Example: fc = 16.0 MHz, fs = 32.768 kHz)
Watchdog Timer Detection Time[s]
WDTT
7.2.4
NORMAL1/2 mode
DV7CK = 0
DV7CK = 1
SLOW
mode
00
2.097
4
4
01
524.288 m
1
1
10
131.072 m
250 m
250 m
11
32.768 m
62.5 m
62.5 m
Watchdog Timer Interrupt (INTWDT)
When WDTCR1<WDTOUT> is cleared to “0”, a watchdog timer interrupt request (INTWDT) is generated
by the binary-counter overflow.
A watchdog timer interrupt is the non-maskable interrupt which can be accepted regardless of the interrupt
master flag (IMF).
When a watchdog timer interrupt is generated while the other interrupt including a watchdog timer interrupt
is already accepted, the new watchdog timer interrupt is processed immediately and the previous interrupt is
held pending. Therefore, if watchdog timer interrupts are generated continuously without execution of the
RETN instruction, too many levels of nesting may cause a malfunction of the microcontroller.
To generate a watchdog timer interrupt, set the stack pointer before setting WDTCR1<WDTOUT>.
Example :Setting watchdog timer interrupt
LD
SP, 013FH
: Sets the stack pointer
LD
(WDTCR1), 00001000B
: WDTOUT ← 0
Page 66
TMP86C420FG
7.2.5
Watchdog Timer Reset
When a binary-counter overflow occurs while WDTCR1<WDTOUT> is set to “1”, a watchdog timer reset
request is generated. When a watchdog timer reset request is generated, the RESET pin outputs a low-level signal and the internal hardware is reset. The reset time is maximum 24/fc [s] (1.5 µs @ fc = 16.0 MHz).
Note:When a watchdog timer reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-frequency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccuracies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate
value because it has slight errors.
219/fc [s]
217/fc
Clock
Binary counter
(WDTT=11)
1
2
3
0
1
2
3
0
Overflow
INTWDT interrupt request
(WDTCR1<WDTOUT>= "0")
Internal reset
A reset occurs
(WDTCR1<WDTOUT>= "1")
WDT reset output
(High-Z)
Write 4EH to WDTCR2
Figure 7-2 Watchdog Timer Interrupt/Reset
Page 67
7. Watchdog Timer (WDT)
7.3 Address Trap
TMP86C420FG
7.3 Address Trap
The Watchdog Timer Control Register 1 and 2 share the addresses with the control registers to generate address
traps.
Watchdog Timer Control Register 1
7
WDTCR1
(0034H)
6
5
4
3
ATAS
ATOUT
(WDTEN)
2
1
(WDTT)
0
(WDTOUT)
(Initial value: **11 1001)
ATAS
Select address trap generation in
the internal RAM area
0: Generate no address trap
1: Generate address traps (After setting ATAS to “1”, writing the control code
D2H to WDTCR2 is required)
ATOUT
Select operation at address trap
0: Interrupt request
1: Reset request
Write
only
Watchdog Timer Control Register 2
WDTCR2
(0035H)
7
5
4
3
2
1
0
(Initial value: **** ****)
WDTCR2
7.3.1
6
Write
Watchdog timer control code
and address trap area control
code
D2H: Enable address trap area selection (ATRAP control code)
4EH: Clear the watchdog timer binary counter (WDT clear code)
B1H: Disable the watchdog timer (WDT disable code)
Others: Invalid
Write
only
Selection of Address Trap in Internal RAM (ATAS)
WDTCR1<ATAS> specifies whether or not to generate address traps in the internal RAM area. To execute
an instruction in the internal RAM area, clear WDTCR1<ATAS> to “0”. To enable the WDTCR1<ATAS> setting, set WDTCR1<ATAS> and then write D2H to WDTCR2.
Executing an instruction in the SFR or DBR area generates an address trap unconditionally regardless of the
setting in WDTCR1<ATAS>.
7.3.2
Selection of Operation at Address Trap (ATOUT)
When an address trap is generated, either the interrupt request or the reset request can be selected by
WDTCR1<ATOUT>.
7.3.3
Address Trap Interrupt (INTATRAP)
While WDTCR1<ATOUT> is “0”, if the CPU should start looping for some cause such as noise and an
attempt be made to fetch an instruction from the on-chip RAM (while WDTCR1<ATAS> is “1”), DBR or the
SFR area, address trap interrupt (INTATRAP) will be generated.
An address trap interrupt is a non-maskable interrupt which can be accepted regardless of the interrupt master flag (IMF).
When an address trap interrupt is generated while the other interrupt including an address trap interrupt is
already accepted, the new address trap is processed immediately and the previous interrupt is held pending.
Therefore, if address trap interrupts are generated continuously without execution of the RETN instruction, too
many levels of nesting may cause a malfunction of the microcontroller.
To generate address trap interrupts, set the stack pointer beforehand.
Page 68
TMP86C420FG
7.3.4
Address Trap Reset
While WDTCR1<ATOUT> is “1”, if the CPU should start looping for some cause such as noise and an
attempt be made to fetch an instruction from the on-chip RAM (while WDTCR1<ATAS> is “1”), DBR or the
SFR area, address trap reset will be generated.
When an address trap reset request is generated, the RESET pin outputs a low-level signal and the internal
hardware is reset. The reset time is maximum 24/fc [s] (1.5 µs @ fc = 16.0 MHz).
Note:When an address trap reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-frequency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccuracies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate
value because it has slight errors.
Page 69
7. Watchdog Timer (WDT)
7.3 Address Trap
TMP86C420FG
Page 70
ECIN Pin
ECNT Pin
fc/214 or fs/26
2
fs/215 or fc/223
fs/25 or fc/213
fs/23 or fc/211
fc/27
fc/23
fs
fc
WGPSCK
S
Y
C
D
E
F
G
B
A
H
B
A
TC1CR1
TC1CR2
2 1 2
1
Timer/Event count modes
2 2
Y
Frequency
measurement mode
Pulse width
measurement mode
3
S
Y
Window pulse
generator
TC1CK
TC1S
fc/213 or fs/25
TREG1B
TC1M
A
B
C
TC1C
Page 71
SGP
SGEDG
WGPSCK
fc/212 or fs/24
00 S
11
10
Y
2
CMP
TREG1AL TREG1AM TREG1AH
18- bit up-counter
CLEAR signal
Edge detector
SGEDG
1
TC1M
1
TC1SR
1
F/F
INTTC1
TMP86C420FG
8. 18-Bit Timer/Counter (TC1)
8.1 Configuration
Figure 8-1 Timer/Counter1
8.2 Control
The Timer/counter 1 is controlled by timer/counter 1 control registers (TC1CR1/TC1CR2), an 18-bit timer register
(TREG1A), and an 8-bit internal window gate pulse setting register (TREG1B).
8. 18-Bit Timer/Counter (TC1)
8.2 Control
TMP86C420FG
Timer register
TREG1AH
(0012H)
R/W
7
6
5
4
3
2
−
−
−
−
−
−
7
6
5
4
3
2
TREG1AM
(0011H)
R/W
0
(Initial value: ∗∗∗∗ ∗∗00)
TREG1AH
1
0
TREG1AM
7
6
5
TREG1AL
(0010H)
R/W
4
(Initial value: 0000 0000)
3
2
1
0
TREG1AL
7
TREG1B
(0013H)
1
6
5
4
(Initial value: 0000 0000)
3
2
Ta
1
0
Tb
(Initial value: 0000 0000)
NORMAL1/2,IDLE1/2 modes
DV7CK=1
SLOW1/2,
SLEEP1/2 modes
(16 - Ta) ×
212/fc
(16 - Ta) × 24/fs
(16 - Ta) × 24/fs
(16 - Ta) ×
213/fc
25/fs
(16 - Ta) × 25/fs
WGPSCK
DV7CK=0
Ta
Tb
Setting "H" level period of the window
gate pulse
00
01
10
Setting "L" level period of the window
gate pulse
00
01
10
14
(16 - Ta) × 2 /fc
(16 - Ta) ×
6
(16 - Ta) × 2 /fs
(16 - Ta) × 26/fs
(16 - Tb) × 212/fc
(16 - Tb) × 24/fs
(16 - Tb) × 24/fs
(16 - Tb) × 213/fc
(16 - Tb) × 25/fs
(16 - Tb) × 25/fs
(16 - Tb) × 214/fc
(16 - Tb) × 26/fs
(16 - Tb) × 26/fs
Page 72
R/W
TMP86C420FG
Timer/counter 1 control register 1
7
TC1CR1
(0014H)
6
TC1C
5
4
3
TC1S
2
1
TC1CK
0
TC1M
(Initial value: 1000 1000)
TC1C
Counter/overfow flag
controll
0:
1:
Clear Counter/overflow flag ( “1” is automatically set after clearing.)
Not clear Counter/overflow flag
R/W
TC1S
TC1 start control
00:
10:
*1:
Stop and counter clear and overflow flag clear
Start
Reserved
R/W
NORMAL1/2,IDLE1/2 modes
TC1CK
TC1 source clock select
DV7CK="0"
DV7CK="1"
SLOW1/2
mode
SLEEP1/2
mode
fc
fs
fc
fs
fc
-
fc
-
fc/223
fs/215
fs/215
fs/215
13
fs/25
fs/25
fs/25
fc/211
fs/23
7
fc/2
fc/27
fc/23
fc/23
fs/23
-
fs/23
-
000:
001:
010:
011:
100:
101:
110:
fc/2
111:
TC1M
TC1 mode select
00:
01:
10:
11:
R/W
External clock (ECIN pin input)
Timer/Event counter mode
Reserved
Pulse width measurement mode
Frequency measurement mode
R/W
Note 1: fc; High-frequency clock [Hz] fs; Low-frequency clock [Hz] * ; Don’t care
Note 2: Writing to the low-byte of the timer register 1A (TREG1AL, TREG1AM), the compare function is inhibited until the highbyte (TREG1AH) is written.
Note 3: Set the mode and source clock, and edge (selection) when the TC1 stops (TC1CR1<TC1S>=00).
Note 4: “fc” can be selected as the source clock only in the timer mode during SLOW mode and in the pulse width measurement
mode during NORMAL 1/2 or IDLE 1/2 mode.
Note 5: When a read instruction is executed to the timer register (TREG1A), the counter immediate value, not the register set
value, is read out. Therefore it is impossible to read out the written value of TREG1A. To read the counter value, the read
instruction should be executed when the counter stops to avoid reading unstable value.
Note 6: Set the timer register (TREG1A) to ≥1.
Note 7: When using the timer mode and pulse width measurement mode, set TC1CR1<TC1CK> (TC1 source clock select) to
internal clock.
Note 8: When using the event counter mode, set TC1CR1<TC1CK> (TC1 source clock select) to external clock.
Note 9: Because the read value is different from the written value, do not use read-modify-write instructions to TREG1A.
Note 10:fc/27, fc/23can not be used as source clock in SLOW/SLEEP mode.
Note 11:The read data of bits 7 to 2 in TREG1AH are always “0”. (Data “1” can not be written.)
Page 73
8. 18-Bit Timer/Counter (TC1)
8.2 Control
TMP86C420FG
Timer/Counter 1 control register 2
7
TC1CR2
(0015H)
6
"0"
SGP
5
4
SGP
SGEDG
Window gate pulse select
Window gate pulse interrupt edge
select
SGEDG
3
2
WGPSCK
1
0
"1"
"0"
00:
01:
10:
11:
ECNT input
Internal window gate pulse (TREG1B)
Reserved
Reserved
0:
1:
Interrupts at the falling edge
Interrupts at the falling/rising edges
NORMAL1/2,IDLE1/2 modes
DV7CK="0"
Window gate pulse source clock
select
WGPSCK
00:
01:
10:
11:
R/W
SLOW1/2
mode
DV7CK="1"
(Initial value: *000 00**)
SLEEP1/2
mode
212/fc
24/fs
24/fs
24/fs
213/fc
25/fs
25/fs
25/fs
214/fc
Reserved
26/fs
Reserved
26/fs
Reserved
26/fs
Reserved
R/W
Note 1: fc; High-frequency clock [Hz] fs; Low-frequency clock [Hz] *; Don't care
Note 2: Set the mode, source clock, and edge (selection) when the TC1 stops (TC1CR1<TC1S> = 00).
Note 3: Make sure to write TC1CR2 register bit 0,7 to "0" and also TC1CR2 register bit 1 to "1".
TC1 status register
TC1SR
(0016H)
7
6
5
4
3
2
1
0
HECF
HEOVF
"0"
"0"
"0"
"0"
"0"
"0"
HECF
HEOVF
Operating Status monitor
0:
1:
Stop (during Tb) or disable
Under counting (during Ta)
Counter overflow monitor
0:
1:
No overflow
Overflow status
Page 74
(Initial value: 0000 0000)
Read
only
TMP86C420FG
8.3 Function
TC1 has four operating modes. The timer mode of the TC1 is used at warm-up when switching form SLOW mode
to NORMAL2 mode.
8.3.1
Timer mode
In this mode, counting up is performed using the internal clock. The contents of TREGIA are compared with
the contents of up-counter. If a match is found, an INTTC1 interrupt is generated, and the counter is cleared.
Counting up resumes after the counter is cleared.
Table 8-1 Source clock (internal clock) of Timer/Counter 1
Source Clock
Resolution
NORMAL1/2, IDLE1/2 Mode
Maximum Time Setting
SLOW Mode
SLEEP Mode
fc = 16 MHz
fs =32.768
kHz
fc = 16 MHz
fs =32.768
kHz
DV7CK = 0
DV7CK = 1
23
fs/215 [Hz]
fs/215 [Hz]
fs/215 [Hz]
0.52 s
1s
38.2 h
72.8 h
fc/213
fs/25
fs/25
fs/25
512 ms
0.98 ms
2.2 min
4.3 min
fc/211
fs/23
fs/23
fs/23
128 ms
244 ms
0.6 min
1.07 min
fc/27
fc/27
-
-
8 ms
-
2.1 s
-
fc/23
fc/23
-
-
0.5 ms
-
131.1 ms
-
fc
fc
fc (Note)
-
62.5 ns
-
16.4 ms
-
fs
fs
-
-
-
30.5 ms
-
8s
fc/2
[Hz]
Note: When fc is selected for the source clock in SLOW mode, the lower bits 11 of TREG1A is invalid, and a match of the upper
bits 7 makes interrupts.
Command Start
Internal clock
Up counter
TREG1A
0
1
2
3
4
n-1
n 0
1
2
3
4
5
6
n
Match detect
Counter clear
INTTC1 interrupt
Figure 8-2 Timing chart for timer mode
8.3.2
Event Counter mode
It is a mode to count up at the falling edge of the ECIN pin input. When using this mode, set
TC1CR1<TC1CK> to the external clock.
The countents of TREG1A are compared with the contents of up-counter. If a match is found, an INTTC1
interrupt is generated, and the counter is cleared. Counting up resumes for ECIN pin input edge each after the
counter is cleared.
The maximum applied frequency is fc/24 [Hz] in NORMAL 1/2 or IDLE 1/2 mode and fs/24[Hz] in SLOW
or SLEEP mode . Two or more machine cycles are required for both the “H” and “L” levels of the pulse width.
Page 75
8. 18-Bit Timer/Counter (TC1)
8.3 Function
TMP86C420FG
Start
ECIN pin input
0
Up counter
1
2
n-1
n
0
1
2
n
TREG1A
Match Detect
Counter clear
INTTC1 interrupt
Figure 8-3 Event counter mode timing chart
8.3.3
Pulse Width Measurement mode
In this mode, pulse widths are counted on the falling edge of logical AND-ed pulse between ECIN pin input
(window pulse) and the internal clock. When using this mode, set TC1CR1<TC1CK> to suitable internal
clock.
An INTTC1 interrupt is generated when the ECIN input detects the falling edge of the window pulse or both
rising and falling edges of the window pulse, that can be selected by TC1CR2<SGEDG>.
The contents of TREG1A should be read while the count is stopped (ECIN pin is low), then clear the counter
using TC1CR1<TC1C> (Normally, execute these process in the interrupt program).
When the counter is not cleared by TC1CR1<TC1C>, counting-up resumes from previous stopping value.
When up counter is counted up from 3FFFFH to 00000H, an overflow occurs. At that time, TC1SR<HEOVF>
is set to “1”. TC1SR<HEOVF> remains the previous data until the counter is required to be cleared by
TC1CR1<TC1C>.
Note:In pulse width measurement mode, if TC1CR1<TC1S> is written to "00" while ECIN input is "1", INTTC1 interrupt occurs. According to the following step, when timer counter is stopped, INTTC1 interrupt latch should be
cleared to "0".
Example :
TC1STOP :
¦
¦
DI
; Clear IMF
CLR
(EIRH). 0
; Clear bit0 of EIRH
LD
(TC1CR1), 00011010B
; Stop timer couter 1
LD
(ILH), 11111110B
; Clear bit0 of ILH
SET
(EIRH). 0
; Set bit0 of EIRH
EI
¦
; Set IMF
¦
Note 1: When SGEDG (window gate pulse interrupt edge select) is set to both edges and ECIN pin input is "1" in
the pulse width measurement mode, an INTTC1 interrupt is generated by setting TC1CR1<TC1S> (TC1
start control) to "10" (start).
Note 2: In the pulse width measurement mode, TC1SR<HECF> (operating status monitor) cannot used.
Note 3: Because the up counter is counted on the falling edge of logical AND-ed pulse (between ECIN pin input and
the internal clock), if ECIN input becomes falling edge while internal source clock is "H" level, the up
counter stops plus "1".
Page 76
TMP86C420FG
Count Start
Count Stop
Count Start
ECIN pin input
Internal clock
AND-ed pulse
(Internal signal)
0
Up counter
1
2
3
n-2
n-1
n
n+1
0
1
2
Read Clear
INTTC1 interrupt
Interrupt
TC1CR1<TC1C>
Figure 8-4 Pulse width measurement mode timing chart
8.3.4
Frequency Measurement mode
In this mode, the frequency of ECIN pin input pulse is measured. When using this mode, set
TC1CR1<TC1CK> to the external clock.
The edge of the ECIN input pulse is counted during “H” level of the window gate pulse selected by
TC1CR2<SGP>. To use ECNT input as a window gate pulse, TC1CR2<SGP> should be set to “00”.
An INTTC1 interrupt is generated on the falling edge or both the rising/falling edges of the window gate
pulse, that can be selected by TC1CR2<SGEDG>. In the interrupt service program, read the contents of
TREG1A while the count is stopped (window gate pulse is low), then clear the counter using
TC1CR1<TC1C>. When the counter is not cleared, counting up resumes from previous stopping value.
The window pulse status can be monitored by TC1SR<HECF>.
When up counter is counted up from 3FFFFH to 00000H, an overflow occurs. At that time,
TC1SR<HEOVF> is set to “1”. TC1SR<HEOVF> remains the previous data until the counter is required to be
cleared by TC1CR1<TC1C>.
When the internal window gate pulse is selected, the window gate pulse is set as follows.
Table 8-2 Internal window gate pulse setting time
NORMAL1/2,IDLE1/2 modes
DV7CK=0
DV7CK=1
SLOW1/2,
SLEEP1/2 modes
WGPSCK
Ta
Tb
Setting "H" level period of the window
gate pulse
00
01
10
(16 - Ta) × 212/fc
(16 - Ta) × 24/fs
(16 - Ta) × 24/fs
213/fc
25/fs
(16 - Ta) × 25/fs
(16 - Ta) × 2 /fc
(16 - Ta) × 2 /fs
(16 - Ta) × 26/fs
Setting "L" level period of the window
gate pulse
00
01
10
(16 - Tb) × 212/fc
(16 - Tb) × 24/fs
(16 - Tb) × 24/fs
(16 - Ta) ×
14
13
(16 - Ta) ×
6
(16 - Tb) × 2 /fc
(16 - Tb) × 2 /fs
(16 - Tb) × 25/fs
214/fc
26/fs
(16 - Tb) × 26/fs
(16 - Tb) ×
5
(16 - Tb) ×
R/W
The internal window gate pulse consists of “H” level period (Ta) that is counting time and “L” level period
(Tb) that is counting stop time. Ta or Tb can be individually set by TREG1B. One cycle contains Ta + Tb.
Note 1: Because the internal window gate pulse is generated in synchronization with the internal divider, it may be
delayed for a maximum of one cycle of the source clock (TC1CR2<WGPSCK>) immediately after start of
the timer.
Note 2: Set the internal window gate pulse when the timer counter is not operating or during the Tb period. When
Tb is overwritten during the Tb period, the update is valid from the next Tb period.
Page 77
8. 18-Bit Timer/Counter (TC1)
8.3 Function
TMP86C420FG
Note 3: Because the up counter is counted on the falling edge of logical AND-ed pulse (between ECIN pin input and
window gate pulse), if window gate pulse becomes falling edge while ECIN input is "H" level, the up
counter stops plus "1". Therefore, if ECIN input is always "H" level, count value becomes "1".
Table 8-3 Table Setting Ta and Tb (WGPSCK = 10, fc = 16 MHz)
Setting Value
Setting time
Setting Value
Setting time
0
16.38ms
8
8.19ms
1
15.36ms
9
7.17ms
2
14.34ms
A
6.14ms
3
13.31ms
B
5.12ms
4
12.29ms
C
4.10ms
5
11.26ms
D
3.07ms
6
10.24ms
E
2.05ms
7
9.22ms
F
1.02ms
Table 8-4 Table Setting Ta and Tb (WGPSCK = 10, fs = 32.768 kHz)
Setting Valuen
Setting time
Setting Value
Setting time
0
31.25ms
8
15.63ms
1
29.30ms
9
13.67ms
2
27.34ms
A
11.72ms
3
25.39ms
B
9.77ms
4
23.44ms
C
7.81ms
5
21.48ms
D
5.86ms
6
19.53ms
E
3.91ms
7
17.58ms
F
1.95ms
ECIN pin input
Window gate
pulse
Ta
Ta
Tb
AND-ed pulse
(Internal signal)
Up counter
INTTC1 interrupt
0
1
2
3
4
5
6
Read Clear
TC1CR1<TC1C>
Page 78
0
1
2
3
4
5
6
TMP86C420FG
9. 8-Bit TimerCounter (TC3, TC4)
9.1 Configuration
PWM mode
Overflow
fc/211 or fs/23
7
fc/2
5
fc/2
fc/23
fs
fc/2
fc
TC4 pin
A
B
C
D
E
F
G
H
Y
A
B
INTTC4
interrupt request
Clear
Y
8-bit up-counter
TC4S
S
PDO, PPG mode
A
B
S
16-bit
mode
S
TC4M
TC4S
TFF4
Toggle
Q
Set
Clear
Y
16-bit mode
Timer, Event
Counter mode
S
TC4CK
PDO4/PWM4/
PPG4 pin
Timer F/F4
A
Y
TC4CR
B
TTREG4
PWREG4
PWM, PPG mode
DecodeEN
PDO, PWM,
PPG mode
TFF4
16-bit
mode
TC3S
PWM mode
fc/211 or fs/23
fc/27
5
fc/2
3
fc/2
fs
fc/2
fc
TC3 pin
Y
8-bit up-counter
Overflow
16-bit mode
PDO mode
16-bit mode
Timer,
Event Couter mode
S
TC3M
TC3S
TFF3
INTTC3
interrupt request
Clear
A
B
C
D
E
F
G
H
Toggle
Q
Set
Clear
PDO3/PWM3/
pin
Timer F/F3
TC3CK
TC3CR
PWM mode
TTREG3
PWREG3
DecodeEN
TFF3
Figure 9-1 8-Bit TimerCounter 3, 4
Page 79
PDO, PWM mode
16-bit mode
9. 8-Bit TimerCounter (TC3, TC4)
9.1 Configuration
TMP86C420FG
9.2 TimerCounter Control
The TimerCounter 3 is controlled by the TimerCounter 3 control register (TC3CR) and two 8-bit timer registers
(TTREG3, PWREG3).
TimerCounter 3 Timer Register
TTREG3
(001CH)
R/W
7
PWREG3
(002CH)
R/W
7
6
5
4
3
2
1
0
(Initial value: 1111 1111)
6
5
4
3
2
1
0
(Initial value: 1111 1111)
Note 1: Do not change the timer register (TTREG3) setting while the timer is running.
Note 2: Do not change the timer register (PWREG3) setting in the operating mode except the 8-bit and 16-bit PWM modes while
the timer is running.
TimerCounter 3 Control Register
TC3CR
(0018H)
TFF3
7
TFF3
6
5
4
TC3CK
Time F/F3 control
3
2
TC3S
0:
1:
1
0
TC3M
(Initial value: 0000 0000)
Clear
Set
R/W
NORMAL1/2, IDLE1/2 mode
TC3CK
Operating clock selection [Hz]
DV7CK = 0
DV7CK = 1
SLOW1/2
SLEEP1/2
mode
000
fc/211
fs/23
fs/23
001
fc/27
fc/27
–
010
fc/25
fc/25
–
011
fc/23
fc/23
–
100
fs
fs
fs
101
fc/2
fc/2
–
110
fc
fc
fc (Note 8)
111
TC3S
TC3 start control
0:
1:
000:
001:
TC3M
TC3M operating mode select
010:
011:
1**:
R/W
TC3 pin input
Operation stop and counter clear
Operation start
R/W
8-bit timer/event counter mode
8-bit programmable divider output (PDO) mode
8-bit pulse width modulation (PWM) output mode
16-bit mode
(Each mode is selectable with TC4M.)
Reserved
R/W
Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock[Hz]
Note 2: Do not change the TC3M, TC3CK and TFF3 settings while the timer is running.
Note 3: To stop the timer operation (TC3S= 1 → 0), do not change the TC3M, TC3CK and TFF3 settings. To start the timer operation (TC3S= 0 → 1), TC3M, TC3CK and TFF3 can be programmed.
Note 4: To use the TimerCounter in the 16-bit mode, set the operating mode by programming TC4CR<TC4M>, where TC3M must
be fixed to 011.
Note 5: To use the TimerCounter in the 16-bit mode, select the source clock by programming TC3CK. Set the timer start control
and timer F/F control by programming TC4CR<TC4S> and TC4CR<TFF4>, respectively.
Note 6: The operating clock settings are limited depending on the timer operating mode. For the detailed descriptions, see Table
9-1 and Table 9-2.
Page 80
TMP86C420FG
Note 7: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 93.
Note 8: The operating clock fc in the SLOW or SLEEP mode can be used only as the high-frequency warm-up mode.
Page 81
9. 8-Bit TimerCounter (TC3, TC4)
9.1 Configuration
TMP86C420FG
The TimerCounter 4 is controlled by the TimerCounter 4 control register (TC4CR) and two 8-bit timer registers
(TTREG4 and PWREG4).
TimerCounter 4 Timer Register
TTREG4
(001DH)
R/W
7
PWREG4
(002DH)
R/W
7
6
5
4
3
2
1
0
(Initial value: 1111 1111)
6
5
4
3
2
1
0
(Initial value: 1111 1111)
Note 1: Do not change the timer register (TTREG4) setting while the timer is running.
Note 2: Do not change the timer register (PWREG4) setting in the operating mode except the 8-bit and 16-bit PWM modes while
the timer is running.
TimerCounter 4 Control Register
TC4CR
(0019H)
TFF4
7
TFF4
6
5
4
TC4CK
Timer F/F4 control
3
2
TC4S
0:
1:
1
0
TC4M
(Initial value: 0000 0000)
Clear
Set
R/W
NORMAL1/2, IDLE1/2 mode
TC4CK
Operating clock selection [Hz]
DV7CK = 0
DV7CK = 1
SLOW1/2
SLEEP1/2
mode
000
fc/211
fs/23
fs/23
001
fc/27
fc/27
–
010
fc/25
fc/25
–
011
fc/2
3
3
–
100
fs
fs
fs
101
fc/2
fc/2
–
110
fc
fc
–
111
TC4S
TC4 start control
0:
1:
000:
001:
010:
TC4M
TC4M operating mode select
011:
100:
101:
110:
111:
fc/2
R/W
TC4 pin input
Operation stop and counter clear
Operation start
R/W
8-bit timer/event counter mode
8-bit programmable divider output (PDO) mode
8-bit pulse width modulation (PWM) output mode
Reserved
16-bit timer/event counter mode
Warm-up counter mode
16-bit pulse width modulation (PWM) output mode
16-bit PPG mode
R/W
Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock [Hz]
Note 2: Do not change the TC4M, TC4CK and TFF4 settings while the timer is running.
Note 3: To stop the timer operation (TC4S= 1 → 0), do not change the TC4M, TC4CK and TFF4 settings.
To start the timer operation (TC4S= 0 → 1), TC4M, TC4CK and TFF4 can be programmed.
Note 4: When TC4M= 1** (upper byte in the 16-bit mode), the source clock becomes the TC3 overflow signal regardless of the
TC4CK setting.
Note 5: To use the TimerCounter in the 16-bit mode, select the operating mode by programming TC4M, where TC3CR<TC3M>
must be set to 011.
Page 82
TMP86C420FG
Note 6: To the TimerCounter in the 16-bit mode, select the source clock by programming TC3CR<TC3CK>. Set the timer start
control and timer F/F control by programming TC4S and TFF4, respectively.
Note 7: The operating clock settings are limited depending on the timer operating mode. For the detailed descriptions, see Table
9-1 and Table 9-2.
Note 8: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 93.
Table 9-1 Operating Mode and Selectable Source Clock (NORMAL1/2 and IDLE1/2 Modes)
Operating mode
fc/211
or
fc/27
fc/25
fc/23
fs
fc/2
fc
TC3
pin input
TC4
pin input
fs/23
8-bit timer
Ο
Ο
Ο
Ο
–
–
–
–
–
8-bit event counter
–
–
–
–
–
–
–
Ο
Ο
8-bit PDO
Ο
Ο
Ο
Ο
–
–
–
–
–
8-bit PWM
Ο
Ο
Ο
Ο
Ο
Ο
Ο
–
–
16-bit timer
Ο
Ο
Ο
Ο
–
–
–
–
–
16-bit event counter
–
–
–
–
–
–
–
Ο
–
Warm-up counter
–
–
–
–
Ο
–
–
–
–
16-bit PWM
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
–
16-bit PPG
Ο
Ο
Ο
Ο
–
–
–
Ο
–
Note 1: For 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on
lower bit (TC3CK).
Note 2: Ο : Available source clock
Table 9-2 Operating Mode and Selectable Source Clock (SLOW1/2 and SLEEP1/2 Modes)
Operating mode
fc/211
or
fc/27
fc/25
fc/23
fs
fc/2
fc
TC3
pin input
TC4
pin input
fs/23
8-bit timer
Ο
–
–
–
–
–
–
–
–
8-bit event counter
–
–
–
–
–
–
–
Ο
Ο
8-bit PDO
Ο
–
–
–
–
–
–
–
–
8-bit PWM
Ο
–
–
–
Ο
–
–
–
–
16-bit timer
Ο
–
–
–
–
–
–
–
–
16-bit event counter
–
–
–
–
–
–
–
Ο
–
Warm-up counter
–
–
–
–
–
–
Ο
–
–
16-bit PWM
Ο
–
–
–
Ο
–
–
Ο
–
16-bit PPG
Ο
–
–
–
–
–
–
Ο
–
Note1: For 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on
lower bit (TC3CK).
Note2: Ο : Available source clock
Page 83
9. 8-Bit TimerCounter (TC3, TC4)
9.1 Configuration
TMP86C420FG
Table 9-3 Constraints on Register Values Being Compared
Operating mode
Register Value
8-bit timer/event counter
1≤ (TTREGn) ≤255
8-bit PDO
1≤ (TTREGn) ≤255
8-bit PWM
2≤ (PWREGn) ≤254
16-bit timer/event counter
1≤ (TTREG4, 3) ≤65535
Warm-up counter
256≤ (TTREG4, 3) ≤65535
16-bit PWM
2≤ (PWREG4, 3) ≤65534
16-bit PPG
and
(PWREG4, 3) + 1 < (TTREG4, 3)
1≤ (PWREG4, 3) < (TTREG4, 3) ≤65535
Note: n = 3 to 4
Page 84
TMP86C420FG
9.3 Function
The TimerCounter 3 and 4 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8bit pulse width modulation (PWM) output modes. The TimerCounter 3 and 4 (TC3, 4) are cascadable to form a 16bit timer. The 16-bit timer has the operating modes such as the 16-bit timer, 16-bit event counter, warm-up counter,
16-bit pulse width modulation (PWM) output and 16-bit programmable pulse generation (PPG) modes.
9.3.1
8-Bit Timer Mode (TC3 and 4)
In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter
and the timer register j (TTREGj) value is detected, an INTTCj interrupt is generated and the up-counter is
cleared. After being cleared, the up-counter restarts counting.
Note 1: In the timer mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj and PPGj pins may output pulses.
Note 2: In the timer mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the
shift register configuration in the timer mode, the new value programmed in TTREGj is in effect immediately
after the programming. Therefore, if TTREGi is changed while the timer is running, an expected operation
may not be obtained.
Note 3: j = 3, 4
Table 9-4 Source Clock for TimerCounter 3, 4 (Internal Clock)
Source Clock
NORMAL1/2, IDLE1/2 mode
Resolution
Maximum Time Setting
DV7CK = 0
DV7CK = 1
SLOW1/2,
SLEEP1/2
mode
fc/211 [Hz]
fs/23 [Hz]
fs/23 [Hz]
128 µs
244.14 µs
32.6 ms
62.3 ms
fc/27
fc/27
–
8 µs
–
2.0 ms
–
fc/25
fc/25
–
2 µs
–
510 µs
–
fc/23
fc/23
–
500 ns
–
127.5 µs
–
fc = 16 MHz
fs = 32.768 kHz
fc = 16 MHz
fs = 32.768 kHz
Example :Setting the timer mode with source clock fc/27 Hz and generating an interrupt 80 µs later
(TimerCounter4, fc = 16.0 MHz)
(TTREG4), 0AH
: Sets the timer register (80 µs÷27/fc = 0AH).
(EIRH). 3
: Enables INTTC4 interrupt.
LD
(TC4CR), 00010000B
: Sets the operating clock to fc/27, and 8-bit timer mode.
LD
(TC4CR), 00011000B
: Starts TC4.
LD
DI
SET
EI
Page 85
9. 8-Bit TimerCounter (TC3, TC4)
9.1 Configuration
TMP86C420FG
TC4CR<TC4S>
Internal
Source Clock
1
Counter
TTREG4
?
2
3
n-1
n 0
1
2
n-1
n 0
1
2
0
n
Match detect
Counter clear
INTTC4 interrupt request
Counter clear
Match detect
Figure 9-2 8-Bit Timer Mode Timing Chart (TC4)
9.3.2
8-Bit Event Counter Mode (TC3, 4)
In the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj pin.
When a match between the up-counter and the TTREGj value is detected, an INTTCj interrupt is generated and
the up-counter is cleared. After being cleared, the up-counter restarts counting at the falling edge of the input
pulse to the TCj pin. Two machine cycles are required for the low- or high-level pulse input to the TCj pin.
Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/24
Hz in the SLOW1/2 or SLEEP1/2 mode.
Note 1: In the event counter mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj and PPGj pins may output
pulses.
Note 2: In the event counter mode, do not change the TTREGj setting while the timer is running. Since TTREGj is
not in the shift register configuration in the event counter mode, the new value programmed in TTREGj is in
effect immediately after the programming. Therefore, if TTREGi is changed while the timer is running, an
expected operation may not be obtained.
Note 3: j = 3, 4
TC4CR<TC4S>
TC4 pin input
0
Counter
TTREG4
?
1
2
n-1
n 0
1
2
n-1
n 0
1
2
0
n
Match detect
INTTC4 interrupt request
Counter
clear
Match detect
Counter
clear
Figure 9-3 8-Bit Event Counter Mode Timing Chart (TC4)
9.3.3
8-Bit Programmable Divider Output (PDO) Mode (TC3, 4)
This mode is used to generate a pulse with a 50% duty cycle from the PDOj pin.
In the PDO mode, the up-counter counts up using the internal clock. When a match between the up-counter
and the TTREGj value is detected, the logic level output from the PDOj pin is switched to the opposite state and
the up-counter is cleared. The INTTCj interrupt request is generated at the time. The logic state opposite to the
timer F/Fj logic level is output from the PDOj pin. An arbitrary value can be set to the timer F/Fj by
TCjCR<TFFj>. Upon reset, the timer F/Fj value is initialized to 0.
To use the programmable divider output, set the output latch of the I/O port to 1.
Page 86
TMP86C420FG
Example :Generating 1024 Hz pulse using TC4 (fc = 16.0 MHz)
Setting port
LD
(TTREG4), 3DH
: 1/1024÷27/fc÷2 = 3DH
LD
(TC4CR), 00010001B
: Sets the operating clock to fc/27, and 8-bit PDO mode.
LD
(TC4CR), 00011001B
: Starts TC4.
Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running.
Since TTREGj is not in the shift register configuration in the programmable divider output mode, the new
value programmed in TTREGj is in effect immediately after programming. Therefore, if TTREGi is changed
while the timer is running, an expected operation may not be obtained.
Note 2: When the timer is stopped during PDO output, the PDOj pin holds the output status when the timer is
stopped. To change the output status, program TCjCR<TFFj> after the timer is stopped. Do not change the
TCjCR<TFFj> setting upon stopping of the timer.
Example: Fixing the PDOj pin to the high level when the TimerCounter is stopped
CLR (TCjCR).3: Stops the timer.
CLR (TCjCR).7: Sets the PDOj pin to the high level.
Note 3: j = 3, 4
Page 87
Page 88
?
INTTC4 interrupt request
PDO4 pin
Timer F/F4
TTREG4
Counter
Internal
source clock
TC4CR<TFF4>
TC4CR<TC4S>
0
n
1
Match detect
2
n 0
1
Match detect
2
n 0
1
Match detect
2
n 0
1
Match detect
2
n 0
1
2
3
Set F/F
Held at the level when the timer
is stopped
0
Write of "1"
9.1 Configuration
9. 8-Bit TimerCounter (TC3, TC4)
TMP86C420FG
Figure 9-4 8-Bit PDO Mode Timing Chart (TC4)
TMP86C420FG
9.3.4
8-Bit Pulse Width Modulation (PWM) Output Mode (TC3, 4)
This mode is used to generate a pulse-width modulated (PWM) signals with up to 8 bits of resolution. The
up-counter counts up using the internal clock.
When a match between the up-counter and the PWREGj value is detected, the logic level output from the
timer F/Fj is switched to the opposite state. The counter continues counting. The logic level output from the
timer F/Fj is switched to the opposite state again by the up-counter overflow, and the counter is cleared. The
INTTCj interrupt request is generated at this time.
Since the initial value can be set to the timer F/Fj by TCjCR<TFFj>, positive and negative pulses can be generated. Upon reset, the timer F/Fj is cleared to 0.
(The logic level output from the PWMj pin is the opposite to the timer F/Fj logic level.)
Since PWREGj in the PWM mode is serially connected to the shift register, the value set to PWREGj can be
changed while the timer is running. The value set to PWREGj during a run of the timer is shifted by the
INTTCj interrupt request and loaded into PWREGj. While the timer is stopped, the value is shifted immediately after the programming of PWREGj. If executing the read instruction to PWREGj during PWM output,
the value in the shift register is read, but not the value set in PWREGj. Therefore, after writing to PWREGj, the
reading data of PWREGj is previous value until INTTCj is generated.
For the pin used for PWM output, the output latch of the I/O port must be set to 1.
Note 1: In the PWM mode, program the timer register PWREGj immediately after the INTTCj interrupt request is
generated (normally in the INTTCj interrupt service routine.) If the programming of PWREGj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of the pulse
different from the programmed value until the next INTTCj interrupt request is generated.
Note 2: When the timer is stopped during PWM output, the PWMj pin holds the output status when the timer is
stopped. To change the output status, program TCjCR<TFFj> after the timer is stopped. Do not change the
TCjCR<TFFj> upon stopping of the timer.
Example: Fixing the PWMj pin to the high level when the TimerCounter is stopped
CLR (TCjCR).3: Stops the timer.
CLR (TCjCR).7: Sets the PWMj pin to the high level.
Note 3: To enter the STOP mode during PWM output, stop the timer and then enter the STOP mode. If the STOP
mode is entered without stopping the timer when fc, fc/2 or fs is selected as the source clock, a pulse is output from the PWMj pin during the warm-up period time after exiting the STOP mode.
Note 4: j = 3, 4
Table 9-5 PWM Output Mode
Source Clock
NORMAL1/2, IDLE1/2 mode
Resolution
Repeated Cycle
DV7CK = 0
DV7CK = 1
SLOW1/2,
SLEEP1/2
mode
fc/211 [Hz]
fs/23 [Hz]
fs/23 [Hz]
128 µs
244.14 µs
32.8 ms
62.5 ms
fc/2
7
–
8 µs
–
2.05 ms
–
fc/2
5
–
2 µs
–
512 µs
–
fc/2
7
fc/2
5
fc = 16 MHz
fs = 32.768 kHz
fc = 16 MHz
fs = 32.768 kHz
fc/23
fc/23
–
500 ns
–
128 µs
–
fs
fs
fs
30.5 µs
30.5 µs
7.81 ms
7.81 ms
fc/2
fc/2
–
125 ns
–
32 µs
–
fc
fc
–
62.5 ns
–
16 µs
–
Page 89
Page 90
?
Shift registar
0
Shift
INTTC4 interrupt request
PWM4 pin
Timer F/F4
?
PWREG4
Counter
Internal
source clock
TC4CR<TFF4>
TC4CR<TC4S>
n
n
n
Match detect
1
n
n+1
Shift
FF
0
n
n
n+1
m
One cycle period
Write to PWREG4
Match detect
1
Shift
FF
0
m
m
m+1
Write to PWREG4
p
Match detect
m
1
Shift
FF
0
p
p
Match detect
1
p
9.1 Configuration
9. 8-Bit TimerCounter (TC3, TC4)
TMP86C420FG
Figure 9-5 8-Bit PWM Mode Timing Chart (TC4)
TMP86C420FG
9.3.5
16-Bit Timer Mode (TC3 and 4)
In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 3 and 4 are cascadable to form a 16-bit timer.
When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after the
timer is started by setting TC4CR<TC4S> to 1, an INTTC4 interrupt is generated and the up-counter is cleared.
After being cleared, the up-counter continues counting. Program the lower byte and upper byte in this order in
the timer register. (Programming only the upper or lower byte should not be attempted.)
Note 1: In the timer mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj, and PPGj pins may output a pulse.
Note 2: In the timer mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the
shift register configuration in the timer mode, the new value programmed in TTREGj is in effect immediately
after programming of TTREGj. Therefore, if TTREGj is changed while the timer is running, an expected
operation may not be obtained.
Note 3: j = 3, 4
Table 9-6 Source Clock for 16-Bit Timer Mode
Source Clock
Resolution
NORMAL1/2, IDLE1/2 mode
Maximum Time Setting
DV7CK = 0
DV7CK = 1
SLOW1/2,
SLEEP1/2
mode
fc/211
fs/23
fs/23
128 µs
244.14 µs
8.39 s
16 s
fc/27
fc/27
–
8 µs
–
524.3 ms
–
fc/25
fc/25
–
2 µs
–
131.1 ms
–
fc/23
fc/23
–
500 ns
–
32.8 ms
–
fc = 16 MHz
fs = 32.768 kHz
fc = 16 MHz
fs = 32.768 kHz
Example :Setting the timer mode with source clock fc/27 Hz, and generating an interrupt 300 ms later
(fc = 16.0 MHz)
(TTREG3), 927CH
: Sets the timer register (300 ms÷27/fc = 927CH).
(EIRH). 3
: Enables INTTC4 interrupt.
LD
(TC3CR), 13H
:Sets the operating clock to fc/27, and 16-bit timer mode
(lower byte).
LD
(TC4CR), 04H
: Sets the 16-bit timer mode (upper byte).
LD
(TC4CR), 0CH
: Starts the timer.
LDW
DI
SET
EI
TC4CR<TC4S>
Internal
source clock
0
Counter
TTREG3
(Lower byte)
TTREG4
(Upper byte)
?
?
INTTC4 interrupt request
1
2
3
mn-1 mn 0
1
2
mn-1 mn 0
1
n
m
Match
detect
Counter
clear
Match
detect
Counter
clear
Figure 9-6 16-Bit Timer Mode Timing Chart (TC3 and TC4)
Page 91
2
0
9. 8-Bit TimerCounter (TC3, TC4)
9.1 Configuration
9.3.6
TMP86C420FG
16-Bit Event Counter Mode (TC3 and 4)
In the event counter mode, the up-counter counts up at the falling edge to the TC3 pin. The TimerCounter 3
and 4 are cascadable to form a 16-bit event counter.
When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after
the timer is started by setting TC4CR<TC4S> to 1, an INTTC4 interrupt is generated and the up-counter is
cleared.
After being cleared, the up-counter restarts counting at the falling edge of the input pulse to the TC3 pin.
Two machine cycles are required for the low- or high-level pulse input to the TC3 pin.
Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/
2 in the SLOW1/2 or SLEEP1/2 mode. Program the lower byte (TTREG3), and upper byte (TTREG4) in this
order in the timer register. (Programming only the upper or lower byte should not be attempted.)
4
Note 1: In the event counter mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj and PPGj pins may output pulses.
Note 2: In the event counter mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in
the shift register configuration in the event counter mode, the new value programmed in TTREGj is in effect immediately after the programming. Therefore, if TTREGj is changed while the timer is running, an expected operation
may not be obtained.
Note 3: j = 3, 4
9.3.7
16-Bit Pulse Width Modulation (PWM) Output Mode (TC3 and 4)
This mode is used to generate a pulse-width modulated (PWM) signals with up to 16 bits of resolution. The
TimerCounter 3 and 4 are cascadable to form the 16-bit PWM signal generator.
The counter counts up using the internal clock or external clock.
When a match between the up-counter and the timer register (PWREG3, PWREG4) value is detected, the
logic level output from the timer F/F4 is switched to the opposite state. The counter continues counting. The
logic level output from the timer F/F4 is switched to the opposite state again by the counter overflow, and the
counter is cleared. The INTTC4 interrupt is generated at this time.
Two machine cycles are required for the high- or low-level pulse input to the TC3 pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/24 to in the SLOW1/2
or SLEEP1/2 mode.
Since the initial value can be set to the timer F/F4 by TC4CR<TFF4>, positive and negative pulses can be
generated. Upon reset, the timer F/F4 is cleared to 0.
(The logic level output from the PWM4 pin is the opposite to the timer F/F4 logic level.)
Since PWREG4 and 3 in the PWM mode are serially connected to the shift register, the values set to
PWREG4 and 3 can be changed while the timer is running. The values set to PWREG4 and 3 during a run of
the timer are shifted by the INTTCj interrupt request and loaded into PWREG4 and 3. While the timer is
stopped, the values are shifted immediately after the programming of PWREG4 and 3. Set the lower byte
(PWREG3) and upper byte (PWREG4) in this order to program PWREG4 and 3. (Programming only the lower
or upper byte of the register should not be attempted.)
If executing the read instruction to PWREG4 and 3 during PWM output, the values set in the shift register is
read, but not the values set in PWREG4 and 3. Therefore, after writing to the PWREG4 and 3, reading data of
PWREG4 and 3 is previous value until INTTC4 is generated.
For the pin used for PWM output, the output latch of the I/O port must be set to 1.
Note 1: In the PWM mode, program the timer register PWREG4 and 3 immediately after the INTTC4 interrupt
request is generated (normally in the INTTC4 interrupt service routine.) If the programming of PWREGj and
the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of
pulse different from the programmed value until the next INTTC4 interrupt request is generated.
Note 2: When the timer is stopped during PWM output, the PWM4 pin holds the output status when the timer is
stopped. To change the output status, program TC4CR<TFF4> after the timer is stopped. Do not program
TC4CR<TFF4> upon stopping of the timer.
Example: Fixing the PWM4 pin to the high level when the TimerCounter is stopped
Page 92
TMP86C420FG
CLR (TC4CR).3: Stops the timer.
CLR (TC4CR).7 : Sets the PWM4 pin to the high level.
Note 3: To enter the STOP mode, stop the timer and then enter the STOP mode. If the STOP mode is entered without stopping of the timer when fc, fc/2 or fs is selected as the source clock, a pulse is output from the PWM4
pin during the warm-up period time after exiting the STOP mode.
Table 9-7 16-Bit PWM Output Mode
Source Clock
NORMAL1/2, IDLE1/2 mode
Resolution
Repeated Cycle
DV7CK = 0
DV7CK = 1
SLOW1/2,
SLEEP1/2
mode
fc/211
fs/23 [Hz]
fs/23 [Hz]
128 µs
244.14 µs
8.39 s
16 s
fc/27
fc/27
–
8 µs
–
524.3 ms
–
fc/25
fc/25
–
2 µs
–
131.1 ms
–
fc/23
fc/23
–
500 ns
–
32.8 ms
–
fc = 16 MHz
fs = 32.768 kHz
fc = 16 MHz
fs = 32.768 kHz
fs
fs
fs
30.5 µs
30.5 µs
2s
2s
fc/2
fc/2
–
125 ns
–
8.2 ms
–
fc
fc
–
62.5 ns
–
4.1 ms
–
Example :Generating a pulse with 1-ms high-level width and a period of 32.768 ms (fc = 16.0 MHz)
Setting ports
LDW
(PWREG3), 07D0H
: Sets the pulse width.
LD
(TC3CR), 33H
: Sets the operating clock to fc/23, and 16-bit PWM output
mode (lower byte).
LD
(TC4CR), 056H
: Sets TFF4 to the initial value 0, and 16-bit PWM signal
generation mode (upper byte).
LD
(TC4CR), 05EH
: Starts the timer.
Page 93
Page 94
?
?
PWREG4
(Upper byte)
16-bit
shift register
0
a
Shift
INTTC4 interrupt request
PWM4 pin
Timer F/F4
?
PWREG3
(Lower byte)
Counter
Internal
source clock
TC4CR<TFF4>
TC4CR<TC4S>
an
n
an
Match detect
1
an
an+1
Shift
FFFF
0
an
an
an+1
m
b
One cycle period
Write to PWREG4
Write to PWREG3
Match detect
1
Shift
FFFF
0
bm
bm bm+1
p
c
Write to PWREG4
Write to PWREG3
Match detect
bm
1
Shift
FFFF
0
cp
Match detect
cp
1
cp
9.1 Configuration
9. 8-Bit TimerCounter (TC3, TC4)
TMP86C420FG
Figure 9-7 16-Bit PWM Mode Timing Chart (TC3 and TC4)
TMP86C420FG
9.3.8
16-Bit Programmable Pulse Generate (PPG) Output Mode (TC3 and 4)
This mode is used to generate pulses with up to 16-bits of resolution. The timer counter 3 and 4 are cascadable to enter the 16-bit PPG mode.
The counter counts up using the internal clock or external clock. When a match between the up-counter and
the timer register (PWREG3, PWREG4) value is detected, the logic level output from the timer F/F4 is
switched to the opposite state. The counter continues counting. The logic level output from the timer F/F4 is
switched to the opposite state again when a match between the up-counter and the timer register (TTREG3,
TTREG4) value is detected, and the counter is cleared. The INTTC4 interrupt is generated at this time.
Two machine cycles are required for the high- or low-level pulse input to the TC3 pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/24 to in the SLOW1/
2 or SLEEP1/2 mode.
Since the initial value can be set to the timer F/F4 by TC4CR<TFF4>, positive and negative pulses can be
generated. Upon reset, the timer F/F4 is cleared to 0.
(The logic level output from the PPG4 pin is the opposite to the timer F/F4.)
Set the lower byte and upper byte in this order to program the timer register. (TTREG3 → TTREG4,
PWREG3 → PWREG4) (Programming only the upper or lower byte should not be attempted.)
For PPG output, set the output latch of the I/O port to 1.
Example :Generating a pulse with 1-ms high-level width and a period of 16.385 ms (fc = 16.0 MHz)
Setting ports
LDW
(PWREG3), 07D0H
: Sets the pulse width.
LDW
(TTREG3), 8002H
: Sets the cycle period.
LD
(TC3CR), 33H
: Sets the operating clock to fc/23, and16-bit PPG mode
(lower byte).
LD
(TC4CR), 057H
: Sets TFF4 to the initial value 0, and 16-bit
PPG mode (upper byte).
LD
(TC4CR), 05FH
: Starts the timer.
Note 1: In the PPG mode, do not change the PWREGi and TTREGi settings while the timer is running. Since
PWREGi and TTREGi are not in the shift register configuration in the PPG mode, the new values programmed in PWREGi and TTREGi are in effect immediately after programming PWREGi and TTREGi.
Therefore, if PWREGi and TTREGi are changed while the timer is running, an expected operation may not
be obtained.
Note 2: When the timer is stopped during PPG output, the PPG4 pin holds the output status when the timer is
stopped. To change the output status, program TC4CR<TFF4> after the timer is stopped. Do not change
TC4CR<TFF4> upon stopping of the timer.
Example: Fixing the PPG4 pin to the high level when the TimerCounter is stopped
CLR (TC4CR).3: Stops the timer
CLR (TC4CR).7: Sets the PPG4 pin to the high level
Note 3: i = 3, 4
Page 95
Page 96
?
TTREG4
(Upper byte)
INTTC4 interrupt request
PPG4 pin
Timer F/F4
?
?
TTREG3
(Lower byte)
PWREG4
(Upper byte)
n
PWREG3
(Lower byte)
?
0
Counter
Internal
source clock
TC4CR<TFF4>
TC4CR<TC4S>
m
r
q
mn
Match detect
1
mn mn+1
Match detect
qr-1 qr 0
mn
Match detect
1
mn mn+1
Match detect
qr-1 qr 0
mn
Match detect
1
F/F clear
0
Held at the level when the timer
stops
mn mn+1
Write of "0"
9.1 Configuration
9. 8-Bit TimerCounter (TC3, TC4)
TMP86C420FG
Figure 9-8 16-Bit PPG Mode Timing Chart (TC3 and TC4)
TMP86C420FG
9.3.9
Warm-Up Counter Mode
In this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is
switched between the high-frequency and low-frequency. The timer counter 3 and 4 are cascadable to form a
16-bit TimerCounter. The warm-up counter mode has two types of mode; switching from the high-frequency to
low-frequency, and vice-versa.
Note 1: In the warm-up counter mode, fix TCiCR<TFFi> to 0. If not fixed, the PDOi, PWMi and PPGi pins may output
pulses.
Note 2: In the warm-up counter mode, only upper 8 bits of the timer register TTREG4 and 3 are used for match
detection and lower 8 bits are not used.
Note 3: i = 3, 4
9.3.9.1
Low-Frequency Warm-up Counter Mode
(NORMAL1 → NORMAL2 → SLOW2 → SLOW1)
In this mode, the warm-up period time from a stop of the low-frequency clock fs to oscillation stability
is obtained. Before starting the timer, set SYSCR2<XTEN> to 1 to oscillate the low-frequency clock.
When a match between the up-counter and the timer register (TTREG4, 3) value is detected after the timer
is started by setting TC4CR<TC4S> to 1, the counter is cleared by generating the INTTC4 interrupt
request. After stopping the timer in the INTTC4 interrupt service routine, set SYSCR2<SYSCK> to 1 to
switch the system clock from the high-frequency to low-frequency, and then clear of SYSCR2<XEN> to
0 to stop the high-frequency clock.
Table 9-8 Setting Time of Low-Frequency Warm-Up Counter Mode (fs = 32.768 kHz)
Minimum Time Setting
(TTREG4, 3 = 0100H)
Maximum Time Setting
(TTREG4, 3 = FF00H)
7.81 ms
1.99 s
Example :After checking low-frequency clock oscillation stability with TC4 and 3, switching to the SLOW1 mode
SET
(SYSCR2).6
: SYSCR2<XTEN> ← 1
LD
(TC3CR), 43H
: Sets TFF3=0, source clock fs, and 16-bit mode.
LD
(TC4CR), 05H
: Sets TFF4=0, and warm-up counter mode.
LD
(TTREG3), 8000H
: Sets the warm-up time.
(The warm-up time depends on the oscillator characteristic.)
: IMF ← 0
DI
SET
(EIRH). 3
: IMF ← 1
EI
SET
:
PINTTC4:
: Enables the INTTC4.
(TC4CR).3
: Starts TC4 and 3.
:
CLR
(TC4CR).3
: Stops TC4 and 3.
SET
(SYSCR2).5
: SYSCR2<SYSCK> ← 1
(Switches the system clock to the low-frequency clock.)
CLR
(SYSCR2).7
: SYSCR2<XEN> ← 0 (Stops the high-frequency clock.)
RETI
:
VINTTC4:
DW
:
PINTTC4
: INTTC4 vector table
Page 97
9. 8-Bit TimerCounter (TC3, TC4)
9.1 Configuration
TMP86C420FG
9.3.9.2
High-Frequency Warm-Up Counter Mode
(SLOW1 → SLOW2 → NORMAL2 → NORMAL1)
In this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation stability is obtained. Before starting the timer, set SYSCR2<XEN> to 1 to oscillate the high-frequency clock.
When a match between the up-counter and the timer register (TTREG4, 3) value is detected after the timer
is started by setting TC4CR<TC4S> to 1, the counter is cleared by generating the INTTC4 interrupt
request. After stopping the timer in the INTTC4 interrupt service routine, clear SYSCR2<SYSCK> to 0 to
switch the system clock from the low-frequency to high-frequency, and then SYSCR2<XTEN> to 0 to
stop the low-frequency clock.
Table 9-9 Setting Time in High-Frequency Warm-Up Counter Mode
Minimum time Setting
(TTREG4, 3 = 0100H)
Maximum time Setting
(TTREG4, 3 = FF00H)
16 µs
4.08 ms
Example :After checking high-frequency clock oscillation stability with TC4 and 3, switching to the NORMAL1 mode
SET
(SYSCR2).7
: SYSCR2<XEN> ← 1
LD
(TC3CR), 63H
: Sets TFF3=0, source clock fc, and 16-bit mode.
LD
(TC4CR), 05H
: Sets TFF4=0, and warm-up counter mode.
LD
(TTREG3), 0F800H
: Sets the warm-up time.
(The warm-up time depends on the oscillator characteristic.)
: IMF ← 0
DI
SET
(EIRH). 3
: IMF ← 1
EI
SET
:
PINTTC4:
: Enables the INTTC4.
(TC4CR).3
: Starts the TC4 and 3.
:
CLR
(TC4CR).3
: Stops the TC4 and 3.
CLR
(SYSCR2).5
: SYSCR2<SYSCK> ← 0
(Switches the system clock to the high-frequency clock.)
CLR
(SYSCR2).6
: SYSCR2<XTEN> ← 0
(Stops the low-frequency clock.)
RETI
VINTTC4:
:
:
DW
PINTTC4
: INTTC4 vector table
Page 98
TMP86C420FG
10. Synchronous Serial Interface (SIO)
The TMP86C420FG has a clocked-synchronous 8-bit serial interface. Serial interface has an 8-byte transmit and
receive data buffer that can automatically and continuously transfer up to 64 bits of data.
Serial interface is connected to outside peripherl devices via SO, SI, SCK port.
10.1 Configuration
SIO control / status register
SIOSR
SIOCR1
SIOCR2
CPU
Transmit and
receive data buffer
(8 bytes in DBR)
Buffer control
circuit
Control circuit
Shift register
Shift
clock
7
6
5
4
3
2
1
0
SO
Serial data output
8-bit transfer
4-bit transfer
SI
Serial data input
INTSIO interrupt request
Serial clock
SCK
Serial clock I/O
Figure 10-1 Serial Interface
Page 99
10. Synchronous Serial Interface (SIO)
10.2 Control
TMP86C420FG
10.2 Control
The serial interface is controlled by SIO control registers (SIOCR1/SIOCR2). The serial interface status can be
determined by reading SIO status register (SIOSR).
The transmit and receive data buffer is controlled by the SIOCR2<BUF>. The data buffer is assigned to address
0F90H to 0F97H for SIO in the DBR area, and can continuously transfer up to 8 words (bytes or nibbles) at one time.
When the specified number of words has been transferred, a buffer empty (in the transmit mode) or a buffer full (in
the receive mode or transmit/receive mode) interrupt (INTSIO) is generated.
When the internal clock is used as the serial clock in the 8-bit receive mode and the 8-bit transmit/receive mode, a
fixed interval wait can be applied to the serial clock for each word transferred. Four different wait times can be
selected with SIOCR2<WAIT>.
SIO Control Register 1
SIOCR1
7
6
(0F98H)
SIOS
SIOINH
SIOS
5
4
Continue / abort transfer
SIOM
2
1
SIOM
Indicate transfer start / stop
SIOINH
3
Transfer mode select
0
SCK
0:
Stop
1:
Start
(Initial value: 0000 0000)
0:
Continuously transfer
1:
Abort transfer (Automatically cleared after abort)
000:
8-bit transmit mode
010:
4-bit transmit mode
100:
8-bit transmit / receive mode
101:
8-bit receive mode
110:
4-bit receive mode
Write
only
Except the above: Reserved
NORMAL1/2, IDLE1/2 mode
SCK
Serial clock select
DV7CK = 0
DV7CK = 1
SLOW1/2
SLEEP1/2
mode
000
fc/213
fs/25
fs/25
001
fc/28
fc/28
-
010
fc/27
fc/27
-
011
fc/26
fc/26
-
100
fc/25
fc/25
-
101
fc/24
fc/24
-
110
Reserved
111
External clock ( Input from SCK pin )
Note 1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz]
Note 2: Set SIOS to "0" and SIOINH to "1" when setting the transfer mode or serial clock.
Note 3: SIOCR1 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc.
SIO Control Register 2
SIOCR2
(0F99H)
7
6
5
4
3
WAIT
Page 100
2
1
BUF
0
(Initial value: ***0 0000)
Write
only
TMP86C420FG
Always sets "00" except 8-bit transmit / receive mode.
WAIT
Wait control
Number of transfer words
(Buffer address in use)
BUF
00:
Tf = TD(Non wait)
01:
Tf = 2TD(Wait)
10:
Tf = 4TD(Wait)
11:
Tf = 8TD (Wait)
000:
1 word transfer
0F90H
001:
2 words transfer
0F90H ~ 0F91H
010:
3 words transfer
0F90H ~ 0F92H
011:
4 words transfer
0F90H ~ 0F93H
100:
5 words transfer
0F90H ~ 0F94H
101:
6 words transfer
0F90H ~ 0F95H
110:
7 words transfer
0F90H ~ 0F96H
111:
8 words transfer
0F90H ~ 0F97H
Write
only
Note 1: The lower 4 bits of each buffer are used during 4-bit transfers. Zeros (0) are stored to the upper 4bits when receiving.
Note 2: Transmitting starts at the lowest address. Received data are also stored starting from the lowest address to the highest
address. ( The first buffer address transmitted is 0F90H ).
Note 3: The value to be loaded to BUF is held after transfer is completed.
Note 4: SIOCR2 must be set when the serial interface is stopped (SIOF = 0).
Note 5: *: Don't care
Note 6: SIOCR2 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc.
SIO Status Register
SIOSR
7
6
(0F99H)
SIOF
SEF
SIOF
SEF
5
4
3
2
1
Serial transfer operating status monitor
0:
1:
Transfer terminated
Transfer in process
Shift operating status monitor
0:
1:
Shift operation terminated
Shift operation in process
0
Note 1: Tf; Frame time, TD; Data transfer time
Note 2: After SIOS is cleared to "0", SIOF is cleared to "0" at the termination of transfer or the setting of SIOINH to "1".
(output)
SCK output
TD
Tf
Figure 10-2 Frame time (Tf) and Data transfer time (TD)
10.3 Serial clock
10.3.1 Clock source
Internal clock or external clock for the source clock is selected by SIOCR1<SCK>.
Page 101
Read
only
10. Synchronous Serial Interface (SIO)
10.3 Serial clock
TMP86C420FG
10.3.1.1 Internal clock
Any of six frequencies can be selected. The serial clock is output to the outside on the SCK pin. The
SCK pin goes high when transfer starts.
When data writing (in the transmit mode) or reading (in the receive mode or the transmit/receive mode)
cannot keep up with the serial clock rate, there is a wait function that automatically stops the serial clock
and holds the next shift operation until the read/write processing is completed.
Table 10-1 Serial Clock Rate
NORMAL1/2, IDLE1/2 mode
DV7CK = 0
SLOW1/2,
SLEEP1/2 mode
DV7CK = 1
SCK
Clock
Baud Rate
Clock
Baud Rate
Clock
Baud Rate
000
fc/213
1.91 Kbps
fs/25
1024 bps
fs/25
1024 bps
001
fc/28
61.04 Kbps
fc/28
61.04 Kbps
-
-
010
fc/27
122.07 Kbps
fc/27
122.07 Kbps
-
-
011
fc/26
244.14 Kbps
fc/26
244.14 Kbps
-
-
100
fc/25
488.28 Kbps
fc/25
488.28 Kbps
-
-
101
fc/24
976.56 Kbps
fc/24
976.56 Kbps
-
-
110
-
-
-
-
-
-
111
External
External
External
External
External
External
Note: 1 Kbit = 1024 bit (fc = 16 MHz, fs = 32.768 kHz)
Automatically
wait function
SCK
pin (output)
SO
a0
pin (output)
Written transmit
data
a1
a2
a3
a
b0
b
b1
b2
b3
c0
c1
c
Figure 10-3 Automatic Wait Function (at 4-bit transmit mode)
10.3.1.2 External clock
An external clock connected to the SCK pin is used as the serial clock. In this case, output latch of this
port should be set to "1". To ensure shifting, a pulse width of at least 4 machine cycles is required. This
pulse is needed for the shift operation to execute certainly. Actually, there is necessary processing time for
interrupting, writing, and reading. The minimum pulse is determined by setting the mode and the program. Therfore, maximum transfer frequency will be 488.3K bit/sec (at fc=16MHz).
SCK
pin (Output)
tcyc = 4/fc (In the NORMAL1/2, IDLE1/2 modes)
4/fs (In the SLOW1/2, SLEEP1/2 modes)
tSCKL, tSCKH > 4tcyc
tSCKL tSCKH
Figure 10-4 External clock pulse width
Page 102
TMP86C420FG
10.3.2 Shift edge
The leading edge is used to transmit, and the trailing edge is used to receive.
10.3.2.1 Leading edge
Transmitted data are shifted on the leading edge of the serial clock (falling edge of the SCK pin input/
output).
10.3.2.2 Trailing edge
Received data are shifted on the trailing edge of the serial clock (rising edge of the SCK pin input/output).
SCK pin
SO pin
Bit 0
Bit 1
Bit 2
Bit 3
Shift register
3210
*321
**32
***3
Bit 2
Bit 3
(a) Leading edge
SCK pin
SI pin
Shift register
Bit 0
Bit 1
0***
****
10**
210*
3210
*; Don’t care
(b) Trailing edge
Figure 10-5 Shift edge
10.4 Number of bits to transfer
Either 4-bit or 8-bit serial transfer can be selected. When 4-bit serial transfer is selected, only the lower 4 bits of
the transmit/receive data buffer register are used. The upper 4 bits are cleared to “0” when receiving.
The data is transferred in sequence starting at the least significant bit (LSB).
10.5 Number of words to transfer
Up to 8 words consisting of 4 bits of data (4-bit serial transfer) or 8 bits (8-bit serial transfer) of data can be transferred continuously. The number of words to be transferred can be selected by SIOCR2<BUF>.
An INTSIO interrupt is generated when the specified number of words has been transferred. If the number of
words is to be changed during transfer, the serial interface must be stopped before making the change. The number of
words can be changed during automatic-wait operation of an internal clock. In this case, the serial interface is not
required to be stopped.
Page 103
10. Synchronous Serial Interface (SIO)
10.6 Transfer Mode
TMP86C420FG
SCK pin
SO pin
a0
a1
a2
a3
INTSIO interrupt
(a) 1 word transmit
SCK pin
SO pin
a0
a1
a2
a3
b0
b1
b2
b3
c0
c1
c2
c3
b3
c0
c1
c2
c3
INTSIO interrupt
(b) 3 words transmit
SCK pin
SI pin
a0
a1
a2
a3
b0
b1
b2
INTSIO interrupt
(c) 3 words receive
Figure 10-6 Number of words to transfer (Example: 1word = 4bit)
10.6 Transfer Mode
SIOCR1<SIOM> is used to select the transmit, receive, or transmit/receive mode.
10.6.1 4-bit and 8-bit transfer modes
In these modes, firstly set the SIO control register to the transmit mode, and then write first transmit data
(number of transfer words to be transferred) to the data buffer registers (DBR).
After the data are written, the transmission is started by setting SIOCR1<SIOS> to “1”. The data are then
output sequentially to the SO pin in synchronous with the serial clock, starting with the least significant bit
(LSB). As soon as the LSB has been output, the data are transferred from the data buffer register to the shift
register. When the final data bit has been transferred and the data buffer register is empty, an INTSIO (Buffer
empty) interrupt is generated to request the next transmitted data.
When the internal clock is used, the serial clock will stop and an automatic-wait will be initiated if the next
transmitted data are not loaded to the data buffer register by the time the number of data words specified with
the SIOCR2<BUF> has been transmitted. Writing even one word of data cancels the automatic-wait; therefore,
when transmitting two or more words, always write the next word before transmission of the previous word is
completed.
Note:Automatic waits are also canceled by writing to a DBR not being used as a transmit data buffer register; therefore, during SIO do not use such DBR for other applications. For example, when 3 words are transmitted, do
not use the DBR of the remained 5 words.
When an external clock is used, the data must be written to the data buffer register before shifting next data.
Thus, the transfer speed is determined by the maximum delay time from the generation of the interrupt request
to writing of the data to the data buffer register by the interrupt service program.
The transmission is ended by clearing SIOCR1<SIOS> to “0” or setting SIOCR1<SIOINH> to “1” in buffer
empty interrupt service program.
Page 104
TMP86C420FG
SIOCR1<SIOS> is cleared, the operation will end after all bits of words are transmitted.
That the transmission has ended can be determined from the status of SIOSR<SIOF> because SIOSR<SIOF>
is cleared to “0” when a transfer is completed.
When SIOCR1<SIOINH> is set, the transmission is immediately ended and SIOSR<SIOF> is cleared to
“0”.
When an external clock is used, it is also necessary to clear SIOCR1<SIOS> to “0” before shifting the next
data; If SIOCR1<SIOS> is not cleared before shift out, dummy data will be transmitted and the operation will
end.
If it is necessary to change the number of words, SIOCR1<SIOS> should be cleared to “0”, then
SIOCR2<BUF> must be rewritten after confirming that SIOSR<SIOF> has been cleared to “0”.
Clear SIOS
SIOCR1<SIOS>
SIOSR<SIOF>
SIOSR<SEF>
SCK pin
(Output)
SO pin
a0
a1
a2
a3
a4
a5
a6
a7
b0
b1
b2
b3
b4
b5
b6
b7
INTSIO interrupt
a
DBR
b
Write Write
(a)
(b)
Figure 10-7 Transfer Mode (Example: 8bit, 1word transfer, Internal clock)
Clear SIOS
SIOCR1<SIOS>
SIOSR<SIOF>
SIOSR<SEF>
SCK pin
(Input)
SO pin
a0
a1
a2
a3
a4
a5
a6
a7
b0
b1
b2
b3
b4
b5
b6
b7
INTSIO interrupt
DBR
a
b
Write Write
(a)
(b)
Figure 10-8 Transfer Mode (Example: 8bit, 1word transfer, External clock)
Page 105
10. Synchronous Serial Interface (SIO)
10.6 Transfer Mode
TMP86C420FG
SCK pin
SIOSR<SIOF>
SO pin
MSB of last word
tSODH = min 3.5/fc [s] ( In the NORMAL1/2, IDLE1/2 modes)
tSODH = min 3.5/fs [s] (In the SLOW1/2, SLEEP1/2 modes)
Figure 10-9 Transmiiied Data Hold Time at End of Transfer
10.6.2 4-bit and 8-bit receive modes
After setting the control registers to the receive mode, set SIOCR1<SIOS> to “1” to enable receiving. The
data are then transferred to the shift register via the SI pin in synchronous with the serial clock. When one word
of data has been received, it is transferred from the shift register to the data buffer register (DBR). When the
number of words specified with the SIOCR2<BUF> has been received, an INTSIO (Buffer full) interrupt is
generated to request that these data be read out. The data are then read from the data buffer registers by the
interrupt service program.
When the internal clock is used, and the previous data are not read from the data buffer register before the
next data are received, the serial clock will stop and an automatic-wait will be initiated until the data are read.
A wait will not be initiated if even one data word has been read.
Note:Waits are also canceled by reading a DBR not being used as a received data buffer register is read; therefore,
during SIO do not use such DBR for other applications.
When an external clock is used, the shift operation is synchronized with the external clock; therefore, the
previous data are read before the next data are transferred to the data buffer register. If the previous data have
not been read, the next data will not be transferred to the data buffer register and the receiving of any more data
will be canceled. When an external clock is used, the maximum transfer speed is determined by the delay
between the time when the interrupt request is generated and when the data received have been read.
The receiving is ended by clearing SIOCR1<SIOS> to “0” or setting SIOCR1<SIOINH> to “1” in buffer full
interrupt service program.
When SIOCR1<SIOS> is cleared, the current data are transferred to the buffer. After SIOCR1<SIOS>
cleared, the receiving is ended at the time that the final bit of the data has been received. That the receiving has
ended can be determined from the status of SIOSR<SIOF>. SIOSR<SIOF> is cleared to “0” when the receiving is ended. After confirmed the receiving termination, the final receiving data is read. When SIOCR1<SIOINH> is set, the receiving is immediately ended and SIOSR<SIOF> is cleared to “0”. (The received data is
ignored, and it is not required to be read out.)
If it is necessary to change the number of words in external clock operation, SIOCR1<SIOS> should be
cleared to “0” then SIOCR2<BUF> must be rewritten after confirming that SIOSR<SIOF> has been cleared to
“0”. If it is necessary to change the number of words in internal clock, during automatic-wait operation which
occurs after completion of data receiving, SIOCR2<BUF> must be rewritten before the received data is read
out.
Note:The buffer contents are lost when the transfer mode is switched. If it should become necessary to switch the
transfer mode, end receiving by clearing SIOCR1<SIOS> to “0”, read the last data and then switch the transfer mode.
Page 106
TMP86C420FG
Clear SIOS
SIOCR1<SIOS>
SIOSR<SIOF>
SIOSR<SEF>
SCK pin
(Output)
SI pin
a0
a1
a2
a3
a4
a5
a6
a7
b0
b1
b2
b3
b4
b5
b6
b7
INTSIO Interrupt
DBR
a
b
Read out
Read out
Figure 10-10 Receive Mode (Example: 8bit, 1word transfer, Internal clock)
10.6.3 8-bit transfer / receive mode
After setting the SIO control register to the 8-bit transmit/receive mode, write the data to be transmitted first
to the data buffer registers (DBR). After that, enable the transmit/receive by setting SIOCR1<SIOS> to “1”.
When transmitting, the data are output from the SO pin at leading edges of the serial clock. When receiving,
the data are input to the SI pin at the trailing edges of the serial clock. When the all receive is enabled, 8-bit
data are transferred from the shift register to the data buffer register. An INTSIO interrupt is generated when
the number of data words specified with the SIOCR2<BUF> has been transferred. Usually, read the receive
data from the buffer register in the interrupt service. The data buffer register is used for both transmitting and
receiving; therefore, always write the data to be transmitted after reading the all received data.
When the internal clock is used, a wait is initiated until the received data are read and the next transfer data
are written. A wait will not be initiated if even one transfer data word has been written.
When an external clock is used, the shift operation is synchronized with the external clock; therefore, it is
necessary to read the received data and write the data to be transmitted next before starting the next shift operation. When an external clock is used, the transfer speed is determined by the maximum delay between generation of an interrupt request and the received data are read and the data to be transmitted next are written.
The transmit/receive operation is ended by clearing SIOCR1<SIOS> to “0” or setting SIOCR1<SIOINH> to
“1” in INTSIO interrupt service program.
When SIOCR1<SIOS> is cleared, the current data are transferred to the buffer. After SIOCR1<SIOS>
cleared, the transmitting/receiving is ended at the time that the final bit of the data has been transmitted.
That the transmitting/receiving has ended can be determined from the status of SIOSR<SIOF>.
SIOSR<SIOF> is cleared to “0” when the transmitting/receiving is ended.
When SIOCR1<SIOINH> is set, the transmit/receive operation is immediately ended and SIOSR<SIOF> is
cleared to “0”.
If it is necessary to change the number of words in external clock operation, SIOCR1<SIOS> should be
cleared to “0”, then SIOCR2<BUF> must be rewritten after confirming that SIOSR<SIOF> has been cleared to
“0”.
If it is necessary to change the number of words in internal clock, during automatic-wait operation which
occurs after completion of transmit/receive operation, SIOCR2<BUF> must be rewritten before reading and
writing of the receive/transmit data.
Page 107
10. Synchronous Serial Interface (SIO)
10.6 Transfer Mode
TMP86C420FG
Note:The buffer contents are lost when the transfer mode is switched. If it should become necessary to switch the
transfer mode, end receiving by clearing SIOCR1<SIOS> to “0”, read the last data and then switch the transfer mode.
Clear SIOS
SIOCR1<SIOS>
SIOSR<SIOF>
SIOSR<SEF>
SCK pin
(output)
SO pin
a0
a1
a2
a3
a4
a5
a6
a7
b0
b1
b2
b3
b4
b5
b6
b7
SI pin
c0
c1
c2
c3
c4
c5
c6
c7
d0
d1
d2
d3
d4
d5
d6
d7
INTSIO interrupt
c
a
DBR
Write (a)
Read out (c)
b
Write (b)
d
Read out (d)
Figure 10-11 Transfer / Receive Mode (Example: 8bit, 1word transfer, Internal clock)
SCK pin
SIOSR<SIOF>
SO pin
Bit 6
Bit 7 of last word
tSODH = min 4/fc [s] ( In the NORMAL1/2, IDLE1/2 modes)
tSODH = min 4/fs [s] (In the SLOW1/2, SLEEP1/2 modes)
Figure 10-12 Transmitted Data Hold Time at End of Transfer / Receive
Page 108
TMP86C420FG
11. 8-Bit AD Converter (ADC)
The TMP86C420FG have a 8-bit successive approximation type AD converter.
11.1 Configuration
The circuit configuration of the 8-bit AD converter is shown in Figure 11-1.
It consists of control registers ADCCR1 and ADCCR2, converted value registers ADCDR1 and ADCDR2, a DA
converter, a sample-and-hold circuit, a comparator, and a successive comparison circuit.
DA converter
VAREF
VSS
R/2
AVDD
AIN0
Analog input
multiplexer
0
R
R/2
Reference
voltage
Sample hold
circuit
Y
8
to
n
Successive approximate circuit
Shift clock
S EN
AINDS
ADCCR1
IREFON
SAIN
INTADC interrupt
Control circuit
4
ADRS
AIN7
Analog
comparator
3
8
ACK
ADCCR2
AD converter control register 1,2
ADCDR1
ADBF
ADCDR2
AD conversion result register1,2
Figure 11-1 8-bit AD Converter (ADC)
Page 109
EOCF
11. 8-Bit AD Converter (ADC)
11.1 Configuration
TMP86C420FG
11.2 Control
The AD converter consists of the following four registers:
1. AD converter control register 1 (ADCCR1)
This register selects the analog channels in which to perform AD conversion and controls the AD converter as it starts operating.
2. AD converter control register 2 (ADCCR2)
This register selects the AD conversion time and controls the connection of the DA converter (ladder
resistor network).
3. AD converted value register (ADCDR1)
This register is used to store the digital value after being converted by the AD converter.
4. AD converted value register (ADCDR2)
This register monitors the operating status of the AD converter.
AD Converter Control Register 1
ADCCR1
(000EH)
7
6
5
4
ADRS
"0"
"1"
AINDS
3
2
1
SAIN
ADRS
AD conversion start
0:
1:
−
Start
AINDS
Analog input control
0:
1:
Analog input enable
Analog input disable
Analog input channel select
0000:
0001:
0010:
0011:
0100:
0101:
0110:
0111:
1000:
1001:
1010:
1011:
1100:
1101:
1110:
1111:
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SAIN
0
(Initial value: 0001 0000)
R/W
Note 1: Select analog input when AD converter stops (ADCDR2<ADBF> = “0”).
Note 2: When the analog input is all use disabling, the ADCCR1<AINDS> should be set to “1”.
Note 3: During conversion, do not perform output instruction to maintain a precision for all of the pins. And port near to analog
input, do not input intense signaling of change.
Note 4: The ADRS is automatically cleared to “0” after starting conversion.
Note 5: Do not set ADCCR1<ADRS> newly again during AD conversion. Before setting ADCCR1<ADRS> newly again, check
ADCDR2<EOCF> to see that the conversion is completed or wait until the interrupt signal (INTADC) is generated (e.g.,
interrupt handling routine).
Note 6: After STOP or SLOW/SLEEP mode are started, AD converter control register 1 (ADCCR1) is all initialized and no data
can be written in this register. Therefore, to use AD converter again, set the ADCCR1 newly after returning to NORMAL1
or NORMAL2 mode.
Note 7: Although ADCCR1<SAIN> is initialized to "Reserved value" after reset, set the suitable analog input channel when using
AD converter.
Note 8: Always set bit 5 in ADCCR1 to “1” and set bit 6 in ADCCR1 to “0”.
Page 110
TMP86C420FG
AD Converter Control Register 2
7
ADCCR2
(000FH)
6
IREFON
ACK
5
4
3
IREFON
“1”
2
1
0
ACK
“0”
(Initial value: **0* 000*)
DA converter (ladder resistor)
connection control
0:
1:
Connected only during AD conversion
Always connected
R/W
AD conversion time select
000:
001:
010:
011:
100:
101:
110:
111:
39/fc
Reserved
78/fc
156/fc
312/fc
624/fc
1248/fc
Reserved
R/W
Note 1: Always set bit 0 in ADCCR2 to “0” and set bit 4 in ADCCR2 to “1”.
Note 2: When a read instruction for ADCCR2, bit 6 to 7 in ADCCR2 read in as undefined data.
Note 3: After STOP or SLOW/SLEEP mode are started, AD converter control register 2 (ADCCR2) is all initialized and no data
can be written in this register. Therefore, to use AD converter again, set the ADCCR2 newly after returning to NORMAL1
or NORMAL2 mode.
Table 11-1 Conversion Time according to ACK Setting and Frequency
Condition
Conbersion
time‘
16MHz
8MHz
4 MHz
2 MHz
10MHz
5 MHz
2.5 MHz
39/fc
-
-
-
19.5 µs
-
-
15.6 µs
010
78/fc
-
-
19.5 µs
39.0 µs
-
15.6 µs
31.2 µs
011
156/fc
-
19.5 µs
39.0 µs
78.0 µs
15.6 µs
31.2 µs
62.4 µs
100
312/fc
19.5 µs
39.0 µs
78.0 µs
156.0 µs
31.2 µs
62.4 µs
124.8 µs
ACK
000
001
Reserved
101
624/fc
39.0 µs
78.0 µs
156.0 µs
-
62.4 µs
124.8 µs
-
110
1248/fc
78.0 µs
156.0 µs
-
-
124.8 µs
-
-
111
Reserved
Note 1: Settings for “−” in the above table are inhibited.
Note 2: Set conversion time by Analog Reference Voltage (VAREF) as follows.
-
VAREF = 4.5 to 5.5 V
(15.6 µs or more)
-
VAREF = 2.7 to 5.5 V
(31.2 µs or more)
-
VAREF = 1.8 to 5.5 V
(124.8 µs or more)
AD Conversion Result Register
ADCDR1
(0020H)
7
6
5
4
3
2
1
0
AD07
AD06
AD05
AD04
AD03
AD02
AD01
AD00
5
4
3
2
1
0
EOCF
ADBF
(Initial value: 0000 0000)
AD Conversion Result Register
ADCDR2
(0021H)
7
EOCF
ADBF
6
(Initial value: **00 ****)
AD conversion end flag
0: Before or during conversion
1: Conversion completed
AD conversion busy flag
0: During stop of AD conversion
1: During AD conversion
Note 1: The ADCDR2<EOCF> is cleared to “0” when reading the ADCDR1.
Therefore, the AD conversion result should be read to ADCDR2 more first than ADCDR1.
Note 2: ADCDR2<ADBF> is set to “1” when AD conversion starts and cleared to “0” when the AD conversion is finished. It
also is cleared upon entering STOP or SLOW mode.
Note 3: If a read instruction is executed for ADCDR2, read data of bits 7, 6 and 3 to 0 are unstable.
Page 111
Read
only
11. 8-Bit AD Converter (ADC)
11.3 Function
TMP86C420FG
11.3 Function
11.3.1 AD Conveter Operation
When ADCCR1<ADRS> is set to "1", AD conversion of the voltage at the analog input pin specified by
ADCCR1<SAIN> is thereby started.
After completion of the AD conversion, the conversion result is stored in AD converted value registers
(ADCDR1) and at the same time ADCDR2<EOCF> is set to “1”, the AD conversion finished interrupt
(INTADC) is generated.
ADCCR1<ADRS> is automatically cleared after AD conversion has started. Do not set ADCCR1<ADRS>
newly again (restart) during AD conversion. Before setting ADRS newly again, check ADCDR<EOCF> to see
that the conversion is completed or wait until the interrupt signal (INTADC) is generated (e.g., interrupt handling routine).
AD conversion start
AD conversion start
ADCCR1<ADRS>
ADCDR2<ADBF>
ADCDR1 status
Indeterminate
First conversion result
Second conversion result
EOCF cleared by reading
conversion result
ADCDR2<EOCF>
INTADC interrupt
Conversion
result read
Reading ADCDR1
Conversion
result read
Reading ADCDR2
Figure 11-2 AD Converter Operation
11.3.2 AD Converter Operation
1. Set up the AD converter control register 1 (ADCCR1) as follows:
• Choose the channel to AD convert using AD input channel select (SAIN).
• Specify analog input enable for analog input control (AINDS).
2. Set up the AD converter control register 2 (ADCCR2) as follows:
• Set the AD conversion time using AD conversion time (ACK). For details on how to set the conversion time, refer to Table 11-1.
• Choose IREFON for DA converter control.
3. After setting up 1. and 2. above, set AD conversion start (ADRS) of AD converter control register 1
(ADCCR1) to “1”.
4. After an elapse of the specified AD conversion time, the AD converted value is stored in AD converted value register 1 (ADCDR1) and the AD conversion finished flag (EOCF) of AD converted
value register 2 (ADCDR2) is set to “1”, upon which time AD conversion interrupt INTADC is generated.
5. EOCF is cleared to “0” by a read of the conversion result. However, if reconverted before a register
read, although EOCF is cleared the previous conversion result is retained until the next conversion is
completed.
Page 112
TMP86C420FG
Example :After selecting the conversion time of 19.5 µs at 16 MHz and the analog input channel AIN3 pin, perform AD
conversion once. After checking EOCF, read the converted value and store the 8-bit data in address 009FH on
RAM.
; AIN SELECT
:
:
:
:
; Before setting the AD converter register, set each port register suitably (For detail, see chapter of I/O port.)
LD
(ADCCR1), 00100011B
; Select AIN3
LD
(ADCCR2), 11011000B
; Select conversion time (312/fc) and operation mode
SET
(ADCCR1). 7
; ADRS = 1
TEST
(ADCDR2). 5
; EOCF = 1 ?
JRS
T, SLOOP
; AD CONVERT START
SLOOP:
; RESULT DATA READ
LD
A, (ADCDR1)
LD
(9FH), A
11.3.3 STOP and SLOW Mode during AD Conversion
When the STOP or SLOW mode is entered forcibly during AD conversion, the AD convert operation is suspended and the AD converter is initialized (ADCCR1 and ADCCR2 are initialized to initial value.). Also, the
conversion result is indeterminate. (Conversion results up to the previous operation are cleared, so be sure to
read the conversion results before entering STOP or SLOW mode.) When restored from STOP or SLOW
mode, AD conversion is not automatically restarted, so it is necessary to restart AD conversion. Note that since
the analog reference voltage is automatically disconnected, there is no possibility of current flowing into the
analog reference voltage.
Page 113
11. 8-Bit AD Converter (ADC)
11.3 Function
TMP86C420FG
11.3.4 Analog Input Voltage and AD Conversion Result
The analog input voltage is corresponded to the 8-bit digital value converted by the AD as shown in Figure
11-3.
AD conversion result
FFH
FEH
FDH
03H
02H
01H
×
0
1
2
3
253
254
Analog input voltage
255
256
VAREF
VSS
256
Figure 11-3 Analog Input Voltage and AD Conversion Result (typ.)
Page 114
TMP86C420FG
11.4 Precautions about AD Converter
11.4.1 Analog input pin voltage range
Make sure the analog input pins (AIN0 to AIN7) are used at voltages within VSS below VAREF. If any voltage outside this range is applied to one of the analog input pins, the converted value on that pin becomes uncertain. The other analog input pins also are affected by that.
11.4.2 Analog input shared pins
The analog input pins (AIN0 to AIN7) are shared with input/output ports. When using any of the analog
inputs to execute AD conversion, do not execute input/output instructions for all other ports. This is necessary
to prevent the accuracy of AD conversion from degrading. Not only these analog input shared pins, some other
pins may also be affected by noise arising from input/output to and from adjacent pins.
11.4.3 Noise countermeasure
The internal equivalent circuit of the analog input pins is shown in Figure 11-4. The higher the output impedance of the analog input source, more easily they are susceptible to noise. Therefore, make sure the output
impedance of the signal source in your design is 5 kΩ or less. Toshiba also recommends attaching a capacitor
external to the chip.
AINx
Allowable signal
source impedance
Internal resistance
5 kΩ (typ)
Analog comparator
Internal capacitance
C = 22 pF (typ.)
5 kΩ (max)
DA converter
Note) i = 7~0
Figure 11-4 Analog Input Equivalent Circuit and Example of Input Pin Processing
Page 115
11. 8-Bit AD Converter (ADC)
11.4 Precautions about AD Converter
TMP86C420FG
Page 116
TMP86C420FG
12. Key-on Wakeup (KWU)
In the TMP86C420FG, the STOP mode is released by not only P20(INT5/STOP) pin but also four (STOP2 to
STOP5) pins.
When the STOP mode is released by STOP2 to STOP5 pins, the STOP pin needs to be used.
In details, refer to the following section " 12.2 Control ".
12.1 Configuration
INT5
STOP
STOP mode
release signal
(1: Release)
STOP2
STOP3
STOP4
STOPCR
(0F9AH)
STOP5
STOP4
STOP3
STOP2
STOP5
Figure 12-1 Key-on Wakeup Circuit
12.2 Control
STOP2 to STOP5 pins can controlled by Key-on Wakeup Control Register (STOPCR). It can be configured as
enable/disable in 1-bit unit. When those pins are used for STOP mode release, configure corresponding I/O pins to
input mode by I/O port register beforehand.
Key-on Wakeup Control Register
STOPCR
7
6
5
4
(0F9AH)
STOP5
STOP4
STOP3
STOP2
3
2
1
0
(Initial value: 0000 ****)
STOP5
STOP mode released by STOP5
0:Disable
1:Enable
Write
only
STOP4
STOP mode released by STOP4
0:Disable
1:Enable
Write
only
STOP3
STOP mode released by STOP3
0:Disable
1:Enable
Write
only
STOP2
STOP mode released by STOP2
0:Disable
1:Enable
Write
only
12.3 Function
Stop mode can be entered by setting up the System Control Register (SYSCR1), and can be exited by detecting the
"L" level on STOP2 to STOP5 pins, which are enabled by STOPCR, for releasing STOP mode (Note1).
Page 117
12. Key-on Wakeup (KWU)
12.3 Function
TMP86C420FG
Also, each level of the STOP2 to STOP5 pins can be confirmed by reading corresponding I/O port data register,
check all STOP2 to STOP5 pins "H" that is enabled by STOPCR before the STOP mode is started (Note2,3).
Note 1: When the STOP mode released by the edge release mode (SYSCR1<RELM> = “0”), inhibit input from STOP2 to
STOP5 pins by Key-on Wakeup Control Register (STOPCR) or must be set "H" level into STOP2 to STOP5 pins
that are available input during STOP mode.
Note 2: When the STOP pin input is high or STOP2 to STOP5 pins input which is enabled by STOPCR is low, executing an
instruction which starts STOP mode will not place in STOP mode but instead will immediately start the release
sequence (Warm up).
Note 3: The input circuit of Key-on Wakeup input and Port input is separated, so each input voltage threshold value is different. Therefore, a value comes from port input before STOP mode start may be different from a value which is
detected by Key-on Wakeup input (Figure 12-2).
Note 4: STOP pin doesn’t have the control register such as STOPCR, so when STOP mode is released by STOP2 to
STOP5 pins, STOP pin also should be used as STOP mode release function.
Note 5: In STOP mode, Key-on Wakeup pin which is enabled as input mode (for releasing STOP mode) by Key-on
Wakeup Control Register (STOPCR) may generate the penetration current, so the said pin must be disabled AD
conversion input (analog voltage input).
Note 6: When the STOP mode is released by STOP2 to STOP5 pins, the level of STOP pin should hold "L" level (Figure
12-3).
External pin
Port input
Key-on wakeup
input
Figure 12-2 Key-on Wakeup Input and Port Input
b) In case of STOP2 to STOP5
a) STOP
STOP pin
STOP pin "L"
STOP mode
Release
STOP mode
STOP2 pin
STOP mode
Release
STOP mode
Figure 12-3 Priority of STOP pin and STOP2 to STOP5 pins
Table 12-1 Release level (edge) of STOP mode
Release level (edge)
Pin name
SYSCR1<RELM>="1"
(Note2)
SYSCR1<RELM>="0"
STOP
"H" level
Rising edge
STOP2
"L" level
Don’t use (Note1)
STOP3
"L" level
Don’t use (Note1)
STOP4
"L" level
Don’t use (Note1)
STOP5
"L" level
Don’t use (Note1)
Page 118
TMP86C420FG
13. LCD Driver
The TMP86C420FG has a driver and control circuit to directly drive the liquid crystal device (LCD). The pins to
be connected to LCD are as follows:
1. Segment output port 32 pins (SEG31 to SEG0)
2. Common output port4 pins (COM3 to COM0)
In addition, C0, C1, V1, V2, V3 pin are provided for the LCD driver’s booster circuit.
The devices that can be directly driven is selectable from LCD of the following drive methods:
1. 1/4 Duty (1/3 Bias) LCD
Max 128 Segments(8 segments × 16 digits)
2. 1/3 Duty (1/3 Bias) LCD
Max 96 Segments(8 segments × 12 digits)
3. 1/2 Duty (1/2 Bias) LCD
Max 64 Segments(8 segments × 8 digits)
4. Static LCD
Max 32 Segments(8 segments × 4 digits)
13.1 Configuration
LCDCR
7
6
EDSP BRES
5
4
VFSEL
3
2
1
DUTY
0
SLF
DBR
fc/217, fs/29
display data area
fc/216, fs/28
fc/215
fc/213
Timing
control
Duty
control
Display data select control
fc/213, fs/25
fc/211, fs/23
Blanking
control
fc/210, fs/22
fc/29
Constant voltage
booster circuit
C0 C1
V1 V2 V3
Display data buffer register
Common driver
COM0
to
Segment driver
COM3
SEG0
SEG31
Figure 13-1 LCD Driver
Note: The LCD driver incorporates a dedicated divider circuit. Therefore, the break function of a debugger (development
tool) will not stop LCD driver output.
Page 119
13. LCD Driver
13.2 Control
TMP86C420FG
13.2 Control
The LCD driver is controlled using the LCD control register (LCDCR). The LCD driver’s display is enabled using
the EDSP.
LCD Driver Control Register
LCDCR
(0028H)
7
6
EDSP
BRES
5
4
3
VFSEL
2
1
DUTY
0
SLF
(Initial value: 0000 0000)
EDSP
LCD Display Control
0: Blanking
1: Enables LCD display (Blanking is released)
BRES
Booster circuit control
0: Disable (use divider resistance)
1: Enable
NORMAL1/2, IDLE/1/2 mode
VFSEL
DUTY
Selection of boost frequency
Selection of driving methods
DV7CK = 0
DV7CK = 1
SLOW1/2,
SLEEP0/1/2 mode
00
fc/213
fs/25
fs/25
01
fc/211
fs/23
fs/23
10
fc/210
fs/22
fs/22
11
fc/29
fc/29
–
NORMAL1/2, IDLE/1/2 mode
SLF
R/W
00: 1/4 Duty (1/3 Bias)
01: 1/3 Duty (1/3 Bias)
10: 1/2 Duty (1/2 Bias)
11: Static
Selection of LCD frame frequency
DV7CK = 0
DV7CK = 1
SLOW1/2,
SLEEP0/1/2 mode
00
fc/217
fs/29
fs/29
01
fc/216
fs/28
fs/28
10
fc/215
fc/215
–
11
fc/213
fc/213
–
Note 1: When <BRES>(Booster circuit control) is set to “0”, VDD ≥ V3 ≥ V2 ≥ V1 ≥ VSS should be satisfied.
When <BRES> is set to “1”, 5.5 [V] ≥ V3 ≥ VDD should be satisfied.
If these conditions are not satisfied, it not only affects the quality of LCD display but also may damage the device due to
over voltage of the port.
Note 2: When used as the booster circuit, bias should be composed to 1/3. Therefore, do not set LCDCR<DUTY> to "10" or "11"
when the booster circuit is enable.
Note 3: Do not set SLF to “10” or “11” in SLOW1/2 modes.
Note 4: Do not set VFSEL to “11” SLOW1/2 modes.
Page 120
TMP86C420FG
13.2.1 LCD driving methods
As for LCD driving method, 4 types can be selected by LCDCR<DUTY>. The driving method is initialized
in the initial program according to the LCD used.
VLCD3
VLCD3
1/fF
1/fF
0
0
−VLCD3
Data "1"
Data "0"
−VLCD3
(a) 1/4 Duty (1/3 Bias)
VLCD3
Data "0"
(b) 1/3 Duty (1/3 Bias)
VLCD3
1/fF
Data "1"
1/fF
0
0
−VLCD3
−VLCD3
Data "1"
Data "0"
Data "1"
(d) Static
(c) 1/2 Duty (1/2 Bias)
Note 1: fF: Frame frequency
Note 2: VLCD3: LCD drive voltage
Figure 13-2 LCD Drive Waveform (COM-SEG pins)
Page 121
Data "0"
13. LCD Driver
13.2 Control
TMP86C420FG
13.2.2 Frame frequency
Frame frequency (fF) is set according to driving method and base frequency as shown in the following Table
13-1. The base frequency is selected by LCDCR<SLF> according to the frequency fc and fs of the basic clock
to be used.
Table 13-1 Setting of LCD Frame Frequency
(a) At the single clock mode. At the dual clock mode (DV7CK = 0).
Frame frequency [Hz]
SLF
Base frequency [Hz]
1/4 Duty
1/3 Duty
4 fc
--- • -------3 2 17
1/2 Duty
Static
4 fc
--- • -------2 2 17
fc
-------17
2
fc
-------17
2
fc
-------17
2
(fc = 16 MHz)
122
163
244
122
(fc = 8 MHz)
61
81
122
61
fc
-------16
2
fc
-------16
2
4 fc
--- • -------2 2 16
fc
-------16
2
(fc = 8 MHz)
122
163
244
122
(fc = 4 MHz)
61
81
122
61
fc
-------15
2
fc
-------15
2
4 fc
--- • -------2 2 15
fc
-------15
2
(fc = 4 MHz)
122
163
244
122
(fc = 2 MHz)
61
81
122
61
fc
-------13
2
fc
-------13
2
4 fc
--- • -------2 2 13
fc
-------13
2
(fc = 1 MHz)
122
244
122
00
4 fc
--- • -------3 2 16
01
4 fc
--- • -------3 2 15
10
11
4 fc
--- • -------3 2 13
163
Note: fc: High-frequency clock [Hz]
Table 13-2
(b) At the dual clock mode (DV7CK = 1 or SYSCK = 1)
Frame frequency [Hz]
SLF
00
01
Base frequency [Hz]
1/4 Duty
1/3 Duty
1/2 Duty
Static
fs
-----9
2
fs
-----9
2
4 fs
--- • -----3 29
4 fs
--- • -----2 29
fs
-----9
2
(fs = 32.768 kHz)
64
85
128
64
fs
-----8
2
fs
-----8
2
4 fs
--- • -----3 28
4 fs
--- • -----2 28
fs
-----8
2
(fs = 32.768 kHz)
128
171
256
128
Note: fs: Low-frequency clock [Hz]
Page 122
TMP86C420FG
13.2.3 Driving method for LCD driver
In the TMP86C420FG, LCD driving voltages can be generated using either an internal booster circuit or an
external resistor divider. This selection is made in LCDCR<BRES>.
13.2.3.1 When using the booster circuit (LCDCR<BRES>="1")
When the reference voltage is connected to the V1 pin, the booster circuit boosts the reference voltage
twofold (V2) or threefold (V3) to generate the output voltages for segment/common signals. When the
reference voltage is connected to the V2 pin, it is reduced to 1/2 (V1) or boosted to 3/2 (V3). When the
reference voltage is connected to the V3 pin, it is reduced to 1/3 (V1) or 2/3 (V2).
LCDCR<VFSEL> is used to select the reference frequency in the booster circuit. The faster the boosting frequency, the higher the segment/common drive capability, but power consumption is increased.
Conversely, the slower the boosting frequency, the lower the segment/common drive capability, but power
consumption is reduced. If the drive capability is insufficient, the LCD may not be displayed clearly.
Therefore, select an optimum boosting frequency for the LCD panel to be used.
Table 13-3 shows the V3 pin current capacity and boosting frequency.
Note: When used as the booster circuit, bias should be composed to 1/3. Therefore, do not set
LCDCR<DUTY> to "10" or "11" when the booster circuit is enable (LCDCR<BRES>="1").
Keep the following
condition.
VDD
V3
V2
V3
V1 = 1/3 x V3
C = 0.1 to 0.47 µF
V1
C
C
Reference voltage
C1
C0
C
VSS
a) Reference pin = V1
Keep the following
condition.
VDD
V3
V2
V3
V2 = 2/3 x V3
C = 0.1 to 0.47 µF
V1
C
C
C
Reference voltage
C1
C0
VSS
b) Reference pin = V2
Page 123
C
13. LCD Driver
13.2 Control
TMP86C420FG
Keep the following
condition.
VDD
V3
V2
V3
V1
C
C
Reference voltage
C
C
= 0.1 to 0.47 µF
C1
C0
C
VSS
c) Reference pin = V3
Keep the following
condition.
VDD
V3
V2
V3 =
V1
C
C
C
C
= 0.1 to 0.47 µF
C1
C0
C
VSS
d) Reference pin = V3
Note 1: When the TMP86C420FG uses the booster circuit to drive the LCD, the power supply and capacitor for the booster circuit
should be connected as shown above.
Note 2: When the reference voltage is connected to a pin other than V1, add a capacitor between V1 and GND.
Note 3: The connection examples shown above are different from those shown in the datasheets of the previous version. Since
the above connection method enhances the boosting characteristics, it is recommended that new boards be designed
using the above connection method. (Using the existing connection method does not affect LCD display.)
Figure 13-3 Connection Examples When Using the Booster Circuit (LCDCR<BRES> = “1”)
Table 13-3 V3 Pin Current Capacity and Boosting Frequency (typ.)
VFSEL
Boosting frequency
fc = 16 MHz
fc = 8 MHz
fc = 4 MHz
fc = 32.768 MHz
00
fc/213 or fs/25
−37 mV/ µA
−80 mV/ µA
−138 mV/ µA
−76 mV/ µA
01
fc/211 or fs/23
−19 mV/ µA
−24 mV/ µA
−37 mV/ µA
−23 mV/ µA
10
fc/210 or fs/22
−17 mV/ µA
−19 mV/ µA
−24 mV/ µA
−18 mV/ µA
11
fc/29
−16 mV/ µA
−17 mV/ µA
−19 mV/ µA
–
Note 1: The current capacity is the amount of voltage that falls per 1µA.
Note 2: The boosting frequency should be selected depending on your LCD panel.
Note 3: For the reference pin V1 or V2, a current capacity ten times larger than the above is recommended to ensure stable operation.
For example, when the boosting frequency is fc/29 (at fc = 8 MHz), −1.7 mV/ µA or more is recommended for the current
capacity of the reference pin V1.
13.2.3.2 When using an external resistor divider (LCDCR<BRES>="0")
When an external resistor divider is used, the voltage of an external power supply is divided and input
on V1, V2, and V3 to generate the output voltages for segment/common signals.
Page 124
TMP86C420FG
The smaller the external resistor value, the higher the segment/common drive capability, but power consumption is increased. Conversely, the larger the external resistor value, the lower the segment/common
drive capability, but power consumption is reduced. If the drive capability is insufficient, the LCD may
not be displayed clearly. Therefore, select an optimum resistor value for the LCD panel to be used.
Adjustment of
contrast
VDD
Adjustment of
contrast
VDD
V3
Adjustment of
contrast
VDD
V3
V3
R1
R1
V2
V2
C0
Open
C1
Open
R2
V2
C0
Open
C0
Open
C1
Open
C1
Open
V1
V1
V1
R2
R3
VSS
VSS
R1
VSS
1/2 Bias (R1 = R2)
1/3 Bias (R1 = R2 = R3)
Keep the following conditon.
VDD V3 V2 V1
Static
VSS
Figure 13-4 Connection Examples When Using an External Resistor Divider
(LCDCR<BRES> = “0”)
13.3 LCD Display Operation
13.3.1 Display data setting
Display data is stored to the display data area (assigned to address 0F80H to 0F8FH, 16bytes) in the DBR.
The display data which are stored in the display data area is automatically read out and sent to the LCD driver
by the hardware. The LCD driver generates the segment signal and common signal according to the display
data and driving method. Therefore, display patterns can be changed by only over writing the contents of display data area by the program. Table 13-5 shows the correspondence between the display data area and SEG/
COM pins.
LCD light when display data is “1” and turn off when “0”. According to the driving method of LCD, the
number of pixels which can be driven becomes different, and the number of bits in the display data area which
is used to store display data also becomes different.
Therefore, the bits which are not used to store display data as well as the data buffer which corresponds to the
addresses not connected to LCD can be used to store general user process data (see Table 13-4).
Note:The display data memory contents become unstable when the power supply is turned on; therefore, the display data memory should be initialized by an initiation routine.
Table 13-4 Driving Method and Bit for Display Data
Driving methods
Bit 7/3
Bit 6/2
Bit 5/1
Bit 4/0
1/4 Duty
COM3
COM2
COM1
COM0
1/3 Duty
–
COM2
COM1
COM0
1/2 Duty
–
–
COM1
COM0
Static
–
–
–
COM0
Page 125
13. LCD Driver
13.3 LCD Display Operation
TMP86C420FG
Note: –: This bit is not used for display data
Table 13-5 LCD Display Data Area (DBR)
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
COM1
COM0
0F80H
SEG1
SEG0
0F81H
SEG3
SEG2
0F82H
SEG5
SEG4
0F83H
SEG7
SEG6
0F84H
SEG9
SEG8
0F85H
SEG11
SEG10
0F86H
SEG13
SEG12
0F87H
SEG15
SEG14
0F88H
SEG17
SEG16
0F89H
SEG19
SEG18
0F8AH
SEG21
SEG20
0F8BH
SEG23
SEG22
0F8CH
SEG25
SEG24
0F8DH
SEG27
SEG26
0F8EH
SEG29
SEG28
0F8FH
SEG31
COM3
COM2
COM1
SEG30
COM0
COM3
COM2
13.3.2 Blanking
Blanking is enabled when EDSP is cleared to “0”.
Blanking turns off LCD through outputting a GND level to SEG/COM pin.
When in STOP mode, EDSP is cleared to “0” and automatically blanked. To redisplay ICD after exiting
STOP mode, it is necessary to set EDSP back to “1”.
Note:During reset, the LCD segment outputs and LCD common outputs are fixed “0” level. But the multiplex terminal of input/output port and LCD segment output becomes high impedance. Therefore, when the reset input is
long remarkably, ghost problem may appear in LCD display.
Page 126
TMP86C420FG
13.4 Control Method of LCD Driver
13.4.1 Initial setting
Figure 13-5 shows the flowchart of initialization.
Example : To operate a 1/4 duty LCD of 32 segments × 4 com-mons at frame frequency fc/216 [Hz], and booster frequency fc/213 [Hz]
LD
(LCDCR), 01000001B
; Sets LCD driving method and frame frequency. Boost frequency
LD
(P*LCR), 0FFH
; Sets segment output control register. (*; Port No.)
:
:
:
:
LD
; Sets the initial value of display data.
(LCDCR), 11000001B
; Display enable
Sets LCD driving method (DUTY).
Sets boost frequency (VFSEL).
Sets frame frequency (SLF).
Enables booster circuit (BRES)
Sets segment output control registers
(P*LCR (*; Port No.))
Initialization of display data area.
Display enable (EDSP)
(Releases from blanking.)
Figure 13-5 Initial Setting of LCD Driver
13.4.2 Store of display data
Generally, display data are prepared as fixed data in program memory (ROM) and stored in display data area
by load command.
Page 127
13. LCD Driver
13.4 Control Method of LCD Driver
TMP86C420FG
Example :To display using 1/4 duty LCD a numerical value which corresponds to the LCD data stored in data memory at address 80H (when pins COM and SEG are connected to LCD as in Figure 13-6), display data
become as shown in Table 13-6.
LD
A, (80H)
ADD
A, TABLE-$-7
LD
HL, 0F80H
LD
W, (PC + A)
LD
(HL), W
RET
TABLE:
DB
11011111B, 00000110B,
11100011B, 10100111B,
00110110B, 10110101B,
11110101B, 00010111B,
11110111B, 10110111B
Note:DB is a byte data difinition instruction.
COM0
COM1
COM2
COM3
SEG0
SEG1
Figure 13-6 Example of COM, SEG Pin Connection (1/4 Duty)
Table 13-6 Example of Display Data (1/4 Duty)
No.
display
Display data
No.
0
11011111
5
10110101
1
00000110
6
11110101
2
11100011
7
00000111
3
10100111
8
11110111
4
00110110
9
10110111
Page 128
display
Display data
TMP86C420FG
Example 2: Table 13-6 shows an example of display data which are displayed using 1/2 duty LCD in the
same way as Table 13-7. The connection between pins COM and SEG are the same as shown in Figure 13-7.
COM0
SEG3
SEG0
SEG2
COM1
SEG1
Figure 13-7 Example of COM, SEG Pin Connection
Table 13-7 Example of Display Data (1/2 Duty)
Display data
Display data
Number
Number
High order address
Low order address
High order address
Low order address
0
**01**11
**01**11
5
**11**10
**01**01
1
**00**10
**00**10
6
**11**11
**01**01
2
**10**01
**01**11
7
**01**10
**00**11
3
**10**10
**01**11
8
**11**11
**01**11
4
**11**10
**00**10
9
**11**10
**01**11
Note: *: Don’t care
Page 129
13. LCD Driver
13.4 Control Method of LCD Driver
TMP86C420FG
13.4.3 Example of LCD drive output
COM0
COM1
COM2
COM3
SEG0
SEG1
EDSP
VLCD3
SEG0
0
VLCD3
SEG1
0
Display data area
VLCD3
COM0
0
Address
0F80H 1011 0101
VLCD3
COM1
0
VLCD3
COM2
0
VLCD3
COM3
0
VLCD3
0
COM0-SEG0
(Selected)
−VLCD3
VLCD3
0
COM2-SEG1
(Non selected)
−VLCD3
Figure 13-8 1/4 Duty (1/3 bias) Drive
Page 130
TMP86C420FG
SEG1
SEG0
SEG2
COM0
COM1
COM2
EDSP
VLCD3
SEG0
0
Display data area
Address
VLCD3
SEG1
0
VLCD3
SEG2
0F80H
*111 *010
0F81H
**** *001
0
VLCD3
COM0
0
VLCD3
*: Don’t care
COM1
0
VLCD3
COM2
0
VLCD3
COM0-SEG1
(Selected)
0
−VLCD3
VLCD3
COM1-SEG2
(Non selected)
0
−VLCD3
Figure 13-9 1/3 Duty (1/3 bias) Drive
Page 131
13. LCD Driver
13.4 Control Method of LCD Driver
TMP86C420FG
COM0
SEG3
COM0
COM2
COM1
COM1
EDSP
VLCD3
SEG0
0
Display data area
Address
VLCD3
SEG1
0
VLCD3
SEG2
0F80H **01 **01
0F81H **11 **10
*: Don’t care
0
VLCD3
SEG3
0
VLCD3
COM0
0
VLCD3
COM1
0
VLCD3
0
COM0-SEG1
(Selected)
VLCD3
−VLCD3
0
−VLCD3
COM1-SEG2
(Non selected)
Figure 13-10 1/2 Duty (1/2 bias) Drive
Page 132
TMP86C420FG
SEG0
SEG1
SEG5
SEG6
SEG4
SEG2
SEG3
SEG7
COM0
Display data area
EDSP
Address
0F80H
***0 ***1
0F81H
***1 ***1
0F82H
***1 ***0
0F83H
***0 ***1
*: Don’t care
VLCD3
SEG0
0
VLCD3
SEG4
0
VLCD3
SEG7
0
VLCD3
COM0
0
VLCD3
COM0-SEG0
(Selected)
0
−VLCD3
VLCD3
COM0-SEG4
0
(Non selected)
−VLCD3
Figure 13-11 Static Drive
Page 133
13. LCD Driver
13.4 Control Method of LCD Driver
TMP86C420FG
Page 134
TMP86C420FG
14. Input/Output Circuitry
14.1 Control Pins
The input/output circuitries of the TMP86C420FG control pins are shown below.
Control Pin
I/O
Input/Output Circuitry
Remarks
Osc. enable
fc
VDD
XIN
XOUT
Resonator connecting pins
(high-frequency)
Rf = 1.2 MΩ (typ.)
VDD
Rf
Input
Output
RO
RO = 1.0 kΩ (typ.)
XIN
XOUT
XTEN
Osc. enable
XTIN
XTOUT
Input
Output
fs
VDD
VDD
Rf
RO
Resonator connecting pins
(Low-frequency)
Rf = 6 MΩ (typ.)
RO = 220 kΩ (typ.)
XTIN
XTOUT
VDD
RESET
Input
Output
RIN
R
Address trap reset
Sink open drain output
Hysteresis input
Pull-up resistor
RIN = 220 kΩ (typ.)
R = 1 kΩ (typ.)
Watchdog timer reset
System clock reset
VDD
TEST
Input
R
RIN
D1
Pull-down resistor
RIN = 70 kΩ (typ.)
R = 1 kΩ (typ.)
Note: The TEST pin of the TMP86P820 does not have a pull-down resistor and protect diode (D1). Fix the TEST pin at low-level
in MCU mode.
Page 135
14. Input/Output Circuitry
14.2 Input/Output Ports
TMP86C420FG
14.2 Input/Output Ports
Port
I/O
Input/Output Circuitry
Remarks
Initial "High-Z"
P1LCR
SEG output
P1
Sink open drain output
Hysteresis input
I/O
Data output
Input from output latch
Pin input
Initial "High-Z"
P5/P7LCR
SEG output
P5
P7
I/O
Sink open drain output
Data output
Input from output latch
Pin input
Initial "High-Z"
P2
I/O
VDD
Sink open drain output
Hysteresis input
Data output
Input from output latch
Pin input
Initial "High-Z"
VDD
Pch control
Data output
P3
I/O
Sink open drain or C-MOS output
Hysteresis input
High current output (Nch)
(Programable port option)
To output latch
Pin input
Initial "High-Z"
VDD
Data output
P6
Tri-state I/O
Hysteresis input
I/O
Disable
Pin input
Note: Port P1, P5 and P7 are sink open drain output. But they are also used as a segment output of LCD. Therefore, absolute
maximum ratings of port input voltage should be used in −0.3 to VDD + 0.3 volts.
Page 136
TMP86C420FG
15. Electrical Characteristics
15.1 Absolute Maximum Ratings
The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant.
Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down
or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when
designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded.
(VSS = 0 V)
Parameter
Symbol
Pins
Rating
Unit
Supply Voltage
VDD
−0.3 to 6.5
V
Input Voltage
VIN
−0.3 to VDD + 0.3
V
VOUT1
−0.3 to VDD + 0.3
V
Output Voltage
Output Current (Per 1 pin)
Output Current (Total)
IOUT1
P3, P6 Port
−1.8
IOUT2
P1, P2, P5, P6, P7 Port
3.2
IOUT3
P3 Port
30
Σ IOUT2
P1, P2, P5, P6, P7 Port
60
Σ IOUT3
P3 Port
80
Power Dissipation [Topr = 85°C]
PD
350
Soldering Temperature (Time)
Tsld
260 (10 s)
Storage Temperature
Tstg
−55 to 125
Operating Temperature
Topr
−40 to 85
Page 137
mA
mW
°C
15. Electrical Characteristics
15.1 Absolute Maximum Ratings
TMP86C420FG
15.2 Recommended Operating Condition
The recommended operating conditions for a device are operating conditions under which it can be guaranteed that
the device will operate as specified. If the device is used under operating conditions other than the recommended
operating conditions (supply voltage, operating temperature range, specified AC/DC values etc.), malfunction may
occur. Thus, when designing products which include this device, ensure that the recommended operating conditions
for the device are always adhered to.
(VSS = 0 V, Topr = −40 to 85°C)
Parameter
Symbol
Pins
Condition
fc = 16 MHz
fc = 8 MHz
Supply Voltage
VDD
NORMAL1, 2 mode
IDLE0, 1, 2 mode
NORMAL1, 2 mode
IDLE0, 1, 2 mode
fc = 4.2
MHz
NORMAL1, 2 mode
fs = 32.768
kHz
SLOW1, 2 mode
Min
Max
Unit
4.5
2.7
5.5
IDLE0, 1, 2 mode
1.8
SLEEP0, 1, 2 mode
V
STOP mode
Input High Level
VIH1
Except Hysteresis input
VIH2
Hysteresis input
VDD < 4.5 V
VIH3
Input Low Level
VDD ≥ 4.5 V
VIL1
Except Hysteresis input
VIL2
Hysteresis input
VDD ≥ 4.5 V
VDD × 0.70
VDD × 0.75
VDD × 0.90
VDD × 0.30
0
VDD = 1.8 V to 5.5 V
Clock Frequency
fc
XIN, XOUT
fs
XTIN, XTOUT
VDD = 2.7 V to 5.5 V
4.2
1.0
8.0
30.0
34.0
VDD = 4.5 V to 5.5 V
Page 138
VDD × 0.25
VDD × 0.10
VDD < 4.5 V
VIL3
VDD
MHz
16.0
kHz
TMP86C420FG
15.3 DC Characteristics
(VSS = 0 V, Topr = −40 to 85°C)
Parameter
Hysteresis Voltage
Input Current
Input Resistance
Output Leakage
Current
Symbol
Pins
Condition
Min
Typ.
Max
Unit
–
0.9
–
V
VDD = 5.5 V, VIN = 5.5 V/0 V
–
–
±2
µA
VHS
Hysteresis input
IIN1
TEST
IIN2
Sink Open Drain,
Tri-state Port
IIN3
RESET, STOP
RIN1
TEST Pull-Down
VDD = 5.5 V, VIN = 5.5 V
–
70
–
RIN2
RESET Pull-Up
VDD = 5.5 V, VIN = 0 V
100
220
450
Sink Open Drain,
Tri-state Port
VDD = 5.5 V, VOUT = 5.5 V/0 V
–
–
±2
4.1
–
–
ILO
Output High Voltage
VOH2
C-MOS, Tri-state Port
VDD = 4.5 V, IOH = −0.7 mA
Output Low Voltage
VOL
Except XOUT and P3
Port
VDD = 4.5 V, IOL = 1.6 mA
–
–
0.4
Output Low Current
IOL
High Current Port (P3
Port)
VDD = 4.5 V, VOL = 1.0 V
–
20
–
VDD = 5.5 V
–
7.5
9
–
5.5
6.5
–
18
42
–
16
25
–
12
20
–
0.5
10
Supply Current in
NORMAL1, 2 mode
VIN = 5.3 V/0.2 V
Supply Current in
IDLE0, 1, 2 mode
fc = 16 MHz
fs = 32.768 kHz
Supply Current in
SLOW1 mode
Supply Current in
SLEEP1 mode
IDD
Supply Current in
SLEEP0 mode
Supply Current in
STOP mode
kΩ
µA
V
mA
mA
VDD = 3.0 V
VIN = 2.8 V/0.2 V
fs = 32.768 kHz
VDD = 5.5 V
VIN = 5.3 V/0.2 V
µA
Note 1: Typical values show those at Topr = 25°C, VDD = 5 V
Note 2: Input current (IIN1, IIN3): The current through pull-up or pull-down resistor is not included.
Note 3: IDD does not include IREF current.
Note 4: The supply currents of SLOW2 and SLEEP2 modes are equivalent to IDLE0, 1, 2.
Page 139
15. Electrical Characteristics
15.3 DC Characteristics
TMP86C420FG
15.4 AD Conversion Characteristics
(VSS = 0.0 V, 4.5 V ≤ VDD ≤ 5.5 V, Topr = −40 to 85°C)
Parameter
Symbol
Analog Reference Voltage
VAREF
Power Supply Voltage of Analog Control
Circuit
AVDD
Condition
Min
Typ.
Max
AVDD − 1.5
–
AVDD
VDD
V
∆VAREF
3.0
–
–
Analog Input Voltage
VAIN
VSS
–
VAREF
Power Supply Current of Analog Reference
Voltage
IREF
–
0.6
1.0
Analog Reference Voltage Range (Note 4)
VDD = AVDD = VAREF = 5.5 V
VSS = 0.0 V
Non linearity Error
VDD = AVDD = 5.0 V
Zero Point Error
VSS = 0.0 V
Full Scale Error
Unit
VAREF = 5.0 V
Total Error
–
–
±1
–
–
±1
–
–
±1
–
–
±2
mA
LSB
(VSS = 0.0 V, 2.7 V ≤ VDD < 4.5 V, Topr = −40 to 85°C)
Parameter
Symbol
Analog Reference Voltage
VAREF
Power Supply Voltage of Analog Control
Circuit
AVDD
Condition
Min
Typ.
Max
AVDD − 1.5
–
AVDD
VDD
V
∆VAREF
2.5
–
–
Analog Input Voltage
VAIN
VSS
–
VAREF
Power Supply Current of Analog Reference
Voltage
IREF
–
0.5
0.8
–
–
±1
Analog Reference Voltage Range (Note 4)
VDD = AVDD = VAREF = 4.5 V
VSS = 0.0 V
Non linearity Error
VDD = AVDD = 2.7 V
Zero Point Error
VSS = 0.0 V
Full Scale Error
Unit
VAREF = 2.7 V
Total Error
–
–
±1
–
–
±1
–
–
±2
mA
LSB
(VSS = 0.0 V, 2.0 V ≤ VDD < 2.7 V, Topr = −40 to 85°C) (Note 5)
(VSS = 0.0 V, 1.8 V ≤ VDD < 2.0 V, Topr = −10 to 85°C) (Note 5)
Parameter
Symbol
Analog Reference Voltage
VAREF
Power Supply Voltage of Analog Control
Circuit
AVDD
Analog Reference Voltage Range (Note 4)
∆VAREF
Analog Input Voltage
VAIN
Power Supply Current of Analog Reference
Voltage
IREF
Condition
Zero Point Error
Typ.
Max
–
AVDD
Unit
VDD
1.8 V ≤ VDD < 2.0 V
1.8
–
–
2.0 V ≤ VDD < 2.7 V
2.0
–
–
VSS
–
VAREF
–
0.3
0.5
–
–
±2
VDD = AVDD = VAREF = 2.7 V
VSS = 0.0 V
Non linearity Error
Full Scale Error
Min
AVDD − 0.9
VDD = AVDD = 1.8 V
VSS = 0.0 V
VAREF = 1.8 V
Total Error
–
–
±2
–
–
±2
–
–
±4
V
mA
LSB
Note 1: The total error includes all errors except a quantization error, and is defined as maximum deviation from the ideal
conversion line.
Note 2: Conversion time is different in recommended value by power supply voltage.
About conversion time, refer to “8-bit AD Conveter”.
Note 3: Please use input voltage to AIN input Pin in limit of VAREF − VSS.
When voltage of range outside is input, conversion value becomes unsettled and gives affect to other channel
conversion value.
Page 140
TMP86C420FG
Note 4: Analog Reference Voltage Range: ∆VAREF = VAREF − VSS
Note 5: When AD is used with VDD < 2.7 V, the guaranteed temperature range varies with the operating voltage.
Note 6: The AVDD pin should be fixed on the VDD level even though AD convertor is not used.
Page 141
15. Electrical Characteristics
15.6 Timer Counter 1 input (ECIN) Characteristics
TMP86C420FG
15.5 AC Characteristics
(VSS = 0 V, VDD = 4.5 to 5.5 V, Topr = −40 to 85°C)
Parameter
Symbol
Condition
Min
Typ.
Max
0.25
–
4
117.6
–
133.3
For external clock operation
(XIN input)
fc = 16 MHz
–
31.25
–
ns
For external clock operation
(XTIN input)
fs = 32.768 kHz
–
15.26
–
µs
NORMAL1, 2 mode
Machine Cycle Time
tcy
IDLE1, 2 mode
µs
SLOW1, 2 mode
SLEEP1, 2 mode
High Level Clock Pulse Width
tWCH
Low Level Clock Pulse Width
tWCL
High Level Clock Pulse Width
tWCH
Low Level Clock Pulse Width
tWCL
Unit
(VSS = 0 V, VDD = 2.7 to 4.5 V, Topr = −40 to 85°C)
Parameter
Symbol
Condition
NORMAL1, 2 mode
Machine Cycle Time
tcy
IDLE1, 2 mode
tWCH
Low Level Clock Pulse Width
tWCL
High Level Clock Pulse Width
tWCH
Low Level Clock Pulse Width
tWCL
Typ.
Max
0.5
–
4
Unit
µs
SLOW1, 2 mode
117.6
–
133.3
For external clock operation
(XIN input)
fc = 8 MHz
–
62.5
–
ns
For external clock operation
(XTIN input)
fs = 32.768 kHz
–
15.26
–
µs
SLEEP1, 2 mode
High Level Clock Pulse Width
Min
(VSS = 0 V, VDD = 1.8 to 2.7 V, Topr = −40 to 85°C)
Parameter
Symbol
Condition
Min
Typ.
Max
0.95
–
4
117.6
–
133.3
For external clock operation
(XIN input)
fc = 4.2 MHz
–
119.05
–
ns
For external clock operation
(XTIN input)
fs = 32.768 kHz
–
15.26
–
µs
NORMAL1, 2 mode
Machine Cycle Time
tcy
IDLE1, 2 mode
µs
SLOW1, 2 mode
SLEEP1, 2 mode
High Level Clock Pulse Width
tWCH
Low Level Clock Pulse Width
tWCL
High Level Clock Pulse Width
tWCH
Low Level Clock Pulse Width
tWCL
Unit
15.6 Timer Counter 1 input (ECIN) Characteristics
(VSS = 0 V, Topr = −40 to 85°C)
Parameter
TC1 input (ECIN input)
Symbol
tTC1
Condition
Min
Typ.
Max
Frequency measurement mode
VDD = 4.5 to 5.5 V
Single edge
count
–
–
16
Frequency measurement mode
VDD = 2.7 to 4.5 V
Single edge
count
–
–
8
Frequency measurement mode
VDD = 1.8 to 2.7 V
Single edge
count
–
–
4.2
Page 142
Unit
MHz
TMP86C420FG
15.7 Recommended Oscillating Conditions
XIN
C1
XOUT
XTIN
C2
XTOUT
C1
(1) High-frequency Oscillation
C2
(2) Low-frequency Oscillation
Note 1: A quartz resonator can be used for high-frequency oscillation only when VDD is 2.7 V or above. If VDD is below 2.7
V, use a ceramic resonator.
Note 2: To ensure stable oscillation, the resonator position, load capacitance, etc. must be appropriate. Because these
factors are greatly affected by board patterns, please be sure to evaluate operation on the board on which the
device will actually be mounted.
Note 3: For the resonators to be used with Toshiba microcontrollers, we recommend ceramic resonators manufactured by
Murata Manufacturing Co., Ltd.
For details, please visit the website of Murata at the following URL:
http://www.murata.com
15.8 Handling Precaution
- The solderability test conditions for lead-free products (indicated by the suffix G in product name) are shown
below.
1. When using the Sn-37Pb solder bath
Solder bath temperature = 230 °C
Dipping time = 5 seconds
Number of times = once
R-type flux used
2. When using the Sn-3.0Ag-0.5Cu solder bath
Solder bath temperature = 245 °C
Dipping time = 5 seconds
Number of times = once
R-type flux used
Note: The pass criteron of the above test is as follows:
Solderability rate until forming ≥ 95 %
- When using the device (oscillator) in places exposed to high electric fields such as cathode-ray tubes, we
recommend electrically shielding the package in order to maintain normal operating condition.
Page 143
15. Electrical Characteristics
15.8 Handling Precaution
TMP86C420FG
Page 144
TMP86C420FG
16. Package Dimensions
QFP64-P-1414-0.80C Rev 01
+0.08
−0.04
Unit: mm
Page 145
16. Package Dimensions
TMP86C420FG
Page 146
This is a technical document that describes the operating functions and electrical specifications of the 8-bit
microcontroller series TLCS-870/C (LSI).
Toshiba provides a variety of development tools and basic software to enable efficient software
development.
These development tools have specifications that support advances in microcomputer hardware (LSI) and
can be used extensively. Both the hardware and software are supported continuously with version updates.
The recent advances in CMOS LSI production technology have been phenomenal and microcomputer
systems for LSI design are constantly being improved. The products described in this document may also
be revised in the future. Be sure to check the latest specifications before using.
Toshiba is developing highly integrated, high-performance microcomputers using advanced MOS
production technology and especially well proven CMOS technology.
We are prepared to meet the requests for custom packaging for a variety of application areas.
We are confident that our products can satisfy your application needs now and in the future.