STMICROELECTRONICS TDA7410ND

TDA7410ND
Signal processor for car radio applications
Features
■
Device Includes Audio Processor, Stereo
Decoder And Noiseblanker
■
No External Components Required
■
Fully Programmable Via I2C Bus
■
Softstep Volume and Bass
■
Low Distortion
■
Low Noise
■
SO20 Package
SO20
Description
TDA7410ND is a signal processor specifically
designed for car radio applications. The device
includes a complete audioprocessor and a stereo
decoder with noiseblanker, stereoblend and all
signal processing functions for car radio system.
Table 1.
Switched-capacitors design technique allows the
users to enjoy these features without external
components or adjustments. This means higher
quality and reliability as well as overall cost
saving.
The device is fully programmable by I2C bus
interface allowing customization of key device
parameters, especially filter characteristics..
Device summary
Part number
Package
Packing
TDA7410ND
SO20
Tube
TDA7410NDTR
SO20
Tape and reel
February 2007
Rev 2
1/34
www.st.com
1
Contents
TDA7410ND
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Pins description and connection diagram . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Audio Processor Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
6
2/34
4.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2
Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Description of the audioprocessor part . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1
Input matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.2
AutoZero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.3
Softstep Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.4
Bass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.5
DC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.6
Treble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.7
Speaker Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.8
Stereodecoder part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.9
Noise blanker part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Description of stereodecoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1
Input stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2
Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3
Deemphasis and highcut . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4
PLL and pilot tone detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.5
Fieldstrength control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.6
LEVEL input and gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.7
Stereoblend control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
TDA7410ND
6.8
7
8
Contents
Highcut Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Functional description of the noiseblanker . . . . . . . . . . . . . . . . . . . . . 22
7.1
Trigger path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.2
Automatic noise controlled threshold adjustment (ATC) . . . . . . . . . . . . . . 22
7.3
Automatic threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.4
Over deviation detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.5
Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
I2C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.1
Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.2
Reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3/34
List of tables
TDA7410ND
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
4/34
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pins list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Stereodecoder electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Noise blanker electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Receive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Transmission mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Subaddress (Receive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Source selector (0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Volume Control (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Speaker attenuation (2, 3, 4, 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Treble / Level gain (6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Stereodecoder adjustment (7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Noise blanker adjustment (8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Fieldstrength Control (9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Test (10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Bass (11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Softstep Control (12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
TDA7410ND
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Soft Step Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bass control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bass normal and DC mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Treble Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Vn timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trigger Threshold vs. VPEAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Deviation Controlled Trigger Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Fieldstrength Controlled Trigger Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Block diagram of the stereodecoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Internal stereoblend characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Relation between internal and external LEVEL voltage and setup of Stereoblend . . . . . . 21
Highcut characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Block diagram of the noiseblander . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SO20 Mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5/34
Block diagram
1
TDA7410ND
Block diagram
Figure 1.
Block diagram
CDL CDG CDR
5
AM
CASS_R
CASS_L
AUX_R
AUX_L
MPX
4
3
Mute
11
8
Mute
1
2
6
7
Volume
15
17 Out_LR
19 Out_LF
16
18 Out_RR
Out_RF
80kHz
LP
Demodulator
& Stereo Blend
& Stereo Adjust
Supply
14
Pilot Detector
20
CREF
25kHz
LP
Noise
Blanker
12
SCL
13
SDA
I2C Bus
Digital Control
9
OutLR
OutLF
OutRR
OutRF
Input
GND
6/34
Treble
Multiplexer
PLL &
VDD
Bass &
Loudness
S&H
Pulse
Generator
High Cut
Control
D
A
10
LEVEL
TDA7410ND
Pins description and connection diagram
2
Pins description and connection diagram
2.1
Connection diagram
Figure 2.
Connection diagram
CASS_R
1
20
CREF
CASS_L
2
19
OUT_LF
CDR
3
18
OUT_RF
CDG
4
17
OUT_LR
CDL
5
16
OUT_RR
AUX_R
6
15
VDD
AUX_L
7
14
GND
AM
8
13
SDA
MPX
9
12
SCL
10
11
MUTE
LEVEL
2.2
Pin description
Table 2.
Pins list
N°
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CASS_R
CASS_L
CDR
CDG
CDL
AUX_R
AUX_L
AM
MPX
LEVEL
MUTE
SCL
SDA
GND
VDD
OUT_RR
OUT_LR
OUT_RF
OUT_LF
CREF
Function
Cassette Input Right
Cassette Input Left
CD Right Channel Input
Ground reference CD
CD Left Channel Input
Aux Input Right
Aux Input Left Channel
AM input
FM Input (MPX)
Level Input Stereodecoder
Mute
I2C Clock Line
I2C Data Line
Supply Ground
Supply Voltage
Right Rear Speaker Output
Left Rear Speaker Output
Right Front Speaker Output
Left Front Speaker Output
Reference Capacitor Pin
Type
I
I
I
I
I
I
I
I
I
I
I
I
I/O
S
S
O
O
O
O
O
Pin Type:
I = input
O = Output
I/O = Input/Output
S = Supply
7/34
Audio Processor Part
3
Audio Processor Part
Input Multiplexer
●
Quasi-differential CD
●
Cassette stereo and Aux stereo input
●
AM mono and MPX
●
Input gain stage with auto zero function
Volume Control
●
1dB attenuator
●
Max. gain 32dB
●
Max. attenuation 79dB
●
Softstep function
Treble
●
2nd order frequency response
●
Fixed center frequency 12.5kHz
●
7x2dB steps
Bass Control
●
2nd order frequency response
●
Fixed center frequency 100Hz
●
DC gain programmable
●
7x 2dB steps
●
Softstep function
Speaker control
●
4 independent speaker controls (control range 50dB)
●
Speaker mute
Mute functions
8/34
●
Direct mute
●
Mute by I2C
TDA7410ND
TDA7410ND
Electrical Specification
4
Electrical Specification
4.1
Absolute maximum ratings
Table 3.
Absolute maximum ratings
Symbol
Parameter
Rth-j pins
Thermal resistance junction-pins
Operating supply voltage
VS
4.2
Value
Unit
85
°C/W
10.5
V
Tamb
Operating ambient temperature
-40 to 85
°C
Tstg
Storage temperature range
-55 to 150
°C
VESD
ESD protection (Human Body Model)
±2000
V
VESD
ESD protection (Machine Model)
±200
V
VESD
ESD protection (Change Device Model)
±750
V
Supply
Table 4.
Supply
Symbol
Parameter
VDD
Supply voltage
IDD
Supply current
Test Condition
VDD = 8.5V
Min
Typ
Max
Unit
7.5
8.5
10
V
15
20
25
mA
4.3
Electrical characteristics
Table 5.
Electrical characteristics
VS = 8.5V; Tamb= 25°C; RL= 10kΩ; all gains = 0dB; f = 1kHz; unless otherwise specified
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
70
100
130
kΩ
Input selector
Rin
Input resistance
VCL
Clipping level
All single ended inputs
CASS, CD, AUX input
AM, MPX input
2
VRMS
1.4
VRMS
GIN_MIN
Min. input gain
0
dB
GIN_MAX
Max. input gain
15
dB
GSTEP
Step resolution
1
dB
Differential stereo inputs
Rin
CMRR
Input resistance
Differential
70
100
Common mode rejection ratio
VCM=1 VRMS@ 1kHz
40
50
130
kΩ
dB
Volume control
9/34
Electrical Specification
Table 5.
TDA7410ND
Electrical characteristics (continued)
VS = 8.5V; Tamb= 25°C; RL= 10kΩ; all gains = 0dB; f = 1kHz; unless otherwise specified
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
GMAX
Max gain
AMAX
Max attenuation
-83
-79
-75
dB
ASTEP
Step resolution
-0.5
1
1.5
dB
EA
Attenuation set error
ET
Tracking error
VDC
DC steps
32
Unit
G = -20 to +15dB
G = -79 to -20dB
dB
0
-4
0
dB
3
dB
2
dB
Adjacent attenuation steps
0.1
3
mV
From 0dB to GMIN
0.5
5
mV
Hz
Bass control
Fc
CRANGE
Center frequency
fC
90
100
110
Q
1.3
1.5
1.7
±13
±14
±15
dB
1
2
3
dB
DC = off
-1
0
1
dB
DC = on
3.5
4.4
5.5
dB
±13
±14
±15
dB
1
2
3
dB
10
12.5
15
kHz
Control range
ASTEP
Step resolution
DCGAIN
Bass-DC-gain
Treble control
CRANGE
ASTEP
fc
Clipping level
Step resolution
Center frequency
fC1
Speaker attenuators
AMAX
Max Attenuation
-53
-50
-47
dB
ASTEP
Step Resolution
0.5
1
2
dB
1.8
2
Audio outputs
VCL
ROUT
Clipping level
Output impedance
RL
Output load resistance
CL
Output load capacitor
VDC
d = 0.3%
30
VRMS
100
2
kΩ
10
DC voltage level
Ω
4.0
nF
V
General
eNO
Output noise
BW=20Hz to 20 kHz all gain =
0dB
15
S/N
Signal to noise ratio
all gain = 0dB flat; Vo=2VRMS
100
D
Distortion
VIN=1VRMS; all stages 0dB
0.01
SC
Channel separation left/right
10/34
80
90
25
μV
dB
0.3
%
dB
TDA7410ND
Description of the audioprocessor part
5
Description of the audioprocessor part
5.1
Input matrix
The input matrix of the TDA7410ND offers several possibilities to adapt the audioprocessor
to the desired application (see Figure 1). Into the standard application we have:
●
CD quasi differential
●
Cassette stereo
●
Phone
●
AM mono
●
Stereodecoder input
Figure 3.
Input Stage
CD
100K
+
CDGND
100K
CASSETTE
100K
IN GAIN
PHONE
100K
AM
100K
STEREODECODER
MPX
100K
D05AU1613
5.2
AutoZero
In order to reduce the number of pins there is no AC coupling between the In-Gain and the
following stage, so that any offset generated by or before the In-Gain stage would be
transferred or even amplified to the output. To avoid that effect a special offset cancellation
stage called AutoZero is implemented. To avoid audible clicks the audioprocessor is muted
before the volume stage during this time. In some cases, for example if the P is executing a
refresh cycle of the I2C bus programming, it is not useful to start a new AutoZero action
because no new source is selected and an undesired mute would appear at the outputs. For
such applications the TDA7410D could be switched in the "Auto Zero Remain" mode (Bit 6
of the subaddress byte). If this bit is set to high, the DATABYTE 0 could be loaded without
invoking the AutoZero and the old adjustment value remains.
11/34
Description of the audioprocessor part
5.3
TDA7410ND
Softstep Volume
When volume level is changed often an audible click appears at the output. The root cause
of those clicks could be either a DC offset before the volume stage or the sudden change of
the envelope of the audio signal. With the Softstep feature both kinds of clicks could be
reduced to a minimum and are no more audible (see Figure 4).
Figure 4.
Soft Step Timing
VOUT
2dB
1dB
Time
10ms
-1dB
-2dB
D97AU635
5.4
Bass
The attenuation is programmable in the bass stage (see Figure 5):
Figure 5.
12/34
Bass control
TDA7410ND
5.5
Description of the audioprocessor part
DC Mode
In this mode the DC gain is increased by 4.4dB. In addition the programmed center
frequency and quality factor is decreased by 25% which can be used to reach alternative
center frequencies or quality factors. (see Figure 6):
Figure 6.
5.6
Bass normal and DC mode
Treble
The attenuation is programmable in the treble stage (see Figure 7):
Figure 7.
Treble Control
13/34
Description of the audioprocessor part
5.7
TDA7410ND
Speaker Attenuator
Due to practical aspects the steps in the speaker attenuators are not linear over the full
range. At attenuations more than 24dB the steps increase from 2dB to 8dB (please see data
byte specification).
5.8
Stereodecoder part
Table 6.
●
No External components necessary
●
PLL with adjustment fully integrated VCO
●
Automatic pilot dependent MONO/STEREO switching
●
Very high suppression of intermodulation and interference
●
Highcut and Stereoblend characteristics programmable in a wide range
●
Internal noiseblanker with threshold controls
●
I2C bus control of all necessary functions
Stereodecoder electrical characteristics
VDD = 8.5V, Deemphasis time const = 50µs, VMPX = 500mV, In Gain = 6dB, 75kHz
deviation, f = 1kHz, Tamb =25°C, unless otherwise spificied
Symbol
Parameter
VIN
MPX input level
Rin
Test Condition
Min.
Max.
Unit
0.5
VRMS
Input resistance
100
kΩ
Gain
Minimum input gain
3.5
dB
Gmax
Maximum input gain
11
dB
GSTEP
Step resolution
2.5
dB
Max. channel separation
40
dB
a
Input gain = 3.5dB
Typ.
Mono/stereo switch
VPTHST1
VPTHST0
VPTHMO1
Pilot threshold voltage
VPTHMO0
For stereo, PTH=1
10
15
25
mV
For stereo, PTH=0
15
25
35
mV
For mono, PTH=1
7
12
17
mV
For mono, PTH=0
10
19
25
mV
PLL
Δf/f
Capture Range
0.5
%
Stereodecoder-Byte
D5=0 VLEVEL >> VHCH
50
μs
τHC75
Stereodecoder-Byte
D5=1 VLEVEL >> VHCH
75
μs
τHC50
Stereodecoder-Byte
D5=0 VLEVEL >> VHCH
150
μs
Stereodecoder-Byte
D5=1 VLEVEL >> VHCH
225
μs
Deemphass and highcut
τHC50
Deemphasis time constant
Highcut time constant
τHC75
14/34
TDA7410ND
Table 6.
Description of the audioprocessor part
Stereodecoder electrical characteristics (continued)
VDD = 8.5V, Deemphasis time const = 50µs, VMPX = 500mV, In Gain = 6dB, 75kHz
deviation, f = 1kHz, Tamb =25°C, unless otherwise spificied
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Stereoblend and highcut control
REF5V
Internal reference voltage
5
V
LGmin
Min. level gain
0
dB
LGmax
Max. level gain
10
dB
LGstep
Level gain step resolution
0.67
dB
VSBLmin
Min. voltage for mono
33
%REF5V
VSBLmax
Max. voltage for mono
58
%REF5V
VSBLstep
Step resolution
8.4
%REF5V
Roll off compensation
2.5
dB
VHCHmin
Min. voltage for no highcut
42
%REF5V
VHCHmax
Max. voltage for no highcut
66
%REF5V
VHCHstep
Step resolution
8.4
%REF5V
VHCLmin
Min. voltage for full highcut
17
%VHCH
VHCLmax
Max. voltage for full highcut
33
%VHCH
Groll
Carrier and harmonic suppression at the output
α19
Pilot signal
f = 19kHz
40
dB
α39
Subcarrier
f = 38kHz
65
dB
α57
Subcarrier
f = 57kHz
55
dB
α76
Subcarrier
f = 76kHz
80
dB
ACI - Adjacent channel interference
α114
Signal
f = 114kHz
80
dB
α190
Signal
f = 190kHz
70
dB
15/34
Description of the audioprocessor part
5.9
TDA7410ND
Noise blanker part
Table 7.
Symbol
VTH
VTRNOISE
VRECT
VRECT DEV
VRECT FS
●
Internal highpass filter
●
Programmable trigger threshold
●
Additional circuit for trigger adjustment (deviation, field-strength)
●
Very low offset current during hold time
●
Selectable pulse suppression times
Noise blanker electrical characteristics
Parameter
Trigger threshold(1),(2)
Noise controlled trigger
threshold(3)
Rectifier voltage
deviation dependent
rectifier voltage(4)
Fieldstrength Controlled
Rectifier Voltage(5)
Test Condition
Min.
Max.
Unit
NBT=111
30
mVOP
NBT=110
35
mVOP
NBT=101
40
mVOP
NBT=100
45
mVOP
NBT=011
50
mVOP
NBT=010
55
mVOP
NBT=001
60
mVOP
NBT=000
65
mVOP
NCT=00
260
mVOP
NCT=01
220
mVOP
NCT=10
180
mVOP
NCT=11
140
mVOP
VMPX = 0mV
0.9
V
VMPX = 50mV; f = 150kHz
1.7
V
VMPX = 100mV; f = 150kHz
2.5
V
OVD=11
0.9(off)
VOP
OVD=10
1.2
VOP
OVD=01
2.0
VOP
OVD=00
2.8
VOP
FSC=11
0.9(off)
V
FSC=10
1.3
V
FSC=01
1.8
V
FSC=00
2.3
V
means. with
VPEAK=0.9V
means. with
VPEAK=1.5V
means. with
VMPX=800mV
(75kHz dev.)
means. with
VMPX=0mV
VLEVEL<<VSBL
(fully mono)
1. All thresholds are measured using a pulse with TR = 2 ms, THIGH = 2 ms and TF = 10ms
2. NBT represents the Noiseblanker-Byte D2~D0 for the noise blanker trigger threshold
3. NAT represents the Noiseblanker-Byte D4~D3 for the noise controlled trigger adjustment
4. OVD represents the Noiseblanker-Byte D7~D6 for the over deviation detector
5. FSC represents the Fieldstrength-Byte D1~D0 for the fieldstrength control
16/34
Typ.
TDA7410ND
Figure 8.
Description of the audioprocessor part
Vn timing diagram
VIN
VOP
DC
TR
D97AU636
Figure 9.
THIGH
Time
TF
Trigger Threshold vs. VPEAK
VTH
260mV(00)
220mV(01)
180mV(10)
140mV(11)
MIN. TRIG. THRESHOLD
NOISE CONTROLLED
TRIG. THRESHOLD
65mV
8 STEPS
30mV
0.9V
1.5V
D97AU648
VPEAK(V)
Figure 10. Deviation Controlled Trigger Adjustment
VPEAK
(VOP)
00
01
2.8
2.0
10
1.2
0.9
D97AU649
DETECTOR OFF (11)
20
32.5
45
75
DEVIATION(KHz)
17/34
Description of the audioprocessor part
TDA7410ND
Figure 11. Fieldstrength Controlled Trigger Adjustment
VPEAK
MONO
STEREO
»3V
2.3V(00)
1.8V(01)
1.3V(10)
NOISE
noisy signal
18/34
0.9V
ATC_SB OFF (11)
D98AU863
good signal
E'
TDA7410ND
6
Description of stereodecoder
Description of stereodecoder
The stereodecoder part of the TDA7410ND (see Figure 12) contains all functions necessary
to demodulate the MPX signal like pilot tone dependent MONO/STEREO switching as well
as "stereoblend" and "highcut" functions. Adaptations like programmable input gain,
selectable deemphasis time constant and a programmable fieldstrength input allow to use
different IF devices.
Figure 12. Block diagram of the stereodecoder
DEMODULATOR
MPX
INGAIN
INFILTER
3.5 ... 11dB
STEP 2.5dB
LP 80KHz
4.th ORDER
DEEMPHASIS
+ HIGHCUT
- PLOT CANC
- ROLL-OFF COMP.
- LP 25KHz
t=50 or 75μs
FM_L
FM_R
100K
PLL +
PILOT-DET.
F19
SB CONTROL
REF 5V
VSBL
HC
CONTROL
D
F38
A
VHCCH
VHCCL
STEREO
LEVEL INPUT
NOISE BLANKER
HOLDN
D05AU1614
6.1
LEVEL INTERN
LP 2.2KHZ
1.th ORDER
GAIN 0..10dB
LEVEL
Input stages
The Ingain stage allows to adjust the MPX signal to a magnitude of about 1Vrms internally
which is the recommended value. The 4th order input filter has a corner frequency of 80kHz
and is used to attenuate spikes and noise and acts as an antialiasing filter for the following
switch capacitor filters.
6.2
Demodulator
In the demodulator block the left and the right channel are separated from the MPX signal.
In this stage also the 19kHz pilot tone is cancelled.
6.3
Deemphasis and highcut
The lowpass filter for the deemphasis allows to choose between a time constant of 50μs and
75μs (bit D5, Stereodecoder Adjustment byte).
The highcut control range will be in both cases tHC = 2·tDeemp. Inside the highcut control
range (between VHCH and VHCL) the LEVEL signal is converted into a 5 bit word which
controls the lowpass time constant between tDeemp...3·tDeemp. There by the resolution will
remain always 5 bits independently of the absolute voltage range between the VHCH and
VHCL values. The highcut function can be switched off by I2C bus (bit D7, Fieldstrength
Control byte set to "0").
19/34
Description of stereodecoder
6.4
TDA7410ND
PLL and pilot tone detector
The PLL has the task to lock on the 19kHz pilotone during a stereo transmission to allow a
correct demodulation. The included detector enables the demodulation if the pilot tone
reaches the selected pilottone threshold VPTHST. Two different thresholds are available.
The detector output (signal STEREO, see block diagram) can be checked by reading the
status byte of the TDA7410ND via I2C bus.
6.5
Fieldstrength control
The fieldstrength input is used to control the highcut and the stereoblend function. In
addition the signal can be also used to control the noiseblanker thresholds.
6.6
LEVEL input and gain
To suppress undesired high frequency modulation on the highcut and stereoblend function
the LEVEL signal is lowpass filtered firstly. The filter is a combination of a 1st order RC
lowpass at 53kHz (working as anti-aliasing filter) and a 1st order switched capacitor lowpass
at 2.2kHz. The second stage is a programmable gain stage to adapt the LEVEL signal
internally to different IF. The gain is widely programmable in 16 steps from 0dB to 10dB
(step = 0.67dB).
6.7
Stereoblend control
The stereoblend control block converts the internal LEVEL voltage (LEVEL INTERN) into an
demodulator
compatible analog signal which is used to control the channel separation between 0dB and
the maximum separation. Internally this control range has a fixed upper limit which is the
internal reference voltage REF5V. The lower limit can be programmed to be 33%, 42%, 50%
or 58% of REF5V (see Figure 13, 14).
Figure 13. Internal stereoblend characteristics
0
-5
-10
-15
-20
CS [dB] -25
-30
-35
-40
-45
-50
0
1
2
3
LEVELINTERN [V]
20/34
4
5
TDA7410ND
Description of stereodecoder
To adjust the external LEVEL voltage to the internal range two values must be defined: the
LEVEL gain LG and VSBL. To adjust the voltage where the full channel separation is
reached (VST) the LEVEL gain LG has to be defined. The following equation can be used to
estimate the gain:
REF5V
L G = ---------------------------------------------------------------------------------------------Field strength voltage [ STEREO ]
The gain can be programmed through 4 bits in the "Level Gain" byte. The MONO voltage
VMO (0dB channel separation) can be choosen selecting 33, 42, 50 or 58% of REF5V.
Figure 14. Relation between internal and external LEVEL voltage and setup of Stereoblend
INTERNAL
VOLTAGES
INTERNAL
VOLTAGES
SETUP OF VST
SETUP OF VMO
LEVEL INTERN
REF 5V
REF 5V
LEVEL
VSBL
VSBL
VMO
6.8
LEVEL INTERN
VST
58%
50%
42%
33%
t
FIELDSTRENGHT VOLTAGE
D97AU639
VMO
VST
t
FIELDSTRENGHT VOLTAGE
Highcut Control
The highcut control setup is similar to the stereoblend control setup : the starting point
VHCH can be set with 2 bits to be 42, 50, 58 or 66% of REF5V whereas the range can be
set to be 17 or 33% of VHCH (see Figure 15).
Figure 15. Highcut characteristics
LOWPASS
TIME CONSTANT
3•τDeemp
τDeemp
VHCL
VHCH
FIELDSTRENGHT
D97AU640
21/34
Functional description of the noiseblanker
7
TDA7410ND
Functional description of the noiseblanker
In the automotive environment the MPX signal is disturbed by spikes produced by the
ignition and for example the wiper motor. The aim of the noiseblanker part is to cancel the
audible influence of the spikes. Therefore the output of the stereodecoder is held at the
actual voltage for 40μs. In a first stage the spikes must be detected but to avoid a wrong
triggering on high frequency (white) noise a complex trigger control is implemented. Behind
the triggerstage a pulse former generates the "blanking" pulse. To avoid any crosstalk to the
signal path the noiseblanker is supplied by its own biasing circuit.
7.1
Trigger path
The incoming MPX signal is highpass filtered, amplified and rectified. This second order
highpass-filter has a corner frequency of 140kHz. The rectified signal, RECT, is lowpass
filtered to generate a signal called PEAK. Also noise with a frequency 140kHz increases the
PEAK voltage. The PEAK voltage is fed to a threshold generator, which adds to the PEAK
voltage a DC dependent threshold VTH. Both signals, RECT and PEAK+VTH are fed to a
comparator which triggers a re-triggerable monoflop. The monoflop's output activates the
sample-and-hold circuits in the signalpath for 40μs. The block diagram of the noiseblanker is
given in Figure 16.
Figure 16. Block diagram of the noiseblander
MPX
HIGH PASS
RECTIFIER
RECT
+
-
+
HOLDN
VTH
PEAK
LOWPASS
MONOFLOP
THRESHOLD
GENERATOR
+
ADDITIONAL
THRESHOLD
CONTROL
D98AU861
7.2
Automatic noise controlled threshold adjustment (ATC)
There are mainly two independent possibilities for programming the trigger threshold:
a)
the low threshold in 8 steps (bits D0 to D2 of the noiseblanker byte)
b)
the noise adjusted threshold in 4 steps (bits D3 and D4 of the noiseblanker byte,
(see Figure 9).
The low threshold is active in combination with a good MPX signal without any noise; the
PEAK voltage is less than 1V. The sensitivity in this operation is high. If the MPX signal is
noisy the PEAK voltage increases
22/34
TDA7410ND
Functional description of the noiseblanker
due to the higher noise, which is also rectified. With increasing of the PEAK voltage the
trigger threshold increases, too. This particular gain is programmable in 4 steps (see
Figure 9).
7.3
Automatic threshold control
Besides the noise controlled threshold adjustment there is an additional possibility for
influencing the trigger threshold. It is depending on the stereoblend control. The point where
the MPX signal starts to become noisy is fixed by the RF part. Therefore also the starting
point of the normal noise-controlled trigger adjustment is fixed (Figure 11). In some cases
the behaviour of the noiseblanker can be improved by increasing the threshold even in a
region of higher fieldstrength. Sometimes a wrong triggering occures for the MPX signal
often shows distortion in this range which can be avoided even if using a low threshold.
Because of the overlap of this range and the range of the stereo/mono transition it can be
controlled by stereoblend. This threshold increase is programmable in 3 steps or switched
off with bits D0 and D1 of the fieldstrength control byte.
7.4
Over deviation detector
If the system is tuned to stations with a high deviation the noiseblanker can trigger on the
higher frequencies of the modulation. To avoid this wrong behaviour, which causes noise in
the output signal, the noiseblanker offers a deviation dependent threshold adjustment. By
rectifying the MPX signal a further signal representing the actual deviation is obtained. It is
used to increase the PEAK voltage. Offset and gain of this circuit are programmable in 3
steps with the bits D6 and D7 of the stereodecoder byte (the first step turns off the detector,
see Figure 10).
7.5
Test Mode
During the test mode which can be activated by setting bit D0 of the testing byte and bit D5
of the subaddress byte to ”1” several internal signals are available at the CASSR pin. During
this mode the input resistance of 100kOhm is disconnected from the pin. The internal
signals available are shown in the software specification.
Figure 17. Application Example
CREF
VDD
100nF
10μF
OUT_LF
OUT_LF
OUT_RF
100nF CASS_R
OUT_LR
CASS_R
CASS_L
CDR
22μF
CDG
100nF
CDL
AUX_R
CDR
CDG
CDL
TDA7410ND
TDA7410D
MPX
AM
SDA
SCL
100nF AUX_R
MUTE
LEVEL
AUX_L
100nF AUX_L
OUT_LR
OUT_RR
100nF CASS_L
100nF
OUT_RF
OUT_RR
100nF
MPX
100nF
AM
SDA
SCL
MUTE
LEVEL
GND
23/34
I2C bus specification
TDA7410ND
8
I2C bus specification
8.1
Interface protocol
The interface protocol comprises:
Table 8.
S
1
●
a start condition (S)
●
a chip address byte (the LSB determines read/write transmission)
●
a subaddress byte
●
a sequence of data (N-bytes + acknowledge)
●
a stop condition (P)
●
the max. clock speed is 500kbits/s
Receive mode
0
0 0 1
1
0
R/W
ACK
X
AZ
TS
AI
A3
A2
A1
A0
ACK
DATA ACK P
S = Start
"0" -> Receive Mode (Chip could be programmed by μP)
R/W =
"1" -> Transmission Mode (Data could be received by μP)
ACK = Acknowledge
P = Stop
TS = Testing mode
AZ = Auto zero remain
AI = Auto increment
Table 9.
S
1
Transmission mode
0
0
0
1
0
0
R/W
ACK
X
X
X
X
ST
X
X
X
ACK
P
ST = Stereo
X = Not Used
The transmitted data is automatic updated after each ACK. Transmission can be repeated
without new chip address.
8.2
Reset condition
A Power-On-Reset is invoked if the Supply-Voltage is below than 3.5V. After that the
following data is written automatically into the registers of all subaddresses:
Table 10.
Reset condition
MSB
1
24/34
LSB
1
1
1
1
1
1
0
I2C bus specification
TDA7410ND
Table 11.
Subaddress (Receive mode)
MSB
LSB
Function
X
AZ
TS
AI
A3
A2
A1
A0
AZ Remain
Off
On
0
1
Test Mode
Off
On
0
1
Auto Increment
Off
On
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
Source Selector
Volume Control
Speaker Attenuator LF
Speaker Attenuator LR
Speaker Attenuator RF
Speaker Attenuator RR
Treble / Level Gain
Stereodecoder Adjustment
Noiseblanker Adjustment
Fieldstrength Control
Test
Bass
Softstep Configuration
25/34
I2C bus specification
TDA7410ND
Table 12.
Source selector (0)
MSB
D7
D6
0
0
:
1
1
D5
0
0
:
1
1
D4
0
0
:
1
1
D3
LSB
Function
Source Selector / Bass
D2
D1
D0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Source Selector
CD
Cassette
Aux
AM
Stereo Decoder
Mute
Not Used
Not Used
Input Gain
0dB
1dB
:
14dB
15dB
0
1
:
0
1
x
Not Used
Table 13.
Volume Control (1)
MSB
LSB
Function
D7
D6
0
0
:
0
0
0
:
1
1
1
0
1
26/34
D5
D4
D3
D2
D1
D0
0
0
:
0
1
1
:
1
1
1
0
0
:
1
0
0
:
0
0
1
0
0
:
1
0
0
:
1
1
x
0
0
:
1
0
0
:
1
1
x
0
0
:
1
0
0
:
1
1
x
0
1
:
1
0
1
:
0
1
x
Gain/Attenuation
+0dB
+1dB
:
+31dB
-0dB
-1dB
:
-78dB
-79dB
mute
Soft Step
on
off
I2C bus specification
TDA7410ND
Table 14.
Speaker attenuation (2, 3, 4, 5)
MSB
D7
x
D6
Speaker Attenuation LF
(LR,RF,RR)
D5
D4
D3
D2
D1
D0
0
0
:
0
0
0
0
0
0
0
0
0
1
0
0
:
1
1
1
1
1
1
1
1
1
x
0
0
:
0
1
1
1
1
1
1
1
1
x
0
0
:
1
0
0
0
0
1
1
1
1
x
0
0
:
1
0
0
1
1
0
0
1
1
x
0
1
:
1
0
1
0
1
0
1
0
1
x
Attenuation
0dB
-1dB
:
-23dB
-25dB
-27dB
-29dB
-31.5dB
-34dB
-37.5dB
-42dB
-50dB
Speaker Mute
Not used
Treble / Level gain (6)
MSB
D6
D5
D4
D3
0
0
:
0
0
1
1
:
1
1
0
0
0
:
1
Function
x
Table 15.
D7
LSB
0
0
0
:
1
0
0
1
:
1
0
1
0
:
1
D2
0
0
:
1
1
1
1
:
0
0
D1
0
0
:
1
1
1
1
:
0
0
LSB
Function
D0
Treble / Level Gain
0
1
:
0
1
1
0
:
1
0
Treble
-14dB
-12dB
:
-2dB
0dB
0dB
+2dB
:
+12dB
+14dB
LEVEL Gain
0dB
0.66dB
1.33dB
:
10dB
27/34
I2C bus specification
TDA7410ND
Table 16.
Stereodecoder adjustment (7)
MSB
D7
D6
D5
D4
D3
D2
D1
LSB
Function
D0
Stereodecoder Adjustment
0
1
0
0
1
1
0
1
0
1
In-Gain 11dB
In-Gain 8.5dB
In-Gain 6dB
In-Gain 3.5dB
Forced MONO
MONO/STEREO switch
automatically
0
1
0
1
Pilot Threshold HIGH
Pilot Threshold LOW
0
1
0
0
1
1
Deemphasis Threshold 50μs
Deemphasis Threshold 75μs
Blank Time Adj
38μs
25.5μs
32μs
22μs
0
1
0
1
Table 17.
Noise blanker adjustment (8)
MSB
D7
D6
D5
D4
0
0
1
1
0
1
0
0
1
1
28/34
STD Unmuted
STD Muted
0
1
0
1
D3
0
1
0
1
LSB
Function
Noiseblanker
D2
D1
D0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Low Threshold 65mV
Low Threshold 60mV
Low Threshold 55mV
Low Threshold 50mV
Low Threshold 45mV
Low Threshold 40mV
Low Threshold 35mV
Low Threshold 30mV
Noise Controlled Threshold 260mV
Noise Controlled Threshold 220mV
Noise Controlled Threshold 180mV
Noise Controlled Threshold 140mV
Noise Blanker OFF
Noise Blanker ON
Over deviation Adjust 2.8V
Over deviation Adjust 2.0V
Over deviation Adjust 1.2V
Over deviation Adjust OFF
I2C bus specification
TDA7410ND
Table 18.
Fieldstrength Control (9)
MSB
D7
D6
D5
D4
D3
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
D2
0
1
0
1
LSB
Function
D1
D0
Fieldstrength Control
0
0
1
1
0
1
0
1
NoiseBlanker Field strength Adj 2.3V
NoiseBlanker Field strength Adj 1.8V
NoiseBlanker Field strength Adj 1.3V
NoiseBlanker Field strength Adj OFF
VSBL at 33% REF 5V
VSBL at 42% REF 5V
VSBL at 50% REF 5V
VSBL at 58% REF 5V
VHCH at 42% REF 5V
VHCH at 50% REF 5V
VHCH at 58% REF 5V
VHCH at 66% REF 5V
VHCL at 17% VHCH
VHCL at 33% VHCH
High cut OFF
High cut ON
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I2C bus specification
TDA7410ND
Table 19.
Test (10)
MSB
D7
D6
D5
D4
D3
D2
D1
LSB
Function
D0
Test
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
1
30/34
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Stereodecoder test signal
OFF
Test signal enabled
External Clock
Internal Clock
Test signal
VHCCH
Level internal
Pilot magnitude
VCO control voltage
Pilot Threshold
HOLDN
NB threshold
F228
VHCCL
VSBL
SBPWM
TBD
PEAK
REF5V
REF5V5
VBG1.95
VCO
OFF
ON
Audio processor test mode
Enabled
OFF
I2C bus specification
TDA7410ND
Table 20.
Bass (11)
MSB
D7
D6
D5
D4
LSB
Function
Bass
D3
D2
D1
D0
0
0
:
0
0
1
1
:
1
1
0
0
:
1
1
1
1
:
0
0
0
0
:
1
1
1
1
:
0
0
0
1
:
0
1
1
0
:
1
0
Bass DC Mode
DC Gain = 0dB
DC Gain = 4.4 dB
0
1
Bass Softstep
On
Off
0
1
x
x
Table 21.
Not Used
Softstep Control (12)
MSB
D7
D6
D5
D4
D3
D2
D1
LSB
Function
D0
Softstep Control
0
1
0
0
1
1
1
0
1
x
Bass
-14dB
-12dB
:
-2dB
0dB
0dB
+2dB
:
+12dB
+14dB
x
1
0
1
0
1
AutoZero Function
Off
On
Soft Step Time
0.84ms
1.68ms
3.36ms
6.72ms
Reserved
STD Discharge
Off
On
Not Used
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Package information
9
TDA7410ND
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 18. SO20 Mechanical data and package dimensions
mm
inch
DIM.
MIN.
TYP.
MAX.
MIN.
2.65
0.093
TYP.
MAX.
A
2.35
A1
0.10
0.30
0.004
0.012
B
0.33
0.51
0.013
0.200
C
0.23
0.32
0.009
0.013
D (1)
12.60
13.00
0.496
0.512
E
7.40
7.60
0.291
0.299
e
1.27
0.104
0.050
H
10.0
10.65
0.394
0.419
h
0.25
0.75
0.010
0.030
L
0.40
1.27
0.016
0.050
k
ddd
OUTLINE AND
MECHANICAL DATA
0˚ (min.), 8˚ (max.)
0.10
0.004
(1) “D” dimension does not include mold flash, protusions or gate
burrs. Mold flash, protusions or gate burrs shall not exceed
0.15mm per side.
SO20
0016022 D
32/34
TDA7410ND
10
Revision history
Revision history
Table 22.
Document revision history
Date
Revision
Changes
20-Feb-2007
1
Initial release.
28-Feb-2007
2
Corrected typos.
33/34
TDA7410ND
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