TDA7403 BASIC SIGNAL PROCESSOR PRELIMINARY DATA DEVICE INCLUDES AUDIO PROCESSOR, STEREO DECODER AND NOISEBLANKER HIGH PERFORMANCE SIGNAL PROCESSOR WITH BASIC FUNCTIONS AM, FM, MPX AND CASSETTE INPUTS NO EXTERNAL COMPONENTS REQUIRED FULLY PROGRAMMABLE VIA I2C BUS LOW DISTORTION AND NOISE SO20 DESCRIPTION The TDA7403 is a high performance signal processor specifically designed for car radio applications focused on the low-end market. The device includes a complete audioprocessor and a stereo decoder with noiseblanker. Switched-capacitors design technique allows to obtain all these features without external components or adjustments. Using TDA7403 results is in a very performant low-cost signal processing ORDERING NUMBER: TDA7403D application The device is fully programmable by I2C bus interface allowing to customize key device parameters and especially filter characteristics. The BICMOS process combined with the optimized signal processing assure low noise and low distortion performances. BLOCK DIAGRAM SM 11 AM CASS R 8 VOLUME SOFT MUTE OUT LR TREBLE OUT LF BASS OUT RR OUT RF 1 INPUT MULTIPLEXER + AUTO ZERO 2 CASS L 17 19 16 18 12 I2C BUS DIGITAL CONTROL 13 OUT LR OUT LF OUT RR OUT RF SCL SDA FM R FM L 9 PILOT CANCELLATION 80KHz LP MPX 15 VS PLL SUPPLY 14 GND October 1998 20 CREF PIL DET DEMODULATOR + STEREO ADJUST + STEREO BLEND 25KHz LP S&H HIGH CUT CONTROL D NOISE BLANKER PULSE FORMER A 10 LEVEL D98AU918 1/26 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. TDA7403 ABSOLUTE MAXIMUM RATINGS Symbol VS Parameter Value Operating Supply Voltage Unit 10.5 V Tamb Operating Ambient Temperature Range -40 to 80 °C Tstg Operating Storage Temperature Range -55 to 150 °C SUPPLY Symbol VS IS SVRR Parameter Test Condition Supply Voltage Min. Typ. Max. Unit 7.5 9 10 V 25 30 35 mA Supply Current VS = 9V Ripple Rejection @ 1KHz Audioprocessor (all filters flat) 60 dB Stereodecoder + Audioprocessor 55 dB ESD All pins are protected against ESD according to the MIL883 standard. PIN CONNECTION CASS R 1 20 CREF CASS L 2 19 OUT LF N.C. 3 18 OUT RF N.C. 4 17 OUT LR N.C. 5 16 OUT RR N.C. 6 15 VS N.C. 7 14 GND AM 8 13 SDA MPX 9 12 SCL 10 11 SM LEVEL D98AU919 THERMAL DATA Symbol Rth-j pins 2/26 Parameter Thermal Resistance Junction-pins Max Value Unit 85 °C/W TDA7403 PIN DESCRIPTION N. Name 1 CASSR Cassette Input Right I 2 CASSL Cassette Input Left I 3 n.c. not connected 4 n.c. not connected 5 n.c. not connected 6 n.c. not connected 7 n.c. not connected 8 AM AM Input I FM Input (MPX) I Level Input Stereodecoder I Soft Mute Drive I 9 MPX 10 LEVEL 11 SM 12 SCL Function Type 2 I/O 2 I/O I C Clock Line 13 SDA I C Data Line 14 GND Supply Ground S 15 VS Supply Voltage S 16 OUTRR Right Rear Speaker Output O 17 OUTLR Left Rear Speaker Output O 18 OUTRF Right Front Spaeaker Output O 19 OUTLF Left Front Speaker Output O 20 CREF Reference Capacitor Pin S (1) See input configuration tree and databyte specification ”configuration” Pin type legenda: I = Input O = Output I/O = Input/Output S = Supply 3/26 TDA7403 AUDIO PROCESSOR PART Bass Control 2nd order frequency response Center frequency programmable in 4(5) steps DC gain programmable 7 x 2dB steps Input Multiplexer MPX input Cassette stereo input AM mono or stereo input Internal beep with 2 frequencies (selectable) Mixable phone and beep signals Treble Control 2nd order frequency response Center frequency programmable in 4 steps 7 x 2dB steps Loudness First or second order frequency response Programmable center frequency and quality factor 15 x 1dB steps Selectable flat-mode (constant attenuation) Speaker Control 4 independentspeaker controls (1dB steps control range 50dB) Volume control 1dB attenuator Max. gain 20dB Max. attenuation 79dB Soft-step gain control Mute Functions Direct mute driven by pin SM Digitally controlled softmute with 4 programmable time constants ELECTRICAL CHARACTERISTICS (VS = 9V; Tamb = 25°C; RL = 10KΩ; all gains = 0dB; f = 1KHz; unless otherwise specified). Symbol Parameter Test Condition Min. Typ. Max. Unit 70 100 130 KΩ INPUT SELECTOR R in Input Resistance VCL Clipping Level 2.2 2.6 SIN Input Separation 80 100 GIN MIN Min. Input Gain -1 0 GIN MAX Max. Input Gain GSTEP Step Resolution VDC DC Steps all inputs except Phone 14 VRMS dB 1 dB dB 2 dB Adjacent Gain Step 0 mV GMIN to GMAX 1 mV mV BEEP CONTROL VRMS Beep Level 350 fBMIN Lower Beep Frequency 600 Hz fBMAX Higher Beep Frequency 1.2 KHz MIXING CONTROL MLEVEL Mixing Level Source 0 dB Source -6 dB Source -12 dB 0 dB Beep/Phone 4/26 TDA7403 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit VOLUME CONTROL GMAX Max Gain 20 dB AMAX Max Attenuation 79 dB ASTEP Step Resolution EA Attenuation Set Error ET Tracking Error VDC DC Steps 1 dB G = -20 to 20dB -1.25 0 1.25 dB G = -60 to 20dB -4 0 3 dB 2 dB Adjacent Attenuation Steps 0.1 3 mV From 0dB to GMIN 0.5 5 mV LOUDNESS CONTROL ASTEP Step Resolution 1 AMAX Max. Attenuation 15 dB dB fCMIN Lower Center Frequency 200 Hz fCMAX Higher Center Frequency 400 Hz SOFT MUTE AMUTE TD Mute Attenuation Delay Time 100 dB T1 70 0.48 ms T2 0.96 ms T3 40.4 ms T4 324 ms VTHlow Low Threshold for SM Pin (1) VTHhigh High Threshold for SM Pin 2.5 R PU Internal Pull-up Resistor 70 VPU Pull-up Voltage 4.7 V Switch Time 10 ms ±14 2 dB fC1 60 Hz fC2 70 Hz fC3 80 Hz 1 V V 100 130 KΩ SOFT STEP TSW BASS CONTROL C RANGE ASTEP fC QBASS DC GAIN Control Range Step Resolution Center Frequency Quality Factor Bass-Dc-Gain (2) fC4 100 Q1 1 Q2 1.25 Q3 1.5 Q4 2 dB Hz DC = off 0 dB DC = on 4.4 dB 1) SM pin is active low (mute condition) 2) See description of Audioprocessor Part - Bass & Treble filter characteristics programming 5/26 TDA7403 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit TREBLE CONTROL C RANGE ASTEP fC Control Range Step Resolution Center Frequency fC1 fC2 fC3 fC4 ±14 2 10 12.5 15 17.5 dB dB KHz KHz KHz KHz 50 1 90 dB dB dB dB mV SPEAKER ATTENUATORS C RANGE ASTEP AMUTE EE VDC Control Range Step Resolution Output Mute Attenuation Attenuation Set Error DC Steps 80 Adjacent Attenuation Steps 0.1 2 5 AUDIO OUTPUTS VCLIP RL CL ROUT VDC Clipping Level Output Load Resistance Output Load Capacitance Output Impedance DC Voltage Level d = 0.3% Output Noise BW = 20 Hz to 20 KHz output muted BW = 20 Hz to 20 KHz all gain = 0dB all gain = 0dB flat; VO = 2VRMS bass treble at 12dB; VO = 2.6VRMS VIN = 1VRMS; all stages 0dB VIN = 1VRMS; Bass & Treble = 12dB 2.2 2 2.6 30 3.8 10 120 VRMS KΩ nF Ω V GENERAL e NO S/N 6/26 Signal to Noise Ratio d Distortion SC ET Channel separation Left/Right Total Tracking Error 80 AV = 0 to -20dB AV = -20 to -60dB 3 µV 6.5 µV 110 100 dB dB 0.002 0.05 100 0 0 % % dB dB dB 1 2 TDA7403 DESCRIPTION OF THE AUDIOPROCESSOR Figure 1. Input stages CASSETTE IN GAIN 100K AM 100K STEREODECODER MPX 100K D98AU951 Input stages The input circuits are the same as in preceeding ST audioprocessors with exception of the CD inputs (see figure 1). The typical input impedance is 100kΩ. AutoZero In order to reduce the number of pins there is no AC coupling between the In-Gain and the following stage, so that any offset generated by or before the In-Gain stage would be transferred or even amplified to the output. To avoid that effect a special offset cancellation stage called AutoZero is implemented. To avoid audible clicks the audioprocessor is muted before the loudness stage during this time. In some cases, for example if the µP is executing a refresh cycle of the I2C bus programming, it is not useful to start a new AutoZero action because no new source is selected and an undesired mute would appear at the outputs. For such applications the TDA7403 could be switched in the ”Auto Zero Remain” mode (Bit 6 of the subaddress byte). If this bit is set to high, the DATABYTE 0 could be loaded without invoking the AutoZero and the old adjustment value remains. Figure 2. Loudness Attenuation @ fc = 400Hz (second order) 0.0 -5.0 -10.0 -15.0 -20.0 10.0 100.0 1.0K 10.0K Figure 3. Loudness Center frequency @ Attn. = 15dB (second order) 0.0 -5.0 -10.0 -15.0 Mixing Stage This stage offers the possibility to mix the internal beep or the phone signal to any other source. Due to the fact that the mixing stage is also located behind the In-Gain stage fine adjustments of the main source level can be done in this way. Loudness There are four parameters programmable in the loudness stage (see fig. 2, 3, 4): -20.0 10.0 100.0 1.0K 10.0K - Attenuation - Center Frequency - Loudness Q - Flat Mode: in this mode the loudness stage works as a 0 - 15dB attenuator. 7/26 TDA7403 Figure 4. Loudness @ Attn. = 15dB, fc = 400Hz Figure 5. Softmute Timing D98AU844 (dB) EXT. MUTE 1 -5 +SIGNAL -10 REF -SIGNAL -15 1 2 -20 10 I C BUS OUT 100 1,000 Hz Softmute The digitally controlled softmute stage allows muting/demuting the signal with a I2C bus programmable slope. The mute process can either be activated by the softmute pin or by the I2C bus. The slope is realized in a special S shaped curve to mute slow in the critical regions (see figure 5). For timing purposes the Bit 3 of the I2C bus output register is set to 1 from the start of muting until the end of demuting. Softstep Volume When volume level is changed often an audible click appears at the output. The root cause of those clicks could be either a DC offset before the volume stage or the sudden change of the envelope of the audio signal. With the Softstep feature both kinds of clicks could be reduced to a minimum and are no more audible (see figure 6). Bass There are three parameters programmable in the bass stage (see figs 7, 8, 9, 10): - Attenuation - Center Frequency (60, 70, 80 and 100Hz) - Quality Factors (1, 1.25, 1.5 and 2) DC Mode In this mode the DC gain is increased by 4.4dB. In addition the programmed center frequency and quality factor is decreased by 25% which can be used to reach alternative center frequencies or quality factors. 8/26 Time D97AU634 Note: Please notice that a started Mute action is always terminated and could not be interrupted by a change of the mute signal. Figure 6. Soft Step Timing VOUT 2dB 1dB Time 10ms -1dB -2dB D97AU635 Note: For steps more than 1dB the softstep mode should be deactivated because it could generate a 1dB error during the blend-time Treble There are two parameters programmable in the treble stage (see figs 11, 12): - Attenuation - Center Frequency (10, 12.5, 15 and 17.5kHz). Speaker Attenuator Due to practical aspects the steps in the speaker attenuators are not linear over the full range. At attenuations more than 24dB the steps increase from 1.5dB to 10dB (please see data byte specification). TDA7403 Figure 7. Bass Control @ fc = 80Hz, Q = 1 Figure 8. Bass Center @ Gain = 14dB, Q = 1 15.0 15.0 10.0 12.5 5.0 10.0 7.5 0.0 5.0 -5.0 2.5 -10.0 0.0 -15.0 10.0 100.0 1.0K 10.0K 10.0 100.0 1.0K Figure 9. Bass Quality factors @ Gain = 14dB, fc = 80Hz Figure 10. Bass normal and DC Mode @ Gain = 14dB, fc = 80Hz 15.0 15.0 10.0K 12.5 12.5 10.0 10.0 7.5 7.5 5.0 5.0 2.5 2.5 0.0 10.0 0.0 10.0 100.0 1.0K 10.0K 100.0 1.0K 10.0K Note: In general the center frequency, Q and DC-mode can be set independently. The exception from this rule is the mode (5/xx1111xx) where the center frequency is set to 150Hz instead of 100Hz. Figure 11. Treble Control @ fc = 17.5KHz Figure 12. Treble Center Frequencies @ Gain = 14dB 15.0 15.0 10.0 12.5 10.0 5.0 7.5 0.0 5.0 -5.0 2.5 -10.0 0.0 -15.0 10.0 100.0 1.0K 10.0K 10.0 100.0 1.0K 10.0K 9/26 TDA7403 STEREODECODER PART Dedicated RDS Softmute Highcut and Stereoblend characterisctics programmable in a wide range Internal Noiseblanker with threshold controls Multipath detector with programmable internal/external influence I2C bus control of all necessary functions No external components necessary PLL with adjustment free fully integrated VCO Automatic pilot dependent MONO/STEREO switching Very high suppression of intermodulation and interference Programmable Roll-Off compensation ELECTRICAL CHARACTERISTICS (VS = 9V; deemphasis time constant = 50µs, VMPX = 500mV, 75KHz deviation, f = 1KHz. GI = 6dB, Tamb = 25°C; unless otherwise specified). Symbol VIN R in Gmin Gmax GSTEP SVRR α THD S+N Parameter MPX Input Level Input Resistance Minimum Input Gain Max Input Gain Step Resolution Supply Voltage Ripple Rejection Max Channel Separation Total Harmonic Distortion Signal plus Noise to Noise Ratio Test Condition Min. Input Gain = 3.5dB Typ. Max. Unit 0.5 100 1.25 VRMS KΩ 3.5 11 2.5 60 50 0.02 91 Vripple = 100mv, f = 1khz S = 2Vrms 0.3 dB dB dB dB dB % dB N MONO/STEREO SWITCH VPTHST1 VPTHST0 VPTHMO1 VPTHMO0 Pilot Threshold Voltage Pilot Threshold Voltage Pilot Threshold Voltage Pilot Threshold Voltage for Stereo, PTH = 1 for Stereo, PTH = 0 for Mono, PTH = 1 for Stereo, PTH = 0 15 25 12 19 mV mV mV mV PLL ∆f/f Capture Range 0.5 % DEEMPHASIS and HIGHCUT τHC50 Deemphasis Time Constant τHC75 Deemphasis Time Constant τHC50 Highcut Time Constant τHC75 Highcut Time Constant Bit = 7, Subadr. 10 = VLEVEL >> VHCH Bit = 7, Subadr. 10 = VLEVEL >> VHCH Bit = 7, Subadr. 10 = VLEVEL >> VHCL Bit = 7, Subadr. 10 = VLEVEL >> VHCL 0 50 µs 1 75 µs 0 150 µs 1 225 µs STEREOBLEND and HIGHCUT-CONTROL REF5V TCREF5V LGmin Internal Reference Voltage Temperature Coefficient Min. LEVEL Gain 5 3300 0 V ppm dB LGmax LGstep VSBL min VSBL max VSBL step Max. LEVEL Gain LEVEL Gain Step Resolution Min.Voltage for Mono Max. Voltage for Mono Step Resolution 10 0.67 33 58 8.4 dB dB %REF5V %REF5V %REF5V 10/26 TDA7403 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit STEREOBLEND and HIGHCUT CONTROL VHCHmin VHCHmax Min.Voltage for NO Highcut Max. Voltage for NO Highcut 42 66 %REF5V %REF5V VHCHstep VHCLmin VHCLmax Step Resolution Min. Voltage for FULL High cut Max. Voltage for FULL High cut 8.4 17 33 %REF5V %VHCH %VHCH 50 75 62 90 dB dB dB dB fmod = 10KHz; fspur = 1KHz; fmod = 13KHz; fspur = 1KHz; 65 75 dB dB f = 57KHz 70 dB 75 dB 95 84 dB dB Carrier and harmonic suppression at the output α19 α38 α57 α76 Pilot Signal Subcarrier Subcarrier Subcarrier f= f= f= f= 19KHz 38KHz 57KHz 76KHz Intermodulation (Note1) α2 Pilot Signal α3 Traffic Radio (Note 2) α57 Signal SCA - Subsidiary Communications Authorization (Note 3) α67 Signal f = 67KHz ACI - Adjacent Channel Interference (Note 4) α114 α190 Signal Signal f = 114KHz f = 190KHz Notes to the characteristics: 1. Intermodulation Suppression: measured with: 91% pilot signal; fm = 10kHz or 13kHz. 2. Traffic Radio (V.F.) Suppression: measured with: 91% stereo signal; 9% pilot signal; fm=1kHz; 5% subcarrier (f = 57kHz, fm = 23Hz AM, m = 60%) 3. SCA ( Subsidiary Communications Authorization ) measured with: 81% mono signal; 9% pilot signal; fm = 1kHz; 10%SCA - subcarrier ( fs = 67kHz, unmodulated ). 4. ACI ( Adjacent Channel Interference ) measured with: 90% mono signal; 9% pilot signal; fm =1kHz; 1% spurious signal ( fs = 110kHz or 186kHz, unmodulated). 11/26 TDA7403 NOISE BLANKER PART internal 2nd order 140kHz high pass filter programmable trigger threshold additional circuits for trigger adjustment (deviation, field-strenght) very low offset current during hold time four selectable pulse suppression times ELECTRICAL CHARACTERISTICS (continued) Symbol VTR Parameter Trigger Threshold 0) 1) Test Condition meas. with VPEAK = 0.9V VTRNOISE Noise Controlled Trigger Threshold 2) meas. with VPEAK = 1.5V Rectifier Voltage VMPX = 0mV VMPX = 50mV; f = 150KHz VMPX = 100mV; f = 150KHz OVD = 11 means. with VMPX = 800mV OVD = 10 (75KHz dev.) OVD = 01 OVD = 00 FSC = 11 means. with VMPX = 0mV FSC = 10 VLEVEL << VSBL FSC = 01 (fully mono) FSC = 00 VRECT VRECT DEV deviation dependent 3) rectifier Voltage VRECT FS Fieldstrength Controlled Rectifier Voltage 4) Min. NBT = 111 NBT = 110 NBT = 101 NBT = 100 NBT = 011 NBT = 010 NBT = 001 NBT = 000 NCT = 00 NCT = 01 NCT = 10 NCT = 11 0) All thresholds are measured using a pulse with TR = 2 µs, THIGH = 2 µs and TF = 10 µs. 1) NBT represents the Noiseblanker-Byte bits D2; D0 for the noise blanker trigger threshold 2) NAT represents the Noiseblanker-Byte bit pair D4,D3 for the noise controlled trigger adjustment 3) OVD represents the Noiseblanker-Byte bit pair D7,D6 for the over deviation detector 4) FSC represents the Fieldstrength-Byte bit pair D1,D0 for the fieldstrength control V IN VOP DC D97AU636 12/26 TR THIGH TF Time Typ. 30 35 40 45 50 55 60 65 260 220 180 140 0.9 1.7 2.5 0.9(off) 1.2 2.0 2.8 0.9(off) 1.3 1.8 2.3 Max. Unit mVOP mVOP mVOP mVOP mVOP mVOP mVOP mVOP mVOP mVOP mVOP mVOP V V V VOP VOP VOP VOP V V V V TDA7403 Figure 13. Trigger Threshold vs. VPEAK VTH 260mV(00) 220mV(01) 180mV(10) 140mV(11) MIN. TRIG. THRESHOLD NOISE CONTROLLED TRIG. THRESHOLD 65mV 8 STEPS 30mV 0.9V VPEAK(V) 1.5V D97AU648 Figure 15. Fieldstrength Controlled Trigger Adjustment Figure 14. Deviation Controlled Trigger Adjustment VPEAK VPEAK (VOP) MONO 00 2.8 STEREO »3V 01 2.3V(00) 1.8V(01) 1.3V(10) 2.0 10 NOISE 1.2 0.9 D97AU649 DETECTOR OFF (11) 20 32.5 45 75 noisy signal DEVIATION(KHz) 0.9V ATC_SB OFF (11) good signal D98AU863 E’ Figure 16. Block diagram of the stereo decoder DEMODULATOR MPX INGAIN INFILTER 3.5 ... 11dB STEP 2.5dB LP 80KHz 4.th ORDER DEEMPHASIS + HIGHCUT - PLOT CANC - ROLL-OFF COMP. - LP 25KHz t=50 or 75µs FM_L FM_R 100K PLL + PILOT-DET. F19 SB CONTROL REF 5V VSBL HC CONTROL D F38 A VHCCH VHCCL STEREO NOISE BLANKER D98AU952 HOLDN LEVEL INPUT LEVEL INTERN LP 2.2KHZ 1.th ORDER GAIN 0..10dB LEVEL 13/26 TDA7403 DESCRIPTION OF STEREODECODER The stereodecoder part of the TDA7403 (see Fig. 16) contains all functions necessary to demodulate the MPX signal like pilot tone dependent MONO/STEREO switching as well as ”stereoblend” and ”highcut” functions. Adaptations like programmable input gain, roll-off compensation, selectable deemphasis time constant and a programmable fieldstrength input allow to use different IF devices. Figure 17. Signals during stereodecoder’s softmute SOFTMUTE COMMAND t STD MUTE t Stereodecoder Mute The TDA7403 has a fast and easy to control RDS mute function which is a combination of the audioprocessor softmute and the high-ohmic mute of the stereodecoder. If the stereodecoder is selected and a softmute command is sent (or activated through the SM pin) the stereodecoder will be set automatically to the high-ohmic mute condition after the audio signal has been softmuted. Hence a checking of alternate frequencies could be performed. To release the system from the mute condition simply the unmute command must be sent: the stereodecoder is unmuted immediately and the audioprocessor is softly unmuted. Fig. 17 shows the output signal VO as well as the internal stereodecoder mute signal. This influence of Softmute on the stereodecoder mute can be switched off by setting bit 3 of the Softmute byte to ”0”. A stereodecoder mute command (bit 0, stereodecoder byte set to ”1”) will set the stereodecoder in any case independently to the high-ohmic mute state. If any other source than the stereodecoder is selected the decoder remains muted and the MPX pin is connected to Vref to avoid any discharge of the coupling capacitor through leakage currents. Input Stages The Ingain stage allows to adjust the MPX signal to a magnitude of about 1Vrms internally which is the recommended value. The 4.th order input filter has a corner frequency of 80kHz and is used to attenuatespikes and noise and acts as an antialiasing filter for the following switch capacitor filters. Demodulator In the demodulator block the left and the right channel are separated from the MPX signal. In this stage also the 19 kHz pilot tone is cancelled. For reaching a high channel separation the TDA7403 offers an I2C bus programmable roll-off adjustment which is able to compensate the low14/26 VO D97AU638 t pass behaviour of the tuner section. If the tuner attenuation at 38kHz is in a range from 20.2% to 31% the TDA7403 needs no external network before the MPX pin. Within this range an adjustment to obtain at least 40dB channel separation is possible. The bits for this adjustment are located together with the fieldstrength adjustment in one byte. This gives the possibility to perform an optimization step during the production of the carradio where the channel separation and the fieldstrength control are trimmed. Deemphasis and Highcut The lowpass filter for the deemphasis allows to choose between a time constant of 50µs and 75µs (bit D7, Stereodecoder byte). The highcut control range will be in both cases tHC = 2 ⋅ tDeemp. Inside the highcut control range (between VHCH and VHCL) the LEVEL signal is converted into a 5 bit word which controls the lowpass time constant between t Deemp...3 ⋅ tDeemp. There by the resolution will remain always 5 bits independently of the absolute voltage range between the VHCH and VHCL values. The highcut function can be switched off by I2C bus (bit D7, Fieldstrength byte set to ”0”). PLL and Pilot Tone Detector The PLL has the task to lock on the 19kHz pilotone during a stereo transmission to allow a correct demodulation. The included detector enables the demodulation if the pilot tone reaches the selected pilottone threshold VPTHST. Two different thresholds are available. The detector output (signal STEREO, see block diagram) can be checked TDA7403 by reading the status byte of the TDA7403 via I2C bus. Figure 18. Internal stereoblend characteristics Fieldstrength Control The fieldstrength input is used to control the high cut and the stereoblend function. In addition the signal can be also used to control the noiseblanker thresholds. LEVEL Input and Gain To suppress undesired high frequency modulation on the highcut and stereoblend function the LEVEL signal is lowpass filtered firstly. The filter is a combination of a 1st order RC lowpass at 53kHz (working as anti-aliasing filter) and a 1storder switched capacitor lowpass at 2.2kHz. The second stage is a programmable gain stage to adapt the LEVEL signal internally to different IF. The gain is widely programmable in 16 steps from 0dB to 10dB (step = 0.67dB). These 4 bits are located together with the Roll-Off bits in the ”Stereodecoder Adjustment” byte to simplify a possible adaptation during the production of the carradio. gain LG and VSBL. To adjust the voltage where the full channel separation is reached (VST) the LEVEL gain LG has to be defined. The following equation can be used to estimate the gain: LG = REF5V Field strength voltage [STEREO] The gain can be programmed through 4 bits in the ”Stereodecoder-Adjustment” byte. The MONO voltage VMO (0dB channel separation) can be choosen selecting 33, 42, 50 or 58% of REF5V. All necessary internal reference voltages like REF5V are derived from a bandgap circuit. Therefore they have a temperature coefficient near zero. This is useful if the fieldstrength signal is also temperature compensated. But most IF devices apply a LEVEL voltage with a TC of 3300ppm. The TDA7403 offers this TC for the reference voltages, too. The TC is selectable with bit D7 of the ”stereodecoder adjustment” byte. Stereoblend Control The stereoblend control block converts the internal LEVEL voltage (LEVEL INTERN) into an demodulator compatible analog signal which is used to control the channel separation between 0dB and the maximum separation. Internally this control range has a fixed upper limit which is the internal reference voltage REF5V. The lower limit can be programmed to be 33%, 42%, 50% or 58% of REF5V (see fig. 19). To adjust the external LEVEL voltage to the internal range two values must be defined: the LEVEL Figure 19. Relation between internal and external LEVEL voltage and setup of Stereoblend INTERNAL VOLTAGES INTERNAL SETUP OF VST VOLTAGES SETUP OF VMO LEVEL INTERN LEVEL INTERN REF 5V REF 5V LEVEL VSBL VSBL 58% 50% 42% 33% t VMO t VST VST FIELDSTRENGHT VOLTAGE D97AU639 VMO FIELDSTRENGHT VOLTAGE 15/26 TDA7403 Highcut Control The highcut control setup is similar to the stereoblend control setup : the starting point VHCH can be set with 2 bits to be 42, 50, 58 or 66% of REF5V whereas the range can be set to be 17 or 33% of VHCH (see fig. 20). supplied by his own biasing circuit. Trigger Path The incoming MPX signal is highpass filtered, amplified and rectified. This second order highpass-filter has a corner frequency of 140kHz. The rectified signal, RECT, is lowpass filtered to generate a signal called PEAK. Also noise with a frequency 140kHz increases the PEAK voltage. The PEAK voltage is fed to a threshold generator, which adds to the PEAK voltage a DC dependent threshold VTH. Both signals, RECT and PEAK+VTH are fed to a comparator which triggers a re-triggerable monoflop. The monoflop’s output activates the sample-and-hold circuits in the signalpath for 40µs. Figure 20. Highcut characteristics LOWPASS TIME CONSTANT 3•τDeemp The block diagram of the noiseblanker is given in fig.20. τDeemp D97AU640 Automatic Noise Controlled Threshold Adjustment (ATC) There are mainly two independent possibilities for programming the trigger threshold: FUNCTIONAL DESCRIPTION OF THE NOISEBLANKER In the automotive environment the MPX signal is disturbed by spikes produced by the ignition and for example the wiper motor. The aim of the noiseblanker part is to cancel the audible influence of the spikes. Therefore the output of the stereodecoder is held at the actual voltage for 40µs. In a first stage the spikes must be detected but to avoid a wrong triggering on high frequency (white) noise a complex trigger control is implemented. Behind the triggerstage a pulse former generates the ”blanking” pulse. To avoid any crosstalk to the signalpath the noiseblanker is a the low threshold in 8 steps (bits D0 to D2 of the noiseblanker byte) b the noise adjusted threshold in 4 steps (bits D3 and D4 of the noiseblanker byte, see fig. 13). The low threshold is active in combination with a good MPX signal without any noise; the PEAK voltage is less than 1V. The sensitivity in this operation is high. If the MPX signal is noisy the PEAK voltage increases due to the higher noise, which is also rectified. With increasing of the PEAK voltage the trigger threshold increases, too. This particular gain is programmable in 4 steps (see fig. 13). VHCL VHCH FIELDSTRENGHT Figure 21. Block diagram of the noiseblanker MPX HIGH PASS RECTIFIER RECT + - + VTH PEAK LOWPASS MONOFLOP THRESHOLD GENERATOR + ADDITIONAL THRESHOLD CONTROL D98AU861 16/26 HOLDN TDA7403 Automatic Threshold Control Besides the noise controlled threshold adjustment there is an additional possibility for influencing the trigger threshold. It is depending on the stereoblend control. The point where the MPX signal starts to become noisy is fixed by the RF part. Therefore also the starting point of the normal noise-controlled trigger adjustment is fixed (fig. 15). In some cases the behaviour of the noiseblanker can be improved by increasing the threshold even in a region of higher fieldstrength. Sometimes a wrong triggering occures for the MPX signal often shows distortion in this range which can be avoided even if using a low threshold. Because of the overlap of this range and the range of the stereo/mono transition it can be controlled by stereoblend. This threshold increase is programmable in 3 steps or switched off with bits D0 and D1 of the fieldstrength control byte. Over Deviation Detector If the system is tuned to stations with a high deviation the noiseblanker can trigger on the higher frequencies of the modulation. To avoid this wrong behaviour, which causes noise in the output signal, the noiseblanker offers a deviation dependent threshold adjustment. By rectifying the MPX signal a further signal representing the actual deviation is obtained. It is used to increase the PEAK voltage. Offset and gain of this circuit are programmable in 3 steps with the bits D6 and D7 of the stereodecoder byte (the first step turns off the detector, see fig. 15). TEST MODE During the test mode which can be activated by setting bit D0 of the testing byte and bit D5 of the subaddress byte to ”1” several internal signals are available at the CASSR pin. During this mode the input resistance of 100kOhm is disconnected from the pin. The internal signals available are shown in the software specification. Figure 23. Application Example. VS CREF 10µF +V CC = OUTLF 100nF OUTLF 9V 100nF CASS R OUTRF OUTRF CASS R OUTLR 100nF CASS L CASS L OUTLR OUTRR OUTRR SDA 220nF MPX SDA SCL SCL MPX SMUTE 220nF AM AM SMUTE LEVEL LEVEL GND D98AUxx5 17/26 TDA7403 I2C BUS INTERFACE DESCRIPTION Interface Protocol The interface protocol comprises: -a start condition (S) -a chip address byte (the LSB bit determines read CHIP ADDRESS MSB S 1 SUBADDRESS LSB 0 0 0 1 1 / write transmission) -a subaddress byte -a sequence of data (N-bytes + acknowledge) -a stop condition (P) DATA 1 to DATA n MSB 0 R/W ACK LSB X AZ T I A3 A2 A1 A0 MSB LSB ACK DATA ACK P D97AU627 S = Start ACK = Acknowledge AZ = AutoZero-Remain T = Testing I = Autoincrement P = Stop MAX CLOCK SPEED 500kbits/s Auto increment If bit I in the subaddress byte is set to ”1”, the autoincrement of the subaddress is enabled. The transmitted data is automatically updated after each ACK. Transmission can be repeated without new chip address. SM = Soft mute activated ST = Stereo X = Not Used TRANSMITTED DATA (send mode) MSB X LSB X X X ST SM X SUBADDRESS (receive mode) MSB X LSB AZ T T = Testmode I = Autoincrement AZ = Auto Zero Remain X = not used 18/26 I A3 A2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FUNCTION Not allowed Loudness / Auto-Zero Volume Softmute / Beep Bass / Treble Attenuator Bass / Treble Configuration Speaker attenuator LF Speaker attenuator LR Speaker attenuator RF Speaker attenuator RR / Blanktime adjust Stereodecoder Noiseblanker Fieldstrength Control Configuration Stereodecoder Adjustment Testing X TDA7403 DATA BYTE SPECIFICATION Input Selector MSB D7 LSB D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 : 1 1 0 0 : 1 1 Source Selector don’t use Cassette don’t use AM Stereo Decoder Input FM Mute don’t use CD Mode CD Full-differential CD Quasi-diff 0 1 0 0 1 1 1 0 0 1 FUNCTION 1 1 0 0 1 1 0 0 AM/FM Mode AM mono AM stereo AM through Stereo/Decoder FM- Stereo/Decoder In-Gain 14dB 12dB : 2 dB 0 dB 0 1 : 0 1 For example to select the CD input in quasi-differential mode with gain of 8dB the Data Byte is: 0/0 1111000 Loudness MSB D7 LSB D6 D5 D4 0 1 0 1 0 1 1 D3 D2 D1 D0 0 0 : 1 1 0 0 : 1 1 0 0 : 1 1 0 1 : 0 1 LOUDNESS Attenuation 0dB -1dB : -14dB -15dB Filter on off (flat) Center Frequency 200Hz 400Hz Loud ness Q low (1st order) nd normal (2 order) must be ”1” Note: The attenuation is specified at high frequencies. Around the center frequency the value is different depending on the programmed attenuation (see Loudness frequency response). 19/26 TDA7403 Mute, Beep and Mixing MSB D7 LSB D6 D5 D4 D3 D2 D1 0 1 0 0 1 1 0 1 0 1 0 1 Mute Enable Softmute Disable Softmute Mute time =0.48 ms Mute time =0.96 ms Mute time =40.4 ms Mute time =324 ms Stereo Decoder Softmute Influence = off Stereo Decoder Softmute Influence = on Beep Beep Frequency = 600Hz Beep Frequency = 1.2KHz Mixing Mix-Source = Beep Mix-Source = Phone Full Mix Signal Source -12dB + Mix-Signal -2.5dB Source -6dB + Mix-Signal -6dB Full Source 0 1 0 1 0 0 1 1 MUTE/BEEP/MIXING D0 0 1 0 1 Note: for more information to the Stereodecoder-Softmute-Influence please refer to the stereodecoder description. Volume MSB D7 0 1 LSB D6 D5 D4 D3 D2 D1 D0 0 0 : 0 0 0 : 0 0 0 : 1 1 0 0 : 0 0 0 : 0 1 1 : 1 1 0 0 : 0 0 0 : 1 0 0 : 0 0 0 0 : 1 1 1 : 1 0 0 : 1 1 0 0 : 1 1 1 : 1 0 0 : 1 1 0 0 : 0 0 1 : 1 0 0 : 1 1 0 1 : 0 1 0 : 1 0 1 : 0 1 ATTENUATION Gain/Attenuation +32dB +31dB : +20dB +19dB +18dB : +1dB 0dB - 1dB : -78dB -79dB Softstep Softstep Volume = off Softstep Volume = on Note: It is not recommended to use a gain more than 20dB for system performance reason. In general, the max. gain should be limited by software to the maximum value, which is needed for the system. 20/26 TDA7403 Bass & Treble Attenuation MSB D7 0 0 : 0 0 1 1 : 1 1 LSB D6 0 0 : 1 1 1 1 : 0 0 D5 0 0 : 1 1 1 1 : 0 0 D4 D3 D2 D1 D0 0 0 : 0 0 1 1 : 1 1 0 0 : 1 1 1 1 : 0 0 0 0 : 1 1 1 1 : 0 0 0 1 : 0 1 1 0 : 1 0 0 1 : 0 1 1 0 : 1 0 BASS & TREBLE ATTENUATION Treble Steps -14dB -12dB : -2dB 0dB 0dB +2dB : +12dB +14dB Bass Steps -14dB -12dB : -2dB 0dB 0dB +2dB : +12dB +14dB For example 12dB Treble and -8dB Bass give the following DATA BYTE : 0 0 1 1 1 0 0 1. Bass & Treble Filter Characteristics MSB D7 LSB D6 D5 1 0 0 1 1 0 1 1 D4 1 0 1 0 1 D3 0 0 1 1 1 D2 0 1 0 1 1 D1 D0 0 0 1 1 0 1 0 1 BASS & TREBLE FILTER Treble Center Frequency = 10 KHz Center Frequency = 12.5 KHz Center Frequency = 15 KHz Center Frequency = 17.5 KHz Bass Center Frequency = 60 Hz Center Frequency = 70 Hz Center Frequency = 80 Hz Center Frequency = 100Hz Center Frequency = 150Hz Quality factor = 1 Quality factor = 1.25 Quality factor = 1.5 Quality factor = 2 DC-Gain = 0dB DC-Gain = ±4.4dB must be ”1” For example Treble center frequency = 15kHz, Bass center frequency = 100Hz, Bass Q = 1 and DC = 0dB give the following DATA BYTE: 1 0 0 0 11 10 21/26 TDA7403 Speaker Attenuation (LF, LR, RF, RR) MSB D7 LSB D6 1 1 0 0 1 1 0 1 0 1 D5 D4 D3 D2 D1 D0 0 0 : 0 0 0 0 0 0 0 0 0 1 0 0 : 1 1 1 1 1 1 1 1 1 0 0 : 0 1 1 1 1 1 1 1 1 0 0 : 1 0 0 0 0 1 1 1 1 0 0 : 1 0 0 1 1 0 0 1 1 0 1 : 1 0 1 0 1 0 1 0 1 D5 D4 D3 D2 D1 Attenuation 0dB -1dB : -23dB -24.5dB -26dB -28dB -30 -32dB -35dB -40dB -50dB Speaker Mute Must be ”1” (except RR speaker; see below) Blank Time adj. (only at RR speaker) 38µs 25.5µs 32µs 22µs Stereodecoder MSB D7 LSB D6 0 1 0 0 1 1 1 1 1 0 1 0 1 22/26 0 1 0 1 0 1 FUNCTION D0 STD Unmuted STD Muted IN-Gain 11dB IN-Gain 8.5dB IN-Gain 6dB IN-Gain 3.5dB must be ”1” Forced MONO MONO/STEREO switch automatically Pilot Threshold HIGH Pilot Threshold LOW Deemphasis 50µs Deemphasis 75µs TDA7403 Noiseblanker MSB D7 LSB D6 D5 D4 0 0 1 1 D3 D2 D1 D0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Low Low Low Low Low Low Low Low Threshold 65mV Threshold 60mV Threshold 55mV Threshold 50mV Threshold 45mV Threshold 40mV Threshold 35mV Threshold 30mV Noise Controlled Threshold 320mV Noise Controlled Threshold 260mV Noise Controlled Threshold 200mV Noise Controlled Threshold 140mV 0 1 0 1 0 1 0 0 1 1 FUNCTION Noise blanker OFF Noise blanker ON Over Over Over Over 0 1 0 1 deviation Adjust 2.8V deviation Adjust 2.0V deviation Adjust 1.2V deviation Detector OFF Fieldstrength Control MSB D7 LSB D6 D5 D4 D3 0 0 1 1 0 0 1 1 1 0 0 1 0 1 0 1 D2 0 1 0 1 D1 D0 0 0 1 1 0 1 0 1 FUNCTION Noiseblanker Field Noiseblanker Field Noiseblanker Field Noiseblanker Field VSBL at 33% VSBL at 42% VSBL at 50% VSBL at 58% VHCH at VHCH at VHCH at VHCH at strength Adj strength Adj strength Adj strength Adj 2.3V 1.8V 1.3V OFF REF 5V REF 5V REF 5V REF 5V 42% REF 5V 50% REF 5V 58% REF 5V 66% REF 5V VHCL at 17% VHCH VHCL at 33% VHCH High cut OFF High cut ON 23/26 TDA7403 Stereodecoder Adjustment MSB D7 LSB D6 0 0 0 : 1 D5 0 0 0 : 1 D4 0 0 1 : 1 D3 D2 D1 D0 0 0 0 : 1 : 1 0 0 1 : 0 : 1 0 1 0 : 0 : 1 FUNCTION Roll-Off Compensation not allowed 20.2% 21.9% : 25.5% : 31.0% LEVEL Gain 0dB 0.66dB 1.33dB : 10dB 0 1 0 : 1 Temperature compensation at LEVEL inpu t TC = 0 TC = 16.7mV/K (3300ppm) 0 1 Testing MSB D7 LSB D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FUNCTION Stereodecoder test signals OFF Test signals enabled if bit D5 of the subaddress (test mode bit) is set to ”1”, too External Clock Internal Clock Testsignals at CASS_R VHCCH Level intern Pilot magnitude VCOCON; VCO Control Voltage Pilot threshold HOLDN NB threshold F228 VHCCL VSBL not used not used PEAK not used REF5V not used VCO OFF ON Audioprocessor test mode only if bit D5 of the subaddress (test mode bit) is set to ”1” OFF Note : This byte is used fortesting or evaluation purposes only and must not be set to other values than the default ”11111110” in the application! 24/26 TDA7403 mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.1 0.3 0.004 0.012 B 0.33 0.51 0.013 0.020 C 0.23 0.32 0.009 0.013 D 12.6 13 0.496 0.512 E 7.4 7.6 0.291 0.299 e 1.27 OUTLINE AND MECHANICAL DATA 0.050 H 10 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.4 1.27 0.016 0.050 SO20 K 0° (min.)8° (max.) L h x 45° A B e A1 K C H D 20 11 E 1 1 0 SO20MEC 25/26 TDA7403 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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