16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S SST34HF16x2x16Mb CSF + 2/4/8 Mb SRAM (x16) MCP ComboMemory Advance Information FEATURES: • Flash Organization: 1M x16 or 2M x8 • Dual-Bank Architecture for Concurrent Read/Write Operation – 16 Mbit: 4 Mbit + 12 Mbit • (P)SRAM Organization: – 2 Mbit: 128K x16 or 256K x8 – 4 Mbit: 256K x16 or 512K x8 – 8 Mbit: 512K x16 or 1024K x8 • Single 2.7-3.3V Read and Write Operations • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption: – Active Current: 25 mA (typical) – Standby Current: 20 µA (typical) • Hardware Sector Protection (WP#) – Protects 4 outer most sectors (4 KWord) in the larger bank by holding WP# low and unprotects by holding WP# high • Hardware Reset Pin (RST#) – Resets the internal state machine to reading data array • Byte Selection for Flash (CIOF pin) – Selects 8-bit or 16-bit mode • Sector-Erase Capability – Uniform 2 KWord sectors • Block-Erase Capability – Uniform 32 KWord blocks • Read Access Time – Flash: 70 ns – (P)SRAM: 70 ns • Erase-Suspend / Erase-Resume Capabilities • Security ID Feature – SST: 128 bits – User: 128 bits • Latched Address and Data • Fast Erase and Word-/Byte-Program (typical): – Sector-Erase Time: 18 ms – Block-Erase Time: 18 ms – Chip-Erase Time: 35 ms – Word-Program Time: 7 µs • Automatic Write Timing – Internal VPP Generation • End-of-Write Detection – Toggle Bit – Data# Polling – Ready/Busy# pin • CMOS I/O Compatibility • JEDEC Standard Command Set • Packages Available – 56-ball LFBGA (8mm x 10mm) – 62-ball LFBGA (8mm x 10mm) PRODUCT DESCRIPTION The SST34HF16x2C/D/S ComboMemory devices integrate either a 1M x16 or 2M x8 CMOS flash memory bank with either a 128K x16/256K x8, 256K x16/512 x8, or 512K x16/1024K x8 CMOS SRAM or pseudo SRAM (PSRAM) memory bank in a multi-chip package (MCP). These devices are fabricated using SST’s proprietary, high-performance CMOS SuperFlash technology incorporating the split-gate cell design and thick-oxide tunneling injector to attain better reliability and manufacturability compared with alternate approaches. The SST34HF16x2C/D/S devices are ideal for applications such as cellular phones, GPS devices, PDAs, and other portable electronic devices in a low power and small form factor system. The SST34HF16x2C/D/S feature dual flash memory bank architecture allowing for concurrent operations between the two flash memory banks and the (P)SRAM. The devices can read data from either bank while an Erase or Program operation is in progress in the opposite bank. The two flash ©2004 Silicon Storage Technology, Inc. S71256-00-000 3/04 1 memory banks are partitioned into 4 Mbit and 12 Mbit with top sector protection options for storing boot code, program code, configuration/parameter data and user data. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore, the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. The SST34HF16x2C/D/S devices offer a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. With high performance Word-Program, the flash memory banks provide a typical Word-Program time of 7 µsec. The entire flash memory bank can be erased and programmed word-by-word in typically 4 seconds for the SST34HF16x2C/D/S, when using interface features such as Toggle Bit, Data# Polling, or RY/ BY# to indicate the completion of Program operation. To The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. Intel is a registered trademark of Intel Corporation. CSF and ComboMemory are trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information Concurrent Read/Write Operation protect against inadvertent flash write, the SST34HF16x2C/D/S devices contain on-chip hardware and software data protection schemes. Dual bank architecture of SST34HF16x2C/D/S devices allows the Concurrent Read/Write operation whereby the user can read from one bank while programming or erasing in the other bank. This operation can be used when the user needs to read system code in one bank while updating data in the other bank. See Figures 1 and 2 for dualbank memory organization. The flash and (P)SRAM operate as two independent memory banks with respective bank enable signals. The memory bank selection is done by two bank enable signals. The (P)SRAM bank enable signals, BES1# and BES2, select the (P)SRAM bank (BES1# and BES2 are NC for SST34HF1602C). The flash memory bank enable signal, BEF#, has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The memory banks are superimposed in the same memory address space where they share common address lines, data lines, WE# and OE# which minimize power consumption and area. CONCURRENT READ/WRITE STATES Flash Bank 1 Bank 2 (P)SRAM Read Write No Operation Write Read No Operation Write No Operation Read No Operation Write Read Write No Operation Write No Operation Write Write Designed, manufactured, and tested for applications requiring low power and small form factor, the SST34HF16x2C/ D/S are offered in both commercial and extended temperatures and a small footprint package to meet board space constraint requirements. See Figures 3 and 4 for pin assignments. Note: For the purposes of this table, write means to Block-, Sector, or Chip-Erase, or Word-/Byte-Program as applicable to the appropriate bank. Device Operation Flash Read Operation The SST34HF16x2C/D/S uses BES1#, BES2 and BEF# to control operation of either the flash or the (P)SRAM memory bank. When BEF# is low, the flash bank is activated for Read, Program or Erase operation. When BES1# is low, and BES2 is high the (P)SRAM is activated for Read and Write operation. BEF# and BES1# cannot be at low level, and BES2 cannot be at high level at the same time. If all bank enable signals are asserted, bus contention will result and the device may suffer permanent damage. All address, data, and control lines are shared by flash and (P)SRAM memory banks which minimizes power consumption and loading. The device goes into standby when BEF# and BES1# bank enables are raised to VIHC (Logic High) or when BEF# is high and BES2 is low. The Read operation of the SST34HF16x2C/D/S is controlled by BEF# and OE#, both have to be low for the system to obtain data from the outputs. BEF# is used for device selection. When BEF# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either BEF# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 8). ©2004 Silicon Storage Technology, Inc. S71256-00-000 2 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information Flash Word-/Byte-Program Operation Flash Chip-Erase Operation These devices are programmed on a word-by-word or byte-by-byte basis depending on the state of the CIOF pin. Before programming, one must ensure that the sector which is being programmed is fully erased. The SST34HF16x2C/D/S provide a Chip-Erase operation, which allows the user to erase all sectors/blocks to the “1” state. This is useful when the device must be quickly erased. The Program operation is accomplished in three steps: The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or BEF#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bits or Data# Polling. See Table 7 for the command sequence, Figure 13 for timing diagram, and Figure 26 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. When WP# is low, any attempt to Chip-Erase will be ignored. 1. Software Data Protection is initiated using the three-byte load sequence. 2. Word address and word data are loaded. During the Word-Program operation, the addresses are latched on the falling edge of either BEF# or WE#, whichever occurs last. The data is latched on the rising edge of either BEF# or WE#, whichever occurs first. 3. The internal Program operation is initiated after the rising edge of the fourth WE# or BEF#, whichever occurs first. The Program operation, once initiated, will be completed typically within 7 µs. Flash Erase-Suspend/-Resume Operations The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an Erase operation. The operation is executed by issuing a one-byte command sequence with Erase-Suspend command (B0H). The device automatically enters read mode within 20 µs after the Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not suspended from an Erase operation. Reading at address location within erase-suspended sectors/blocks will output DQ2 toggling and DQ6 at “1”. While in Erase-Suspend mode, a Word-/Byte-Program operation is allowed except for the sector or block selected for Erase-Suspend. To resume Sector-Erase or Block-Erase operation which has been suspended, the system must issue an Erase-Resume command. The operation is executed by issuing a one-byte command sequence with Erase Resume command (30H) at any address in the one-byte sequence. See Figures 9 and 10 for WE# and BEF# controlled Program operation timing diagrams and Figure 22 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during an internal Program operation are ignored. Flash Sector- (Block-) Erase Operation These devices offer both Sector-Erase and Block-Erase operations. These operations allow the system to erase the devices on a sector-by-sector (or block-by-block) basis. The sector architecture is based on a uniform sector size of 2 KWord. The Block-Erase mode is based on a uniform block size of 32 KWord. The Sector-Erase operation is initiated by executing a six-byte command sequence with a Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. Any commands issued during the Block- or SectorErase operation are ignored except Erase-Suspend and Erase-Resume. See Figures 14 and 15 for timing waveforms. ©2004 Silicon Storage Technology, Inc. S71256-00-000 3 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information Flash Write Operation Status Detection Flash Data# Polling (DQ7) The SST34HF16x2C/D/S provide one hardware and two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The hardware detection uses the Ready/Busy# (RY/BY#) pin. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. When the devices are in an internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or BEF#) pulse for Program operation. For Sector-, Block-, or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or BEF#) pulse. See Figure 11 for Data# Polling (DQ7) timing diagram and Figure 23 for a flowchart. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Ready/Busy# (RY/ BY#), Data# Polling (DQ7) or Toggle Bit (DQ6) read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Toggle Bits (DQ6 and DQ2) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating “1”s and “0”s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. The toggle bit is valid after the rising edge of the fourth WE# (or BEF#) pulse for Program operations. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or BEF#) pulse. DQ6 will be set to “1” if a Read operation is attempted on an Erase-suspended Sector/Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle. Ready/Busy# (RY/BY#) The SST34HF16x2C/D/S include a Ready/Busy# (RY/ BY#) output signal. RY/BY# is an open drain output pin that indicates whether an Erase or Program operation is in progress. Since RY/BY# is an open drain output, it allows several devices to be tied in parallel to VDD via an external pull-up resistor. After the rising edge of the final WE# pulse in the command sequence, the RY/BY# status is valid. An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check whether a particular sector is being actively erased or erase-suspended. Table 1 shows detailed status bit information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or BEF#) pulse of a Write operation. See Figure 12 for Toggle Bit timing diagram and Figure 23 for a flowchart. When RY/BY# is actively pulled low, it indicates that an Erase or Program operation is in progress. When RY/BY# is high (Ready), the devices may be read or left in standby mode. TABLE 1: WRITE OPERATION STATUS Byte/Word (CIOF) Status The device includes a CIOF pin to control whether the device data I/O pins operate x8 or x16. If the CIOF pin is at logic “1” (VIH) the device is in x16 data configuration: all data I/0 pins DQ0-DQ15 are active and controlled by BEF# and OE#. Normal Operation EraseSuspend Mode If the CIOF pin is at logic “0”, the device is in x8 data configuration: only data I/O pins DQ0-DQ7 are active and controlled by BEF# and OE#. The remaining data pins DQ8DQ14 are at Hi-Z, while pin DQ15 is used as the address input A-1 for the Least Significant Bit of the address bus. DQ7 DQ6 DQ2 RY/BY# Standard Program DQ7# Toggle No Toggle 0 Standard Erase 0 Toggle Toggle 0 Read From Erase Suspended Sector/Block 1 1 Toggle 1 Read From Non-Erase Suspended Sector/Block Data Data Data 1 Program DQ7# Toggle N/A 0 T1.0 1256 Note: DQ7, DQ6, and DQ2 require a valid address when reading status information. ©2004 Silicon Storage Technology, Inc. S71256-00-000 4 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information Data Protection Software Data Protection (SDP) The SST34HF16x2C/D/S provide both hardware and software features to protect nonvolatile data from inadvertent writes. The SST34HF16x2C/D/S provide the JEDEC standard Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. The SST34HF16x2C/D/S are shipped with the Software Data Protection permanently enabled. See Table 7 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC. The contents of DQ15DQ8 are “Don’t Care” during any SDP command sequence. Hardware Data Protection Noise/Glitch Protection: A WE# or BEF# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, BEF# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Hardware Block Protection Security ID The SST34HF16x2C/D/S provide a hardware block protection which protects the outermost 8 KWord in Bank 1. The block is protected when WP# is held low. See Figures 1 and 2 for Block-Protection location. The SST34HF16x2C/D/S devices offer a 256-bit Security ID space. The Secure ID space is divided into two 128-bit segments—one factory programmed segment and one user programmed segment. The first segment is programmed and locked at SST with a unique, 128-bit number. The user segment is left un-programmed for the customer to program as desired. To program the user segment of the Security ID, the user must use the Security ID Word-Program command. End-of-Write status is checked by reading the toggle bits. Data# Polling is not used for Security ID End-of-Write detection. Once programming is complete, the Sec ID should be locked using the User-SecID-Program-Lock-Out. This disables any future corruption of this space. Note that regardless of whether or not the Sec ID is locked, neither Sec ID segment can be erased. The Secure ID space can be queried by executing a threebyte command sequence with Query-Sec-ID command (88H) at address 5555H in the last byte sequence. To exit this mode, the Exit-Sec-ID command should be executed. Refer to Table 7 for more details. A user can disable block protection by driving WP# high thus allowing erase or program of data into the protected sectors. WP# must be held high prior to issuing the write command and remain stable until after the entire Write operation has completed. Hardware Reset (RST#) The RST# pin provides a hardware method of resetting the device to read array data. When the RST# pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode (see Figure 19). When no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST# is driven high before a valid Read can take place (see Figure 18). The Erase operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity. See Figures 18 and 19 for timing diagrams. ©2004 Silicon Storage Technology, Inc. S71256-00-000 5 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information Product Identification (P)SRAM Operation The Product Identification mode identifies the device as the SST34HF16x2C/D/S and manufacturer as SST. This mode may be accessed by software operations only. The hardware device ID Read operation, which is typically used by programmers cannot be used on this device because of the shared lines between flash and (P)SRAM in the multichip package. Therefore, application of high voltage to pin A9 may damage this device. Users may use the software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Tables 4 and 7 for software operation, Figure 16 for the Software ID Entry and Read timing diagram and Figure 24 for the ID Entry command sequence flowchart. With BES1# low, BES2 and BEF# high, the SST34HF16x2C/D/S operate as either 128K x16, 256K x16, or 512K x16 CMOS (P)SRAM, with fully static operation requiring no external clocks or timing strobes. The SST34HF16x2C/D/S (P)SRAM is mapped into the first 512 KWord address space. When BES1#, BEF# are high and BES2 is low, all memory banks are deselected and the device enters standby. Read and Write cycle times are equal. The control signals UBS# and LBS# provide access to the upper data byte and lower data byte (UBS# and LBS# signals are NC for SST3416x2S parts). See Table 4 for x16 (P)SRAM Read and Write data byte control modes of operation. See Table 5 for x8 SRAM Read and Write data byte control modes of operation. TABLE 2: PRODUCT IDENTIFICATION (P)SRAM Read Manufacturer’s ID ADDRESS DATA BK0000H 00BFH BK0001H 734AH The (P)SRAM Read operation of the SST34HF16x2C/D/S is controlled by OE# and BES1#, both have to be low with WE# and BES2 high for the system to obtain data from the outputs. BES1# and BES2 are used for (P)SRAM bank selection. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to the Read cycle timing diagram, Figure 5, for further details. Device ID SST34HF16x2C/D/S T2.0 1256 Note: BK = Bank Address (A19-A18) Product Identification Mode Exit (P)SRAM Write In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit command is ignored during an internal Program or Erase operation. See Table 7 for software command codes, Figure 17 for timing waveform and Figure 24 for a flowchart. The (P)SRAM Write operation of the SST34HF16x2C/D/S is controlled by WE# and BES1#, both have to be low, BES2 must be high for the system to write to the (P)SRAM. During the Word-Write operation, the addresses and data are referenced to the rising edge of either BES1#, WE#, or the falling edge of BES2 whichever occurs first. The write time is measured from the last falling edge of BES#1 or WE# or the rising edge of BES2 to the first rising edge of BES1#, or WE# or the falling edge of BES2. Refer to the Write cycle timing diagrams, Figures 6 and 7, for further details. ©2004 Silicon Storage Technology, Inc. S71256-00-000 6 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information FUNCTIONAL BLOCK DIAGRAM Address Buffers AMS1- A0 SA 5 SuperFlash Memory (Bank 1) RST# BEF# WP# LBS#3 UBS#3 WE#2 OE#2 BES1#4 BES24 RY/BY# SuperFlash Memory (Bank 2) Control Logic I/O Buffers Address Buffers DQ15/A-1 - DQ0 2 / 4 / 8 Mbit SRAM or PSRAM 1256 B1.0 Notes: 1. AMS = Most significant address 2. For LS package only: WE# = WEF# and/or WES# OE# = OEF# and/or OES# 3. For SST34FH16x2S, LBS# and UBS# are No Connect. 4. For SST34HF1602C, BES1#, BES2, SA, LBS#, and UBS# are No Connect 5. Additional Address for x8 SRAM ©2004 Silicon Storage Technology, Inc. S71256-00-000 7 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information Top Block Protection; 32 KWord Blocks; 2 KWord Sectors 8 KWord Block Protection (4 - 2 KWord Sectors) Block 31 Block 30 Block 29 Block 28 Block 27 Block 26 Block 25 Block 24 Block 23 Block 22 Block 21 Block 20 Block 19 Bank 2 Block 18 Block 17 Block 16 Block 15 Block 14 Block 13 Block 12 Block 11 Block 10 Block 9 Block 8 Block 7 Block 6 Block 5 Block 4 Block 3 Bank 1 FFFFFH FE000H FDFFFH F8000H F7FFFH F0000H EFFFFH E8000H E7FFFH E0000H DFFFFH D8000H D7FFFH D0000H CFFFFH C8000H C7FFFH C0000H BFFFFH B8000H B7FFFH B0000H AFFFFH A8000H A7FFFH A0000H 9FFFFH 98000H 97FFFH 90000H 8FFFFH 88000H 87FFFH 80000H 7FFFFH 78000H 77FFFH 70000H 6FFFFH 68000H 67FFFH 60000H 5FFFFH 58000H 57FFFH 50000H 4FFFFH 48000H 47FFFH 40000H 3FFFFH 38000H 37FFFH 30000H 2FFFFH 28000H 27FFFH 20000H 1FFFFH 18000H 17FFFH 10000H 0FFFFH 08000H 07FFFH 00000H Block 2 Block 1 Block 0 1256 F01.0 Note: The address input range in x16 mode (BYTE#=VIH) is A19-A0 FIGURE 1: SST34HF16X2C/D, CONCURRENT SUPERFLASH DUAL-BANK MEMORY ORGANIZATION ©2004 Silicon Storage Technology, Inc. S71256-00-000 8 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information Top Block Protection; 64 KByte Blocks; 4 KByte Sectors 16 KByte Block Protection (4 - 4 KByte Sectors) Block 31 Block 30 Block 29 Block 28 Block 27 Block 26 Block 25 Block 24 Block 23 Block 22 Block 21 Block 20 Block 19 Bank 2 Block 18 Block 17 Block 16 Block 15 Block 14 Block 13 Block 12 Block 11 Block 10 Block 9 Block 8 Block 7 Block 6 Block 5 Block 4 Block 3 Bank 1 1FFFFFH 1FC000H 1FBFFFH 1F0000H 1EFFFFH 1E0000H 1DFFFFH 1D0000H 1CFFFFH 1C0000H 1BFFFFH 1B0000H 1AFFFFH 1A0000H 19FFFFH 190000H 18FFFFH 180000H 17FFFFH 170000H 16FFFFH 160000H 15FFFFH 150000H 14FFFFH 140000H 13FFFFH 130000H 12FFFFH 120000H 11FFFFH 110000H 10FFFFH 100000H 0FFFFFH 0F0000H 0EFFFFH 0E0000H 0DFFFFH 0D0000H 0CFFFFH 0C0000H 0BFFFFH 0B0000H 0AFFFFH 0A0000H 09FFFFH 090000H 08FFFFH 080000H 07FFFFH 070000H 06FFFFH 060000H 05FFFFH 050000H 04FFFFH 040000H 03FFFFH 030000H 02FFFFH 020000H 01FFFFH 010000H 00FFFFH 000000H Block 2 Block 1 Block 0 1256 F01b.0 Note: The address input range in x8 mode (BYTE#=VIL) is A19-A-1 FIGURE 2: SST34HF16X2S, 2M X8 CONCURRENT SUPERFLASH DUAL-BANK MEMORY ORGANIZATION ©2004 Silicon Storage Technology, Inc. S71256-00-000 9 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information TOP VIEW (balls facing down) 6 5 4 3 A11 A8 A12 A19 NC A13 A9 NC A14 A10 A16 CIOF 7 NC NOTE* DQ7 DQ14 5 DQ4 VDDS NC WP# RST# RY/BY# 4 DQ3 VDDF DQ11 A17 DQ1 DQ9 DQ10 DQ2 2 A7 A6 A5 A4 VSS OE# DQ0 DQ8 1 A A3 A2 A1 A0 B C D E BEF# BES1# F G A15 NC NC A16 CIOF VSS A11 A12 A13 A14 SA DQ7 DQ14 A8 A19 A9 A10 6 DQ6 DQ13 DQ12 DQ5 WE# BES2 NC LBS# UBS# A18 8 VSS NOTE* DQ6 DQ13 DQ12 DQ5 WE# BES2 NC DQ4 VDDS NC WP# RST# RY/BY# DQ3 VDDF DQ11 3 NC NC A18 A17 DQ1 DQ9 DQ10 DQ2 A7 A6 A5 A4 VSS OE# A3 A2 A1 A0 B C D E 2 DQ0 DQ8 1 H A Note* = DQ15/A-1 BEF# BES1# F G 1256 56-lfbga P1b.0 7 A15 1256 56-lfbga P1a.0 8 TOP VIEW (balls facing down) H Note* = DQ15/A-1 SST34HF1622S / SST34HF1642S SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D Note: 1. For SST34HF1602C, VDDS, SA, BES2, and BES1# are No Connect. FIGURE 3: PIN ASSIGNMENTS FOR 56-BALL LFBGA (8MM X 10MM) TOP VIEW (balls facing down) 8 NC 7 NC A11 A15 A14 A16 A8 A10 A9 A13 A12 VSSF NC NC DQ15 WES# DQ14 DQ7 6 WEF# RY/BY# DQ13 DQ6 VSSS RST# DQ12 BES2 VDDS VDDF DQ4 DQ5 5 WP# NC A19 DQ11 DQ10 DQ2 DQ3 DQ9 DQ8 DQ0 DQ1 A3 A2 A1 BES1# 3 LBS# UBS# OES# 2 1 A18 A17 A7 A6 NC NC A5 A4 A0 A B C D E BEF# VSSF OEF# F G NC NC J K H 1256 62-lfbga P2.0 4 SST34HF16x2C/D Note: 1. For SST34HF1602C, VSSS, VDDS, WES#, BES2, OES#, UBS#, LBS#, and BES1# are No Connect. FIGURE 4: PIN ASSIGNMENTS FOR 62-BALL LFBGA (8MM ©2004 Silicon Storage Technology, Inc. X 10MM) S71256-00-000 10 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information TABLE 3: PIN DESCRIPTION Symbol Pin Name AMS1 to A0 Address Inputs SA SRAM x8 Address Functions To provide flash address, A19-A0. To provide (P)SRAM address, AMS-A0 To provide additional address for x8 SRAM DQ14-DQ0 Data Inputs/Outputs To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a flash Erase/Program cycle. The outputs are in tri-state when OE# is high or BES1# is high or BES2 is low and BEF# is high. DQ15/A-1 Data Input/Output and LBS Address DQ15 is used as data I/O pin when in x16 mode (CIOF = “1”) A-1 is used as the LBS address pin when in x8 mode (CIOF = “0”) BEF# Flash Memory Bank Enable To activate the Flash memory bank when BEF# is low BES1# (P)SRAM Memory Bank Enable To activate the (P)SRAM memory bank when BES1# is low BES2 (P)SRAM Memory Bank Enable To activate the (P)SRAM memory bank when BES2 is high OEF#2 Output Enable To gate the data output buffers for Flash2 only OES#2 Output Enable To gate the data output buffers for SRAM2 only WEF#2 Write Enable To control the Write operations for Flash2 only WES#2 Write Enable To control the Write operations for SRAM2 only OE# Output Enable To gate the data output buffers WE# Write Enable To control the Write operations CIOF Byte Selection for Flash When low, select Byte mode. When high, select Word mode. UBS# Upper Byte Control ((P)SRAM) To enable DQ15-DQ8 LBS# Lower Byte Control ((P)SRAM) To enable DQ7-DQ0 WP# Write Protect To protect and unprotect the top 8 KWord (4 sectors) from Erase or Program operation RST# Reset To Reset and return the device to Read mode RY/BY# Ready/Busy# To output the status of a Program or Erase Operation RY/BY# is a open drain output, so a 10KΩ - 100KΩ pull-up resistor is required to allow RY/BY# to transition high indicating the device is ready to read. VSSF2 Ground Flash2 only VSSS2 Ground SRAM2 only VSS Ground VDDF VDDS Power Supply (Flash) Power Supply ((P)SRAM) 2.7-3.3V Power Supply to (P)SRAM only NC No Connection Unconnected pins 2.7-3.3V Power Supply to Flash only T3.0 1256 1. AMS = Most Significant Address AMS = A16 for SST34HF1622C/S, A17 for SST34HF1642C/D/S, and A18 for SST34HF1682D 2. LS package only ©2004 Silicon Storage Technology, Inc. S71256-00-000 11 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information TABLE 4: OPERATIONAL MODES SELECTION FOR X16 (P)SRAM DQ15-8 BEF#1 BES1#1,2 BES21,2 OE#2,3 WE#2,3 LBS#2 UBS#2 DQ7-0 CIOF = VIH CIOF = VIL Full Standby VIH VIH X X X X X HIGH-Z HIGH-Z HIGH-Z X VIL X X X X Output Disable VIH VIL VIH VIH VIH X X HIGH-Z HIGH-Z HIGH-Z VIL VIH X X VIH VIH VIL VIH X VIH VIH X X HIGH-Z HIGH-Z HIGH-Z X VIL VIL VIH X VIL VIH X X DOUT DOUT X VIL DQ14-8 = HIGH-Z DQ15 = A-1 VIH VIL X X DIN DIN DQ14-8 = HIGH-Z DQ15 = A-1 VIH VIL X X X X X VIL VIH VIL VIL DOUT DOUT DOUT VIH VIL HIGH-Z DOUT DOUT VIL VIH DOUT HIGH-Z HIGH-Z Mode Flash Read Flash Write VIL VIH X X VIL Flash Erase VIL VIH X X VIL VIL VIH (P)SRAM Read (P)SRAM Write Product Identification4 VIH VIH VIL VIL VIH VIH VIL X VIL VIL VIH VIL VIL DIN DIN DIN VIH VIL HIGH-Z DIN DIN VIL VIH DIN HIGH-Z HIGH-Z X X Manufacturer’s ID5 Device ID5 T4.0 1256 1. Do not apply BEF# = VIL, BES1# = VIL and BES2 = VIH at the same time 2. X can be VIL or VIH, but no other value. 3. OE# = OEF# and OES# WE# = WEF# and WES# for LS package only 4. Software mode only 5. With A19-A18 = VIL; SST Manufacturer’s ID = BFH, is read with A0=0, SST34HF16x2C/D/S Device ID = 734AH, is read with A0=1 ©2004 Silicon Storage Technology, Inc. S71256-00-000 12 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information TABLE 5: OPERATIONAL MODES SELECTION FOR X8 SRAM DQ15-8 BEF#1 BES1#1,2 BES21,2 OE#2 WE#2 SA2 DQ7-0 CIOF = VIH CIOF = VIL Full Standby VIH VIH X X X X HIGH-Z HIGH-Z HIGH-Z X VIL X X X Output Disable VIH VIL VIH VIH VIH X HIGH-Z HIGH-Z HIGH-Z VIL VIH X X VIH VIL VIH X VIH VIH X HIGH-Z HIGH-Z HIGH-Z X VIL VIL VIH X VIL VIH X DOUT DOUT X VIL DQ14-8 = HIGH-Z DQ15 = A-1 VIH VIL X DIN DIN DQ14-8 = HIGH-Z DQ15 = A-1 VIH VIL X X X X VIL VIH SA DOUT HIGH-Z HIGH-Z HIGH-Z Mode Flash Read Flash Write VIL VIH X X VIL Flash Erase VIL VIH X X VIL VIL VIH SRAM Read VIH SRAM Write VIH VIL VIH X VIL SA DIN HIGH-Z Product Identification3 VIL VIH VIL VIL VIH X Manufacturer’s ID4 Device ID4 Manufacturer’s ID4 Device ID4 T5.0 1256 1. 2. 3. 4. Do not apply BEF# = VIL, BES1# = VIL and BES2 = VIH at the same time X can be VIL or VIH, but no other value. Software mode only With A19-A18 = VIL; SST Manufacturer’s ID = BFH, is read with A0=0, SST34HF16x2C/D/S Device ID = 734AH, is read with A0=1, for x8 A-1 will not be part of the Device ID TABLE 6: OPERATIONAL MODES SELECTION FOR 0 MBIT SRAM: SST34HF1602C DQ15-8 BEF# OE#1,2 Full Standby VIH X X X Output Disable VIH VIH VIH X X VIL VIH VIH HIGH-Z HIGH-Z HIGH-Z Flash Read VIL VIL VIH DOUT DOUT DQ14-8 = HIGH-Z DQ15 = A-1 Flash Write VIL VIH VIL DIN DIN DQ14-8 = HIGH-Z Mode WE#1,2 DQ7-0 CIOF = VIH CIOF = VIL X HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z DQ15 = A-1 Flash Erase VIL VIH VIL X X Product Identification3 VIL VIL VIH Manufacturer’s ID4 Device ID4 Manufacturer’s ID4 Device ID4 X T6.0 1256 1. 2. 3. 4. X can be VIL or VIH, but no other value. OE# = OEF#, WE# = WEF# Software mode only With A19-A18 = VIL; SST Manufacturer’s ID = BFH, is read with A0=0, SST34HF1602C Device ID = 734AH, is read with A0=1, for x8 A-1 will not be part of the Device ID ©2004 Silicon Storage Technology, Inc. S71256-00-000 13 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information TABLE 7: SOFTWARE COMMAND SEQUENCE Command Sequence 1st Bus Write Cycle 2nd Bus Write Cycle 3rd Bus Write Cycle 4th Bus Write Cycle Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Word-/Byte-Program 5555H AAH 2AAAH 55H 5555H A0H WA3 Data Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 5th Bus Write Cycle 6th Bus Write Cycle Addr1 Data2 Addr1 Data2 2AAAH 55H SAX4 30H 50H 10H Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BAX4 Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H Erase-Suspend XXXXH B0H Erase-Resume XXXXH 30H ID5 Query Sec 5555H AAH 2AAAH 55H 5555H 88H User Security ID Word-/Byte-Program 5555H AAH 2AAAH 55H 5555H A5H SIWA6 Data User Security ID Program Lock-out7 5555H AAH 2AAAH 55H 5555H 85H XXH 0000H Software ID Entry8 5555H AAH 2AAAH 55H BKX9 5555H 90H Software ID Exit/ Sec ID Exit10,11 5555H AAH 2AAAH 55H 5555H F0H Software ID Exit/ Sec ID Exit10,11 XXH F0H T7.0 1256 1. Address format A14-A0 (Hex), Addresses A19-A15 can be VIL or VIH, but no other value, for the command sequence when in x16 mode. When in x8 mode, Addresses A19-A15, Address A-1 and DQ14-DQ8 can be VIL or VIH, but no other value, for the command sequence. 2. DQ15-DQ8 can be VIL or VIH, but no other value, for the command sequence 3. WA = Program word/byte address 4. SAX for Sector-Erase; uses A19-A10 address lines BAX for Block-Erase; uses A19-A15 address lines 5. For SST34HF16x2C/D/S, SST ID is read with A3 = 0 (Address range = 00000H to 00007H), User ID is read with A3 = 1 (Address range = 00010H to 00017H). Lock Status is read with A7-A0 = 000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0. 6. SIWA = User Security ID Program word/byte address For SST34HF16x2C/D/S, valid Word-Addresses for User Sec ID are from C0010H-C0017H. All 4 cycles of User Security ID Word-Program and Program Lock-out must be completed before going back to Read-Array mode. 7. The User Security ID Program Lock-out command must be executed in x16 mode (BYTE#=VIH). 8. The device does not remain in Software Product Identification mode if powered down. 9. A19 and A18 = VIL 10. Both Software ID Exit operations are equivalent 11. If users never lock after programming, User Sec ID can be programmed over the previously unprogrammed bits (data=1) using the User Sec ID mode again (the programmed “0” bits cannot be reversed to “1”). For SST34HF16x2C/D/S, valid Word-Addresses for User Sec ID are from C0010H-C0017H. ©2004 Silicon Storage Technology, Inc. S71256-00-000 14 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD1+0.3V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD1+1.0V Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. VDD = VDDF and VDDS 2. Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE Range Ambient Temp Commercial Extended AC CONDITIONS OF VDD 0°C to +70°C 2.7-3.3V -20°C to +85°C 2.7-3.3V TEST Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF See Figures 20 and 21 ©2004 Silicon Storage Technology, Inc. S71256-00-000 15 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information TABLE 8: DC OPERATING CHARACTERISTICS (VDD = VDDF AND VDDS = 2.7-3.3V) Limits Symbol Parameter IDD1 Active VDD Current Min Max Units Test Conditions Address input = VILT/VIHT, at f=1/TRC Min, VDD=VDD Max, all DQs open Read OE#=VIL, WE#=VIH Flash 35 mA BEF#=VIL, BES1#=VIH, or BES2=VIL (P)SRAM 30 mA BEF#=VIH, BES1#=VIL , BES2=VIH 60 mA BEF#=VIH, BES1#=VIL , BES2=VIH Concurrent Operation Write2 WE#=VIL Flash 40 mA BEF#=VIL, BES1#=VIH, or BES2=VIL, OE#=VIH (P)SRAM 30 mA BEF#=VIH, BES1#=VIL , BES2=VIH 30 85 µA µA VDD = VDD Max, BEF#=BES1#=VIHC, BES2=VILC 30 µA RST#=GND ISB Standby VDD Current SRAM PSRAM IRT Reset VDD Current ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max ILIW Input Leakage Current on WP# pin and RST# pin 10 µA WP#=GND to VDD, VDD=VDD Max RST#=GND to VDD, VDD=VDD Max ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max VIL Input Low Voltage 0.8 V VDD=VDD Min VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max VIH Input High Voltage 0.7 VDD V VDD=VDD Max VIHC Input High Voltage (CMOS) VDD-0.3 VOLF Flash Output Low Voltage VOHF Flash Output High Voltage VOLS (P)SRAM Output Low Voltage VOHS (P)SRAM Output High Voltage V VDD=VDD Max 0.2 V IOL=100 µA, VDD=VDD Min V IOH=-100 µA, VDD=VDD Min 0.4 V IOL =1 mA, VDD=VDD Min V IOH =-500 µA, VDD=VDD Min VDD-0.2 2.2 T8.0 1256 1. Address input = VILT/VIHT, VDD=VDD Max (See Figure 20) 2. IDD active while Erase or Program is in progress. ©2004 Silicon Storage Technology, Inc. S71256-00-000 16 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information TABLE 9: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter Minimum Units TPU-READ1 Power-up to Read Operation 100 µs Power-up to Write Operation 100 µs TPU-WRITE 1 T9.0 1256 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 10: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum CI/O1 I/O Pin Capacitance VI/O = 0V 20 pF Input Capacitance VIN = 0V 16 pF CIN 1 T10.0 1256 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 11: FLASH RELIABILITY CHARACTERISTICS Symbol NEND 1 Parameter Minimum Specification Units Endurance 10,000 Cycles JEDEC Standard A117 100 Years JEDEC Standard A103 100 + IDD mA TDR1 Data Retention ILTH1 Latch Up Test Method JEDEC Standard 78 T11.0 1256 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2004 Silicon Storage Technology, Inc. S71256-00-000 17 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information AC CHARACTERISTICS TABLE 12: (P)SRAM READ CYCLE TIMING PARAMETERS Min Max Units 70 ns TRCS Read Cycle Time TAAS Address Access Time TBES Bank Enable Access Time 70 ns TOES Output Enable Access Time 35 ns TBYES UBS#, LBS# Access Time TBLZS1 BES# to Active Output 0 ns TOLZS1 Output Enable to Active Output 0 ns TBYLZS1 UBS#, LBS# to Active Output 0 ns TBHZS 1 70 ns 70 ns BES# to High-Z Output 25 ns TOHZS1 Output Disable to High-Z Output 25 ns TBYHZS1 UBS#, LBS# to High-Z Output TOHS Output Hold from Address Change 35 10 ns ns T12.0 1256 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 13: (P)SRAM WRITE CYCLE TIMING PARAMETERS Symbol Parameter Min TWCS Write Cycle Time 70 Max Units TBWS Bank Enable to End-of-Write 60 ns TAWS Address Valid to End-of-Write 60 ns TASTS Address Set-up Time 0 ns TWPS Write Pulse Width 60 ns TWRS Write Recovery Time 0 ns TBYWS UBS#, LBS# to End-of-Write 60 ns TODWS Output Disable from WE# Low TOEWS Output Enable from WE# High 0 TDSS Data Set-up Time 30 ns TDHS Data Hold from Write Time 0 ns ns 30 ns ns T13.0 1256 ©2004 Silicon Storage Technology, Inc. S71256-00-000 18 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information TABLE 14: FLASH READ CYCLE TIMING PARAMETERS VDD = 2.7-3.3V Symbol Parameter Min TRC Read Cycle Time 70 Max Units TCE Chip Enable Access Time 70 ns TAA Address Access Time 70 ns TOE Output Enable Access Time TCLZ1 BEF# Low to Active Output 0 TOLZ1 OE# Low to Active Output 0 TCHZ1 BEF# High to High-Z Output TOHZ1 TOH1 TRP1 TRHR1 TRY1,2 OE# High to High-Z Output ns 35 Output Hold from Address Change ns ns ns 20 ns 20 ns 0 ns RST# Pulse Width 500 ns RST# High Before Read 50 ns RST# Pin Low to Read 20 µs T14.0 1256 1. This parameter is measured only for initial qualification and after the design or process change that could affect this parameter. 2. This parameter applies to Sector-Erase, Block-Erase and Program operations. This parameter does not apply to Chip-Erase. TABLE 15: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol Parameter Min Max TBP Word-Program Time TAS Address Setup Time 0 ns TAH Address Hold Time 40 ns TCS WE# and BEF# Setup Time 0 ns TCH WE# and BEF# Hold Time 0 ns TOES OE# High Setup Time 0 ns TOEH OE# High Hold Time 10 ns TCP BEF# Pulse Width 40 ns TWP WE# Pulse Width 40 ns TWPH1 WE# Pulse Width High 30 ns TCPH 1 10 Units µs BEF# Pulse Width High 30 ns TDS Data Setup Time 30 ns TDH1 Data Hold Time 0 TIDA1 Software ID Access and Exit Time TES Erase-Suspend Latency TBY1,2 RY/BY# Delay Time TBR 1 ns 150 ns 20 µs 90 ns Bus# Recovery Time 1 µs TSE Sector-Erase 25 ms TBE Block-Erase 25 ms TSCE Chip-Erase 50 ms T15.0 1256 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. This parameter applies to Sector-Erase, Block-Erase, and Program operations. This parameter does not apply to Chip-Erase operations. ©2004 Silicon Storage Technology, Inc. S71256-00-000 19 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information TRCS ADDRESSES AMSS-0 TOHS TAAS BES1# TBES BES2 TBES TBLZS TBHZS TOES OE# TOLZS TOHZS TBYES UBS#, LBS# TBYLZS TBYHZS DQ15-0 DATA VALID 1256 F04.0 Note: AMSS = Most Significant Address AMSS = A16 for SST34HF1622C/S, A17 for SST34HF1622C/D/S, and A18 for SST34HF1682D For SST34HF16x2S, LBS# and UBS# are No Connect and in x8 mode, the additional SRAM address is SA. FIGURE 5: (P)SRAM READ CYCLE TIMING DIAGRAM TWCS ADDRESSES AMSS3-0 TASTS TWPS TWRS WE# TAWS TBWS BES1# TBWS BES2 TBYWS UBS#, LBS# TODWS DQ15-8, DQ7-0 TDSS NOTE 2 TOEWS TDHS NOTE 2 VALID DATA IN 1256 F05.0 Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance. 2. If BES1# goes Low or BES2 goes high coincident with or after WE# goes Low, the output will remain at high impedance. If BES1# goes High or BES2 goes low coincident with or before WE# goes High, the output will remain at high impedance. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied. 3. AMSS = Most Significant SRAM Address AMSS = A16 for SST34HF1622C/S, A17 for SST34HF1622C/D/S, and A18 for SST34HF1682D For SST34HF16x2S, LBS# and UBS# are No Connect and in x8 mode, the additional SRAM address is SA. FIGURE 6: (P)SRAM WRITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)1 ©2004 Silicon Storage Technology, Inc. S71256-00-000 20 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information TWCS ADDRESSES AMSS3-0 TWPS TWRS WE# TBWS BES1# TBWS BES2 TAWS TASTS TBYWS UBS#, LBS# TDSS DQ15-8, DQ7-0 NOTE 2 TDHS VALID DATA IN NOTE 2 1256 F06.0 Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance. 2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied. 3. AMSS = Most Significant SRAM Address AMSS = A16 for SST34HF1622C, A17 for SST34HF1622C/D, and A18 for SST34HF1682D FIGURE 7: (P)SRAM WRITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROLLED)1 X16 (P)SRAM ONLY ©2004 Silicon Storage Technology, Inc. S71256-00-000 21 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information TRC TAA ADDRESS A19-0 TCE BEF# TOE OE# TOHZ TOLZ VIH WE# HIGH-Z DQ15-0 TCHZ TOH TCLZ HIGH-Z DATA VALID DATA VALID 1256 F07.0 FIGURE 8: FLASH READ CYCLE TIMING DIAGRAM FOR WORD MODE (FOR BYTE MODE A-1 = ADDRESS INPUT) TBP 5555 TAH ADDRESS A19-0 2AAA 5555 ADDR TWP WE# TAS TWPH OE# TCH BEF# TCS TBY RY/BY# TBR TDS TDH DQ15-0 XXAA XX55 XXA0 VALID DATA WORD (ADDR/DATA) 1256 F08.0 Note: X can be VIL or VIH, but no other value. FIGURE 9: FLASH WE# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM (FOR BYTE MODE A-1 = ADDRESS INPUT) ©2004 Silicon Storage Technology, Inc. FOR WORD MODE S71256-00-000 22 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information TBP 5555 TAH ADDRESS A19-0 2AAA 5555 ADDR TCP BEF# TAS TCPH OE# TCH WE# TCS TBY RY/BY# TBR TDS TDH DQ15-0 XXAA XX55 XXA0 VALID DATA WORD (ADDR/DATA) 1256 F09.0 Note: X can be VIL or VIH, but no other value. FIGURE 10: FLASH BEF# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM (FOR BYTE MODE A-1 = ADDRESS INPUT) FOR WORD MODE ADDRESS A19-0 TCE BEF# TOES TOEH OE# TOE WE# TBY RY/BY# DQ7 DATA DATA# DATA# DATA 1256 F10.0 FIGURE 11: FLASH DATA# POLLING TIMING DIAGRAM FOR WORD MODE (FOR BYTE MODE A-1 = ADDRESS INPUT) ©2004 Silicon Storage Technology, Inc. S71256-00-000 23 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information ADDRESS A19-0 TCE BEF# TOEH TOE OE# WE# TBR DQ6 VALID DATA TWO READ CYCLES WITH SAME OUTPUTS 1256 F11.0 FIGURE 12: FLASH TOGGLE BIT TIMING DIAGRAM FOR WORD MODE (FOR BYTE MODE A-1 = DON’T CARE) TSCE SIX-BYTE CODE FOR CHIP-ERASE ADDRESS A19-0 5555 2AAA 5555 5555 2AAA 5555 BEF# OE# TWP WE# TBY TBR RY/BY# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX10 VALID 1256 F12.0 Note: This device also supports BEF# controlled Chip-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 15.) X can be VIL or VIH, but no other value. FIGURE 13: FLASH WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM (FOR BYTE MODE A-1 = DON’T CARE) ©2004 Silicon Storage Technology, Inc. FOR WORD MODE S71256-00-000 24 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information TBE SIX-BYTE CODE FOR BLOCK-ERASE ADDRESS A19-0 5555 2AAA 5555 5555 2AAA BAX BEF# OE# TWP WE# TBR TBY RY/BY# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX50 VALID 1256 F13.0 Note: This device also supports BEF# controlled Block-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 15.) BAX = Block Address X can be VIL or VIH, but no other value. FIGURE 14: FLASH WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM (FOR BYTE MODE A-1 = DON’T CARE) FOR WORD MODE SIX-BYTE CODE FOR SECTOR-ERASE ADDRESS A19-0 5555 2AAA 5555 5555 2AAA TSE SAX BEF# OE# TWP WE# TBY TBR RY/BY# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX30 VALID 1256 F14.0 Note: This device also supports BEF# controlled Sector-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 15.) SAX = Sector Address X can be VIL or VIH, but no other value. FIGURE 15: FLASH WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM (FOR BYTE MODE A-1 = DON’T CARE) ©2004 Silicon Storage Technology, Inc. FOR WORD MODE S71256-00-000 25 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information Three-Byte Sequence For Software ID Entry 5555 ADDRESS A14-0 2AAA 5555 0000 0001 BEF# OE# TIDA TWP WE# TWPH DQ15-0 XXAA TAA XX55 XX90 00BF Device ID 1256 F15.0 Note: X can be VIL or VIH, but no other value. Device ID - 734AH for SST34HF16x2C/DS FIGURE 16: FLASH SOFTWARE ID ENTRY (FOR BYTE MODE A-1 = 0) AND READ FOR WORD MODE Three-Byte Sequence for Software ID Exit and Reset 5555 ADDRESS A14-0 DQ15-0 XXAA 2AAA 5555 XX55 XXF0 TIDA BEF# OE# TWP WE# TWHP 1256 F16.0 Note: X can be VIL or VIH, but no other value FIGURE 17: FLASH SOFTWARE ID EXIT (FOR BYTE MODE A-1 = 0) FOR WORD MODE ©2004 Silicon Storage Technology, Inc. S71256-00-000 26 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information RY/BY# 0V TRP RST# BEF#/OE# TRHR FIGURE 18: RST# TIMING (WHEN 1256 F17.0 NO INTERNAL OPERATION IS IN PROGRESS) TRY RY/BY# RST# TRP BEF# TBR OE# 1256 F18.0 FIGURE 19: RST# TIMING (DURING SECTOR- OR BLOCK-ERASE ©2004 Silicon Storage Technology, Inc. OPERATION) S71256-00-000 27 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 1256 F19.0 AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 20: AC INPUT/OUTPUT REFERENCE WAVEFORMS TO TESTER TO DUT CL 1256 F20.0 FIGURE 21: A TEST LOAD EXAMPLE ©2004 Silicon Storage Technology, Inc. S71256-00-000 28 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information Start Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH Load data: XXA0H Address: 5555H Load Word Address/Word Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 1256 F21.0 Note: X can be VIL or VIH, but no other value. FIGURE 22: WORD-PROGRAM ALGORITHM ©2004 Silicon Storage Technology, Inc. S71256-00-000 29 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information Internal Timer Toggle Bit Data# Polling Program/Erase Initiated Program/Erase Initiated Program/Erase Initiated Wait TBP, TSCE, TSE or TBE Read word Read DQ7 Read same word Program/Erase Completed No Is DQ7 = true data? Yes No Does DQ6 match? Program/Erase Completed Yes Program/Erase Completed 1256 F22.0 FIGURE 23: WAIT OPTIONS ©2004 Silicon Storage Technology, Inc. S71256-00-000 30 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information Software Product ID Entry Command Sequence Software ID Exit Command Sequence Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX90H Address: 5555H Load data: XXF0H Address: 5555H Wait TIDA Wait TIDA Read Software ID Return to normal operation 1256 F23.0 Note: X can be VIL or VIH, but no other value. FIGURE 24: SOFTWARE PRODUCT ID COMMAND FLOWCHARTS ©2004 Silicon Storage Technology, Inc. S71256-00-000 31 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information Sec ID Query Entry Command Sequence Sec ID Exit Command Sequence Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XXF0H Address: XXH Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Wait TIDA Load data: XX88H Address: 5555H Load data: XXF0H Address: 5555H Return to normal operation 1256 F24.0 Wait TIDA Wait TIDA Read Sec ID Return to normal operation X can be VIL or VIH, but no other value FIGURE 25: SOFTWARE SEC ID COMMAND FLOWCHARTS ©2004 Silicon Storage Technology, Inc. S71256-00-000 32 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information Chip-Erase Command Sequence Sector-Erase Command Sequence Block-Erase Command Sequence Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX80H Address: 5555H Load data: XX80H Address: 5555H Load data: XX80H Address: 5555H Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX10H Address: 5555H Load data: XX30H Address: SAX Load data: XX50H Address: BAX Wait TSCE Wait TSE Wait TBE Chip erased to FFFFH Sector erased to FFFFH Block erased to FFFFH 1256 F25.0 Note: X can be VIL or VIH, but no other value. FIGURE 26: ERASE COMMAND SEQUENCE ©2004 Silicon Storage Technology, Inc. S71256-00-000 33 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information PRODUCT ORDERING INFORMATION Device Speed SST34HF16x2X- XXX Suffix1 - XX Suffix2 - XXXX Package Attribute E = non-Pb Package Modifier P = 56 balls S = 62 balls Package Type L1 = LFBGA (8mm x 10mm x 1.4mm, 0.45mm ball size) L = LFBGA (8mm x 10mm x 1.4mm, 0.40mm ball size) B1 = TFBGA (8mm x 10mm x 1.2mm, 0.45mm ball size) Temperature Range C = Commercial = 0°C to +70°C E = Extended = -20°C to +85°C Minimum Endurance 4 =10,000 cycles Read Access Speed 70 = 70 ns Version C = x16 Mbit SRAM D = x16 Mbit PSRAM S = x8 Mbit SRAM Bank Split 2 = 4 Mbit + 12 Mbit SRAM Density 0 = No SRAM 2 = 2 Mbit 4 = 4 Mbit 8 = 8 Mbit Flash Density 16 = 16 Mbit Voltage H = 2.7-3.3V Product Series 34 = Concurrent SuperFlash + SRAM ComboMemory ©2004 Silicon Storage Technology, Inc. S71256-00-000 34 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information Valid combinations for SST34HF1602C SST34HF1602C-70-4C-L1P SST34HF1602C-70-4C-L1PE SST34HF1602C-70-4C-LS SST34HF1602C-70-4C-LSE SST34HF1602C-70-4C-B1P SST34HF1602C-70-4C-B1PE SST34HF1602C-70-4E-L1P SST34HF1602C-70-4E-L1PE SST34HF1602C-70-4E-LS SST34HF1602C-70-4E-LSE SST34HF1602C-70-4E-B1P SST34HF1602C-70-4E-B1PE Valid combinations for SST34HF1622C SST34HF1622C-70-4C-L1P SST34HF1622C-70-4C-L1PE SST34HF1622C-70-4C-LS SST34HF1622C-70-4C-LSE SST34HF1622C-70-4E-L1P SST34HF1622C-70-4E-L1PE SST34HF1622C-70-4E-LS SST34HF1622C-70-4E-LSE Valid combinations for SST34HF1622S SST34HF1622S-70-4C-L1P SST34HF1622S-70-4C-L1PE SST34HF1622S-70-4E-L1P SST34HF1622S-70-4E-L1PE Valid combinations for SST34HF1642C SST34HF1642C-70-4C-L1P SST34HF1642C-70-4C-L1PE SST34HF1642C-70-4C-LS SST34HF1642C-70-4C-LSE SST34HF1642C-70-4E-L1P SST34HF1642C-70-4E-L1PE SST34HF1642C-70-4E-LS SST34HF1642C-70-4E-LSE Valid combinations for SST34HF1642D SST34HF1642D-70-4C-L1P SST34HF1642D-70-4C-L1PE SST34HF1642D-70-4C-LS SST34HF1642D-70-4C-LSE SST34HF1642D-70-4E-L1P SST34HF1642D-70-4E-L1PE SST34HF1642D-70-4E-LS SST34HF1642D-70-4E-LSE Valid combinations for SST34HF1642S SST34HF1642S-70-4C-L1P SST34HF1642S-70-4C-L1PE SST34HF1642S-70-4E-L1P SST34HF1642S-70-4E-L1PE Valid combinations for SST34HF1682D SST34HF1682D-70-4C-L1P SST34HF1682D-70-4C-L1PE SST34HF1682D-70-4C-LS SST34HF1682D-70-4C-LSE SST34HF1682D-70-4E-L1P SST34HF1682D-70-4E-L1PE SST34HF1682D-70-4E-LS SST34HF1682D-70-4E-LSE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2004 Silicon Storage Technology, Inc. S71256-00-000 35 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information PACKAGING DIAGRAMS BOTTOM VIEW 10.00 ± 0.20 5.60 TOP VIEW 0.80 8 8 7 7 6 6 5.60 5 5 8.00 ± 0.20 4 4 3 3 2 2 1 1 0.80 H G F E D C B A A B C D E F G H A1 CORNER 0.45 ± 0.05 (56X) A1 CORNER 1.30 ± 0.10 SIDE VIEW 0.12 SEATING PLANE 56-lfbga-L1P-8x10-450mic-3 0.35 ± 0.05 1mm Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.12 mm 4. The actual shape of the corners may be slightly different than as portrayed in the drawing. 56-BALL LOW-PROFILE, FINE-PITCH BALL GRID ARRAY (LFBGA) 8MM SST PACKAGE CODE: L1P ©2004 Silicon Storage Technology, Inc. X 10MM S71256-00-000 36 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information BOTTOM VIEW 10.00 ± 0.20 7.20 0.80 TOP VIEW 8 8 7 7 6 6 5 5 8.00 ± 0.20 5.60 4 4 3 3 2 2 1 1 0.40 ± 0.05 (62X) 0.80 K J H G F E D C B A A B C D E F G H J K A1 CORNER A1 CORNER SIDE VIEW 1.30 ± 0.10 0.12 SEATING PLANE Note: 0.32 ± 0.05 62-lfbga-LS-8x10-400mic-3 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.12 mm 4. The actual shape of the corners may be slightly different than as portrayed in the drawing. 62-BALL LOW-PROFILE, FINE-PITCH BALL GRID ARRAY (LFBGA) 8MM SST PACKAGE CODE: LS ©2004 Silicon Storage Technology, Inc. X 1mm 10MM S71256-00-000 37 3/04 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory SST34HF1602C / SST34HF1622C / SST34HF1642C SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S Advance Information TOP VIEW BOTTOM VIEW 10.00 ± 0.20 5.60 0.80 8 8 7 7 6 6 5.60 5 5 8.00 ± 0.20 4 4 3 3 2 2 1 1 0.80 0.45 ± 0.05 (56X) H G F E D C B A A B C D E F G H A1 CORNER A1 CORNER 1.2 max SIDE VIEW 1mm 0.12 SEATING PLANE 0.35 ± 0.05 Note: 1. 2. 3. 4. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered. All linear dimensions are in millimeters. Coplanarity: 0.12 mm 56-tfbga-B1P-8x10-450mic-1 Ball opening size is 0.38 mm (± 0.05 mm) 56-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 8MM SST PACKAGE CODE: B1P X 10MM TABLE 16: REVISION HISTORY Number 00 Description • Date Mar 2004 Initial Release Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.sst.com ©2004 Silicon Storage Technology, Inc. S71256-00-000 38 3/04