RoboClock® CY7B9973V High-Speed Multi-Output PLL Clock Buffer Features Functional Description • 10-MHz – 200-MHz output operation The CY7B9973V Low-Voltage PLL Clock Buffer offers user-selectable frequency control over system clock functions. This twelve output clock driver provides the system integrator selectable frequency ratios of 1:1, 2:1, 3:1, 3:2, 4:3, 5:1, 5:2, 5:3, 6:1 and 6:5 between outputs. An additional output is dedicated to providing feedback information to allow the internal PLL to multiply an external reference frequency by 4, 6, 8, 10, 12, 16 or 20. The completely integrated PLL reduces jitter and simplifies board layout. • Output-to-output skews < 350 ps • 13 LVTTL 50% duty-cycle outputs capable of driving 50Ω terminated lines • Phase-locked loop (PLL) LOCK indicator • 3.3V LVTTL/LV differential (LVPECL) hot insertable reference inputs • Multiply/divide ratios of (4, 6, 8, 10, 12, 16, 20):(2, 4, 6, 8, 10, 12, 16, 20) The thirteen configurable outputs can each drive terminated transmission lines with impedances as low as 50Ω while delivering minimal and specified output skews at LVTTL levels. • Operation with outputs operating at up to 10x input frequency The CY7B9973V has a flexible reference input scheme with three different hot-insertion capable inputs. These inputs allow the use of either differential LVPECL or single-ended LVTTL inputs which can be dynamically selected to provide the reference frequency. • Low cycle-to-cycle jitter (< ±75 ps peak-peak) • Single 3.3V ± 10% supply • Pin-compatible with Motorola MPC973 • 52-pin TQFP package Logic Diagram PECL_CLK (11) PECL_CLK (12) PLL_En (6) LOCK (25) Ref_Sel (7) TCLK_Sel (8) Qa0 (50) 1 TCLK0 (9) 0 TCLK1 (10) 1 D Q 0 0 ÷2/÷1 PHASE DETECTOR VCO 1 Qa1 (48) Qa2 (46) LPF Qa3 (44) Ext_FB (31) Qb0 (38) D Q VCO_Sel (52) Qb1 (36) Qb2 (34) fselFB2 (5) Qb3 (32) MR/OE (2) 2 fsela0:1 (43,42) fselb0:1 (41,40) 2 Reset ÷4, ÷6, ÷8, ÷12 ÷4, ÷6, ÷8, ÷10 ÷2, ÷4, ÷6, ÷8 D Q Qc1 (21) D Q 2 fselFB0:1 (27,26) Qc2 (18) Qc3 (16) 2 fselc0:1 (20,19) Qc0 (23) ÷4, ÷6, ÷8, ÷10 0 ÷2 1 D Q QFB (29) Data Generator Inv_Clk (14) Cypress Semiconductor Corporation Document #: 38-07430 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised September 27, 2006 [+] Feedback RoboClock® CY7B9973V fselFB0 VCCF QFB GNDO Ext_FB Qb3 VCCO Qb2 GNDO Qb1 VCCO Qb0 GNDO 52-Lead Pinout (Top View) 39 38 37 36 35 34 33 32 31 30 29 28 27 26 fselFB1 41 25 LOCK fsela1 42 24 GNDO fsela0 43 23 Qc0 22 VCCO 21 Qc1 20 fselc0 fselb1 40 fselb0 Qa3 44 VCCO 45 CY7B9973V VCCO Qa0 50 16 Qc3 GNDO 51 15 GNDO VCO_Sel 52 14 Inv_Clk 4 5 6 7 8 9 10 11 12 13 VCCA 3 PECL_CLK 2 PECL_CLK 1 TCLK1 49 TCLK0 VCCO TCLK_Sel Qc2 17 Ref_Sel 48 Qa1 PLL_En fselc1 18 fselFB2 19 FT2 47 FT1 GNDO MR/OE 46 GNDA Qa2 Table 1. Divider Function Selects for Qa, Qb, Qc fsela1 fsela0 0 0 0 1 1 0 1 1 Qa ÷4 ÷6 ÷8 ÷12 fselb1 fselb0 0 0 0 1 1 0 1 1 Table 2. Divider Function Select for QFB fselFB2 fselFB1 fselFB0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Document #: 38-07430 Rev. *B Qb fselc1 fselc0 0 0 0 1 ÷4 ÷6 ÷8 ÷10 1 0 1 1 Qc ÷2 ÷4 ÷6 ÷8 Table 3. Control Pin Function Selects QFB ÷4 ÷6 ÷8 ÷10 ÷8 ÷12 ÷16 ÷20 Control Pin Logic ‘0’ Logic ‘1’ VCO_Sel VCO/2 VCO Ref_Sel Controlled by TCLK_Sel PECL TCLK_Sel TCLK0 TCLK1 PLL_En Bypass PLL Enable PLL MR/OE Master Reset/Output Hi-Z Enable Outputs Inv_Clk Noninverted Qc2, Qc3 Inverted Qc2, Qc3 Page 2 of 8 [+] Feedback RoboClock® CY7B9973V Pin Definitions Name Pin # Type Description LVTTL Output Clock Output. These outputs provide numerous divide functions determined by the fsel[a:c][0:1] and the fselFB[0:2] inputs. See Table 1 and Table 2 QFB 50,48,46,44 38,36,34,32 23,21,18,16 29 Ext_FB 31 LVTTL Input[1] PLL Feedback Input. This input is used to connect one of the Clock Outputs (usually QFB) to the feedback input of the PLL. Ref_Sel 7 LVTTL Input[1] Reference Select Input. The Ref_Sel input controls the reference input to the PLL. When LOW the input is selected by the TCLK_Sel input. When HIGH the PECL_CLK is selected. This input has an internal pull-up. TCLK_Sel 8 LVTTL Input[1] TTL Clock Select Input. The TCLK_Sel input controls which TCLK[0,1] input will be used as the reference input if Ref_Sel is LOW. When TCLK_Sel is LOW TCLK0 is selected. When TCLK_Sel is HIGH TCLK1 is selected. This input has an internal pull-up. TCLK0 TCLK1 9, 10 LVTTL Input[1] LVTTL Reference Inputs. These inputs provide the Reference frequency for the internal PLL when selected by Ref_Sel and TCLK_Sel. PECL_CLK 11,12 PECL_CLK LV-Diff. PECL Input Differential Reference Inputs. This LV-Differential PECL input provides the Reference frequency for the internal PLL when selected by Ref_Sel. fsel[a:c][0:1] 43, 42, 41, 40, 20,19 LVTTL Input[1] Output Divider Function Select. Each pair controls the divider function of the respective bank of outputs. See Table 1. fselFB[0:1] fselFB2 27,26 5 LVTTL Input[1] Feedback Output Divider Function Select. These inputs control the divider function of the Feedback output QFB. See Table 2. VCO_Sel 52 LVTTL Input[1] VCO Frequency Select Input. This input selects the nominal operating range of the VCO used in the PLL. When VCO_Sel is HIGH the VCO range is 200-480 MHz. When VCO_Sel is LOW the VCO range is 100-240 MHz. PLL_En 6 LVTTL Input[1] PLL Bypass Select. When this input is HIGH the internal Phase Locked Loop (PLL) provides the internal clocks to operate the part. When this input is LOW the internal PLL is bypassed and the selected reference input provides the clocks to operate the part. FT1, FT2 3, 4 LVTTL Input[1] PLL Bypass Mode Control Inputs. When PLL_En is HIGH these inputs are ignored and may be set to any logic level or left open. These inputs have an internal pull-up. Inv_Clk 14 LVTTL Input[1] Invert Mode. This input only affects the Qc bank. When this input is HIGH, Qc2 and Qc3 are inverted from the “normal” phase of Qc0 and Qc1. When this input is LOW all outputs of the Qc bank are in the “normal” phase alignment. MR/OE 2 LVTTL Input[1] Master Reset (active LOW) and Output Enable (active HIGH) Input. Note: when MR/OE is deasserted (set to HIGH) the PLL will have been disturbed and the outputs will be at an indeterminate frequency until it is relocked. VCCA 13 Power PLL Power. VCCF 28 Power Feedback Buffer Power. VCCO 17, 22, 33, 37,45,49 Power Output Buffer Power. GNDA 1 Ground PLL Ground. GNDO 15, 24, 30, Ground 35, 39, 47, 51 Output Buffer Ground. LOCK 25 PLL Lock Indicator. When HIGH this output indicates that the internal PLL is locked to the reference signal. When LOW the PLL is attempting to acquire lock. Note: If there is no activity on the selected reference input LOCK may not accurately reflect the state of the internal PLL. This pin will drive logic, but not Thevenin terminated transmission lines. It is always active and does not go to a high impedance state. This output provides TEST MODE information when PLL_En is LOW. Q[a:c][0:3] LVTTL Output Note: 1. Includes internal PULL-UP. If this pin is left unconnected it will assume a HIGH level. Document #: 38-07430 Rev. *B Page 3 of 8 [+] Feedback RoboClock® CY7B9973V Block Diagram Description (see figure, page 1) Phase Frequency Detector and Filter These two blocks accept signals from the reference inputs (TCLK0, TCLK1 or PECL_CLK) and the FB input (Ext_FB). Correction information is then generated to control the frequency of the Voltage Controlled Oscillator (VCO). These two blocks, along with the VCO, form a (PLL) that tracks the incoming reference signal. The Robo973 has a flexible reference input scheme. These inputs allow the use of either differential LVPECL or one of two single-ended LVTTL inputs. The reference inputs are tolerant to hot insertion and can be changed dynamically. VCO, Control Logic, and Divider The VCO accepts analog control inputs from the PLL filter block. The VCO_Sel control pin setting determines the nominal operational frequency range of the VCO (fNOM). When VCO_Sel is HIGH the VCO operating range is 200–480 MHz. For systems that need lower frequencies, VCO_Sel can be set LOW, which changes the VCO operating range to 100–240 MHz. Data Generator The Data Generator is comprised of four independent banks: three banks for clock outputs and one bank for feedback. Each clock output bank has four low-skew, high-fanout output buffers (Q[a:c][0:3]), controlled by two divide function select inputs (fsel[a:c][0:1]). The feedback bank has one high-fanout output buffer (QFB). This output is usually connected to the selected feedback input (Ext_FB). This feedback output has three divider function selects fselFB[0:2]. Inv_Clk Pin Function The Qc bank has signal invert capability. The four outputs of the Qc bank will act as two pairs of complementary outputs when the Inv_Clk pin is driven HIGH. In complementary output mode, Qc0 and Qc1 are noninverting (i.e., in phase with the other banks), Qc2 and Qc3 are inverting outputs (i.e., inverted from the other banks). When the Inv_Clk pin is driven LOW, the outputs will not invert. Inversion of the outputs are independent of the divide functions. Therefore, clock outputs of Qc bank can be inverted and divided at the same time. Lock Detect Output Description The LOCK detect output indicates the lock condition of the integrated PLL. Lock detection is accomplished by comparing the phase difference between the reference and feedback inputs. An unacceptable phase error is declared when the phase difference between the two inputs is greater than about 700 ps. Document #: 38-07430 Rev. *B When in the locked state, after four or more consecutive feedback clock cycles with phase-errors, the LOCK output will be forced LOW to indicate out-of-lock state. When in the out-of-lock state, 32 consecutive phase-errorless feedback clock cycles are required to allow the LOCK output to indicate lock condition (LOCK = HIGH). If the feedback clock is removed after LOCK has gone HIGH, a Watchdog circuit is implemented to indicate the out-of-lock condition after a time-out period by deasserting LOCK LOW. This time-out period is based upon a divided down reference clock. This assumes that there is activity on the selected reference input. If there is no activity on the selected reference input then the LOCK detect pin may not accurately reflect the state of the internal PLL. The LOCK pin has been designed with an intentionally reduced output drive capability to minimize noise and power dissipation. This pin will drive logic, but not Thevenin-terminated transmission lines. It is also unaffected by the MR/OE input and is always active. PLL Bypass Mode Description The device will enter PLL bypass mode when the PLL_En is driven LOW. In factory PLL bypass mode, the device will operate with its internal PLL disconnected; input signals supplied to the reference input will be used in place of the PLL output. In PLL bypass mode the Ext_FB input is ignored. All functions of the device are still operational in PLL bypass mode. Factory Test Reset When in PLL bypass mode (PLL_En = LOW), the device can be reset to a deterministic state by driving the MR/OE input LOW. When the MR/OE input is driven LOW in PLL bypass mode, all clock outputs will go to HI-Z; after the selected reference clock pin has 5 positive transitions, all the internal finite state machines (FSM) will be set to a deterministic state. The deterministic state of the state machines will depend on the configurations of the divide selects and frequency select input. All clock outputs will stay in high-impedance mode and all FSMs will stay in the deterministic state until MR/OE is deasserted. When MR/OE is deasserted (with PLL_En still at LOW), the device will reenter PLL bypass mode. Safe Operating Zone The device will operate below its maximum allowable junction temperature (tJ < 150°C) in any configuration of multiply or divide with all outputs loaded to the data sheet maximum (i.e., with 25-pF load and 0-m/s air flow). Page 4 of 8 [+] Feedback RoboClock® CY7B9973V Absolute Maximum Conditions Output Current into Outputs (LOW)............................. 40 mA Static Discharge Voltage........................................... > 2000V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-up Current...................................................... ±200 mA Storage Temperature ................................. –40°C to +150°C Operating Range Ambient Temperature with Power Applied .. –40°C to +125°C Supply Voltage to Ground Potential ............... –0.5V to +4.6V Range DC Input Voltage....................................–0.3V to VCC + 0.5V Commercial Ambient Temperature VCC 0°C to +70°C 3.3V ±10% DC CHARACTERISTICS Over the Operating Range Parameter Description Test Conditions Min. Typ. Max. Unit VIH Input HIGH Voltage 2.0 – VCC + 0.3 V VIL Input LOW Voltage – – 0.8 V VPP Peak-to-Peak Input Voltage PECL_CLK VCMR Common Mode Range (Crossing) PECL_CLK VOH VOL IIN Note 2 mA[3] 400 – Vcc mV 0.8 – Vcc V Output HIGH Voltage All “Q” Outputs IOH = –20 2.4 – – V Output HIGH Voltage LOCK Output IOH = –2 mA[3] 2.4 – – V Output LOW Voltage “Q” Output IOL = +20 mA – – 0.5 V Output LOW Voltage LOCK Output IOL = +2 mA – – 0.5 V All control inputs GND < VIN < VCC – – +150 uA PECL_CLK and TCLK[0:1] GND < VIN < VCC – – +500 uA Input Current[4] II Hot Insertion Input Current PECL_CLK and TCLK[0:1] VIN < 3.63V VCC = GND – – 100 uA ICCQ Maximum Quiescent Supply Current Sum all VCC pins PLL_En=LOW reference off – 50 150 mA ICCD Maximum Dynamic Supply Current (Neglecting Output Load Current) Outputs unloaded fselFB = 010 (÷8) ref = 50 MHz – 320 400 mA CIN Input Capacitance Note 5 – – 4 pF PLL INPUT REFERENCE CHARACTERISTICS Over the Operating Range Parameter Description Test Conditions Min. Max. Unit tr, tf TCLK Input Rise/Fall Time – 3.0 ns fref Reference Input Frequency 14 120 MHz trefDC Reference Input Duty Cycle 25 75 % Note 5 Notes: 2. VCMR is the measured at the point that both inputs achieve the same voltage. 3. The CY7B9973V clock outputs can drive series or parallel terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge. 4. Inputs have pull-up resistors which affect input current. 5. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-07430 Rev. *B Page 5 of 8 [+] Feedback RoboClock® CY7B9973V AC CHARACTERISTICS Over the Operating Range Parameter Description Test Conditions Min. Typ. Max. Unit tr Output Rise Time 0.8 to 2.0V Note 13 0.15 – 1.2 ns. tf Output Fall Time 2.0 to 0.8V Note 13 0.15 – 1.2 ns. tpw Output Duty Cycle fmax < 125 MHz, Notes 6, 7 tCYCLE/2 tCYCLE/2 tCYCLE/2 –400 +200 +400 ps fmax > 125 MHz, Notes 6, 7 tCYCLE/2 tCYCLE/2 tCYCLE/2 –450 +225 +450 ps tpd Propagation Delay (Selected Reference Input Rise to Ext_FB Rise) QFB = ÷ 8 Notes 7, 8 –350 – +350 tos Output to Output Skew Notes 7, 15 fVCO VCO Lock Range fmax Maximum Output Frequency Note 12 – tjitter (CC) Cycle to Cycle Jitter (Peak-Peak), 10,000 clocks Note 16 – tjitter (PER) Period Jitter (Peak-Peak), 10,000 clocks – – +350 ps 200 – 480 MHz – 200 MHz +50 +75 ps Note 16 Period Jitter (Peak-Peak), RMS tjitter (PHASE) I/O Phase Jitter (Peak-Peak), 10,000 clocks, ÷ 4 Note 16 feedback, VCO = 250 MHz I/O Phase jitter (Peak-Peak), RMS tOLZ, tOHZ Output Disable Time Note 9 tOZL, tOZH Output Enable Time Notes 10, 11 tlock Maximum PLL Lock Time tTB Total Timing Budget window ps – 120 168 ps – 12 15.5 ps – 175 280 ps – 24 46 ps 1 – 10 ns 0.5 – 14 ns – – 10 ms – – 775 ps Note 14 AC Test Loads and Waveform[17] 3.3V R1 For LOCK output only R1 = 910 Ω R2 = 910 Ω CL < 30 pF OUTPUT For all other outputs R1 = 100Ω CL R2 = 100Ω CL < 25 pF (at output pin) (Includes fixture and probe capacitance) R2 (a) LVTTL AC Test Load 3.3V 2.0V 2.0V 0.8V GND < 1 ns (b) TTL Input Test Waveform 2.0V 0.8V < 1 ns 90% 90% 10% 1.0V < 1 ns 10% < 1 ns (c) LVPECL Input Test Waveform Notes: 6. tPW is measured at Vcc/2. 7. 50Ω transmission line terminated into VCC/2. 8. tPD is specified for a 50 MHz input reference. The tPD does not include jitter. 9. Measured at 0.5V deviation from starting voltage. 10. For tOZL and tOZH minimum, CL = 0pF, RL = 1k (to VCC for tOZL, to GND for tOZH). For tOZL and tOZH maximum, CL= 25pF and RL = 100Ω (to VCC for tOZL, to GND for tOZH). 11. tOZL maximum is measured at 0.5V. tOZH maximum is measured at 2.4V. 12. fmax measured with CL = 25pF. 13. Measured with no load. 14. tTB = tpd + tOS + tjitter, this parameter is calculated and is the worst case between devices. 15. All outputs operating at the same frequency. 16. Not a tested parameter. Guaranteed by characterization. 17. These figures are for illustrations only. The actual ATE loads may vary. Document #: 38-07430 Rev. *B Page 6 of 8 [+] Feedback RoboClock® CY7B9973V AC Timing Diagrams trefdc trefdc TCLK[0:1] or PECL_CLK tpw t pd tpw Vcc 2 Ext_FB tos any Qa[0:3] Qb[0:3] Qc[0,3] QFB tos other Qa[0:3] Qb[0:3] Qc[0,3] QFB tjitter Qa[0:3] Qb[0:3] Qc[0,3] QFB Ordering Information Ordering Code CY7B9973V-AC Package Name Package Type A52 52-Lead Thin Quad Flat Pack Operating Range Commercial Package Diagrams 52-Lead Thin Plastic Quad Flat Pack (10 × 10 × 1.4 mm) A52 51-85131-** RoboClock is a registered trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07430 Rev. *B Page 7 of 8 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. [+] Feedback RoboClock® CY7B9973V Document History Page Document Title: CY7B9973V RoboClock® High-Speed Multi-Output PLL Clock Buffer Document Number: 38-07430 REV. ECN No. Issue Date Orig. of Change ** 115842 06/10/02 HWT New Data Sheet Description of Change *A 128182 09/15/03 RGL Added phase and period jitter specifications Tightened duty cycle spec and split duty cycle based on output frequency *B 506217 See ECN RGL Minor Change: To post on web Document #: 38-07430 Rev. *B Page 8 of 8 [+] Feedback