CY28325-2 PRELIMINARY FTG for VIA Pentium 4 Chipsets Features • Spread Spectrum Frequency Timing Generator for VIA Pentium 4 Chipsets • Programmable clock output frequency with less than 1 MHz increment • Integrated fail-safe Watchdog Timer for system recovery • Automatically switch to hardware-selected or softwareprogrammed clock frequency when Watchdog Timer time-out • Capable of generate system RESET after a Watchdog Timer time-out occurs or a change in output frequency via SMBus interface • Support SMBus Byte Read/Write and Block Read/Write operations to simplify system BIOS development • Vendor ID and Revision ID support • Programmable-drive strength support • Programmable-output skew support • Three copies of 66-MHz output • Power management control inputs • Available in 48-pin SSOP CPU AGP PCI REF APIC 48M 24_48M x3 x3 x9 x1 x2 x1 x1 Pin Configuration[1] Block Diagram XTAL OSC *(FS0:4) VTT_PWRGD# *CPU_STOP# *MULTSEL1 PLL Ref Freq Divider Network VDD_CPU_CS (2.5V) CPUT_CS, CPUC_CS VDD_CPU (3.3V) CPUT_0, CPUC_0 Stop Clock Control ~ PLL 1 VDD_APIC APIC0:1 VDD_AGP AGP0:2 VDD_PCI PCI_F PD# SSOP-48 VDD_REF REF Stop Clock Control PCI1:8 *PCI_STOP# VDD_48MHz 48MHz PLL2 *FS4/REF VDD_REF GND_REF X1 X2 VDD_48MHz *FS3/48MHz *FS2/24_48MHz GND_48MHz *FS0/PCI_F *FS1/PCI1 *MULT_SEL1/PCI2 GND_PCI PCI3 PCI4 VDD_PCI PCI5 PCI6 PCI7 GND_PCI PCI8 *PD# AGP0 VDD_AGP 24_48MHz 2 SDATA SCLK SMBus Logic Cypress Semiconductor Corporation Document #: 38-07119 Rev. ** 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 CY28325-2 X1 X2 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDD_APIC GND_APIC APIC0 APIC1 GND_CPU VDD_CPU_CS(2.5V) CPUT_CS_F CPUC_CS_F CPUT_0 CPUC_0 VDD_CPU(3.3V) IREF GND_CPU CPUT_1 CPUC_1 VTT_PWRGD# CPU_STOP#* PCI_STOP#* RST# SDATA SCLK AGP2 AGP1 GND_AGP Note: 1. Pins marked with [*] have internal pull-up resistors. Pins marked with[^] have internal pull-down resistors. RST# • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised February 27, 2002 PRELIMINARY CY28325-2 Pin Definitions Pin No. Pin Type X1 4 I Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. X2 5 O Crystal Connection: Connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. REF/FS4 1 I/O Reference Clock Output/Frequency Select 4: 3.3V 14.318-MHz output. This pin also serves as a power-on strap option to determine device operating frequency as described in the Frequency Selection Table. CPUT_0:1 40, 39, 35, 34 O CPU Clock Outputs: Frequency is set by the FS0:4 inputs or through serial input interface. 42, 41 O CPU Clock Outputs for Chipset: Frequency is set by the FS0:4 inputs or through serial input interface. APIC0:1 46, 45 O APIC Clock Output: APIC clock outputs running at half of PCI output frequency. AGP 0:2 Pin Name CPUC_0:1 CPUT_CS_F CPUC_CS_F Pin Description 23, 26, 27 O AGP Clock Output: 3.3V AGP clock. PCI_F/FS0 10 I/O Free-running PCI Output 1/Frequency Select 1: 3.3V free-running PCI output. This pin also serves as a power-on strap option to determine device operating frequency as described in the Frequency Selection Table. PCI1/FS1 11 I/O PCI Output 1 /Frequency Select 1: 3.3V PCI output. This pin also serves as a power-on strap option to determine device operating frequency as described in the Frequency Selection Table. PCI2/MULTSEL 1 12 I/O PCI Output 2/Current Multiplier Selection 1: 3.3V PCI output. This pin also serves as a power-on strap option to determine the current multiplier for the CPU clock outputs. The MULTSEL definitions are as follows: MULTISEL 0 = Ioh is 4 × IREF 1 = Ioh is 6 × IREF 14, 15, 17, 18, 19, 21 O PCI Clock Output 3 to 8: 3.3V PCI clock outputs. 48MHz/FS3 7 I/O 48-MHz Output/Frequency Select 3: 3.3V fixed 48-MHz, non-spread spectrum output. This pin also serves as a power-on strap option to determine device operating frequency as described in the Frequency Selection Table. 24_48MHz/FS2 8 I/O 24- or 48-MHz Output/Frequency Select 2: 3.3V fixed 24- or 48-MHz non-spread spectrum output. This pin also serves as a power-on strap option to determine device operating frequency as described in the Frequency Selection Table. CPU_STOP# 32 I CPU Output Control: 3.3V LVTTL-compatible input that disables CPUT_CS, CPUC_CS, CPUT_0:1 and CPUC_0:1. PCI_ST0P# 31 I PCI Output Control: 3.3V LVTTL-compatible input that disables PCI1:8. PD# 22 I Power-down Control: 3.3V LVTTL-compatible input that places the device in power down mode when held LOW. SCLK 28 I SMBus Clock Input: Clock pin for serial interface. SDATA 29 I/O RST# 30 IREF 37 PCI3:8 Document #: 38-07119 Rev. ** SMBus Data Input: Data pin for serial interface. O System Reset Output: Open-drain system reset output. (open-d rain) I Current Reference for CPU output: A precision resistor is attached to this pin, which is connected to the internal current reference. Page 2 of 19 CY28325-2 PRELIMINARY Pin Definitions (continued) Pin No. Pin Type VTT_PWRGD# 33 I Power-good from Voltage Regulator Module (VRM): 3.3V LVTTL input. VTT_PWRGD# is a level sensitive strobe used to determine when FS0:4 and MULTSEL inputs are valid and OK to be sampled (Active LOW). Once VTT_PWRGD# is sampled LOW, the status of this input will be ignored. VDD_CPU_CS, 43, 48 P 2.5V Power Connection: Power supply for CPU_CS outputs buffers and APIC output buffers. Connect to 2.5V. 2, 6, 16, 24, 38 P 3.3V Power Connection: Power supply for CPU outputs buffers, 3V66 output buffers, PCI output buffers, reference output buffers and 48-MHz output buffers. Connect to 3.3V. 3, 9, 13, 20, 25, 36, 44, 47 G Ground Connection: Connect all ground pins to the common system ground plane. Pin Name Pin Description VDD_APIC VDD_REF, VDD_48MHz, VDD _PCI, VDD_AGP, VDD_CPU GND_REF GND_48MHz, GND_PCI, GND_AGP, GND_CPU, GND_APIC Swing Select Functions through Hardware MULTSEL1 Board Target Trace/Term Z Output Current 0 50Ω VOH @ Z, Rr = 221 1%, IREF = 5.00 mA IOH = 4*Iref 1.0V @ 50 0 60Ω Rr = 221 1%, IREF = 5.00 mA IOH = 4*Iref 1.2V @ 60 1 50Ω Rr = 221 1%, IREF = 5.00 mA IOH = 6*Iref 1.5V @ 50 1 60Ω Rr = 221 1%, IREF = 5.00 mA IOH = 6*Iref 1.8V @ 60 0 50Ω Rr = 475 1%, IREF = 2.32 mA IOH = 4*Iref 0.47V @ 50 0 60Ω Rr = 475 1%, IREF = 2.32 mA IOH = 4*Iref 0.56V @ 60 1 50Ω Rr = 475 1%, IREF = 2.32 mA IOH = 6*Iref 0.7V @ 50 1 60Ω Rr = 475 1%, IREF = 2.32 mA IOH = 6*Iref 0.84V @ 60 Reference R, IREF = VDD/(3*Rr) Swing Select Functions MultSEL0 Board Target Trace/Term Z Reference R, IREF = MultSEL1 0 0 50Ω 0 0 0 1 Document #: 38-07119 Rev. ** Output Current VOH @ Z Rr = 221 1%, IREF = 5.00 mA IOH = 4*Iref 1.0V @ 50 60Ω Rr = 221 1%, IREF = 5.00 IOH = 4*Iref 1.2V @ 60 50Ω Rr = 221 1%, IREF = 5.00 mA IOH = 5*Iref 1.25V @ 50 VDD/(3*Rr) Page 3 of 19 CY28325-2 PRELIMINARY Swing Select Functions (continued) MultSEL0 Board Target Trace/Term Z Reference R, IREF = MultSEL1 0 1 60Ω 1 0 1 Output Current VOH @ Z Rr = 221 1%, IREF = 5.00 mA IOH = 5*Iref 1.5V @ 60 50Ω Rr = 221 1%, IREF = 5.00 mA IOH = 6*Iref 1.5V @ 50 0 60Ω Rr = 221 1%, IREF = 5.00 mA IOH = 6*Iref 1.8V @ 60 1 1 50Ω Rr = 221 1%, IREF = 5.00 mA IOH = 7*Iref 1.75V @ 50 1 1 60Ω Rr = 221 1%, IREF = 5.00 mA IOH = 7*Iref 2.1V @ 60 0 0 50Ω Rr = 475 1%, IREF = 2.32 mA IOH = 4*Iref 0.47V @ 50 0 0 60Ω Rr = 475 1%, IREF = 2.32 mA IOH = 4*Iref 0.56V @ 60 0 1 50Ω Rr = 475 1%, IREF = 2.32 mA IOH = 5*Iref 0.58V @ 50 0 1 60Ω Rr = 475 1%, IREF = 2.32 mA IOH = 5*Iref 0.7V @ 60 1 0 50Ω Rr = 475 1%, IREF = 2.32 mA IOH = 6*Iref 0.7V @ 50 1 0 60Ω Rr = 475 1%, IREF = 2.32 mA IOH = 6*Iref 0.84V @ 60 1 1 50 Ohm Rr = 475 1%, IREF = 2.32mA IOH = 7*Iref 0.81V @ 50 1 1 60 Ohm Rr = 475 1%, IREF = 2.32mA IOH = 7*Iref 0.97V @ 60 VDD/(3*Rr) Serial Data Interface Data Protocol To enhance the flexibility and function of the clock synthesizer, a two signal serial interface is provided. Through the Serial Data Interface, various device functions such as individual clock output buffers, etc. can be individually enabled or disabled. The clock driver serial protocol accepts Byte Write, Byte Read, Block Write and Block Read operation from the controller. For Block Write/Read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For Byte Write and Byte Read operations, the system controller can access individual indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 1. The registers associated with the Serial Data Interface initializes to it’s default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. The Block Write and Block Read protocol is outlined in Table 2, while Table 3 outlines the corresponding Byte Write and Byte Read protocol. The slave receiver address is 11010010 (D2h). Table 1. Command Code Definition Bit 7 6:0 Document #: 38-07119 Rev. ** Descriptions 0 = Block Read or Block Write operation 1 = Byte Read or Byte Write operation Byte offset for Byte Read or Byte Write operation. For Block Read or Block Write operations, these bits should be “0000000.” Page 4 of 19 CY28325-2 PRELIMINARY Table 2. Block Read and Block Write Protocol Block Write Protocol Bit Description Block Read Protocol Bit Description 1 Start 1 Start 2:8 Slave address – 7 bits 2:8 Slave address – 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 11:18 Command Code – 8 bits “00000000” stands for block operation 11:18 Command Code – 8 bits “00000000” stands for block operation 19 Acknowledge from slave 19 Acknowledge from slave 20:27 Byte Count – 8 bits 20 Repeat start 28 Acknowledge from slave 21:27 Slave address – 7 bits 29:36 Data byte 0 – 8 bits 28 Read 37 Acknowledge from slave 29 Acknowledge from slave 38:45 Data byte 1 – 8 bits 30:37 Byte count from slave – 8 bits 46 Acknowledge from slave 38 Acknowledge ... Data byte N/Slave acknowledge... 39:46 Data byte from slave – 8 bits ... Data Byte N – 8 bits 47 Acknowledge ... Acknowledge from slave 48:55 Data byte from slave – 8 bits ... Stop 56 Acknowledge ... Data bytes from slave/acknowledge ... Data byte N from slave – 8 bits ... Not acknowledge ... Stop Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Bit Description Byte Read Protocol Bit Description 1 Start 1 Start 2:8 Slave address – 7 bits 2:8 Slave address – 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 11:18 Command Code – 8 bits “1xxxxxxx” stands for byte operation; bit[6:0] of the command code represents the offset of the byte to be accessed 11:18 Command Code – 8 bits “1xxxxxxx” stands for byte operation; bit[6:0] of the command code represents the offset of the byte to be accessed 19 Acknowledge from slave 19 Acknowledge from slave 20:27 Data byte – 8 bits 20 Repeat start 28 Acknowledge from slave 21:27 Slave address – 7 bits 29 Stop 28 Read Document #: 38-07119 Rev. ** 29 Acknowledge from slave 30:37 Data byte from slave – 8 bits 38 Not acknowledge 39 Stop Page 5 of 19 CY28325-2 PRELIMINARY Data Byte Configuration Map Data Byte 0 Bit Pin# Name Description Power-on Default Bit 7 – Reserved Reserved 0 Bit 6 – SEL2 SW Frequency selection bits. Refer to Frequency Selection Table 0 Bit 5 – SEL1 SW Frequency selection bits. Refer to Frequency Selection Table 0 Bit 4 – SEL0 SW Frequency selection bits. Refer to Frequency Selection Table 0 Bit 3 – FS_Override 0 = Select operating frequency by FS[4:0] input pins 1 = Select operating frequency by SEL[4:0] settings 0 Bit 2 – SEL4 SW Frequency selection bits. Refer to Frequency Selection Table 0 Bit 1 – SEL3 SW Frequency selection bits. Refer to Frequency Selection Table 0 Bit 0 – Reserved Reserved 0 Data Byte 1 Bit Pin# Name Description Power-on Default Bit 7 – Reserved Reserved 0 Bit 6 – Spread Select2 “000” = OFF 0 Bit 5 – Spread Select1 “001” = Reserved 0 Bit 4 – Spread Select0 “010” = Reserved 0 ‘011” = Reserved “100“ = ± 0.25% “101“ = – 0.5% “110“= ±0.5% “111“ = ±0.38% Bit 3 42, 41 CPUT_CS, CPUC_CS (Active/Inactive) 1 Bit 2 35, 34 CPUT_1, CPUC_1 (Active/Inactive) 1 Bit 1 40, 39 CPUT_0, CPUC_0 (Active/Inactive) 1 Bit 0 – 1 = CPUT_CS_F and CPUC_CS_F are Free-running outputs 1 CPU_CS_F STOP Control 0 = CPUT_CS_F and CPUC_CS_F will be disabled when CPU_STOP# is active Data Byte 2 Bit Pin# Name Pin Description Power-on Default Bit 7 21 PCI8 (Active/Inactive) 1 Bit 6 19 PCI7 (Active/Inactive) 1 Bit 5 18 PCI6 (Active/Inactive) 1 Bit 4 17 PCI5 (Active/Inactive) 1 Bit 3 15 PCI4 (Active/Inactive) 1 Bit 2 14 PCI3 (Active/Inactive) 1 Bit 1 12 PCI2 (Active/Inactive) 1 Bit 0 11 PCI1 (Active/Inactive) 1 Document #: 38-07119 Rev. ** Page 6 of 19 CY28325-2 PRELIMINARY Data Byte 3 Bit Pin# Name Pin Description Power-on Default Bit 7 – Reserved Reserved 0 Bit 6 8 SEL_48MHZ 0 = 24 MHz 1 = 48 MHz 0 Bit 5 7 48MHz (Active/Inactive) 1 Bit 4 8 24_48MHz (Active/Inactive) 1 Bit 3 10 PCI_F (Active/Inactive) 1 Bit 2 27 AGP2 (Active/Inactive) 1 Bit 1 26 AGP1 (Active/Inactive) 1 Bit 0 23 AGP0 (Active/Inactive) 1 Data Byte 4 Bit Pin# Name Bit 7 – PCI_Skew1 Bit 6 – PCI_Skew0 Bit 5 – WD_TIMER4 Bit 4 – WD_TIMER3 Bit 3 – WD_TIMER2 Bit 2 – WD_TIMER1 Bit 1 – WD_TIMER0 Bit 0 – WD_PRE_SCALER Pin# Name Pin Description Power-on Default PCI skew control 00 = Normal 01 = –500 ps 10 = Reserved 11 = +500 ps 0 These bits store the time-out value of the Watchdog Timer. The scale of the timer is determine by the prescaler. The timer can support a value of 150 ms to 4.8 sec when the prescaler is set to 150 ms. If the prescaler is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec. When the Watchdog Timer reaches “0,” it will set the WD_TO_STATUS bit and generate Reset if RST_EN_WD is enabled. 1 0 = 150 ms 1 = 2.5 sec 0 0 1 1 1 1 Data Byte 5 Bit Pin Description Power-on Default Bit 7 7 48MHz_DRV 48-MHz clock output drive strength 0 = Normal 1 = High Drive 1 Bit 6 8 24_48MHz_DRV 24_48 MHz clock output drive strength 0 = Normal 1 = High Drive 1 Bit 5 45 APCI1 (Active/Inactive) 1 Bit 4 46 APIC0 (Active/Inactive) 1 Bit 3 – SW_MULTSEL1 – SW_MULTSEL0 IREF multiplier 00 = Ioh is 4 × IREF 01 = Ioh is 5 × IREF 10 = Ioh is 6 × IREF 11 = Ioh is 7 × IREF 0 Bit 2 Bit 1 1 REF (Active/Inactive) 1 Bit 0 – MULTSEL_Override This bit control the selection of IREF multipler. 0 = HW control; IREF multiplier is determined by MULTSEL1 input pin 1 = SW control; IREF multiplier is determined by SW_MULTSEL[0:1] Document #: 38-07119 Rev. ** 0 0 Page 7 of 19 CY28325-2 PRELIMINARY Data Byte 6 Bit Pin# Name Pin Description Power-on Default Bit 7 – Reserved Reserved 1 Bit 6 – Reserved Reserved 1 Bit 5 – Reserved Reserved 1 Bit 4 – Reserved Reserved 1 Bit 3 – Reserved Reserved 1 Bit 2 – Reserved Reserved 1 Bit 1 – Reserved Reserved 1 Bit 0 – Reserved Reserved 1 Data Byte 7 Bit Pin# Name Pin Description Power-on Default Bit 7 – Reserved Reserved 1 Bit 6 – Reserved Reserved 1 Bit 5 – Reserved Reserved 1 Bit 4 – Reserved Reserved 1 Bit 3 – Reserved Reserved 1 Bit 2 – Reserved Reserved 1 Bit 1 – Reserved Reserved 1 Bit 0 – Reserved Reserved 1 Data Byte 8 Bit Pin# Name Pin Description Power-on Default Bit 7 – Revision_ID3 Revision ID bit[3] 0 Bit 6 – Revision_ID2 Revision ID bit[2] 0 Bit 5 – Revision_ID1 Revision ID bit[1] 0 Bit 4 – Revision_ID0 Revision ID bit[0] 0 Bit 3 – Vendor_ID3 Bit[3] of Cypress’s Vendor ID. This bit is Read-only. 1 Bit 2 – Vendor_ID2 Bit[2] of Cypress’s Vendor ID. This bit is Read-only. 0 Bit 1 – Vendor _ID1 Bit[1] of Cypress’s Vendor ID. This bit is Read-only. 0 Bit 0 – Vendor _ID0 Bit[0] of Cypress’s Vendor ID. This bit is Read-only. 0 Data Byte 9 Bit Pin# Name Pin Description Power-on Default Bit 7 – Reserved Reserved 0 Bit 6 – PCI_DRV PCI clock output drive strength 0 = Normal 1 = High Drive 0 Bit 5 – AGP_DRV AGP clock output drive strength 0 = Normal 1 = High Drive 0 Bit 4 – RST_EN_WD This bit will enable the generation of a Reset pulse when a Watchdog timer time-out occurs. 0 = Disabled 1 = Enabled 0 Document #: 38-07119 Rev. ** Page 8 of 19 CY28325-2 PRELIMINARY Data Byte 9 (continued) Bit Pin# Name Pin Description Power-on Default Bit 3 – RST_EN_FC This bit will enable the generation of a Reset pulse after a frequency change occurs. 0 = Disabled 1 = Enabled 0 Bit 2 – WD_TO_STAT US Watchdog Timer Time-out Status Bit 0 = No time-out occurs (Read); Ignore (Write) 1 = time-out occurred (Read); Clear WD_TO_STATUS (Write) 0 Bit 1 – WD_EN 0 = Stop and re-load Watchdog timer 1 = Enable Watchdog timer. It will start counting down after a frequency change occurs. Note: CY28325-2 will generate system reset, re-load a recovery frequency, and lock itself into a recovery frequency mode after a Watchdog timer time-out occurs. Under recovery frequency mode, CY28325-2 will not respond to any attempt to change output frequency via the SMBus control bytes. System software can unlock W305B from its recovery frequency mode by clearing the WD_EN bit. 0 Bit 0 – Reserved Reserved 0 Data Byte 10 Bit Pin# Name Bit 7 – CPU_CS_F Skew2 Bit 6 – CPU_CS_F Skew1 Bit 5 – CPU_CS_F Skew0 Bit 4 – CPU_Skew2 Bit 3 – CPU_Skew1 Bit 2 – CPU_Skew0 Bit 1 – AGP_Skew1 Bit 0 – AGP_Skew0 Document #: 38-07119 Rev. ** Pin Description Power-on Default CPU_CS_F Skew Control 000 = Normal 001 = –150 ps 010 = –300 ps 011 = –450 ps 100 = +150 ps 101 = +300 ps 110 = +450 ps 111 = +600 ps 0 CPUT_0:1 and CPUC_0:1 Skew Control 000 = Normal 001 = –150 ps 010 = –300 ps 011 = –450 ps 100 = +150 ps 101 = +300 ps 110 = +450 ps 111 = +600 ps 0 AGP Skew control 00 = Normal 01 = –150 ps 10 = +150 ps 11 = +300 ps 0 0 0 0 0 0 Page 9 of 19 CY28325-2 PRELIMINARY Data Byte 11 Bit Pin# Name Pin Description If ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency when a Watchdog Timer time-out occurs. The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When FS_Override bit is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. Power-on Default Bit 7 – ROCV_FREQ_N7 Bit 6 – ROCV_FREQ_N6 Bit 5 – ROCV_FREQ_N5 Bit 4 – ROCV_FREQ_N4 Bit 3 – ROCV_FREQ_N3 Bit 2 – ROCV_FREQ_N2 Bit 1 – ROCV_FREQ_N1 0 Bit 0 – ROCV_FREQ_N0 0 0 0 0 0 0 0 Data Byte 12 Power-on Default Bit Pin# Name Pin Description Bit 7 – ROCV_FREQ_SEL ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog tImer time-out occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL. 0 = From latched FS[4:0] 1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0] 0 Bit 6 – ROCV_FREQ_M6 If ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be use to determine the recovery CPU output frequency.when a Watchdog Timer time-out occurs. The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When FS_Override bit is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. 0 Bit 5 – ROCV_FREQ_M5 Bit 4 – ROCV_FREQ_M4 Bit 3 – ROCV_FREQ_M3 Bit 2 – ROCV_FREQ_M2 Bit 1 – ROCV_FREQ_M1 Bit 0 – ROCV_FREQ_M0 0 0 0 0 0 0 Data Byte 13 Bit Pin# Name Pin Description If Prog_Freq_EN is set, the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] will be used to determine the CPU output frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. Power-on Default Bit 7 – CPU_FSEL_N7 Bit 6 – CPU_FSEL_N6 Bit 5 – CPU_FSEL_N5 Bit 4 – CPU_FSEL_N4 Bit 3 – CPU_FSEL_N3 Bit 2 – CPU_FSEL_N2 0 Bit 1 – CPU_FSEL_N1 0 Bit 0 – CPU_FSEL_N0 0 0 0 0 0 0 Data Byte 14 Bit Bit 7 Pin# – Name Pro_Freq_EN Document #: 38-07119 Rev. ** Pin Description Programmable output frequencies enabled 0 = Disabled 1 = Enabled Power-on Default 0 Page 10 of 19 CY28325-2 PRELIMINARY Data Byte 14 (continued) Bit Pin# Name Bit 6 – CPU_FSEL_M6 Bit 5 – CPU_FSEL_M5 Bit 4 – CPU_FSEL_M4 Bit 3 – CPU_FSEL_M3 Bit 2 – CPU_FSEL_M2 Bit 1 – CPU_FSEL_M1 Bit 0 – CPU_FSEL_M0 Pin Description If Prog_Freq_EN is set, the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] will be used to determine the CPU output frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. Power-on Default 0 0 0 0 0 0 0 Data Byte 15 Bit Pin# Name Pin Description Latched FS[4:0] inputs. These bits are Read-only. Power-on Default Bit 7 1 Latched FS4 input Bit 6 7 Latched FS3 input X X Bit 5 8 Latched FS2 input X Bit 4 11 Latched FS1 input X Bit 3 10 Latched FS0 input Bit 2 – Reserved X Reserved 0 Bit 1 – Vendor Test Mode Reserved. Write with “1” 1 Bit 0 – Vendor Test Mode Reserved. Write with “1” 1 Data Byte 16 Bit Pin# Name Pin Description Power-on Default Bit 7 – Reserved Reserved 0 Bit 6 – Reserved Reserved 0 Bit 5 – Reserved Reserved 0 Bit 4 – Reserved Reserved 0 Bit 3 – Reserved Reserved 0 Bit 2 – Reserved Reserved 0 Bit 1 – Reserved Reserved 0 Bit 0 – Reserved Reserved 0 Data Byte 17 Bit Pin# Name Pin Description Power-on Default Bit 7 – Reserved Reserved 0 Bit 6 – Reserved Reserved 0 Bit 5 – Reserved Reserved 0 Bit 4 – Reserved Reserved 0 Bit 3 – Reserved Reserved 0 Bit 2 – Reserved Reserved 0 Bit 1 – Reserved Reserved 0 Bit 0 – Reserved Reserved 0 Document #: 38-07119 Rev. ** Page 11 of 19 CY28325-2 PRELIMINARY Table 4. Frequency Selection Table Input Conditions Output Frequency FS4 FS3 FS2 FS1 FS0 SEL4 SEL3 SEL2 SEL1 SEL0 CPU AGP PCI APIC PLL Gear Constants (G) 0 0 0 0 0 102.0 68.0 34.0 17.0 48.00741 0 0 0 0 1 105.0 70.0 35.0 17.5 48.00741 0 0 0 1 0 108.0 72.0 36.0 18.0 48.00741 0 0 0 1 1 111.0 74.0 37.0 18.5 48.00741 0 0 1 0 0 114.0 76.0 38.0 19.0 48.00741 0 0 1 0 1 117.0 78.0 39.0 19.5 48.00741 0 0 1 1 0 120.0 80.0 40.0 20.0 48.00741 0 0 1 1 1 123.0 82.0 41.0 20.5 48.00741 0 1 0 0 0 126.0 63.0 31.5 18.0 48.00741 0 1 0 0 1 130.0 65.0 32.5 18.5 48.00741 0 1 0 1 0 136.0 68.0 34.0 17.0 48.00741 0 1 0 1 1 140.0 70.0 35.0 17.5 48.00741 0 1 1 0 0 144.0 72.0 36.0 18.0 48.00741 0 1 1 0 1 148.0 74.0 37.0 18.5 48.00741 0 1 1 1 0 152.0 76.0 38.0 19.0 48.00741 0 1 1 1 1 156.0 78.0 39.0 19.5 48.00741 1 0 0 0 0 160.0 80.0 40.0 20.0 48.00741 1 0 0 0 1 164.0 82.0 41.0 20.5 48.00741 1 0 0 1 0 166.6 66.6 33.3 16.7 48.00741 1 0 0 1 1 170.0 68.0 34.0 17.0 48.00741 1 0 1 0 0 175.0 70.0 35.0 17.5 48.00741 1 0 1 0 1 180.0 72.0 36.0 18.0 48.00741 1 0 1 1 0 185.0 74.0 37.0 18.5 48.00741 1 0 1 1 1 190.0 76.0 38.0 19.0 48.00741 1 1 0 0 0 66.8 66.8 33.4 16.7 48.00741 1 1 0 0 1 100.2 66.8 33.4 16.7 48.00741 1 1 0 1 0 133.6 66.8 33.4 16.7 48.00741 1 1 0 1 1 200.4 66.8 33.4 16.7 48.00741 1 1 1 0 0 66.6 66.6 33.3 16.5 48.00741 1 1 1 0 1 100.0 66.6 33.3 16.5 48.00741 1 1 1 1 0 200.0 66.6 33.3 16.5 48.00741 1 1 1 1 1 133.3 66.6 33.3 16.5 48.00741 Programmable Output Frequency, Watchdog Timer and Recovery Output Frequency Functional Description The Programmable Output Frequency feature allows users to generate any CPU output frequency from the range of 50 MHz to 248 MHz. Cypress offers the most dynamic and the simplest programming interface for system developers to utilize this feature in their platforms. Document #: 38-07119 Rev. ** The Watchdog Timer and Recovery Output Frequency features allow users to implement a recovery mechanism when the system hangs or getting unstable. System BIOS or other control software can enable the Watchdog timer before they attempt to make a frequency change. If the system hangs and a Watchdog timer time-out occurs, a system reset will be generated and a recovery frequency will be activated. All the related registers are summarized in the following table. Page 12 of 19 CY28325-2 PRELIMINARY Register Summary Name Description Pro_Freq_EN Programmable output frequencies enabled 0 = Disabled (default). 1 = Enabled. When it is disabled, the operating output frequency will be determined by either the latched value of FS[4:0] inputs or the programmed value of SEL[4:0]. If FS_Override bit is clear, latched FS[4:0] inputs will be used. If FS_Override bit is set, programmed value of SEL[4:0] will be used. When it is enabled, the CPU output frequency will be determined by the programmed value of CPUFSEL_N, CPUFSEL_M and the PLL Gear Constant. The program value of FS_Override, SEL[4:0] or the latched value of FS[4:0] will determine the PLL Gear Constant and the frequency ratio between CPU and other frequency outputs. FS_Override When Pro_Freq_EN is cleared or disabled 0 = Select operating frequency by FS input pins (default). 1 = Select operating frequency by SEL bits in SMBus control bytes. When Pro_Freq_EN is set or enabled 0 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are based on the latched value of FS input pins (default). 1 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are based on the programmed value of SEL bits in SMBus control bytes. CPU_FSEL_N, CPU_FSEL_M When Prog_Freq_EN is set or enabled, the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] determines the CPU output frequency. The new frequency will start to load whenever there is an update to either CPU_FSEL_N[7:0] or CPU_FSEL_M[6:0]. Therefore, it is recommended to use Word or Block Write to update both registers within the same SMBus bus operation. The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PIC. When FS_Override is cleared or disabled, the frequency ratio follows the latched value of the FS input pins. When FS_Override is set or enabled, the frequency ratio follows the programmed value of SEL bits in SMBus control bytes. ROCV_FREQ_SEL ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog timer time-out occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL. 0 = From latched FS[4:0] 1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0]. ROCV_FREQ_N[7:0], ROCV_FREQ_M[6:0] When ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency when a Watchdog Timer time-out occurs. The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PIC. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. The new frequency will start to load whenever there is an update to either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recommended to use Word or Block Write to update both registers within the same SMBus bus operation. WD_EN 0 = Stop and reload Watchdog Timer. 1 = Enable Watchdog Timer. It will start counting down after a frequency change occurs. WD_TO_STATUS Watchdog Timer Time-out Status bit 0 = No time-out occurs (Read); Ignore (Write) 1 = time-out occurred (Read); Clear WD_TO_STATUS (Write). WD_TIMER[4:0] These bits store the time-out value of the Watchdog Timer. The scale of the timer is determine by the prescaler. The timer can support a value of 150 ms to 4.8 sec when the pre-scaler is set to 150 ms. If the pre-scaler is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec. When the Watchdog Timer reaches “0,” it will set the WD_TO_STATUS bit. WD_PRE_SCALER 0 = 150 ms 1 = 2.5 sec RST_EN_WD This bit will enable the generation of a Reset pulse when a Watchdog timer time-out occurs. 0 = Disabled 1 = Enabled RST_EN_FC This bit will enable the generation of a Reset pulse after a frequency change occurs. 0 = Disabled 1 = Enabled Document #: 38-07119 Rev. ** Page 13 of 19 CY28325-2 PRELIMINARY Program the CPU output frequency When the programmable output frequency feature is enabled (Pro_Freq_EN bit is set), the CPU output frequency is determined by the following equation: Fcpu = G * (N+3)/(M+3). “N” and “M” are the values programmed in Programmable Frequency Select N-Value Register and M-Value Register, respectively. “G” stands for the PLL Gear Constant, which is determined by the programmed value of FS[4:0] or SEL[4:0]. The value is listed in Table 4. The ratio of (N+3) and (M+3) need to be greater than “1” [(N+3)/(M+3) > 1]. The following table lists set of N and M values for different frequency output ranges.This example use a fixed value for the M-Value Register and select the CPU output frequency by changing the value of the N-Value Register. Table 5. Examples of N and M Value for Different CPU Frequency Range Frequency Ranges Gear Constants Fixed Value for M-Value Register Range of N-Value Register for Different CPU Frequency 50 MHz–129 MHz 48.00741 93 97 - 255 130 MHz–248 MHz 48.00741 45 127 - 245 Document #: 38-07119 Rev. ** Page 14 of 19 CY28325-2 PRELIMINARY Maximum Ratings Storage Temperature (Non-Condensing) ... –65°C to +150°C (Above which the useful life may be impaired. For user guidelines, not tested.) Max. Soldering Temperature (10 sec) ...................... +260°C Supply Voltage ................................................. –0.5 to +7.0V Input Voltage ..............................................–0.5V to VDD+0.5 Junction Temperature ............................................... +150°C Package Power Dissipation...............................................1Ω Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................ > 2000V Operating Conditions Over which Electrical Parameters are Guaranteed Min. Max. Unit VDD_REF, VDD_PCI,VDD_AGP, VDD_CPU, VDD_48MHz Parameter 3.3V Supply Voltages Description 3.135 3.465 V VDD_CPPU_CS CPU_CS Supply Voltage 2.375 3.625 V TA Operating Temperature, Ambient 0 70 °C Cin Input Pin Capacitance 5 pF CXTAL XTAL Pin Capacitance 22.5 pF CL Max. Capacitive Load on 24_48MHz, 48 MHz, REF PCI, AGP f(REF) Reference Frequency, Oscillator Nominal Value pF 20 30 14.318 14.318 MHz Electrical Characteristics Over the Operating Range Parameter Description VIH High-level Input Voltage Test Conditions Min. Max. Unit Except Crystal Pads. Threshold voltage for crystal pads = VDD/2 VIL Low-level Input Voltage Except Crystal Pads VOH High-level Output Voltage 24_48MHz, 48 MHz, REF, AGP VOL Low-level Output Voltage PCI IOL = 1 mA IIH Input HIGH Current 0 < VIN < VDD IIL Input LOW Current 0 < VIN < VDD IOH High-level Output Current CPUT0:1,CPUC0:1 For IOH =6*IRef Configuration Type X1, VOH = 0.65V REF, 24_48MHz, 48 MHz Type 3, VOH = 1.00V 2.0 0.8 IOH = –1 mA 2.4 PCI IOH = –1 mA 2.4 24_48MHz, 48 MHz, REF, AGP IOL = 1 mA Type 5, VOH = 1.00V 0.55 V 5 mA –5 5 12.9 REF, 24_48MHz, 48 MHz Type 3, VOL = 1.95V 14.9 –23 –33 –33 29 Type 3, VOL = 0.4V AGP, PCI Type 5, VOL =1.95 V Type 5, VOL = 0.4V IOZ Output Leakage Current IDD IDDPD mA mA –29 Type 5, VOH = 3.135V Low-level Output Current V V –5 Type X1, VOH = 0.74V AGP, PCI V V 0.4 Type 3, VOH = 3.135V IOL V mA 27 30 38 Three-state 10 Power Supply Current 3.3 VDD = 3.465V, 2.5V VDD – 2.625V 360 mA Shutdown Current 3.3 VDD = 3.465V, 2.5V VDD – 2.625V 20 mA Document #: 38-07119 Rev. ** mA Page 15 of 19 CY28325-2 PRELIMINARY - Switching Characteristics[2] Over the Operating Range Parameter Output Description [3] Test Conditions Min. Max. Unit t1 24_48 MHz, 48 MHz, REF, AGP, PCI Output Duty Cycle Measured at 1.5V 45 55 % t1 CPU_CS Output Duty Cycle[3] t2 24_48 MHz Measured at 1.5V 45 55 % [6] Between 0.4V and 2.4V 0.5 2.0 ps [6] Rising Edge Rate t2 PCI, AGP Rising Edge Rate Between 0.4V and 2.4V 0.5 2.0 ps t3 24_48 MHz, 48 MHz Falling Edge Rate Between 2.4V and 0.4V 0.5 2.0 ps t3 PCI,AGP Falling Edge Rate[6.] Between 2.4V and 0.4V 1.0 4.0 V/ns t5 AGP[0:2] AGP-AGP Skew Measured at 1.5V 300 ps t6 PCI PCI-PCI Skew Measured at 1.5V 500 ps t9 AGP Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 250 ps t9 24_48 MHz, 48 MHz Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 350 ps t9 PCI Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 500 ps t9 REF Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 1000 ps CPUT0:1, CPUC0:1 0.7V Switching Characteristics t2 CPU Rise Time Measured single ended waveform from 0.14V to 0.56V 175 700 ps t3 CPU Fall Time Measured single ended waveform from 0.14V to 0.56V 175 700 ps t4 CPU CPU-CPU Skew Measured at Crossover 150 ps t8 CPU Cycle-Cycle Clock Jitter Measured at Crossover t8 = t8A – t8B With all outputs running 150 ps CPU Rise/Fall Matching Measured with test loads[4, 5] 20 % 0.85 V [5] Voh CPU High-level Output Voltage including overshoot Measured with test loads Vol CPU Low-level Output Voltage including undershoot Measured with test loads[5] -0.15 Vcrossover CPU Crossover Voltage Measured with test loads[5] 0.28 V 0.43 V Notes: 2. All parameters specified with loaded outputs. 3. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V. 4. Determined as a fraction of 2*(Trp – Trn)/(Trp +Trn) where Trp is a rising edge and Trp is an intersecting falling edge. 5. The 0.7V test load is Rs = 33.2 ohm, Rp = 49.9 ohm in test circuit. 6. Characterize with control register, data byte 9, bits 5 and 6 = 1. Document #: 38-07119 Rev. ** Page 16 of 19 CY28325-2 PRELIMINARY Switching Waveforms Duty Cycle Timing (Single-ended Output) t1B t1A Duty Cycle Timing (CPU Differential Output) t1B t1A All Outputs Rise/Fall Time VDD OUTPUT 0V t3 t2 CPU-CPU Clock Skew Host_b Host Host_b Host t4 AGP-AGP Clock Skew AGP AGP t5 PCI-PCI Clock Skew PCI PCI t6 Document #: 38-07119 Rev. ** Page 17 of 19 CY28325-2 PRELIMINARY Switching Waveforms (continued) CPU Clock Cycle-Cycle Jitter t8A t8B Host_b Host Cycle-Cycle Clock Jitter t9A t9B CLK Ordering Information Ordering Code CY28325-2 Package Name Package Type PVC 48-pin Shrunk Small Outline Package (SSOP) Operating Range Commercial Package Diagram 48-lead Shrunk Small Outline Package O48 51-85061-*C Pentium 4 is a registered trademark of Intel Corporation. VIA is a trademark of VIA Technologies, Inc. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07119 Rev. ** Page 18 of 19 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY28325-2 PRELIMINARY Document Title: CY28325-2 FTG for Via Pentium 4 Chipsets Document Number: 38-07119 REV. ECN NO. Issue Date Orig. of Change ** 111733 03/06/02 IKA Document #: 38-07119 Rev. ** Description of Change New Data Sheet Added notes to page 18 Page 19 of 19