MMBT4126LT1 Preferred Device General Purpose Transistor PNP Silicon • Moisture Sensitivity Level: 1 • ESD Rating – Human Body Model: >4000 V ESD Rating – Machine Model: >400 V http://onsemi.com MAXIMUM RATINGS Rating Symbol Value Unit Collector–Emitter Voltage VCEO –25 Vdc Collector–Base Voltage VCBO –25 Vdc Emitter–Base Voltage VEBO –4 Vdc IC –200 mAdc Characteristic Symbol Max Unit Total Device Dissipation FR–5 Board (Note 1.) TA = 25°C Derate above 25°C PD 225 mW Collector Current–Continuous COLLECTOR 3 1 BASE 2 EMITTER THERMAL CHARACTERISTICS 3 1.8 mW/°C 1 Thermal Resistance, Junction to Ambient (Note 1.) RJA 556 °C/W Total Device Dissipation Alumina Substrate, (Note 2.) TA = 25°C Derate above 25°C PD 300 mW 2.4 mW/°C Thermal Resistance, Junction to Ambient (Note 2.) RJA 417 °C/W MARKING DIAGRAM TJ, Tstg –55 to +150 °C C3 M Junction and Storage Temperature Range 2 SOT–23 CASE 318 STYLE 6 1. FR–5 = 1.0 0.75 0.062 in. 2. Alumina = 0.4 0.3 0.024 in. 99.5% alumina. C3 = Device Code M = Date Code ORDERING INFORMATION Device Package Shipping MMBT4126LT1 SOT–23 3000/Tape & Reel Preferred devices are recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2001 March, 2001 – Rev. 0 1 Publication Order Number: MMBT4126LT1/D MMBT4126LT1 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Characteristic Min Max –25 – –25 – –4 – – –50 120 60 300 – – –0.4 – –0.95 250 – – 4.5 – 10 120 2.5 480 – – 4.0 Unit OFF CHARACTERISTICS Collector–Emitter Breakdown Voltage (Note 3.) (IC = –1.0 mAdc, IB = 0) V(BR)CEO Collector–Base Breakdown Voltage (IC = –10 Adc, IE = 0) V(BR)CBO Emitter–Base Breakdown Voltage (IE = –10 Adc, IC = 0) V(BR)EBO Collector Cutoff Current (VCE = –30 Vdc, VEB = –3.0 Vdc) Vdc Vdc Vdc ICEX nAdc ON CHARACTERISTICS (Note 3.) DC Current Gain (IC = –2.0 mAdc, VCE = –1.0 Vdc) (IC = –50 mAdc, VCE = –1.0 Vdc) HFE Collector–Emitter Saturation Voltage (IC = –50 mAdc, IB = –5.0 mAdc) VCE(sat) Base–Emitter Saturation Voltage (IC = –50 mAdc, IB = –5.0 mAdc) VBE(sat) – Vdc Vdc SMALL–SIGNAL CHARACTERISTICS Current–Gain – Bandwidth Product (IC = –10 mAdc, VCE = –20 Vdc, f = 100 MHz) fT MHz Output Capacitance (VCB = –5.0 Vdc, IE = 0, f = 1.0 MHz) Cobo Input Capacitance (VEB = –0.5 Vdc, IC = 0, f = 1.0 MHz) Cibo Small–Signal Current Gain (IC = –2.0 mAdc, VCE = –10 Vdc, f = 1.0 kHz) (IC = 10 mAdc, VCE = 20 Vdc, f = 100 MHz) hfe Noise Figure (IC = –100 Adc, VCE = –5.0 Vdc, RS = 1.0 kΩ, f = 1.0 kHz) NF pF pF – dB 3. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%. TYPICAL TRANSIENT CHARACTERISTICS 10 5000 7.0 3000 2000 Cobo 5.0 Q, CHARGE (pC) CAPACITANCE (pF) TJ = 25°C TJ = 125°C Cibo 3.0 2.0 1.0 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 REVERSE BIAS (VOLTS) 1000 700 500 300 200 100 70 50 20 30 40 VCC = 40 V IC/IB = 10 QT 1.0 Figure 1. Capacitance 2.0 3.0 QA 5.0 7.0 10 20 30 50 70 100 IC, COLLECTOR CURRENT (mA) Figure 2. Charge Data http://onsemi.com 2 200 MMBT4126LT1 TYPICAL AUDIO SMALL–SIGNAL CHARACTERISTICS NOISE FIGURE VARIATIONS (VCE = –5.0 Vdc, TA = 25°C, Bandwidth = 1.0 Hz) 12 SOURCE RESISTANCE = 200 IC = 1.0 mA 4.0 f = 1.0 kHz SOURCE RESISTANCE = 200 IC = 0.5 mA 3.0 SOURCE RESISTANCE = 2.0 k IC = 50 A 2.0 SOURCE RESISTANCE = 2.0 k IC = 100 A 1.0 0 0.1 0.2 0.4 IC = 1.0 mA 10 NF, NOISE FIGURE (dB) NF, NOISE FIGURE (dB) 5.0 1.0 2.0 4.0 10 f, FREQUENCY (kHz) 20 40 8 6 4 IC = 50 A 2 IC = 100 A 0 100 IC = 0.5 mA 0.1 0.2 40 0.4 1.0 2.0 4.0 10 20 Rg, SOURCE RESISTANCE (k OHMS) Figure 3. 100 Figure 4. h PARAMETERS (VCE = –10 Vdc, f = 1.0 kHz, TA = 25°C) 100 hoe, OUTPUT ADMITTANCE ( mhos) h fe , DC CURRENT GAIN 300 200 100 70 50 70 50 30 20 10 7 30 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 IC, COLLECTOR CURRENT (mA) 5 5.0 7.0 10 0.1 0.2 Figure 5. Current Gain h re , VOLTAGE FEEDBACK RATIO (X 10 -4 ) h ie , INPUT IMPEDANCE (k OHMS) 10 7.0 5.0 3.0 2.0 1.0 0.7 0.5 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 IC, COLLECTOR CURRENT (mA) 5.0 7.0 10 Figure 6. Output Admittance 20 0.3 0.2 0.3 0.5 0.7 1.0 2.0 3.0 IC, COLLECTOR CURRENT (mA) 10 7.0 5.0 3.0 2.0 1.0 0.7 0.5 5.0 7.0 10 0.1 Figure 7. Input Impedance 0.2 0.3 0.5 0.7 1.0 2.0 3.0 IC, COLLECTOR CURRENT (mA) 5.0 7.0 10 Figure 8. Voltage Feedback Ratio http://onsemi.com 3 MMBT4126LT1 h FE, DC CURRENT GAIN (NORMALIZED) TYPICAL STATIC CHARACTERISTICS 2.0 TJ = +125°C VCE = 1.0 V +25°C 1.0 0.7 -55°C 0.5 0.3 0.2 0.1 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 IC, COLLECTOR CURRENT (mA) 20 30 50 70 100 200 VCE, COLLECTOR EMITTER VOLTAGE (VOLTS) Figure 9. DC Current Gain 1.0 TJ = 25°C 0.8 IC = 1.0 mA 10 mA 30 mA 100 mA 0.6 0.4 0.2 0 0.01 0.02 0.03 0.05 0.07 0.1 0.2 0.3 0.5 IB, BASE CURRENT (mA) 0.7 1.0 2.0 3.0 5.0 7.0 10 1.0 TJ = 25°C V, VOLTAGE (VOLTS) 0.8 V , TEMPERATURE COEFFICIENTS (mV/ °C) Figure 10. Collector Saturation Region VBE(sat) @ IC/IB = 10 VBE @ VCE = 1.0 V 0.6 0.4 VCE(sat) @ IC/IB = 10 0.2 0 1.0 2.0 50 5.0 10 20 IC, COLLECTOR CURRENT (mA) 100 200 1.0 0.5 VC FOR VCE(sat) 0 +25°C TO +125°C -55°C TO +25°C -0.5 +25°C TO +125°C -1.0 -55°C TO +25°C VB FOR VBE(sat) -1.5 -2.0 0 Figure 11. “ON” Voltages 20 40 60 80 100 120 140 IC, COLLECTOR CURRENT (mA) 160 Figure 12. Temperature Coefficients http://onsemi.com 4 180 200 MMBT4126LT1 INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.037 0.95 0.037 0.95 0.079 2.0 0.035 0.9 0.031 0.8 inches mm SOT–23 SOT–23 POWER DISSIPATION into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 225 milliwatts. The power dissipation of the SOT–23 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RθJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT–23 package, PD can be calculated as follows: PD = PD = 150°C – 25°C 556°C/W = 225 milliwatts The 556°C/W for the SOT–23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 225 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT–23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. TJ(max) – TA RθJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS • The soldering temperature and time shall not exceed 260°C for more than 10 seconds. • When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less. • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. • Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 5 MMBT4126LT1 PACKAGE DIMENSIONS SOT–23 TO–236AB CASE 318–09 ISSUE AF A L 3 1 V B 2 S DIM A B C D G H J K L S V G C D H NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. MAXIUMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. K J INCHES MIN MAX 0.1102 0.1197 0.0472 0.0551 0.0385 0.0498 0.0140 0.0200 0.0670 0.0826 0.0040 0.0098 0.0034 0.0070 0.0180 0.0236 0.0350 0.0401 0.0830 0.0984 0.0177 0.0236 STYLE 6: PIN 1. BASE 2. EMITTER 3. COLLECTOR http://onsemi.com 6 MILLIMETERS MIN MAX 2.80 3.04 1.20 1.40 0.99 1.26 0.36 0.50 1.70 2.10 0.10 0.25 0.085 0.177 0.45 0.60 0.89 1.02 2.10 2.50 0.45 0.60 MMBT4126LT1 Notes http://onsemi.com 7 MMBT4126LT1 Thermal Clad is a registered trademark of the Bergquist Company ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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