CY62138FV30 MoBL® 2-Mbit (256 K × 8) Static RAM 2-Mbit (256 K × 8) Static RAM Features Functional Description ■ Very high-speed: 45 ns The CY62138FV30 is a high performance CMOS static RAM organized as 256K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption. Place the device into standby mode reducing power consumption when deselected (CE1 HIGH or CE2 LOW). ■ Temperature ranges ❐ Industrial: –40 °C to 85 °C ❐ Automotive-A: –40 °C to 85 °C ■ Wide voltage range: 2.20 V to 3.60 V ■ Pin compatible with CY62138CV25/30/33 ■ Ultra low standby power ❐ Typical standby current: 1 A ❐ Maximum standby current: 5 A ■ Ultra low active power ❐ Typical active current: 1.6 mA at f = 1 MHz ■ Easy memory expansion with CE1, CE2, and OE Features ■ Automatic power down when deselected ■ Complementary metal oxide semiconductor (CMOS) for Optimum speed and power ■ Offered in Pb-free 36-ball VFBGA, 32-pin TSOP II, 32-pin SOIC, 32-pin TSOP I and 32-pin STSOP packages To write to the device, take Chip Enable (CE1 LOW and CE2 HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A17). To read from the device, take Chip Enable (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW and CE2 HIGH and WE LOW). Logic Block Diagram Cypress Semiconductor Corporation Document #: 001-08029 Rev. *K • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 16, 2011 [+] Feedback CY62138FV30 MoBL® Contents Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Document #: 001-08029 Rev. *K Truth Table ........................................................................ 9 Ordering Information ...................................................... 10 Ordering Code Definitions ......................................... 10 Package Diagrams .......................................................... 11 Acronyms ........................................................................ 16 Document Conventions ................................................. 16 Units of Measure ....................................................... 16 Document History Page ................................................. 17 Sales, Solutions, and Legal Information ...................... 18 Worldwide Sales and Design Support ....................... 18 Products .................................................................... 18 PSoC Solutions ......................................................... 18 Page 2 of 18 [+] Feedback CY62138FV30 MoBL® Pin Configuration Figure 1. 36-ball VFBGA (Top View) [1] 1 2 3 4 5 6 A0 A1 CE2 A3 A6 A8 A I/O4 A2 WE A4 A7 I/O0 B NC A5 I/O1 C I/O5 VSS VCC D VCC VSS E I/O2 F I/O6 NC A17 Figure 2. 32-pin SOIC/TSOP II (Top View) I/O7 OE CE1 A16 A15 I/O3 G A9 A10 A11 A12 A13 A14 H A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS Figure 3. 32-pin TSOP I (Top View) A11 A9 A8 A13 WE CE2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 TSOP I Top View (not to scale) 1 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 32 31 2 3 4 30 29 5 6 28 27 26 25 7 8 9 10 24 23 22 11 12 13 14 15 16 21 20 19 18 17 Figure 4. 32-pin STSOP (Top View) A11 A9 A8 A13 WE CE2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 25 26 27 26 28 29 30 31 32 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 STSOP Top View (not to scale) OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 Product Portfolio Power Dissipation Product CY62138FV30LL Range Industrial / Automotive-A VCC Range (V) Min Typ [2] Max 2.2 3.0 3.6 Speed (ns) 45 Operating ICC (mA) f = 1 MHz f = fmax Standby ISB2 (A) Typ [2] Max Typ [2] Max Typ [2] Max 1.6 2.5 13 18 1 5 Notes 1. NC pins are not connected on the die. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C. Document #: 001-08029 Rev. *K Page 3 of 18 [+] Feedback CY62138FV30 MoBL® DC input voltage [3, 4] .....................................–0.3 V to 3.9 V Maximum Ratings Output current into outputs (LOW) ............................. 20 mA Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Static Discharge Voltage ........................................ > 2001 V (MIL-STD-883, Method 3015) Storage temperature ................................ –65 °C to +150 °C Latch-up current .................................................... > 200 mA Ambient temperature with power applied .......................................... –55 °C to +125 °C Operating Range Supply voltage to ground potential .........................................................–0.3 V to 3.9 V DC voltage applied to outputs in High Z State [3, 4] ........................................–0.3 V to 3.9 V Product Range Ambient Temperature VCC [5] CY62138FV30LL Industrial / Automotive-A –40 °C to +85 °C 2.2 V to 3.6 V Electrical Characteristics Over the Operating Range Parameter Description Output HIGH voltage VOH Output LOW voltage VOL Test Conditions 45 ns (Industrial / Automotive-A) Typ [6] Max IOH = –0.1 mA 2.0 – – V IOH = –1.0 mA, VCC > 2.70 V 2.4 – – V – – 0.4 V – 0.4 V IOL = 0.1 mA IOL = 2.1 mA, VCC > 2.70 V Input HIGH voltage VIH Input LOW voltage VIL Unit Min VCC = 2.2 V to 2.7 V 1.8 – VCC + 0.3 V V VCC= 2.7 V to 3.6 V 2.2 – VCC + 0.3 V V VCC = 2.2 V to 2.7 V For BGA package –0.3 – 0.6 V VCC= 2.7 V to 3.6 V –0.3 – 0.8 V VCC = 2.2 V to 3.6 V For other packages –0.3 – 0.6 V IIX Input leakage current GND < VI < VCC –1 – +1 A IOZ Output leakage current GND < VO < VCC, output disabled –1 – +1 A ICC VCC Operating supply current f = fmax = 1/tRC – 13 18 mA – 1.6 2.5 – 1 5 A – 1 5 A f = 1 MHz ISB1[7] Automatic CE Power-down current–CMOS inputs VCC = VCCmax, IOUT = 0 mA, CMOS levels CE1 > VCC – 0.2 V or CE2 < 0.2 V, VIN > VCC – 0.2 V, VIN < 0.2 V, f = fmax (address and data only), f = 0 (OE, and WE), VCC = 3.60 V ISB2 [7] Automatic CE Power-down current–CMOS inputs CE1 > VCC – 0.2 V or CE2 < 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0, VCC = 3.60 V Notes 3. VIL(min) = –2.0 V for pulse durations less than 20 ns. 4. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns. 5. Full device AC operation assumes a 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization. 6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C. 7. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. Document #: 001-08029 Rev. *K Page 4 of 18 [+] Feedback CY62138FV30 MoBL® Capacitance Parameter[8] Description Test Conditions CIN Input Capacitance COUT Output Capacitance Max TA = 25 °C, f = 1 MHz, VCC = VCC(typ.) Unit 10 pF 10 pF Thermal Resistance Parameter[8] JA Description Test Conditions Thermal resistance Still air, soldered on a 3 × 4.5 (Junction to Ambient) inch, two layer printed circuit board Thermal resistance JC (Junction to Case) 32-pin SOIC 36-ball VFBGA 32-pin TSOP II 32-pin STSOP 32-pin TSOP I Unit 44.53 38.49 44.16 59.72 50.19 C/W 24.05 17.66 11.97 15.38 14.59 C/W AC Test Loads and Waveforms Figure 5. AC Test Loads and Waveforms R1 VCC OUTPUT ALL INPUT PULSES VCC R2 30 pF INCLUDING JIG AND SCOPE 90% 10% 90% 10% GND Rise Time = 1 V/ns Equivalent to: Fall Time = 1 V/ns THEVENIN EQUIVALENT OUTPUT RTH V Parameter 2.5 V (2.2 V to 2.7 V) 3.0 V (2.7 V to 3.6 V) Unit R1 16667 1103 R2 15385 1554 RTH 8000 645 VTH 1.20 1.75 V Note 8. Tested initially and after any design or process changes that may affect these parameters. Document #: 001-08029 Rev. *K Page 5 of 18 [+] Feedback CY62138FV30 MoBL® Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR Description Conditions VCC for data retention [10] Data retention current VCC = 1.5 V, CE1 > VCC 0.2 V or CE2 < 0.2 V, VIN > VCC 0.2 V or VIN < 0.2 V Industrial / Automotive-A Min Typ [9] Max Unit 1.5 – – V – 1 4 A tCDR [11] Chip deselect to data retention time 0 – – ns tR [12] Operation recovery time 45 – – ns Data Retention Waveform Figure 6. Data Retention Waveform [13] DATA RETENTION MODE VCC VCC(min) tCDR VDR > 1.5 V VCC(min) tR CE Notes 9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C. 10. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. 11. Tested initially and after any design or process changes that may affect these parameters. 12. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 13. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. Document #: 001-08029 Rev. *K Page 6 of 18 [+] Feedback CY62138FV30 MoBL® Switching Characteristics Over the Operating Range Parameter [14] Description 45 ns (Industrial/ Automotive-A) Min Max Unit Read Cycle tRC Read cycle time 45 – ns tAA Address to data valid – 45 ns tOHA Data hold from address change 10 – ns tACE CE1 LOW and CE2 HIGH to data valid – 45 ns tDOE OE LOW to data valid – 22 ns tLZOE OE LOW to Low Z [15] 5 – ns OE HIGH to High Z tHZOE tLZCE [15, 16] – 18 ns [15] 10 – ns [15, 16] – 18 ns CE1 LOW and CE2 HIGH to Low Z tHZCE CE1 HIGH or CE2 LOW to High Z tPU CE1 LOW and CE2 HIGH to Power-up 0 – ns CE1 HIGH or CE2 LOW to Power-down – 45 ns tWC Write cycle time 45 – ns tSCE CE1 LOW and CE2 HIGH to write end 35 – ns tAW Address setup to write end 35 – ns tHA Address hold from write end 0 – ns tSA Address setup to Write Start 0 – ns tPWE WE pulse Width 35 – ns tSD Data setup to write end 25 – ns tHD Data hold from write end 0 – ns – 18 ns 10 – ns tPD Write Cycle [17] [15, 16] tHZWE WE LOW to High Z tLZWE WE HIGH to Low Z [15] Notes 14. Test conditions for all parameters other than tristate parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the AC Test Loads and Waveforms on page 5. 15. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 16. tHZOE, tHZCE, and tHZWE transitions are measured when the output enters a high impedance state. 17. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. Reference the data input setup and hold timing to the edge of the signal that terminates the write. Document #: 001-08029 Rev. *K Page 7 of 18 [+] Feedback CY62138FV30 MoBL® Switching Waveforms Figure 7. Read Cycle 1 (Address transition controlled) [18, 19] tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 8. Read Cycle No. 2 (OE controlled) [19, 20, 21] ADDRESS tRC CE tACE OE tHZOE tDOE tHZCE tLZOE HIGH IMPEDANCE DATA OUT DATA VALID tLZCE tPD tPU VCC SUPPLY CURRENT HIGH IMPEDANCE 50% 50% Figure 9. Write Cycle No. 1 (WE controlled) ICC ISB [21, 22, 23, 24] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD DATA I/O NOTE 25 tHD DATA VALID tHZOE Notes 18. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 19. WE is HIGH for read cycle. 20. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH. 21. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 22. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. Reference the data input setup and hold timing to the edge of the signal that terminates the write. 23. Data I/O is high impedance if OE = VIH. 24. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state. 25. During this period, the I/Os are in output state. Do not apply input signals. Document #: 001-08029 Rev. *K Page 8 of 18 [+] Feedback CY62138FV30 MoBL® Switching Waveforms (continued) Figure 10. Write Cycle No. 2 (CE1 or CE2 controlled) [26, 27, 28, 29] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID Figure 11. Write Cycle No. 3 (WE controlled, OE LOW) [26, 29] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD NOTE 30 DATA I/O tHD DATA VALID tLZWE tHZWE Truth Table CE1 CE2 WE OE H X[31] Inputs/Outputs Mode Power X X High Z Deselect/Power-down Standby (ISB) X[31] L X X High Z Deselect/Power-down Standby (ISB) L H H L Data out Read Active (ICC) L H H H High Z Output disabled Active (ICC) L H L X Data in Write Active (ICC) Notes 26. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 27. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. Reference the data input setup and hold timing to the edge of the signal that terminates the write. 28. Data I/O is high impedance if OE = VIH. 29. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains iin high impedance state. 30. During this period, the I/Os are in output state. Do not apply input signals. 31. The ‘X’ (Don’t care) state for the Chip enables (CE1 and CE2) in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted. Document #: 001-08029 Rev. *K Page 9 of 18 [+] Feedback CY62138FV30 MoBL® Ordering Information Speed (ns) 45 Ordering Code Package Diagram Package Type CY62138FV30LL-45BVXI 51-85149 36-ball VFBGA (Pb-free) CY62138FV30LL-45ZSXI 51-85095 32-pin TSOP II (Pb-free) CY62138FV30LL-45ZAXI 51-85094 32-pin STSOP (Pb-free) CY62138FV30LL-45ZXI 51-85056 32-pin TSOP I (Pb-free) CY62138FV30LL-45SXI 51-85081 32-pin SOIC (Pb-free) CY62138FV30LL-45ZAXA 51-85094 32-pin STSOP (Pb-free) Operating Range Industrial Automotive-A Ordering Code Definitions CY 621 3 8 F V30 LL - 45 XX X X Temperature Grade: X = I or A I = Industrial; A = Automotive-A Pb-free Package Type: XX = BV or ZS or ZA or Z or S BV = 36-ball VFBGA ZS= 32-pin TSOP II ZA = 32-pin STSOP Z = 32-pin TSOP I S = 32-pin SOIC Speed Grade: 45 ns LL = Low Power Voltage Range: 3 V Typical F = Process Technology 90 nm Buswidth = × 8 Density = 2-Mbit Family Code: MoBL SRAM family Company ID: CY = Cypress Document #: 001-08029 Rev. *K Page 10 of 18 [+] Feedback CY62138FV30 MoBL® Package Diagrams Figure 12. 36-ball VFBGA (6 × 8 × 1.0 mm) BV36A, 51-85149 51-85149 *D Document #: 001-08029 Rev. *K Page 11 of 18 [+] Feedback CY62138FV30 MoBL® Figure 13. 32-pin TSOP II (20.95 × 11.76 × 1.0 mm) ZS32, 51-85095 51-85095 *B Document #: 001-08029 Rev. *K Page 12 of 18 [+] Feedback CY62138FV30 MoBL® Figure 14. 32-pin Molded SOIC (450 Mil) S32.45/SZ32.45, 51-85081 51-85081 *C Document #: 001-08029 Rev. *K Page 13 of 18 [+] Feedback CY62138FV30 MoBL® Figure 15. 32-pin TSOP I (8 × 20 ×1.0 mm) Z32, 51-85056 51-85056 *F Document #: 001-08029 Rev. *K Page 14 of 18 [+] Feedback CY62138FV30 MoBL® Figure 16. 32-pin STSOP (8 × 13.4 × 1.2 mm) ZA32, 51-85094 51-85094 *F Document #: 001-08029 Rev. *K Page 15 of 18 [+] Feedback CY62138FV30 MoBL® Acronyms Acronym Document Conventions Description Units of Measure BGA ball grid array CMOS complementary metal oxide semiconductor °C degree Celsius I/O input/output MHz Mega Hertz OE output enable A micro Amperes SOIC small-outline integrated circuit s micro seconds SRAM static random access memory mA milli Amperes STSOP small thin small outline package mm milli meter TSOP thin small outline package ns nano seconds VFBGA very fine-pitch ball grid array ohms WE write enable % percent pF pico Farads V Volts W Watts Document #: 001-08029 Rev. *K Symbol Unit of Measure Page 16 of 18 [+] Feedback CY62138FV30 MoBL® Document History Page Document Title: CY62138FV30 MoBL®, 2-Mbit (256 K × 8) Static RAM Document Number: 001-08029 Rev. ECN No. Submission Date Orig. of Change Description of Change ** 463660 See ECN NXR New data sheet *A 467351 See ECN NXR Added 32-pin TSOP II package, 32 pin TSOP I and 32 pin STSOP packages Changed ball A3 from NC to CE2 in 36-ball FBGA pin out *B 566724 See ECN NXR Converted from Preliminary to Final Corrected typo in 32 pin TSOP II pin configuration diagram on page #2 (changed pin 24 from CE1to OE and pin 22 from CE to CE1) Changed the ICC(max) value from 2.25 mA to 2.5 mA for test condition f=1 MHz Changed the ISB2(typ) value from 0.5 A to 1 A Changed the ISB2(max) value from 2.5 A to 5 A Changed the ICCDR(typ) value from 0.5 A to 1 A and ICCDR(max) value from 2.5 A to 4 A *C 797956 See ECN VKN Added 32-pin SOIC package Updated VIL spec for SOIC, TSOP-II, TSOP-I, and STSOP packages on Electrical characteristics table *D 809101 See ECN VKN Corrected typo in the Ordering Information table *E 940341 See ECN VKN Added footnote #7 related to ISB2 and ICCDR *F 2769239 09/25/09 *G 3055119 10/12/2010 RAME Updated and converted all tablenotes into Footnote Added Acronyms and Units of Measure table Added Updated All Package Diagrams. Updated datasheet as per new template. *H 3061313 10/15/2010 RAME Minor changes: Corrected “IO” to “I/O” *I 3078557 11/04/2010 RAME Corrected 55 C to -55C in Ambient Temperature with Power applied in Maximum Ratings Section *J 3235744 04/20/2011 RAME Removed the note “For best practice recommendations, refer to the Cypress application Note “System Design Guidelines” at http://www.cypress.com “ in page 1 and its reference in Functional Description. Updated Package Diagrams. *K 3285093 06/16/2011 RAME Updated in new template. Document #: 001-08029 Rev. *K VKN/AESA Included Automotive-A information Page 17 of 18 [+] Feedback CY62138FV30 MoBL® Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-08029 Rev. *K Revised June 16, 2011 Page 18 of 18 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback