CY25823 CK-SSCD Spread Spectrum Differential Clock Specification Features • 3.3V operation • 96- and 100-MHz frequency support • Selectable slew rate control • 200-ps jitter • I2C programmability • 250-µA power-down current • Lexmark Spread Spectrum for best electromagnetic interference (EMI) reduction • 16-pin TSSOP package Block Diagram VDD VDDA REFOUT Clock Input Freq. Divider M Phase Detector Charge Pump SCLK PWRDWN Post Dividers VCO CLKOUT (SSCG Output) CLKOUT# Modulating Waveform SDATA Logic Control Σ Feedback Divider N PLL VSS Pin Configuration CLKIN S3 S2 S1 PW RDW N REFOUT/SEL SCLK SDATA 1 2 3 4 5 6 7 8 VSSA 16 15 14 13 12 11 10 9 VDDA VSSA IREF VSSIREF CLKOUT CLKOUT# VSS VDD 16 pin TSSOP Cypress Semiconductor Corporation Document #: 38-07579 Rev. *C • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised September 02, 2004 CY25823 Pin Definitions Pin No. Name Type Description 1 CLKIN Input 3.3V 14.131818-MHz single-ended clock input 2,3,4 S[3:1] Input Spread Spectrum configuration 5 PWRDWN Input 3.3V LVTTL input for power-down active high, no pull-up or pull-down 6 REFOUT/SEL I/O Latched input during power-up, 1 (10K external pull-up) = 100 MHz or 0 (10K external pull-down) = 96 MHz. After power-up it becomes 14.31818-MHz REFOUT clock. 7 SCLK Input SMBus-compatible SCLK 8 SDATA I/O SMBus-compatible SDATA 9 VDD 3.3V 10 VSS Ground Ground for logic and outputs 11 CLKOUT# Output 0.7V 96-MHz or 100-MHz Spread Spectrum differential clock output 12 CLKOUT Output 0.7V 96-MHz or 100-MHz Spread Spectrum differential clock output 13 VSSIREF Ground Current reference ground 14 IREF Input 15 VSSA Ground 16 VDDA 3.3V 3.3V power supply for logic and outputs Typically a precision 475Ω external resistor is connected between this pin and VSSIREF to set IOUT (drive current) of CLKOUT differential driver. Ground for PLL 3.3V power supply for PLL Serial Data Interface Data Protocol To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions such as individual clock output buffers can be individually enabled or disabled. The clock driver serial protocol accepts byte write, byte read, block write, and block read operation from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individual indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 1. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. The block write and block read protocol is outlined in Table 2 while Table 3 outlines the corresponding byte write and byte read protocol.The combined 7 bits slave address and read/write bit form a complete block write (D4h) or block read (D5h) command. Table 1. Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 Description Start Slave address – 7 bits (D4) Block Read Protocol Bit 1 2:8 Description Start Slave address – 7 bits (D5) 9 Write = 0 9 Read = 0 10 Acknowledge from slave 10 Acknowledge from slave Document #: 38-07579 Rev. *C Page 2 of 12 CY25823 Table 2. Block Read and Block Write Protocol (continued) Block Write Protocol Bit Block Read Protocol Description 11:18 Bit Command Code – 8 bits '00000000' stands for block operation 19 11:18 Acknowledge from slave 20:27 19 Byte Count – 8 bits 28 20 Acknowledge from slave 29:36 37 38:45 21:27 Acknowledge from slave Repeat start Slave address – 7 bits Data byte 0 – 8 bits 28 Read = 1 Acknowledge from slave 29 Acknowledge from slave Data byte 1 – 8 bits 46 Description Command Code – 8 bits '00000000' stands for block operation 30:37 Acknowledge from slave 38 39:46 Byte count from slave – 8 bits Acknowledge .... ...................... .... Data Byte (N–1) –8 bits 47 Data byte from slave – 8 bits .... Acknowledge from slave 48:55 .... Data Byte N –8 bits 56 Acknowledge .... Acknowledge from slave .... Data bytes from slave/Acknowledge .... Stop .... Data byte N from slave – 8 bits .... Not Acknowledge .... Stop Acknowledge Data byte from slave – 8 bits Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Bit Byte Read Protocol Description 1 Bit Start 2:8 1 Slave address – 7 bits (D4) 9 2:8 Write = 1 10 Acknowledge from slave 11:18 19 Acknowledge from slave 20:27 Acknowledge from slave 29 Stop Read = 1 10 Acknowledge from slave 19 Data byte from master – 8 bits 28 Slave address – 7 bits (D5) 9 11:18 Command Code – 8 bits '100000xx' stands for byte operation, bits[1:0] of the command code represents the offset of the byte to be accessed Description Start 20 21:27 Command Code – 8 bits '100000xx' stands for byte operation, bits[1:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address – 7 bits 28 Read = 1 29 Acknowledge from slave 30:37 Data byte from slave – 8 bits 38 Not Acknowledge 39 Stop Byte 0: Control Register Bit @Power-up Pin# Name Pin Description 7 0 11, 12 SS0 – 6 S1 11, 12 SS1 – 5 S2 11, 12 SS2 – 4 S3 11, 12 SS3 – 3 SEL100/96# SEL100/96# Select output frequency, 1 = 100 MHz, 0 = 96 MHz Document #: 38-07579 Rev. *C 6 Page 3 of 12 CY25823 Byte 0: Control Register (continued) Bit @Power-up 2 0 1 1 0 0 Pin# Name Pin Description Reserved must equal 0 11, 12 Spread Enable Spread spectrum enable, 0 = Disable, 1 = Enable HW/SW Control Hardware/software control of S[3:0], and output frequency. 0 = hardware control, 1= software control. Table 4. Spread Spectrum Select (Charge Pump = 00 or Default Condition) SS3 SS2 SS1 SS0 Spread Mode Spread Amount % 0 0 0 0 Down 0.65 0 0 0 1 Down 0.80 0 0 1 0 Down 0.90 0 0 1 1 Down 1.10 0 1 0 0 Down 1.30 0 1 0 1 Down 1.40 0 1 1 0 Down 1.80 0 1 1 1 Down 2.25 1 0 0 0 Center ±0.25 1 0 0 1 Center ±0.30 1 0 1 0 Center ±0.40 1 0 1 1 Center ±0.45 1 1 0 0 Center ±0.60 1 1 0 1 Center ±0.80 1 1 1 0 Center ±1.00 1 1 1 1 Center ±1.10 Table 5. Spread Spectrum Select (Charge Pump = 11 and 01) SS3 SS2 SS1 SS0 Spread Mode Spread Amount % (Charge pump = 11) Spread Amount % (Charge pump = 01) 0 0 0 0 Down 0.80 0.90 0 0 0 1 Down 0.90 1.10 0 0 1 0 Down 1.20 1.40 0 0 1 1 Down 1.40 1.60 0 1 0 0 Down 1.60 2.00 0 1 0 1 Down 1.75 2.20 0 1 1 0 Down 2.20 2.75 0 1 1 1 Down 2.60 3.30 1 0 0 0 Center ±0.38 ±0.40 1 0 0 1 Center ±0.40 ±0.50 1 0 1 0 Center ±0.50 ±0.60 1 0 1 1 Center ±0.60 ±0.70 1 1 0 0 Center ±0.75 ±0.90 1 1 0 1 Center ±1.00 ±1.25 1 1 1 0 Center ±1.15 ±1.45 1 1 1 1 Center ±1.30 ±1.65 Document #: 38-07579 Rev. *C Page 4 of 12 CY25823 Byte1[7:2] Control Register Bit @Pup Pin# Name Pin Description 7 0 Reserved set equal to ‘0’ 6 0 Reserved set equal to ‘0’ 5 0 Reserved set equal to ‘0’ 4 0 Reserved set equal to ‘0’ 3 0 2 1 Reserved set equal to ‘0’ 11,12 CLKEN CLKOUT/CLKOUT# enable 0 =Disable, 1 = Enable Byte 1: [1:0] Control Register (Charge Pump Settings) Bit Default Value One Step Higher Than Default Two Steps Higher Than Default 1 0 @Pup 0 1 1 0 0 0 1 0 Bytes 2 through 5: Reserved Registers Byte 6: Vendor/Revision ID Register Bit Pin# Name 7 0 @Pup – – Revision ID Bit 3 6 0 – – Revision ID Bit 2 5 0 – – Revision ID Bit 1 4 0 – – Revision ID Bit 0 3 1 – – Vendor ID Bit 3 2 0 – – Vendor ID Bit 2 1 0 – – Vendor ID Bit 1 0 0 – – Vendor ID Bit 0 Spread Enable and Spread Select[3:0] Spread Enable and Spread Select[3:0] register bits are used to enable and disable spread spectrum on CLKOUT and to change the spread modulation. When the spread selection changes, the CLKOUT output transits to the target spread selection without deviating from clock specifications. At device power-up spread spectrum is enabled and hardware control mode is enabled. The initial spread-spectrum configuration is determined by the S[3:1] pins, which correspond to the S[3:1] bits in Table 4. The S0 configuration bit is hard-coded to zero when hardware control mode is selected. All four spread spectrum configuration bits, S[3:0], can also be set when the device is in the software control mode. Charge Pump Select Byte1 [1:0] Programming these bits (Byte1[1:0]) via I2C enables the user to have more spread percentage options as described in Table 5. At the start up the default value for byte1[1:0] bits is set to ‘00’, this value can be changed via I2C to have higher spread percentage on CLKOUT and CLKOUT#. Setting the byte[1:0] bits to ‘11’ allows the user to have a slightly higher Document #: 38-07579 Rev. *C Pin Description spread percentage than the default value(00). The ‘01’ option is the highest spread option for maximum EMI reduction. PWRDWN (Power-down) Clarification The PWRDWN (Power-down) pin is used to shut off the clock prior to shutting off power to the device. PWRDWN is an asynchronous active HIGH input. This signal is synchronized internally to the device powering down the clock synthesizer. PWRDWN also is an asynchronous function for powering up the system. When PWRDWN is high, all clocks are tri-stated and the oscillator and PLL are also powered down. All clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the stopped state. The CLKIN input must be on and within specified operating parameters before PWRDWN is asserted and it must remain in this state while PWRDWN is asserted, see Figure 1. When PWRDWN is de-asserted (CLKIN starts after powerdown de-assertion to meet the IDD≤250µA specification) the clocks should remain stopped until the VCO is stable and within specification (tSTABLE)., see Figure 2. Page 5 of 12 CY25823 PW RDW N C L K IN On C lo c k V C O O ff C LKO UT TpHZ CLKO UT# REFOUT Figure 1. Power-down Assertion VDD PWRDWN CLKIN Starting Off Clock VCO Stable Tstable CLKOUT CLKOUT# TpZH REFOUT Figure 2. Power-down Deassertion IR E F 3.3V IO U T C1 + - M IR E F 2R V REF ∼ 1.1V R C LK OUT C LK OUT # R REF Figure 3. Current Reference Circuit Document #: 38-07579 Rev. *C Page 6 of 12 CY25823 CLKOUT/CLKOUT# Enable Clarification Current Reference, IREF The CLKOUT enable I2C register bit (Byte1, bit2) is used to enable/disable the CLKOUT clock. The PLL and crystal oscillator remains on when the outputs are disabled. The details of the current reference circuit are shown in Figure 3. The operational amplifier in the current reference circuit drives the gate of MIREF with feedback to establish VREF = 1.1V at both inputs of the amplifier. Thus the reference current is established according to the following formula: When CLKOUT is disabled, the disabled clock is three-stated. The transition to this mode (three-state) is glitch free. Similarly, when CLKOUT is enabled the clock starts in a predictable manner without any glitches or abnormal behavior. IREF = 1.1V / RREF where RREF is the external resistor and 1.1V is the reference voltage. The IREF is scaled by 6x at the output stage and IOUT is given as: IOUT = 6 x IREF. The recommended value for RREF is 475 Ohms, which corresponds to the IREF of 2.32mA. Document #: 38-07579 Rev. *C Page 7 of 12 CY25823 Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit VDD Core Supply Voltage –0.5 4.6 V VDDA Analog Supply Voltage –0.5 4.6 V VIN Input Voltage Relative to VSS –0.5 VDD + 0.5 VDC TS Temperature, Storage Non-functional –65 150 °C TA Temperature, Operating Ambient Functional 0 70 °C TJ Temperature, Junction Functional – 150 °C ØJC Dissipation, Junction to Case Mil-Spec 883E Method 1012.1 – 33.89 °C/W ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) – 117.36 °C/W ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 2000 – V DC Electrical Specifications Parameter Description Condition Min. Max. Unit VDD Power supply for logic and outputs 3.3 ± 5% 3.135 3.465 V VDDA Power supply for PLL 3.3 ± 5% 3.135 3.465 V VILI2C Input Low Voltage SDATA, SCLK VSS–0.5 0.8 V VIHI2C Input High Voltage SDATA, SCLK 2.0 VDD V VIL Input Low Voltage VSS – 0.5 0.8 V VIH Input High Voltage 2.0 VDD V IIL Input Leakage Current –5 5 µA IOZ High-impedance Output Current –10 10 µA IDD Dynamic Supply Current – 50 mA IDDS Total Power Supply Current in Shutdown Shutdown active mode (No Input Clock) – 250 µA CIN Input Pin Capacitance 2 5 pF COUT Output Pin Capacitance 3 6 pF LIN Input Pin Inductance – 5 nH RPU SCLK and SDATA pull-up resistors when PWRDWN = 1 50 200 kΩ RREF IREF external reference resistor 1% tolerance 200 500 W except internal pull-ups resistors, 0 < VIN < VDD without output load AC Electrical Specifications Parameter Description Condition Min. Max. Unit CLKIN/REFOUT AC Specifications TDC Duty Cycle Measured at 1.5V crossing point 40 60 % TR / TF Rise and Fall Times Measured between 0.8V and 2.0V (REFOUT with max. 30 pF Lumped capacitive load) – 1.2 ns TCCJ Cycle to Cycle Jitter As an average over 1-µs duration – 1000 ps LACC Long-term Accuracy Over 150 ms – 300 ppm Measured at crossing point VOX 45 55 % CLKOUT/CLKOUT# AC Specifications TDC CLKOUT and CLKOUT# Duty Cycle TPERIOD 100 MHz CLKOUT and CLKOUT# Period Measured at crossing point VOX 9.990 10.010 ns TPERIOD 96 MHz CLKOUT and CLKOUT# Period Measured at crossing point VOX 10.406 10.427 ns TCCJ CLKOUT/CLKOUT# Cycle to Cycle Jitter with Spread Spectrum Enabled Measured at crossing point VOX – 200 ps Document #: 38-07579 Rev. *C Page 8 of 12 CY25823 AC Electrical Specifications (continued) Parameter Description Condition Min. Max. Unit 175 700 ps – 20 % – 3.0 ms TR / TF CLKOUT and CLKOUT# Rise and Fall Times Measured from VOL = 0.175 to VOH = 0.525V TRFM Rise/Fall Matching Tstable[1] All clock stabilization from Power-up ∆TR Rise Time Variation – 125 ps ∆TF Fall Time Variation – 125 ps VHIGH Voltage High 660 850 mv VLOW Voltage Low –150 – mv Determined as a fraction of 2*(TR – TF)/(TR + TF) VOX Crossing Point Voltage at 0.7V Swing 250 550 mv VOVS Maximum Overshoot Voltage – VHIGH + 0.3 V VUDS Minimum Undershoot Voltage –0.3 – V VRB Ring Back Voltage – 0.2 V Measure SE Application Schematic[2,3] V DD 1 V DDA CLKIN 2 V DD 9 0.1µF C1 S3 3 S2 4 S1 CLKOUT CLKOUT# 7 SCLOCK 8 IREF 12 11 V SSIREF PW RDW N V SS V DD 6 V SSA REFOUT/SEL 33Ω 49.9Ω 1% R5 5% 33Ω R6 R4 33Ω Source Termination 5% 14 SDA TA 5 10ΚΩ R1 5% 16 R3 475Ω 1% R7 49.9Ω 1% 13 10 15 Separate Ground 5% R2 Figure 4. Application Schematic Notes: 1. Not 100% tested, guaranteed by design. 2. VDD and VDDA should be tied together and connected to 3.3V. 3. VSSIREF and VSS are tied together and are common ground. Document #: 38-07579 Rev. *C Page 9 of 12 CY25823 TRise (CLCKOUT) VOH = 0.525V CL KO UT # UT KO L C VCROSS VOL = 0.175V TFall (CLCKOUT) Figure 5. Single-ended Measurement Points for TRise and TFall (CLKOUT and CLKOUT#) CLKO UT TPCB 33Ω 4 9 .9 Ω C LKO U T# IR E F 33Ω M e a s u re m e n t P o in t 2pF TPCB 4 9 .9 Ω M e a s u re m e n t P o in t 2pF 475Ω Figure 6. 0.7V Load Configuration Ordering Information Part Number Package Type Product Flow CY25823ZXC 16-pin TSSOP (Lead-free) Commercial, 0°C to 70°C CY25823ZXCT 16-pin TSSOP – Tape and Reel (Lead-free) Commercial, 0°C to 70°C Document #: 38-07579 Rev. *C Page 10 of 12 CY25823 Package Drawing and Dimension 16-lead TSSOP 4.40 MM Body Z16.173 PIN 1 ID DIMENSIONS IN MM[INCHES] MIN. MAX. 1 REFERENCE JEDEC MO-153 6.25[0.246] 6.50[0.256] PACKAGE WEIGHT 0.05 gms PART # 4.30[0.169] 4.50[0.177] Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG. 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 4.90[0.193] 5.10[0.200] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85091-*A All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07579 Rev. *C Page 11 of 12 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY25823 Document History Page Document Title: CY25823 CK-SSCD Spread Spectrum Differential Clock Specification Document #: 38-07579 Rev. *C Rev. ECN No. Issue Date Orig. of Change ** 131662 12/10/03 RGL New Data Sheet *A 203801 See ECN RGL Fixed the I2C Block Read/Write Protocol and Byte Read/Write Protocol tables *B 252269 See ECN RGL Corrected to New Lead Free Code *C 260155 See ECN RGL Minor Change: Corrected the package diagram Document #: 38-07579 Rev. *C Description of Change Page 12 of 12