58 PRELIMINARY CY28358 200-MHz Differential Clock Buffer/Driver Features Description • Up to 200 MHz operation • Phase-locked loop clock distribution for Double Data Rate Synchronous DRAM applications • Distributes one clock input to six differential outputs • External feedback pin FBIN is used to synchronize the outputs to the clock input • Conforms to the DDR1 specification • Spread Aware™ for EMI reduction • 28-pin SSOP package This PLL clock buffer is designed for 2.5 VDD and 2.5 AVDD operation and differential output levels. This device is a zero delay buffer that distributes a clock input CLKIN to six differential pairs of clock outputs (CLKT[0:5], CLKC[0:5]) and one feedback clock output FBOUT. The clock outputs are controlled by the input clock CLKIN and the feedback clock FBIN. The two line serial bus can set each output clock pair (CLKT[0:5], CLKC[0:5]) to the Hi-Z state. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. The PLL in this device uses the input clock CLKIN and the feedback clock FBIN to provide high-performance, low-skew, low–jitter output differential clocks. Block Diagram Pin Configuration CLKT0 CLKC0 CLKT1 CLKC1 SCLK SDATA Serial Interface Logic CLKIN PLL CLKT2 CLKC2 CLKC1 GND SCLK CLKT3 CLKC3 CLKIN NC CLKT4 CLKC4 AVDD CLKT5 CLKC5 FBIN CLKC0 CLKT0 VDD CLKT1 AGND VDD CLKT2 CLKC2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 CY28358 10 GND CLKC5 CLKT5 CLKC4 CLKT4 VDD SDATA NC FBIN FBOUT NC CLKT3 CLKC3 GND FBOUT AVDD 28 pin SSOP Cypress Semiconductor Corporation Document #: 38-07417 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 14, 2002 CY28358 PRELIMINARY Pin Description[1] Pin Name I/O Description Electrical Characteristics 8 CLKIN I Clock Input. Input 20 FBIN I Feedback Clock Input. Connect to FBOUT for accessing the PLL. Input Differential Outputs 2,4,13,17,24,26 CLKT(0:5) O Clock Outputs 1,5,14,16,25,27 CLKC(0:5) O Clock Outputs 19 FBOUT O Feedback Clock Output. Connect to FBIN for normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. Output 7 SCLK I Serial Clock Input. Clocks data at SDATA into the internal register. Data Input for the two line serial bus 22 SDATA I/O Serial Data Input. Input data is clocked to the internal register to enable/disable individual outputs. This provides flexibility in power management. Data Input and Output for the two line serial bus 3,12,23 VDD 2.5V Power Supply for Logic 2.5V Nominal 10 AVDD 2.5V Power Supply for PLL 2.5V Nominal 6,15,28 GND Ground 11 AGND Analog Ground for PLL 9, 18, 21 NC Not Connected Function Table Inputs Outputs PLL CLKIN CLKT(0:5)[2] CLKC(0:5)[2] FBOUT GND L L H L GND H H L H BYPASSED/OFF 2.5V L L H L On VDDA BYPASSED/OFF 2.5V H H L H On 2.5V < 20 MHz Hi-Z Hi-Z Hi-Z Off Zero Delay Buffer When used as a zero delay buffer the CY28358 will likely be in a nested clock tree application. For these applications the CY28358 offers a clock input as a PLL reference. The CY28358 then can lock onto the reference and translate with near zero delay to low-skew outputs. For normal operation, the external feedback input, FBIN, is connected to the feedback output, FBOUT. By connecting the feedback output to the feedback input the propagation delay through the device is eliminated. The PLL works to align the output edge with the input reference edge thus producing a near zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs. When VDDA is strapped LOW, the PLL is turned off and bypassed for test purposes. Power Management The individual output enable/disable control of the CY28358 allows the user to implement unique power management schemes into the design. Outputs are three-stated when disabled through the two-line interface as individual bits are set low in Byte0 and Byte1 registers. The feedback output FBOUT cannot be disabled via two line serial bus. The enabling and disabling of individual outputs is done in such a manner as to eliminate the possibility of partial “runt” clocks. Notes: 1. A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces. 2. Each output pair can be three-stated via the two line serial interface. Document #: 38-07417 Rev. *A Page 2 of 11 CY28358 PRELIMINARY Serial Data Interface Data Protocol To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. The clock driver serial protocol accepts block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. The block write and block read protocol is outlined in Table 1. The slave receiver address is 11010010 (D2h). T Table 1. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 Description Start Slave address – 7 bits Block Read Protocol Bit 1 2:8 Description Start Slave address – 7 bits 9 Write = 0 9 Write = 0 10 Acknowledge from slave 10 Acknowledge from slave 11:18 19 20:27 28 29:36 37 38:45 Command Code – 8 bits '00000000' stands for block operation 11:18 Command Code – 8 bits '00000000' stands for block operation Acknowledge from slave 19 Acknowledge from slave Byte Count – 8 bits 20 Repeat start Acknowledge from slave 21:27 Slave address – 7 bits Data byte 1 – 8 bits 28 Read = 1 Acknowledge from slave 29 Acknowledge from slave Data byte 2 – 8 bits 30:37 46 Acknowledge from slave .... ...................... .... Data Byte (N–1) – 8 bits 47 .... Acknowledge from slave 48:55 .... Data Byte N – 8 bits 56 Acknowledge .... Acknowledge from slave .... Data bytes from slave/Acknowledge .... Stop .... Data byte N from slave – 8 bits .... Not Acknowledge .... Stop Document #: 38-07417 Rev. *A 38 Byte count from slave – 8 bits 39:46 Acknowledge Data byte from slave – 8 bits Acknowledge Data byte from slave – 8 bits Page 3 of 11 CY28358 PRELIMINARY Byte0: Output Register1 (1 = Enable, 0 = Disable) Bit @Pup Pin# Description 7 1 2, 1 CLKT0, CLKC0 6 1 4, 5 CLKT1, CLKC1 5 1 Reserved 4 1 Reserved 3 1 13, 14 CLKT2, CLKC2 2 1 26, 27 CLKT5, CLKC5 1 1 0 1 24, 25 CLKT4, CLKC4 Reserved Byte1: Output Register 2 (1 = Enable, 0 = Disable) Bit @Pup Pin# Description 7 1 6 1 5 0 Reserved 4 0 Reserved 3 0 Reserved 2 0 Reserved 1 0 Reserved 0 0 Reserved Reserved 17, 16 CLKT3, CLKC3 Byte2: Test Register 3 Bit @Pup 7 1 Reserved 6 1 Reserved 5 1 Reserved 4 1 Reserved 3 1 Reserved 2 1 Reserved 1 1 Reserved 0 1 Reserved Document #: 38-07417 Rev. *A Pin# Description Page 4 of 11 CY28358 PRELIMINARY Parameter Measurement Information CLKIN 1.25V 1.25V FBIN 1.25V 1.25V t(∅)n+1 t(∅)n t(∅)n = Σ n1=N N t(∅)n (N is large number of samples) Figure 1. Static Phase Offset CLKIN 1.25V 1.25V FBIN td(∅) t(∅) td(∅) td(∅) t(∅ ) td(∅) Figure 2. Dynamic Phase Offset CLKT[0:5], FBOUT CLKC[0:5] CLKT[0:5], FBOUT CLKC[0:5] tsk(o) Figure 3. Output Skew Document #: 38-07417 Rev. *A Page 5 of 11 CY28358 PRELIMINARY CLKT[0:5], FBOUT CLKC[0:5] tc(n) CLKT[0:5], FBOUT CLKC[0:5] 1 f(o) tjit(hper) = tc(n) - 1 fo Figure 4. Period Jitter CLKT[0:5], FBOUT CLKC[0:5] t(hper_N+1) t(hper_n) 1 f(o) t jit(hper) = thper(n) - 1 2x fo Figure 5. Half-Period Jitter CLKT[0:5], FBOUT CLKC[0:5] t c(n) t c(n) t jit(cc) = t c(n) - t c(n+1) Figure 6. Cycle-to-cycle Jitter Document #: 38-07417 Rev. *A Page 6 of 11 CY28358 PRELIMINARY T PCB M easurem ent Point CLKT 16 pF CLKIN 100 Ω 50 Ω CLKC T PCB M easurem ent Point 16 pF FBIN FBOUT 50 Ω Figure 7. Differential Signal Using Direct Termination Resistor Document #: 38-07417 Rev. *A Page 7 of 11 CY28358 PRELIMINARY Maximum Ratings[3] Storage Temperature: ................................ –65°C to + 150°C This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: Operating Temperature: .................................... 0°C to +85°C VSS < (Vin or Vout) < VDD Maximum Power Supply: ................................................3.5V Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). Input Voltage Relative to VSS:...............................VSS – 0.3V Input Voltage Relative to VDDQ or AVDD:.............. VDD + 0.3V DC Parameters[4] (VDDA = VDDQ = 2.5V + 5%, TA = 0°C to +70°C) Parameter Description Conditions Min. VIL Input Low Voltage SDATA, SCLK VIH Input High Voltage SDATA, SCLK VIL Input Voltage Low CLKIN, FBIN VIH Input Voltage High CLKIN, FBIN 2.1 IIN Input Current VIN = 0V or VIN = VDDQ, CLKIN, FBIN –10 Typ. Max. Unit 1.0 V 2.2 V 0.4 V V 10 µA IOL Output Low Current VDDQ = 2.375V, VOUT = 1.2V 26 35 mA IOH Output High Current VDDQ = 2.375V, VOUT = 1V –18 –32 mA VOL Output Low Voltage VDDQ = 2.375V, IOL = 12 mA VOH Output High Voltage VDDQ = 2.375V, IOH = –12 mA VOUT Output Voltage Swing[5} VOC Output Crossing Voltage[6] IOZ High-Impedance Output Current VO = GND or VO = VDDQ IDDQ Dynamic Supply Current[7] All VDDQ and VDDI, FO = 200 MHz IDSTAT Static Supply Current IDD PLL Supply Current CIN Input Pin Capacitance 0.6 V 1.1 (VDDQ/2) – 0.2 VDDA only V 1.7 VDDQ–0.4 V (VDDQ/2) + 0.2 V 10 µA 235 300 mA 2 mA 9 12 mA 4 6 pF VDDQ/2 –10 Notes: 3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 4. Unused inputs must be held high or low to prevent them from floating 5. For load conditions see Figure 7. 6. The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120Ω resistor. See Figure 7. 7. All outputs switching loaded with 16pF in 60Ω environment. SeeFigure 7 Document #: 38-07417 Rev. *A Page 8 of 11 CY28358 PRELIMINARY AC Parameters[8,9] (VDD = VDDQ = 2.5V±5%, TA = 0°C to +70°C) Parameter Description Conditions Min. fCLK Operating Clock Frequency 60 tDC Input Clock Duty Cycle 40 tLOCK Maximum PLL lock Time 1 Max. Unit 200 MHz 60 % 100 µs 2.5 V/ns tR/tF Output Clocks Slew Rate tPZL,tPZH Output Enable Time[10] (all outputs) 3 ns tPLZ,tPHZ Output Disable Time[10] (all outputs) 3 ns tCCJ Cycle to Cycle Jitter[12] jitter[12] 20% to 80% of VOD Typ. f > 66 MHz –100 f > 66 MHz –100 100 ps tjit(h-per) Half-period 100 ps tPLH Low-to-High Propagation Delay, CLKIN to CLKT[0:5] 1.5 3.5 6 ns tPHL High-to-Low Propagation Delay, CLKIN to CLKT[0:5] 1.5 3.5 6 ns tSKEW Any Output to Any Output Skew[11] 100 ps –150 150 ps –50 50 ps Error[11] tPHASE Phase tPHASEJ Phase Error Jitter f > 66 MHz Notes: 8. Parameters are guaranteed by design and characterization. Not 100% tested in production. 9. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30kHz and 33.3kHz with a down spread of –0.5%. 10. Refers to transition of non-inverting outpu.t 11. All differential input and output terminals are terminated with 120Ω/16pF as shown in Figure 7. 12. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other. Document #: 38-07417 Rev. *A Page 9 of 11 PRELIMINARY CY28358 Ordering Information Part Number CY28358OC CY28358OCT Package Type Product Flow 28-Pin SSOP Commercial, 0° to 70°C 28-Pin SSOP -Tape and Reel Commercial, 0° to 70°C Package Drawing and Dimensions 28-Lead (5.3 mm) Shrunk Small Outline Package O28 51-85079-*C Spread Aware is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07417 Rev. *A Page 10 of 11 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.. CY28358 PRELIMINARY Document History Page Document Title: CY28358 200-MHz Differential Clock Buffer/Driver Document #: 38-07417 REV. ECN NO. Issue Date Orig. of Change ** 118004 09/11/02 INA New Data Sheet *A 122925 12/14/02 RBI Add power up requirements to operating condicitons information. Document #: 38-07417 Rev. *A Description of Change Page 11 of 11