CY25823:CK-SSCD Spread Spectrum Differential Clock Specification

CY25823
CK-SSCD Spread Spectrum Differential
Clock Specification
CK-SSCD Spread Spectrum Differential Clock Specification
Features
n
3.3 V operation
n
96- and 100-MHz frequency support
n
Selectable slew rate control
n
200-ps jitter
n
I2C programmability
n
250-A power-down current
n
Lexmark Spread Spectrum for best electromagnetic
interference (EMI) reduction
n
16-pin TSSOP package
n
For a complete list of related documentation, click here.
Logic Block Diagram
VDD
VDDA
REFOUT
Clock Input
Freq.
Divider
M
Phase
Detector
Charge
Pump
VCO
Post
Dividers
CLKOUT
(SSCG Output)
CLKOUT#
Modulating
Waveform
SDATA
SCLK
PWRDWN

Logic
Control
Feedback
Divider
N
PLL
VSS
Cypress Semiconductor Corporation
Document Number: 38-07579 Rev. *G
•
VSSA
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 24, 2015
CY25823
Contents
Pin Configuration ............................................................. 3
Pin Definitions .................................................................. 3
Functional Overview ........................................................ 4
Serial Data Interface .................................................... 4
Control All Test Mode .................................................. 4
Control All Charge Pump ............................................. 4
Data Protocol ............................................................... 5
Spread Enable and Spread Select[3:0] ....................... 7
Charge Pump Select Byte1 [1:0] ................................. 8
PWRDWN (Power-down) Clarification ........................ 9
CLKOUT/CLKOUT# Enable Clarification .................. 10
Current Reference, IREF ........................................... 10
Absolute Maximum Conditions ..................................... 11
DC Electrical Specifications .......................................... 11
AC Electrical Specifications .......................................... 12
Document Number: 38-07579 Rev. *G
Application Schematic ................................................... 13
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Package Drawing and Dimensions ............................... 16
Acronyms ........................................................................ 17
Document Conventions ................................................. 17
Units of Measure ....................................................... 17
Document History Page ................................................. 18
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC® Solutions ...................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
Page 2 of 19
CY25823
Pin Configuration
Figure 1. 16-pin TSSOP pinout
CLKIN
S3
S2
S1
PW RDW N
REFOUT/SEL
SCLK
SDATA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDDA
VSSA
IREF
VSSIREF
CLKOUT
CLKOUT#
VSS
VDD
Pin Definitions
Pin No
Name
Type
1
CLKIN
Input
3.3 V 14.131818-MHz single-ended clock input
Description
2,3,4
S[3:1]
Input
Spread Spectrum configuration
5
PWRDWN
Input
3.3 V LVTTL input for power-down active high, no pull-up or pull-down
6
REFOUT/SEL
I/O
7
SCLK
Input
SMBus-compatible SCLK
8
SDATA
I/O
SMBus-compatible SDATA
9
VDD
3.3 V
10
VSS
Ground
Latched input during power-up, 1 (10K external pull-up) = 100 MHz or 0 (10K external
pull-down) = 96 MHz. After power-up it becomes 14.31818-MHz REFOUT clock.
3.3 V power supply for logic and outputs
Ground for logic and outputs
11
CLKOUT#
Output
0.7 V 96-MHz or 100-MHz Spread Spectrum differential clock output
12
CLKOUT
Output
0.7 V 96-MHz or 100-MHz Spread Spectrum differential clock output
13
VSSIREF
Ground
Current reference ground
14
IREF
Input
15
VSSA
Ground
16
VDDA
3.3 V
Document Number: 38-07579 Rev. *G
Typically a precision 475 external resistor is connected between this pin and
VSSIREF to set IOUT (drive current) of CLKOUT differential driver.
Ground for PLL
3.3 V power supply for PLL
Page 3 of 19
CY25823
Functional Overview
The registers associated with the Serial Data Interface initializes
to their default setting upon power-up, and therefore use of this
interface is optional. Clock device register changes are normally
made upon system initialization, if any are required. The
interface can also be used during system operation for power
management functions.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a
two-signal serial interface is provided. Through the Serial Data
Interface, various device functions such as individual clock
output buffers can be individually enabled or disabled.
Byte 0: Control Register
Bit
@Power-up
Pin#
Name
Pin Description
7
0
11, 12
SS0
–
6
S1
11, 12
SS1
–
5
S2
11, 12
SS2
–
4
S3
11, 12
3
SEL100/96#
2
0
1
1
0
0
6
SS3
–
SEL100/96#
Select output frequency, 1 = 100 MHz, 0 = 96 MHz
Spread Enable
Spread spectrum enable, 0 = Disable, 1 = Enable
HW/SW Control
Hardware/software control of S[3:0], and output frequency.
0 = hardware control, 1 = software control.
Reserved must equal 0
11, 12
Byte 1: [7:2] Control Register
Bit
@Pup
Pin#
Name
Pin Description
7
0
Reserved set equal to ‘0’
6
0
Reserved set equal to ‘0’
5
0
Reserved set equal to ‘0’
4
0
Reserved set equal to ‘0’
3
0
Reserved set equal to ‘0’
2
1
11,12
CLKEN
CLKOUT/CLKOUT# enable
0 =Disable, 1 = Enable
Byte 1: [1:0] Control Register (Charge Pump Settings)
Bit
@Pup
Default Value
One Step Higher Than Default
Two Steps Higher Than Default
1
0
0
1
1
0
0
0
1
0
Bytes 2 through 5: Reserved Registers
Bytes 2 through 5 are Reserved Registers.
Byte 6: Vendor/Revision ID Register
Bit
@Pup
Pin#
Name
7
0
–
–
Revision ID Bit 3
6
0
–
–
Revision ID Bit 2
5
0
–
–
Revision ID Bit 1
4
0
–
–
Revision ID Bit 0
3
1
–
–
Vendor ID Bit 3
2
0
–
–
Vendor ID Bit 2
1
0
–
–
Vendor ID Bit 1
0
0
–
–
Vendor ID Bit 0
Document Number: 38-07579 Rev. *G
Pin Description
Page 4 of 19
CY25823
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operation from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant bit
first) with the ability to stop after any complete byte has been
transferred. For byte write and byte read operations, the system
controller can access individual indexed bytes. The offset of the
indexed byte is encoded in the command code, as described in
Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines the corresponding byte write and byte read
protocol.The combined 7 bits slave address and read/write bit
form a complete block write (D4h) or block read (D5h) command.
Table 1. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation
1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
2:8
Description
Start
Slave address – 7 bits (D4)
9
Write = 0
10
Acknowledge from slave
11:18
19
20:27
28
29:36
37
38:45
Command Code – 8 bits
'00000000' stands for block operation
Acknowledge from slave
Byte Count – 8 bits
Acknowledge from slave
Block Read Protocol
Bit
1
2:8
Description
Start
Slave address – 7 bits (D5)
9
Read = 0
10
Acknowledge from slave
11:18
19
20
21:27
Command Code – 8 bits
'00000000' stands for block operation
Acknowledge from slave
Repeat start
Slave address – 7 bits
Data byte 0 – 8 bits
28
Read = 1
Acknowledge from slave
29
Acknowledge from slave
Data byte 1 – 8 bits
30:37
Acknowledge from slave
....
......................
....
Data Byte (N–1) –8 bits
47
....
Acknowledge from slave
48:55
....
Data Byte N –8 bits
56
Acknowledge
....
Acknowledge from slave
....
Data bytes from slave/Acknowledge
....
Stop
....
Data byte N from slave – 8 bits
....
Not Acknowledge
....
Stop
Document Number: 38-07579 Rev. *G
38
Byte count from slave – 8 bits
46
39:46
Acknowledge
Data byte from slave – 8 bits
Acknowledge
Data byte from slave – 8 bits
Page 5 of 19
CY25823
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
2:8
Description
Start
Slave address – 7 bits (D4)
Byte Read Protocol
Bit
1
2:8
Description
Start
Slave address – 7 bits (D5)
9
Write = 1
9
Read = 1
10
Acknowledge from slave
10
Acknowledge from slave
11:18
19
20:27
Command Code – 8 bits
'100000xx' stands for byte operation, bits[1:0] of the
command code represents the offset of the byte to
be accessed
11:18
Command Code – 8 bits
'100000xx' stands for byte operation, bits[1:0] of the
command code represents the offset of the byte to
be accessed
Acknowledge from slave
19
Acknowledge from slave
Data byte from master – 8 bits
20
Repeat start
28
Acknowledge from slave
29
Stop
21:27
Read = 1
29
Acknowledge from slave
30:37
Document Number: 38-07579 Rev. *G
Slave address – 7 bits
28
Data byte from slave – 8 bits
38
Not Acknowledge
39
Stop
Page 6 of 19
CY25823
Spread Enable and Spread Select[3:0]
Spread Enable and Spread Select[3:0] register bits are used to
enable and disable spread spectrum on CLKOUT and to change
the spread modulation. When the spread selection changes, the
CLKOUT output transits to the target spread selection without
deviating from clock specifications.
At device power-up spread spectrum is enabled and hardware
control mode is enabled. The initial spread-spectrum
configuration is determined by the S[3:1] pins, which correspond
to the S[3:1] bits in Table 4. The S0 configuration bit is
hard-coded to zero when hardware control mode is selected. All
four spread spectrum configuration bits, S[3:0], can also be set
when the device is in the software control mode.
Table 4. Spread Spectrum Select (Charge Pump = 00 or Default Condition)
SS3
SS2
SS1
SS0
Spread Mode
Spread Amount %
0
0
0
0
Down
0.65
0
0
0
1
Down
0.80
0
0
1
0
Down
0.90
0
0
1
1
Down
1.10
0
1
0
0
Down
1.30
0
1
0
1
Down
1.40
0
1
1
0
Down
1.80
0
1
1
1
Down
2.25
1
0
0
0
Center
±0.25
1
0
0
1
Center
±0.30
1
0
1
0
Center
±0.40
1
0
1
1
Center
±0.45
1
1
0
0
Center
±0.60
1
1
0
1
Center
±0.80
1
1
1
0
Center
±1.00
1
1
1
1
Center
±1.10
Document Number: 38-07579 Rev. *G
Page 7 of 19
CY25823
Charge Pump Select Byte1 [1:0]
2
Programming these bits (Byte1[1:0]) via I C enables the user to
have more spread percentage options as described in Table 5.
At the start up the default value for byte1[1:0] bits is set to ‘00’,
this value can be changed via I2C to have higher spread
percentage on CLKOUT and CLKOUT#. Setting the byte[1:0]
bits to ‘11’ allows the user to have a slightly higher spread
percentage than the default value(00). The ‘01’ option is the
highest spread option for maximum EMI reduction.
Table 5. Spread Spectrum Select (Charge Pump = 11 and 01)
SS3
SS2
SS1
SS0
Spread Mode
Spread Amount %
(Charge pump = 11)
Spread Amount %
(Charge pump = 01)
0
0
0
0
Down
0.80
0.90
0
0
0
1
Down
0.90
1.10
0
0
1
0
Down
1.20
1.40
0
0
1
1
Down
1.40
1.60
0
1
0
0
Down
1.60
2.00
0
1
0
1
Down
1.75
2.20
0
1
1
0
Down
2.20
2.75
0
1
1
1
Down
2.60
3.30
1
0
0
0
Center
±0.38
±0.40
1
0
0
1
Center
±0.40
±0.50
1
0
1
0
Center
±0.50
±0.60
1
0
1
1
Center
±0.60
±0.70
1
1
0
0
Center
±0.75
±0.90
1
1
0
1
Center
±1.00
±1.25
1
1
1
0
Center
±1.15
±1.45
1
1
1
1
Center
±1.30
±1.65
Document Number: 38-07579 Rev. *G
Page 8 of 19
CY25823
PWRDWN (Power-down) Clarification
The PWRDWN (Power-down) pin is used to shut off the clock
prior to shutting off power to the device. PWRDWN is an
asynchronous active HIGH input. This signal is synchronized
internally to the device powering down the clock synthesizer.
PWRDWN also is an asynchronous function for powering up the
system. When PWRDWN is high, all clocks are tri-stated and the
oscillator and PLL are also powered down. All clocks are shut
down in a synchronous manner so has not to cause glitches
while transitioning to the stopped state. The CLKIN input must
be on and within specified operating parameters before
PWRDWN is asserted and it must remain in this state while
PWRDWN is asserted, see Figure 2.
When PWRDWN is de-asserted (CLKIN starts after powerdown
de-assertion to meet the IDD250A specification) the clocks
should remain stopped until the VCO is stable and within
specification (tSTABLE)., see Figure 3.
Figure 2. Power-down Assertion
PW RDW N
C L K IN
On
C lo c k V C O
O ff
C LKO UT
TpHZ
CLKO UT#
REFOUT
Figure 3. Power-down Deassertion
VDD
PWRDWN
CLKIN
Clock VCO
Off
Stable
Tstable
CLKOUT
CLKOUT#
Starting
TpZH
REFOUT
Document Number: 38-07579 Rev. *G
Page 9 of 19
CY25823
CLKOUT/CLKOUT# Enable Clarification
The CLKOUT enable I2C register bit (Byte1, bit2) is used to
enable/disable the CLKOUT clock. The PLL and crystal oscillator
remains on when the outputs are disabled.
the gate of MIREF with feedback to establish VREF = 1.1 V at both
inputs of the amplifier. Thus the reference current is established
according to the following formula:
IREF = 1.1 V / RREF
When CLKOUT is disabled, the disabled clock is three-stated.
The transition to this mode (three-state) is glitch free. Similarly,
when CLKOUT is enabled the clock starts in a predictable
manner without any glitches or abnormal behavior.
where RREF is the external resistor and 1.1 V is the reference
voltage.
Current Reference, IREF
The recommended value for RREF is 475 Ohms, which
corresponds to the IREF of 2.32mA.
The details of the current reference circuit are shown in Figure 4.
The operational amplifier in the current reference circuit drives
The IREF is scaled by 6x at the output stage and IOUT is given as:
IOUT = 6 x IREF.
Figure 4. Current Reference Circuit
IR E F
3.3V
IO U T
C1
+
-
M IR E F
2R
V REF
 1.1V
R
C LK OUT
C LK OUT #
R REF
Document Number: 38-07579 Rev. *G
Page 10 of 19
CY25823
Absolute Maximum Conditions
Parameter
Description
Condition
Min
Max
Unit
–0.5
4.6
V
VDD
Core Supply Voltage
VDDA
Analog Supply Voltage
–0.5
4.6
V
VIN
Input Voltage
Relative to VSS
–0.5
VDD + 0.5
VDC
TS
Temperature, Storage
Non-functional
–65
150
°C
TA
Temperature, Operating Ambient Functional
0
70
°C
TJ
Temperature, Junction
Functional
–
150
°C
ØJC
Dissipation, Junction to Case
Mil-Spec 883E Method 1012.1
–
33.89
°C/W
ØJA
Dissipation, Junction to Ambient JEDEC (JESD 51)
–
117.36
°C/W
ESDHBM
ESD Protection (Human Body
Model)
2000
–
V
Min
Max
Unit
MIL-STD-883, Method 3015
DC Electrical Specifications
Parameter
Description
Condition
VDD
Power supply for logic and
outputs
3.3 ± 5%
3.135
3.465
V
VDDA
Power supply for PLL
3.3 ± 5%
3.135
3.465
V
VILI2C
Input Low Voltage
SDATA, SCLK
VSS – 0.5
0.8
V
VIHI2C
Input High Voltage
SDATA, SCLK
2.0
VDD
V
VIL
Input Low Voltage
VSS – 0.5
0.8
V
VIH
Input High Voltage
2.0
VDD
V
IIL
Input Leakage Current
–5
5
A
IOZ
High-impedance Output Current
–10
10
A
IDD
Dynamic Supply Current
–
50
mA
IDDS
Total Power Supply Current in
Shutdown active
Shutdown mode (No Input Clock)
–
250
A
CIN
Input Pin Capacitance
2
5
pF
COUT
Output Pin Capacitance
3
6
pF
LIN
Input Pin Inductance
–
5
nH
RPU
SCLK and SDATA pull-up
resistors
when PWRDWN = 1
50
200
k
RREF
IREF external reference resistor
1% tolerance
200
500
W
Document Number: 38-07579 Rev. *G
except internal pull-ups resistors, 0 < VIN < VDD
without output load
Page 11 of 19
CY25823
AC Electrical Specifications
Parameter
Description
Condition
Min
Max
Unit
CLKIN/REFOUT AC Specifications
TDC
Duty Cycle
Measured at 1.5 V crossing point
40
60
%
TR / TF
Rise and Fall Times
Measured between 0.8 V and 2.0 V (REFOUT
with max. 30 pF Lumped capacitive load)
–
1.2
ns
TCCJ
Cycle to Cycle Jitter
As an average over 1-s duration
–
1000
ps
LACC
Long-term Accuracy
Over 150 ms
–
300
ppm
CLKOUT/CLKOUT# AC Specifications
TDC
CLKOUT and CLKOUT# Duty
Cycle
Measured at crossing point VOX
45
55
%
TPERIOD
100 MHz CLKOUT and
CLKOUT# Period
Measured at crossing point VOX
9.990
10.010
ns
TPERIOD
96 MHz CLKOUT and CLKOUT# Measured at crossing point VOX
Period
10.406
10.427
ns
TCCJ
CLKOUT/CLKOUT# Cycle to
Measured at crossing point VOX
Cycle Jitter with Spread Spectrum
Enabled
–
200
ps
TR / TF
CLKOUT and CLKOUT# Rise
and Fall Times
Measured from VOL = 0.175 to VOH = 0.525 V
175
700
ps
TRFM
Rise/Fall Matching
Determined as a fraction of
2 × ((TR – TF)/(TR + TF))
–
20
%
Tstable[1]
All clock stabilization from
Power-up
–
3.0
ms
TR
Rise Time Variation
–
125
ps
TF
Fall Time Variation
–
125
ps
VHIGH
Voltage High
660
850
mv
VLOW
Voltage Low
–150
–
mv
VOX
Crossing Point Voltage at 0.7 V
Swing
250
550
mv
VOVS
Maximum Overshoot Voltage
–
VHIGH + 0.3
V
VUDS
Minimum Undershoot Voltage
–0.3
–
V
VRB
Ring Back Voltage
–
0.2
V
Measure SE
Note
1. Not 100% tested, guaranteed by design.
Document Number: 38-07579 Rev. *G
Page 12 of 19
CY25823
Application Schematic
Figure 5. Application Schematic [2, 3]
V DD
1
V DDA
CLKIN
2
V DD
9
0.1F
C1
S3
3
S1
CLKOUT
CLKOUT#
12
11

1%
5%

R6
R5
R4

Source
Termination
S2
4
5%
7
SCLOCK
8
IR EF
14
SDA TA
5
PW R DW N
V SSIREF
V SS
V DD
6
V SSA
REFOUT/SEL

R1
5%
16

R3

1%
R7

1%
13
10
15
Separate Ground
5%
R2
Notes
2. VDD and VDDA should be tied together and connected to 3.3 V.
3. VSSIREF and VSS are tied together and are common ground.
Document Number: 38-07579 Rev. *G
Page 13 of 19
CY25823
Figure 6. Single-ended Measurement Points for TRise and TFall (CLKOUT and CLKOUT#)
TRise (CLCKOUT)
VOH = 0.525V
CL
KO
UT
#
UT
KO
CL
VCROSS
VOL = 0.175V
TFall (CLCKOUT)
Figure 7. 0.7 V Load Configuration
CLKO UT
TPCB

   
C LKO U T#

M e a s u re m e n t
P o in t
2pF
TPCB
   
M e a s u re m e n t
P o in t
2pF
IR E F

Document Number: 38-07579 Rev. *G
Page 14 of 19
CY25823
Ordering Information
Part Number
Package Type
Product Flow
CY25823ZXC
16-pin TSSOP (Lead-free)
Commercial, 0 °C to 70 °C
CY25823ZXCT
16-pin TSSOP – Tape and Reel (Lead-free) Commercial, 0 °C to 70 °C
Ordering Code Definitions
CY 25823
Z
X
C
(T)
T = Tape and Reel, Blank = Tube
Temperature Grade: C = Commercial
X = Pb free
16-pin TSSOP Package
Part Identifier
Company ID: CY = Cypress
Document Number: 38-07579 Rev. *G
Page 15 of 19
CY25823
Package Drawing and Dimensions
Figure 8. 16-pin TSSOP (4.40 mm Body) Package Outline, 51-85091
51-85091 *E
Document Number: 38-07579 Rev. *G
Page 16 of 19
CY25823
Acronyms
Table 6. Acronyms Used in this Document
Acronym
Description
Acronym
Description
CLKIN
Reference Clock IN
LVCMOS
Low Voltage Complementary Metal Oxide
Semiconductor
DL
Drive Level
OE
Output Enable
DNU
Do Not Use
OSC
Oscillator
DUT
Device Under Test
PD
Power-Down
EIA
Electronic Industries Alliance
PLL
Phase Locked Loop
EMI
Electromagnetic Interference
PPM
Parts Per Million
ESD
Electrostatic Discharge
QFN
Quad Flat No Lead
EXCLKIN
External Clock IN
SS
Spread Spectrum
FAE
Field Application Engineer
SSC
Spread Spectrum Clock
FS
Frequency Select
SSON
Spread Spectrum ON
JEDEC
Joint Electron Device Engineering Council
Document Conventions
Units of Measure
Table 7. Units of Measure
Symbol
°C
Unit of Measure
Symbol
Unit of Measure
degree Celsius
µVrms
microvolts root-mean-square
dB
decibel
µW
microwatt
dBc/Hz
decibel relative to the carrier per Hertz
mA
milliampere
fC
femtoCoulomb
mm
millimeter
fF
femtofarad
ms
millisecond
Hz
hertz
mV
millivolt
KB
1024 bytes
nA
nanoampere
Kbit
1024 bits
ns
nanosecond
kHz
kilohertz
nV
nanovolt
k
kilohm

ohm
MHz
megahertz
pA
picoampere
M
megaohm
pF
picofarad
µA
microampere
pp
peak-to-peak
µF
microfarad
ppm
parts per million
µH
microhenry
ps
picosecond
µs
microsecond
sps
samples per second
µV
microvolt

sigma: one standard deviation
Document Number: 38-07579 Rev. *G
Page 17 of 19
CY25823
Document History Page
Document Title: CY25823, CK-SSCD Spread Spectrum Differential Clock Specification
Document Number: 38-07579
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
**
131662
RGL
12/10/03
New Data Sheet
*A
203801
RGL
See ECN
Fixed the I2C Block Read/Write Protocol (Table 2) and Byte Read/Write
Protocol tables (Table 3).
*B
252269
RGL
See ECN
Corrected to New Lead Free Code
*C
260155
RGL
See ECN
Minor Change: Corrected the package diagram
*D
3196237
BASH
03/15/11
Added Ordering Code Definitions under Ordering Information.
Updated Package Drawing and Dimensions:
spec 51-85091 – Changed revision from *A to *C.
Added Acronyms and Units of Measure.
Template updates.
*E
4296180
XHT
03/03/2014
Updated Package Drawing and Dimensions:
spec 51-85091 – Changed revision from *C to *D.
Updated in new template.
Completing Sunset Review.
*F
4587350
XHT
12/05/2014
Added related documentation hyperlink in page 1.
Updated package diagram.
*G
4669367
XHT
02/27/2015
Sunset review, no change required.
Document Number: 38-07579 Rev. *G
Page 18 of 19
CY25823
Sales, Solutions, and Legal Information
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Community | Forums | Blogs | Video | Training
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cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2003-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
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critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07579 Rev. *G
Revised February 24, 2015
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