CYPRESS CY7C1049CV33

CY7C1049CV33 Automotive
4-Mbit (512 K × 8) Static RAM
4-Mbit (512 K × 8) Static RAM
Features
Functional Description
■
Temperature ranges
❐ Automotive -A: –40 °C to 85 °C
❐ Automotive-E: –40 °C to 125 °C
The CY7C1049CV33 Automotive is a high performance CMOS
Static RAM organized as 524,288 words by eight bits. Easy
memory expansion is provided by an active LOW Chip Enable
(CE), an active LOW Output Enable (OE), and three-state
drivers. Writing to the device is accomplished by taking Chip
Enable (CE) and Write Enable (WE) inputs LOW. Data on the
eight I/O pins (I/O0 through I/O7) is then written into the location
specified on the address pins (A0 through A18).
■
High speed
❐ tAA = 10 ns
■
Low active power
❐ 360 mW (max)
■
2.0 V data retention
■
Automatic power down when deselected
■
TTL-compatible inputs and outputs
■
Easy memory expansion with CE and OE features
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
The eight input and output pins (I/O0 through I/O7) are placed in
a high impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1049CV33 Automotive is available in standard
400-mil-wide 36-pin SOJ package and 44-pin TSOP II package
with center power and ground (revolutionary) pinout.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
IO0
INPUT BUFFER
IO1
512K x 8
ARRAY
IO3
IO4
IO5
IO6
CE
•
IO7
POWER
DOWN
A18
A17
A15
A13
A14
OE
A16
COLUMN DECODER
WE
Cypress Semiconductor Corporation
Document #: 001-67511 Rev. **
IO2
SENSE AMPS
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
198 Champion Court
•
San Jose, CA 95134-1709
•408-943-2600
Revised February 16, 2011
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CY7C1049CV33 Automotive
Contents
Selection Guide ................................................................ 3
Pin Configuration ............................................................. 3
Pin Definitions .................................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 4
Thermal Resistance .......................................................... 4
AC Switching Characteristics ......................................... 6
Switching Waveforms ...................................................... 7
Truth Table ........................................................................ 8
Document #: 001-67511 Rev. **
Ordering Information ....................................................... 9
Ordering Code Definitions ........................................... 9
Package Diagrams ......................................................... 10
Acronyms ........................................................................ 11
Document Conventions ................................................. 11
Units of Measure ....................................................... 11
Document History Page ................................................. 12
Sales, Solutions, and Legal Information ...................... 13
Worldwide Sales and Design Support ....................... 13
Products .................................................................... 13
PSoC Solutions ......................................................... 13
Page 2 of 13
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CY7C1049CV33 Automotive
Selection Guide
Description
-10
-12
-15
Unit
10
12
15
ns
Automotive-A
100
95
–
mA
Automotive-E
–
–
95
mA
Automotive-A
10
10
–
mA
Automotive-E
–
–
15
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Pin Configuration
Figure 1. 36-pin SOJ (Top View)
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VCC
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Figure 2. 44-pin TSOP II (Top View)
NC
NC
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VCC
VSS
I/O2
I/O3
WE
A5
A6
A7
A8
A9
NC
NC
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
VCC
I/O5
I/O4
A14
A13
A12
A11
A10
NC
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A18
A17
A16
A15
OE
I/O7
I/O6
VSS
VCC
I/O5
I/O4
A14
A13
A12
A11
A10
NC
NC
NC
Pin Definitions
Pin Name
36 SOJ
Pin Number
44 TSOP II
Pin Number
A0–A18
1–5, 14–18,
3–7, 16–20,
20–24, 32–35 26–30, 38–41
I/O0–I/O7
7, 8, 11, 12, 9, 10, 13, 14,
25, 26, 29, 30 31, 32, 35, 36
I/O Type
Input
Description
Address inputs used to select one of the address locations.
Input/Output Bidirectional data I/O lines. Used as input or output lines depending
on operation
NC[1]
19, 36
1, 2, 21, 22,
23, 24, 25, 42,
43, 44
WE
13
15
Input/Control Write Enable input, active LOW. When selected LOW, a WRITE is
conducted. When selected HIGH, a READ is conducted.
CE
6
8
Input/Control Chip Enable input, active LOW. When LOW, selects the chip. When
HIGH, deselects the chip.
OE
31
37
Input/Control Output Enable, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins are allowed to behave as outputs. When
deasserted HIGH, I/O pins are three-stated, and act as input data pins.
VSS, GND
10, 28
12, 34
VCC
9, 27
11, 33
No Connect
Ground
No connects. This pin is not connected to the die
Ground for the device. Should be connected to ground of the system.
Power Supply Power supply inputs to the device.
Note
1. NC pins are not connected on the die.
Document #: 001-67511 Rev. **
Page 3 of 13
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CY7C1049CV33 Automotive
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65 C to +150C
Ambient Temperature with
Power Applied .......................................... –55 C to +125 C
Voltage Applied to Outputs
in High Z State[2] .................................. –0.5 V to VCC + 0.5 V
Input Voltage[2] .................................... –0.5 V to VCC + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Operating Range
Range
Supply Voltage on VCC to Relative GND[2]–0.5 V to +4.6 VDC
Ambient Temperature
VCC
Automotive-A
–40 C to +85 C
3.3 V  0.3 V
Automotive-E
–40 C to +125 C
Electrical Characteristics
Over the Operating Range
Parameter
Description
VOH
Output HIGH Voltage VCC = Min; IOH = –4.0 mA
VOL
VIH
Output LOW Voltage VCC = Min; IOL = 8.0 mA
Input HIGH Voltage
VIL
Input LOW Voltage[2]
IIX
Input Load Current
GND < VI < VCC
ICC
VCC Operating
Supply Current
VCC = Max, f = fMAX = 1/tRC
ISB1
ISB2
-10
Test Conditions
-12
-15
Unit
Min
Max
Min
Max
Min
Max
2.4
–
2.4
–
2.4
–
V
–
0.4
–
0.4
–
0.4
V
2.0
VCC
+ 0.3
2.0
VCC
+ 0.3
2.0
VCC
+ 0.3
V
–0.3
0.8
–0.3
0.8
–0.3
0.8
V
Auto-A
–1
+1
–1
+1
–
–
A
Auto-E
–
–
–
–
–20
+20
Auto-A
–
100
–
95
–
–
Auto-E
–
–
–
–
–
95
mA
Automatic CE
Max. VCC, CE > VIH;
Power Down Current VIN > VIH or VIN < VIL, f = fMAX
—TTL Inputs
Auto-A
–
40
–
40
–
–
mA
Auto-E
–
–
–
–
–
45
mA
Max. VCC, CE > VCC – 0.3 V,
Automatic CE
Power Down Current VIN > VCC – 0.3 V, or VIN < 0.3 V,
—CMOS Inputs
f=0
Auto-A
–
10
–
10
–
–
mA
Auto-E
–
–
–
–
–
15
mA
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter[3]
Description
CIN
Input Capacitance
COUT
I/O Capacitance
Test Conditions
TA = 25 C, f = 1 MHz, VCC = 3.3 V
Max
Unit
8
pF
8
pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter[3]
Description
JA
Thermal Resistance
(Junction to Ambient)
JC
Thermal Resistance
(Junction to Case)
Test Conditions
36-pin SOJ
44-pin TSOP-II
Unit
Test conditions follow standard
test methods and procedures for
measuring thermal impedance,
per EIA / JESD51.
46.51
41.66
°C/W
18.8
10.56
°C/W
Notes
2. VIL (min) = –2.0 V and VIH(max) = VCC + 0.5 V for pulse durations of less than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-67511 Rev. **
Page 4 of 13
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CY7C1049CV33 Automotive
Figure 3. AC Test Loads and Waveforms [4]
10-ns devices:
12-, 15-ns devices:
Z = 50 
50
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
3.0 V
GND
Rise Time: 1 V/ns
R 317
3.3 V
OUTPUT
30 pF*
OUTPUT
(a)
(b)
High Z characteristics:
ALL INPUT PULSES
90%
10%
(c)
R 317
3.3 V
90%
10%
R2
351
30 pF
1.5 V
Fall Time: 1 V/ns
OUTPUT
R2
351
5 pF
(d)
Notes
4. AC characteristics (except High Z) for 10 ns parts are tested using the load conditions shown in Figure 3 (a). All other speeds are tested using the Thevenin load shown
in Figure 3 (b). High Z characteristics are tested for all speeds using the test load shown in Figure 3 (d).
Document #: 001-67511 Rev. **
Page 5 of 13
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CY7C1049CV33 Automotive
AC Switching Characteristics
Over the Operating Range [5]
-10
Parameter
Description
-12
-15
Min
Max
Min
Max
Min
Max
Unit
Read Cycle
tpower[6]
VCC(typical) to the first access
100
–
100
–
100
–
s
tRC
Read Cycle Time
10
–
12
–
15
–
ns
tAA
Address to Data Valid
–
10
–
12
–
15
ns
tOHA
Data Hold from Address Change
3
–
3
–
–
3
ns
tACE
CE LOW to Data Valid
–
10
–
12
–
15
ns
tDOE
OE LOW to Data Valid
–
5
–
6
–
7
ns
tLZOE
OE LOW to Low Z
0
–
0
–
0
–
ns
–
5
–
6
–
7
ns
3
–
3
–
3
–
ns
–
5
–
6
–
7
ns
Z[7, 8]
tHZOE
OE HIGH to High
tLZCE
CE LOW to Low Z[8]
Z[7, 8]
tHZCE
CE HIGH to High
tPU
CE LOW to Power Up
0
–
0
–
0
–
ns
tPD
CE HIGH to Power Down
–
10
–
12
–
15
ns
Write Cycle [9, 10]
tWC
Write Cycle Time
10
–
12
–
15
–
ns
tSCE
CE LOW to Write End
7
–
8
–
10
–
ns
tAW
Address Setup to Write End
7
–
8
–
10
–
ns
tHA
Address Hold from Write End
0
–
0
–
0
–
ns
tSA
Address Setup to Write Start
0
–
0
–
0
–
ns
tPWE
WE Pulse Width
7
–
8
–
10
–
ns
tSD
Data Setup to Write End
5
–
6
–
7
–
ns
tHD
Data Hold from Write End
0
–
0
–
0
–
ns
tLZWE
WE HIGH to Low Z[8]
3
–
3
–
3
–
ns
–
5
–
6
–
7
ns
tHZWE
WE LOW to High
Z[7, 8]
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V.
6. tPOWER gives the minimum amount of time that the power supply should be at stable, typical VCC values until the first memory access can be performed.
7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) ofFigure 3 on page 5. Transition is measured ±500 mV from steady-state voltage.
8. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
9. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of
these signals can terminate the Write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the Write.
10. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 001-67511 Rev. **
Page 6 of 13
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CY7C1049CV33 Automotive
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled) [11, 12]
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2 (OE Controlled) [12, 13]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
tHZCE
tLZOE
HIGH IMPEDANCE
DATA OUT
DATA VALID
tLZCE
tPD
tPU
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
50%
50%
ICC
ISB
Figure 6. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [14, 15]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
OE
tSD
DATA I/O
NOTE 16
tHD
DATA VALID
tHZOE
Notes
11. Device is continuously selected. OE, CE = VIL.
12. WE is HIGH for read cycles.
13. Address valid before or similar to CE transition LOW.
14. Data I/O is high impedance if OE = VIH.
15. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
16. During this period, the I/Os are in output state. Do not apply input signals.
Document #: 001-67511 Rev. **
Page 7 of 13
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CY7C1049CV33 Automotive
Switching Waveforms
(continued)
Figure 7. Write Cycle No. 2 (WE Controlled, OE LOW) [17]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
tSD
NOTE 18
DATA I/O
tHD
DATA VALID
tLZWE
tHZWE
Truth Table
CE
OE
WE
I/O0–I/O7
H
X
X
High Z
Mode
Power Down
Power
Standby (ISB)
L
L
H
Data Out
Read
Active (ICC)
L
X
L
Data In
Write
Active (ICC)
L
H
H
High Z
Selected, Outputs Disabled
Active (ICC)
Notes
17. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
18. During this period, the I/Os are in output state. Do not apply input signals.
Document #: 001-67511 Rev. **
Page 8 of 13
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CY7C1049CV33 Automotive
Ordering Information
Speed
(ns)
Ordering Code
Package
Diagram
Package Type
Operating
Range
10
CY7C1049CV33-10VXA
51-85090
36-pin (400-Mil) Molded SOJ (Pb-free)
Automotive-A
12
CY7C1049CV33-12ZSXA
51-85087
44-pin TSOP II (Pb-free)
Automotive-A
15
CY7C1049CV33-15VXE
51-85090
36-pin (400-Mil) Molded SOJ (Pb-free)
Automotive-E
CY7C1049CV33-15ZSXE
51-85087
44-pin TSOP II (Pb-free)
Automotive-E
Ordering Code Definitions
CY 7C
1
04
9
C V33 - XX XX X
X
Temperature Range: X = A or E
A = Automotive-A or E = Automotive-E
X = Pb-free; X Absent = Leaded
Package Type: XX = V or ZS
V = 36-pin Molded SOJ
ZS = 44-pin TSOP II
Speed Grade: XX = 10 ns or 12 ns or 15 ns
V33 = 3.0 V to 3.6 V
Process Technology: C  150 nm
Data width: × 8-bits
4-Mbit density
Fast Asynchronous SRAM
Marketing Code: 7C = SRAMs
Company ID: CY = Cypress
Document #: 001-67511 Rev. **
Page 9 of 13
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CY7C1049CV33 Automotive
Package Diagrams
Figure 8. 36-pin (400-Mil) Molded SOJ, 51-85090
51-85090 *E
Figure 9. 44-pin TSOP II, 51-85087
51-85087 *C
Document #: 001-67511 Rev. **
Page 10 of 13
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CY7C1049CV33 Automotive
Acronyms
Acronym
Description
CMOS
complementary metal oxide semiconductor
CE
Chip Enable
OE
Output Enable
RAM
Random Access Memory
I/O
Input/Output
SOJ
small outline J-lead
TTL
transistor-transistor logic
TSOP
thin small outline package
WE
Write Enable
Document Conventions
Units of Measure
Symbol
Unit of Measure

ohms
ns
nano seconds
V
Volts
µs
micro seconds
µA
micro Amperes
mA
milli Amperes
mm
milli meter
ms
milli seconds
MHz
Mega Hertz
pF
pico Farad
%
percent
mW
milli Watts
W
Watts
°C
degree Celcius
Document #: 001-67511 Rev. **
Page 11 of 13
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CY7C1049CV33 Automotive
Document History Page
Document Title: CY7C1049CV33 Automotive 4-Mbit (512 K × 8) Static RAM
Document Number: 001-67511
Rev.
ECN
Orig. of
Change
**
3186792
PRAS
Document #: 001-67511 Rev. **
Submission
Date
Description of Change
03/03/2011 Separation of the automotive datasheet from CY7C1049CV33 spec no.
38-05006 Rev. *J. Further rev of 38-05006 would include only industrial /
commercial parts.
Page 12 of 13
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CY7C1049CV33 Automotive
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2002-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-67511 Rev. **
Revised February 16, 2011
Page 13 of 13
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