CY7C1010DV33 2-Mbit (256K x 8) Static RAM Features Functional Description ■ Pin and function compatible with CY7C1010CV33 ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 90 mA at 10 ns ■ Low CMOS standby power ❐ ISB2 = 10 mA The CY7C1010DV33 is a high performance CMOS Static RAM organized as 256K words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. ■ 2.0V data retention ■ Automatic power down when deselected ■ TTL-compatible inputs and outputs ■ Easy memory expansion with CE and OE features ■ Available in Pb-Free 36-pin SOJ and 44-pin TSOP II packages The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a Write operation (CE LOW, and WE LOW). The CY7C1010DV33 is available in 36-pin SOJ and 44-pin TSOP II packages with center power and ground (revolutionary) pinout. Refer to the Cypress application note AN1064, SRAM System Guidelines for best practice recommendations. Logic Block Diagram IO0 INPUT BUFFER IO1 256K x 8 ARRAY IO3 IO4 IO5 IO6 CE • IO7 POWER DOWN A17 A16 A15 A11 OE A12 A13 A14 COLUMN DECODER WE Cypress Semiconductor Corporation Document Number: 001-00062 Rev. *B IO2 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 6, 2008 [+] Feedback CY7C1010DV33 Selection Guide Description –10 10 90 10 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Unit ns mA mA Pin Configuration Figure 1. 36-Pin SOJ [1] A4 A3 A2 A1 A0 CE IO0 IO1 VCC GND IO2 IO3 WE A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A5 A6 A7 A8 OE IO7 IO6 GND VCC IO5 IO4 A9 A10 A11 A12 NC NC Figure 2. 44-Pin TSOP II [1] NC NC A4 A3 A2 A1 A0 CE IO0 IO1 VCC VSS IO2 IO3 WE A17 A16 A15 A14 A13 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC NC A5 A6 A7 A8 OE IO7 IO6 VSS VCC IO5 IO4 A9 A10 A11 A12 NC NC NC NC Note: 1. NC pins are not connected on the die. Document Number: 001-00062 Rev. *B Page 2 of 11 [+] Feedback CY7C1010DV33 Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Static Discharge Voltage.................................................>2001V (MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch Up Current ..................................................... >200 mA Ambient Temperature with Power Applied ............................................ –55°C to +125°C Operating Range Supply Voltage on VCC Relative to GND [2] ....–0.5V to +4.6V Range VCC DC Voltage Applied to Outputs in High Z State [2] ................................... –0.3V to VCC + 0.3V Ambient Temperature Industrial –40°C to +85°C 3.3V ± 0.3V DC Input Voltage [2] ............................... –0.3V to VCC + 0.3V Electrical Characteristics Over the Operating Range Test Conditions Parameter –10 Description Min VOH Output HIGH Voltage VCC = Min.; IOH = –4.0 mA VOL Output LOW Voltage VCC = Min.; IOL = 8.0 mA Max 2.4 Unit V 0.4 V VIH Input HIGH Voltage 2.0 VCC + 0.3 V VIL Input LOW Voltage[2] –0.3 0.8 V IIX Input Leakage Current GND < VI < VCC –1 +1 μA IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled –1 +1 μA ICC VCC Operating Supply Current VCC = Max., f = fMAX = 1/tRC 100 MHz 90 mA 83 MHz 80 66 MHz 70 40 MHz 60 ISB1 Automatic CE Power-down Current —TTL Inputs Max. VCC, CE > VIH; VIN > VIH or VIN < VIL, f = fMAX 20 mA ISB2 Automatic CE Power-down Current —CMOS Inputs Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 10 mA SOJ TSOP II Unit 8 8 pF 8 8 pF Capacitance Tested initially and after any design or process changes that may affect these parameters. Description Test Conditions CIN Parameter Input Capacitance TA = 25°C, f = 1 MHz, VCC = 3.3V COUT IO Capacitance Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions Still air, soldered on a 3 × 4.5 inch, four layer printed circuit board SOJ TSOP II Unit 59.17 50.66 °C/W 32.63 17.77 °C/W Note 2. VIL (min.) = –2.0V and VIH (max.) = VCC + 2.0V for pulse durations of less than 20 ns. Document Number: 001-00062 Rev. *B Page 3 of 11 [+] Feedback CY7C1010DV33 Figure 3. AC Test Loads and Waveforms[3] Z = 50Ω 50Ω * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT ALL INPUT PULSES 3.0V OUTPUT 30 pF* GND 1.5V (a) High-Z characteristics: 90% 90% 10% 10% Rise Time: 1 V/ns (b) Fall Time: 1 V/ns R 317Ω 3.3V OUTPUT 5 pF (c) R2 351Ω Note 3. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c). Document Number: 001-00062 Rev. *B Page 4 of 11 [+] Feedback CY7C1010DV33 AC Switching Characteristics Over the Operating Range [4] –10 Parameter Description Min. Max. Unit Read Cycle tpower[5] VCC(typical) to the first access 100 μs tRC Read Cycle Time 10 ns tAA Address to Data Valid tOHA Data Hold from Address Change tACE 10 ns CE LOW to Data Valid 10 ns tDOE OE LOW to Data Valid 5 ns tLZOE OE LOW to Low-Z 3 0 High-Z[6, 7] tHZOE OE HIGH to tLZCE CE LOW to Low-Z[7] CE HIGH to tPU CE LOW to Power-up tPD CE HIGH to Power-down ns 5 3 High-Z[6, 7] tHZCE ns ns ns 5 0 ns ns 10 ns Write Cycle[8, 9] tWC Write Cycle Time 10 ns tSCE CE LOW to Write End 7 ns tAW Address Set-up to Write End 7 ns tHA Address Hold from Write End 0 ns tSA Address Set-up to Write Start 0 ns tPWE WE Pulse Width 7 ns tSD Data Set-up to Write End 5 ns tHD Data Hold from Write End 0 ns 3 ns tLZWE tHZWE WE HIGH to Low-Z[7] WE LOW to High-Z[6, 7] 5 ns Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 5. tPOWER gives the minimum amount of time that the power supply should be at stable, typical VCC values until the first memory access can be performed. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured when the outputs enter a high impedance state. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 001-00062 Rev. *B Page 5 of 11 [+] Feedback CY7C1010DV33 Data Retention Characteristics Over the Operating Range [10] Parameter Description Conditions VDR VCC for Data Retention ICCDR Data Retention Current tCDR [11] Chip Deselect to Data Retention Time tR [ 12] Min Max 2 V 10 VCC = VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V Operation Recovery Time Unit mA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE VCC 3.0V VDR > 2V 3.0V tR tCDR CE Switching Waveforms Figure 4. Read Cycle No. 1 [13, 14] tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Notes 10. No inputs may exceed VCC + 0.3V 11. Tested initially and after any design or process changes that may affect these parameters. 12. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 μs or stable at VCC(min.) > 50 μs. 13. The device is continuously selected. OE, CE = VIL. 14. WE is HIGH for read cycle. Document Number: 001-00062 Rev. *B Page 6 of 11 [+] Feedback CY7C1010DV33 Switching Waveforms (continued) Figure 5. Read Cycle No. 2 (OE Controlled) [14, 15] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tHZCE tLZOE HIGH IMPEDANCE DATA VALID tLZCE tPD tPU VCC SUPPLY CURRENT HIGH IMPEDANCE 50% 50% ICC ISB Figure 6. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [16, 17] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 18 tHZOE Notes 15. Address valid before or similar to CE transition LOW. 16. Data IO is high impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. 18. During this period, the I/Os are in output state and input signals should not be applied. Document Number: 001-00062 Rev. *B Page 7 of 11 [+] Feedback CY7C1010DV33 Switching Waveforms (continued) Figure 7. Write Cycle No. 2 (WE Controlled, OE LOW) [17] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD NOTE 18 DATA I/O tHD DATA VALID tLZWE tHZWE Truth Table CE H OE X WE X IO0–IO7 High-Z IO8–IO15 Mode Power High-Z Power Down Standby (ISB) L L H Data Out Data Out Read All Bits Active (ICC) L X L Data In Data In Write All Bits Active (ICC) L H H High-Z High-Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 10 Ordering Code Package Diagram Package Type CY7C1010DV33-10VXI 51-85090 36-pin (400-Mil) Molded SOJ (Pb-free) CY7C1010DV33-10ZSXI 51-85087 44-pin TSOP II (Pb-Free) Document Number: 001-00062 Rev. *B Operating Range Industrial Page 8 of 11 [+] Feedback CY7C1010DV33 Package Diagrams Figure 8. 36-Pin (400-Mil) Molded SOJ (51-85090) 5 1-85 090 -*C Document Number: 001-00062 Rev. *B Page 9 of 11 [+] Feedback CY7C1010DV33 Package Diagrams (continued) Figure 9. 44-Pin TSOP II (51-85087) 51-85087-*A Document Number: 001-00062 Rev. *B Page 10 of 11 [+] Feedback CY7C1010DV33 Document History Page Document Title: CY7C1010DV33, 2-Mbit (256K x 8) Static RAM Document Number: 001-00062 REV. ECN NO. Submission Date Orig. of Change Description of Change ** 342195 See ECN PCI New Data sheet *A 459073 See ECN NXR Converted Preliminary to Final. Removed Commercial Operating Range from product offering. Removed -8 ns and -12 speed bin Removed the Pin definitions table. Modified Maximum Ratings for DC input voltage from -0.5V to -0.3V and VCC + 0.5V to VCC + 0.3V Changed ICC max from 65 mA to 90 mA Changed the description of IIX from “Input Load Current” to “Input Leakage Current” Updated the Thermal Resistance table. Updated footnote #7 on High-Z parameter measurement Added footnote #12 Updated the Ordering Information and replaced Package Name column with Package Diagram in the Ordering Information table. *B 2602853 11/07/08 VKN/PYRS Added 36-pin SOJ package and its related information Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. 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Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-00062 Rev. *B Revised November 6, 2008 Page 11 of 11 All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback