CY7C1019CV33 1-Mbit (128 K × 8) Static RAM 1-Mbit (128 K × 8) Static RAM Features Functional Description ■ Temperature Ranges ❐ Industrial: –40 °C to 85 °C ❐ Automotive-A: –40 °C to 85 °C ■ Pin and Function compatible with CY7C1019BV33 ■ High Speed ❐ tAA = 10 ns ■ CMOS for optimum Speed and Power ■ Data Retention at 2.0 V ■ Center Power/Ground Pinout ■ Automatic Power Down when deselected ■ Easy Memory Expansion with CE and OE Options ■ Available in Pb-free 32-pin TSOP II package The CY7C1019CV33 is a high performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tristate drivers. This device has an automatic power down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). Logic Block Diagram I/O 0 INPUT BUFFER I/O 1 I/O 2 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 128K x 8 ARRAY I/O 3 I/O 4 I/O 5 COLUMN DECODER CE I/O 6 POWER DOWN I/O WE A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 7 OE Cypress Semiconductor Corporation Document #: 38-05130 Rev. *K • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 8, 2011 [+] Feedback CY7C1019CV33 Contents Selection Guide ................................................................ 3 Pin Configuration ............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 4 AC Test Loads and Waveforms ....................................... 5 Switching Characteristics ................................................ 6 Switching Waveforms ...................................................... 7 Truth Table ........................................................................ 9 Ordering Information ........................................................ 9 Ordering Code Definitions ........................................... 9 Document #: 38-05130 Rev. *K Package Diagram ............................................................ 10 Acronyms ........................................................................ 11 Document Conventions ................................................. 11 Units of Measure ....................................................... 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support ....................... 13 Products .................................................................... 13 PSoC Solutions ......................................................... 13 Page 2 of 13 [+] Feedback CY7C1019CV33 Selection Guide -10 (Industrial/ Auto-A) Unit Maximum Access Time 10 ns Maximum Operating Current 80 mA Maximum Standby Current 5 mA Description Pin Configuration Figure 1. 32-pin TSOP II (Top View) [1] A0 A1 A2 A3 CE I/O0 I/O1 VCC V SS I/O2 I/O3 WE A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 VSS VCC I/O5 I/O4 A12 A11 A10 A9 A8 Note 1. NC pins are not connected on the die. Document #: 38-05130 Rev. *K Page 3 of 13 [+] Feedback CY7C1019CV33 Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Latch up Current ..................................................... >200 mA Storage Temperature ............................... –65 °C to +150 °C Operating Range Ambient Temperature with Power Applied ......................................... –55 °C to +125 °C Range Supply Voltage on VCC to Relative GND[2] ................................–0.5 V to +4.6 V Ambient Temperature VCC 0 °C to +70 °C 3.3 V 10% Industrial –40 C to +85 C 3.3 V 10% Automotive-A –40 C to +85 C 3.3 V 10% Commercial DC Voltage Applied to Outputs in High Z State[2] ................................. –0.5 V to VCC + 0.5 V DC Input Voltage[2] ............................. –0.5 V to VCC + 0.5 V Electrical Characteristics Over the Operating Range Parameter Description Test Conditions -10 (Industrial/Auto-A) Unit Min Max 2.4 – V – 0.4 V VOH Output HIGH Voltage VCC = Min, IOH = –4.0 mA VOL Output LOW Voltage VCC = Min, IOL = 8.0 mA VIH Input HIGH Voltage 2.0 VCC + 0.3 V VIL Input LOW Voltage[2] –0.3 0.8 V IIX Input Leakage Current GND < VI < VCC –1 +1 A IOZ Output Leakage Current GND < VI < VCC, Output Disabled –1 +1 A ICC VCC Operating Supply Current VCC = Max, IOUT = 0 mA, f = fMAX = 1/tRC – 80 mA ISB1 Automatic CE Power down Current —TTL Inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX – 15 mA ISB2 Automatic CE Power down Current —CMOS Inputs Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0 – 5 mA Max Unit 8 pF 8 pF Capacitance Parameter[3] Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = 5.0 V Notes 2. VIL (min.) = –2.0 V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05130 Rev. *K Page 4 of 13 [+] Feedback CY7C1019CV33 AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms [4] R 317 3.3 V 3.0 V OUTPUT R2 GND 351 30 pF (a) Rise Time: 1 V/ns High-Z characteristics: ALL INPUT PULSES 90% 90% 10% 10% R 317 3.3 V OUTPUT R2 351 5 pF (b) Fall Time: 1 V/ns (c) Note 4. AC characteristics (except High Z) for all speeds are tested using the Thevenin load shown in section (a) in Figure 2. High Z characteristics are tested for all speeds using the test load shown in section (c) in Figure 2. Document #: 38-05130 Rev. *K Page 5 of 13 [+] Feedback CY7C1019CV33 Switching Characteristics Over the Operating Range Parameter[5] Description -10 (Industrial/ Auto-A) Min Max Unit Read Cycle tRC Read Cycle Time 10 – ns tAA Address to Data Valid – 10 ns tOHA Data Hold from Address Change 3 – ns tACE CE LOW to Data Valid – 10 ns tDOE OE LOW to Data Valid – 5 ns tLZOE OE LOW to Low Z 0 – ns – 5 ns 3 – ns – 5 ns tHZOE tLZCE tHZCE tPU [8] tPD[8] Write OE HIGH to High CE LOW to Low Z[6, 7] Z[7] CE HIGH to High Z[6, 7] CE LOW to Power Up 0 – ns CE HIGH to Power Down – 10 ns Cycle[9, 10] tWC Write Cycle Time 10 – ns tSCE CE LOW to Write End 8 – ns tAW Address Setup to Write End 8 – ns tHA Address Hold from Write End 0 – ns tSA Address Setup to Write Start 0 – ns tPWE WE Pulse Width 7 – ns tSD Data Setup to Write End 5 – ns tHD Data Hold from Write End 0 – ns 3 – ns – 5 ns Z[7] tLZWE WE HIGH to Low tHZWE WE LOW to High Z[6, 7] Notes 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of Figure 2 on page 5. Transition is measured 500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. This parameter is guaranteed by design and is not tested. 9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write. 10. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05130 Rev. *K Page 6 of 13 [+] Feedback CY7C1019CV33 Switching Waveforms Figure 3. Read Cycle No. 1 [11, 12] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 4. Read Cycle No. 2 (OE Controlled) [12, 13] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tHZCE tLZOE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU ICC 50% 50% ISB Figure 5. Write Cycle No. 1 (CE Controlled) [14, 15] tWC ADDRESS tSCE CE tSA tSCE tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID Notes 11. Device is continuously selected. OE, CE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. 14. Data I/O is high impedance if OE = VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document #: 38-05130 Rev. *K Page 7 of 13 [+] Feedback CY7C1019CV33 Switching Waveforms (continued) Figure 6. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [16, 17] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 18 tHZOE Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) [17] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 18 tHD DATA VALID tHZWE tLZWE Notes 16. Data I/O is high impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. 18. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05130 Rev. *K Page 8 of 13 [+] Feedback CY7C1019CV33 Truth Table I/O0–I/O7 WE Mode Power CE OE H X X High Z Power Down Standby (ISB) L L H Data Out Read Active (ICC) L X L Data In Write Active (ICC) L H H High Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 10 Package Diagram Ordering Code Package Type CY7C1019CV33-10ZXA 51-85095 32-pin TSOP II (Pb-free) CY7C1019CV33-10ZXAT 51-85095 32-pin TSOP II (Pb-free) Operating Range Automotive-A Ordering Code Definitions CY 7 C 1019 C V33 - 10 Z X A X X = T or Blank T = Tape and Reel; Blank = Tube Temperature Range: A = Automotive-A Pb-free Package Type: Z = 32-pin TSOP II Speed Grade: 10 ns V33 = 3.3 V Process Technology 0.16 µm Part Identifier Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document #: 38-05130 Rev. *K Page 9 of 13 [+] Feedback CY7C1019CV33 Package Diagram Figure 8. 32-pin TSOP II (20.95 × 11.76 × 1.0 mm) ZS32 51-85095 *B Document #: 38-05130 Rev. *K Page 10 of 13 [+] Feedback CY7C1019CV33 Acronyms Acronym Document Conventions Description Units of Measure CMOS complementary metal oxide semiconductor CE chip enable °C degree Celsius I/O input/output MHz Mega Hertz OE output enable µA micro Amperes SRAM static random access memory mA milli Amperes TSOP thin small outline package mm milli meter TTL transistor-transistor logic ms milli seconds WE write enable ns nano seconds % percent pF pico Farad V Volts W Watts Document #: 38-05130 Rev. *K Symbol Unit of Measure Page 11 of 13 [+] Feedback CY7C1019CV33 Document History Page Document Title: CY7C1019CV33, 1-Mbit (128 K × 8) Static RAM Document Number: 38-05130 REV. ECN NO. Submission Date Orig. of Change ** 109245 12/16/01 HGK New Data Sheet *A 113431 04/10/02 NSL AC Test Loads split based on speed *B 115047 08/01/02 HGK Added TSOP II Package and I Temp. Improved ICC limits Description of Change *C 119796 10/11/02 DFP Updated standby current from 5 nA to 5 mA *D 123030 12/17/02 DFP Updated Truth Table to reflect single Chip Enable option *E 419983 See ECN NXR Added 48-ball VFBGA Package Added lead-free parts in Ordering Information Table Replaced Package Name column with Package Diagram in the Ordering Information Table *F 493543 See ECN NXR Removed 8 ns speed bin from Product offering Added note #1 on page #2 Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Removed IOS parameter from DC Electrical Characteristics table Updated Ordering Information *G 2761448 09/09/2009 VKN *H 2897691 03/23/2010 RAME Updated Ordering Information Updated Package Diagrams *I 3057593 10/13/2010 PRAS Updated Ordering Information and added Ordering Code Definitions. Updated Package Diagram. *J 3072834 11/11/2010 PRAS Removed obsolete parts and package diagrams. *K 3277371 06/08/2011 AJU Document #: 38-05130 Rev. *K Included Automotive-A information Updated Features. Updated Selection Guide (Removed -12 (Industrial) and -15 (Industrial) columns). Updated Electrical Characteristics (Removed -12 (Industrial) and -15 (Industrial) columns). Updated Switching Characteristics (Removed -12 (Industrial) and -15 (Industrial) columns). Updated Package Diagram. Updated in new template. Page 12 of 13 [+] Feedback CY7C1019CV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2001-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. 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Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05130 Rev. *K Revised June 8, 2011 Page 13 of 13 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback