CY29940-1 2.5V or 3.3V, 200-MHz 1:18 Clock Distribution Buffer Features 200-MHz clock support LVPECL or LVCMOS/LVTTL clock input LVCMOS/LVTTL-compatible inputs 18 clock outputs: drive up to 36 clock lines 150 ps max. output-to-output skew 23Ω output impedance Dual or single supply operation: — 3.3V core and 3.3V outputs — 3.3V core and 2.5V outputs — 2.5V core and 2.5V outputs • Pin-compatible with MPC940L, MPC9109 • Available in commercial and industrial temperature ranges • 32-pin TQFP package Block Diagram The CY29940-1 is a low-voltage 200-MHz clock distribution buffer with the capability to select either a differential LVPECLor a LVCMOS/LVTTL-compatible input clock. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL-compatible. The eighteen outputs are 2.5V or 3.3V LVCMOS/LVTTL-compatible and can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:36. Low output-to-output skews make the CY29940-1 an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems. Cypress Semiconductor Corporation Document #: 38-07487 Rev. ** • 3901 North First Street VSS Q5 Q4 Q3 VDDC Q2 VDD 20 Q9 6 19 Q10 VDD 7 18 Q11 VDDC 8 17 VSS PECL_CLK 5 PECL_CLK# • CY29940-1 9 10 11 12 13 14 15 16 VDDC 4 Q12 TCLK_SEL Q13 TCLK_SEL Q8 21 TCLK 2 3 Q0-Q17 1 Q7 22 VSS Q14 18 Q6 23 1 VSS TCLK 0 32 31 30 29 28 27 26 25 24 VSS Q16 PECL_CLK PECL_CLK# VDDC Q17 VDD Q1 Q0 Pin Configuration Q15 • • • • • • • Description San Jose, CA 95134 • 408-943-2600 Revised January 28, 2003 CY29940-1 Pin Description[1] Pin Name PWR I/O Description 5 PECL_CLK I, PU PECL Input Clock 6 PECL_CLK# I, PD PECL Input Clock 3 TCLK 9, 10, 11, 13, Q(17:0) 14, 15, 18, 19, 20, 22, 23, 24, 26, 27, 28, 30, 31, 32 4 I, PD External Reference/Test Clock Input VDDC TCLK_SEL O Clock Outputs I, PD Clock Select Input. When LOW, PECL clock is selected and when HIGH TCLK is selected. 8, 16, 29 VDDC 3.3V or 2.5V Power Supply for Output Clock Buffers 7, 21 VDD 3.3V or 2.5V Power Supply 1, 2, 12, 17, 25 VSS Common Ground Note: 1. PD = Internal Pull-down; PU = Internal Pull-up. Document #: 38-07487 Rev. ** Page 2 of 7 CY29940-1 Storage Temperature: ................................–65°C to + 150°C This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: Operating Temperature: ................................ –40°C to +85°C VSS < (Vin or Vout) < VDD Maximum ESD Protection............................................... 2 kV Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). Absolute Maximum Conditions Maximum Input Voltage Relative to VSS: ............ VSS – 0.3V Maximum Input Voltage Relative to VDD: ............. VDD + 0.3V Maximum Power Supply: ................................................5.5V Maximum Input Current: ............................................±20 mA DC Electrical Specifications: VDD = 3.3V ±5% or 2.5V ±5%, VDDC = 3.3V ±5% or 2.5V ±5% Parameter Description Conditions Min. Typ. Max. Unit VIL Input Low Voltage VSS 0.8 V VIH Input High Voltage 2.0 VDD V IIL Input Low Current[2] –200 µA IIH Input High Current[2] 200 µA VPP Peak-to-Peak Input Voltage PECL_CLK 500 1000 mV VCMR Common Mode Range[3] PECL_CLK VDD = 3.3V VDD – 1.4 VDD – 0.6 V VDD = 2.5V VDD – 1.0 VDD – 0.6 Voltage[4,5,6] VOL Output Low VOH Output High Voltage[4,5,6] IOL = 20 mA, VDDC = 3.3V 0.5 V IOL = 16 mA, VDDC = 2.5V IDDQ Quiescent Supply Current IDD Dynamic Supply Current Zout Output Impedance Cin Input Capacitance IOH = –20 mA, VDDC = 3.3V 2.4 IOH = –16 mA, VDDC = 2.5V 1.8 V 5 VDD = 3.3V, Outputs @ 150 MHz, CL=10 pF 285 VDD = 3.3V, Outputs @ 200 MHz, CL=10 pF 335 VDD = 2.5V, Outputs @ 150 MHz, CL=10 pF 200 VDD = 2.5V, Outputs @ 200 MHz, CL=10 pF 240 18 23 4 7 mA mA 28 Ω pF Notes: 2. Inputs have pull-up/pull-down resistors that effect input current. 3. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR range and the input lies within the VPP specification. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines. 4. Outputs driving 50Ω transmission lines. 5. See Figure 1 and Figure 2. 6. 50% input duty cycle. Document #: 38-07487 Rev. ** Page 3 of 7 CY29940-1 AC Electrical Specifications (VDD = 3.3V ±5% or 2.5V ±5%, VDDC = 3.3V ±5% or 2.5V ±5%)[7] Parameter Fmax TPD Description Conditions Input Frequency PECL_CLK to Q Delay[4,5,10] </ =150 MHz LVCMOS to Q Delay[4,5,10] </ =150 MHz FoutDC Output Duty Cycle[4,5,6] Tskew Output-to-Output Skew[4,5] Tskew(pp) Part-to-Part Skew[8] Tskew(pp) Part-to-Part Skew[8] Tskew(pp) Part to Part Skew[9] tR/tF Output Clocks Rise/Fall Time[4,5] Min. Typ. Max. Unit LVCMOS Input 200 MHz LVPECL Input 180 VDD = 3.3V 2.0 4.0 VDD = 2.5V 2.6 5.2 VDD = 3.3V 1.8 3.4 VDD = 2.5V 2.3 4.0 FCLK < 134 MHz 45 55 FCLK > 134 MHz 40 60 PECL, VDDC = 3.3V ns % 150 ps 1.4 ns PECL, VDDC = 2.5V 2.2 TCLK, VDDC = 3.3V 1.2 TCLK, VDDC = 2.5V 1.7 PECL_CLK 850 TCLK 750 0.7V to 2.0V, VDDC = 3.3V 0.3 1.1 0.5V to 1.8V, VDDC = 2.5V 0.3 1.3 ns ps ns CY29940-1 DUT Pulse Generator Z = 50 ohm Zo = 50 ohm Zo = 50 ohm RT = 50 ohm VTT RT = 50 ohm VTT Figure 1. LVCMOS_CLK CY29940-1 Test Reference for VCC = 3.3V and VCC = 2.5V Zo = 50 ohm Differential Pulse Generator Z = 50 ohm CY29940-1 DUT Zo = 50 ohm Zo = 50 ohm RT = 50 ohm RT = 50 ohm VTT VTT Figure 2. PECL_CLK CY29940-1 Test Reference for VCC = 3.3V and VCC = 2.5V Notes: 7. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. 8. Across temperature and voltage ranges, includes output skew. 9. For a specific temperature and voltage, includes output skew. 10. Parameters tested @ 150 MHz. Document #: 38-07487 Rev. ** Page 4 of 7 CY29940-1 VCC PECL_CLK VCMR VPP PECL_CLK VCC /2 tP VCC Q VCC /2 tPD GND T0 DC = tP / T0 x 100% GND Figure 3. Propagation Delay (TPD) Test Reference Figure 5. Output Duty Cycle (FoutDC) VCC VCC LVCMOS_CLK VCC /2 VCC /2 GND GND VCC VCC Q VCC /2 VCC /2 tPD tSK(0) GND Figure 4. LVCMOS Propagation Delay (TPD) Test Reference GND Figure 6. Output-to-Output Skew tsk(0) Ordering Information Part Number CY29940AC–1 Package Type Production Flow 32-pin TQFP Commercial, 0°C to 70°C CY29940AC–1T 32-pin TQFP – Tape and Reel Commercial, 0°C to 70°C CY29940AI–1 32-pin TQFP Industrial, –40°C to +85°C CY29940AI–1T 32-pin TQFP – Tape and Reel Industrial, –40°C to +85°C Document #: 38-07487 Rev. ** Page 5 of 7 CY29940-1 Package Drawing and Dimensions 32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.4 mm A32.14 51-85088-*B All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07487 Rev. ** Page 6 of 7 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY29940-1 Document History Page Document Title: CY29940-1 2.5V or 3.3V, 200-MHz 1:18 Clock Distribution Buffer Document Number: 38-07487 REV. ECN NO. Issue Date Orig. of Change ** 119820 01/29/03 BRK Document #: 38-07487 Rev. ** Description of Change New Data Sheet Page 7 of 7