Preliminary information June 2000 AS6UA25617 1.65V to 3.6V 256K×16 Intelliwatt™ low power CMOS SRAM with two chip enables • Low power consumption: STANDBY - 72 µW max at 3.6V - 41 µW max at 2.7V - 28 µW max at 2.3V • 1.2V data retention • Equal access and cycle times • Easy memory expansion with CS1, CS2, OE inputs • Smallest footprint package - 400-mil 44-pin TSOP II - 48-ball FBGA • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA Features • • • • • • • • • AS6UA25617 Intelliwatt™ active power circuitry Industrial and commercial temperature ranges available Organization: 262,144 words × 16 bits 2.7V to 3.6V at 55 ns 2.3V to 2.7V at 70 ns 1.65V to 2.3V at 100 ns CS1 and CS2 for chip selection Low power consumption: ACTIVE - 144 mW at 3.6V and 55 ns - 68 mW at 2.7V and 70 ns - 28 mW at 2.3 V and 100 ns Pin arrangement (top view) Logic block diagram VDD Row Decoder A0 A1 A2 A3 A4 A6 A7 A8 A12 A13 I/O1–I/O8 I/O9–I/O16 400-pin 400-mil TSOP II A0 1 A17 44 A1 2 43 A16 A2 3 42 A15 A3 4 41 OE 5 40 UB A4 LB 6 39 CS1 I/O16 I/O1 7 38 I/O15 I/O2 8 37 I/O14 I/O3 9 36 I/O13 I/O4 10 35 VSS VCC 11 34 VCC VSS 12 33 I/O12 I/O5 13 32 I/O11 I/O6 14 31 I/O7 I/O10 15 30 I/O8 I/O9 16 29 WE CS2 17 28 A5 A14 18 27 A6 A13 19 26 A7 A12 20 25 A8 21 A11 24 A9 22 A10 23 1024 × 256 × 16 Array (4,194,304) I/O buffer Control circuit VSS Column decoder A5 A9 A10 A11 A14 A15 A16 A17 WE UB OE LB CS1 CS2 48-CSP Ball-Grid-Array Package 1 2 3 4 5 6 A LB OE A0 A1 A2 CS2 B I/O9 UB A3 A4 CS1 I/O1 C I/O10 I/O11 A5 A6 I/O2 I/O3 D VSS I/O12 A17 A7 I/O4 VCC E VCC I/O13 NC A16 I/O5 VSS F I/O15 I/O14 A14 A15 I/O6 I/O7 G I/O16 NC A12 A13 WE I/O8 H NC A8 A9 A10 A11 NC Selection guide VCC Range Power Dissipation Typ2 (V) Max (V) Speed (ns) Operating (ICC1) Standby (ISB2) Product Min (V) Max (mA) Max (µA) AS6UA25617 2.7 3.0 3.6 55 2 20 AS6UA25617 2.3 2.5 2.7 70 1 15 AS6UA25617* 1.65 2.0 2.3 100 1 12 ALLIANCE SEMICONDUCTOR 1 Copyright ©2000 Alliance Semiconductor. All rights reserved. AS6UA25617 Functional description The AS6UA25617 is a low-power CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 262,144 words × 16 bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 55/70/100 ns are ideal for low-power applications. Active high and low chip selects (CS1 and CS2) permit easy memory expansion with multiple-bank memory systems. When CS1 is high, or UB and LB are high or CS2 is low, the device enters standby mode: the AS6UA25617 is guaranteed not to exceed 72 µW power consumption at 3.6V and 55 ns; 41 µW at 2.7V and 70 ns; or 28 µW at 2.3V and 100 ns. The device also returns data when V CC is reduced to 1.5V for even lower power consumption. A write cycle is accomplished by asserting write enable (WE) and chip select (CS1) low, UB and/or LB low, and CS2 high. Data on the input pins I/O1–I/O16 is written on the rising edge of WE (write cycle 1) or CS1, CS2 (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE), chip select (CS1) low, UB and/or LB low, with write enable (WE) and CS2 high. The chip drives I/O pins with the data word referenced by the input address. When either chip select or output enable is inactive, or write enable is active, or (UB) and (LB), output drivers stay in high-impedance mode. This device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16. All chip inputs and outputs are CMOS-compatible, and operation is from either a single 1.65V to 3.6V supply. The device is available in the JEDEC standard 48-ball FBGA and 44-pin TSOPII packages. Absolute maximum ratings Parameter Device Symbol Min Max Unit Voltage on VCC relative to VSS VtIN –0.5 VCC + 0.5 V Voltage on any I/O pin relative to GND VtI/O –0.5 Power dissipation PD – 1.0 W Storage temperature (plastic) Tstg –65 +150 °C Temperature with VCC applied Tbias –55 +125 °C DC output current (low) IOUT – 20 mA V Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specificati on is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CS1 CS2 OE WE LB UB I/O1–8 I/O9–16 Mode Power H X X X X X High-Z High-Z Deselected Standby X L X X X X High-Z High-Z Deselected Standby X X X X H H High-Z High-Z Deselected Standby L H H H L X High-Z High-Z Output Disabled Active L H H H X L High-Z High-Z Output Disabled Active L H L H L H DOUT High-Z Lower Byte Read Active L H L H H L High-Z DOUT Upper Byte Read Active L H L H L L DOUT DOUT Word Read Active L H X L L H DIN High-Z Lower Byte Write Active L H X L H L High-Z DIN Upper Byte Write Active L H X L L L DIN DIN Word Write Active Key: X = Don’t care, L = Low, H = High. 2 AS6UA25617 Recommended operating condition (over the operating range) Parameter VOH VOL VIH VIL IIX IOZ ICC ICC1 @ 1 MHz ICC2 ISB ISB1 ISBDR Description Test Conditions VCC = 2.7V IOH = 2.1mA IOH = 1.5mA Output HIGH Voltage VCC = 2.3V VCC = 1.65V IOH = 1.65mA IOL = 2.1mA VCC = 2.7V Output LOW Voltage VCC = 2.3V IOL = 0.5mA VCC = 1.65V IOL = 0.1mA VCC = 2.7V Input HIGH Voltage VCC = 2.3V VCC = 1.65V VCC = 2.7V Input LOW Voltage VCC = 2.3V VCC = 1.65V Input Load Current GND < VIN < VCC Output Load Current GND < VO < VCC; Outputs High Z VCC = 3.6V CS1 = VIL, V IN = VIL VCC Operating Supply or VIH, IOUT = 0mA, VCC = 2.7V Current f=0 VCC = 2.3V V CS1 ≤ 0.2V, VIN ≤ CC = 3.6V Average VCC Operating 0.2V or VIN ≥ VCC – VCC = 2.7V Supply Current at 1 MHz 0.2V, f = 1mS VCC = 2.3V VCC = 3.6V (55/70/100 ns) Average VCC Operating CS1 ≤ VIL, VIN = VIL, VCC = 2.7V (55/70/100 ns) Supply Current or VIH, f = fMax VCC = 2.3V (55/70/100 ns) CS1 ≥ VIH, CS2 = VIH, VCC = 3.6V CS1, CS2 Power Down or UB = LB ≥ VIH, VCC = 2.7V Current; TTL inputs other inputs = VIL or VCC = 2.3V VIH, f = 0 CS1, CS2 Power Down Current; CMOS Inputs Data Retention CS1 > VCC – 0.2V, CS2 = + 0.2V, or UB = LB > VCC – 0.2V, other input = 0V – VCC, f = fMax CS1 > VCC – 0.1V, CS2 < + 0.1V, or UB = LB = VCC – 0.1V, f = 0 Min 2.4 2.0 1.5 2.2 2.0 1.4 –0.5 –0.3 –0.3 –1 –1 Max Unit V 0.4 0.4 0.2 VCC + 0.5 VCC + 0.3 VCC + 0.3 0.8 0.6 0.4 +1 +1 2 1 1 2 1 1 40/30/20 30/25/15 25/20/12 100 V V V µA µA mA mA mA µA VCC = 3.6V 20 VCC = 2.7V 15 VCC = 2.3V 12 VCC = 1.2V 2 µA Max 5 7 Unit pF pF µA Capacitance (f = 1 MHz, T a = Room temperature, VCC = NOMINAL)2 Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals A, CS1, CS2, WE, OE, LB, UB I/O Test conditions VIN = 0V VIN = VOUT = 0V 3 AS6UA25617 Read cycle (over the operating range) –55 Parameter –70 –100 Symbol Min Max Min Max Min Max Unit Read cycle time tRC 55 – 70 – 100 – ns Address access time tAA – 55 – 70 – 100 ns 3 tACS1,2 – 55 – 70 – 100 ns 3 Output enable (OE) access time tOE – 25 – 35 – 50 ns Output hold from address change tOH 10 – 10 – 15 – ns 5 Chip selects low to output in low Z tCLZ 10 – 10 – 10 – ns 4, 5 Chip selects high to output in high Z tCHZ 0 20 0 20 0 20 ns 4, 5 OE low to output in low Z tOLZ 5 – 5 – 5 – ns 4, 5 UB/LB access time tBA – 55 – 70 – 100 ns UB/LB low to low Z tBLZ 10 – 10 – 10 – ns 4, 5 UB/LB high to high Z tBHZ 0 20 0 20 0 20 ns 4, 5 OE high to output in high Z tOHZ 0 20 0 20 0 20 ns 4, 5 Power up time tPU 0 – 0 – 0 – ns 4, 5 Power down time tPD – 55 – 70 – 100 ns 4, 5 Chip selects access time Shaded areas indicate preliminary information. Key to switching waveforms Rising input Falling input Undefined/don’t care Read waveform 1 (address controlled) tRC Address tAA tOH D OUT tOH Previous data valid Data valid Read waveform 2 (chip selects, OE, UB, LB controlled) tRC Address tAA OE tOE tOLZ tOH CS1 tLZ tLZ tOHZ tHZ ttOHZ OHZ tACS1 tACS1 CS2 tOLZ tOH tOE tHZ LB, UB tBLZ DOUT 4 tBA tBHZ Data valid Notes AS6UA25617 Write cycle (over the operating range) –55 Parameter –70 –100 Symbol Min Max Min Max Min Max Unit Notes Write cycle time tWC 55 – 70 – 100 – ns Chip selects to write end tCW 40 – 60 – 80 – ns Address setup to write end tAW 40 – 60 – 80 – ns Address setup time tAS 0 – 0 – 0 – ns Write pulse width tWP 35 – 55 – 70 – ns Address hold from end of write tAH 0 – 0 – 0 – ns Data valid to write end tDW 25 – 30 – 40 – ns Data hold time tDH 0 – 0 – 0 – ns 4, 5 Write enable to output in high Z tWZ 0 20 0 20 0 20 ns 4, 5 Output active from write end tOW 5 – 5 – 5 – ns 4, 5 UB/LB low to end of write tBW 35 – 55 – 70 – ns 12 12 Shaded areas indicate preliminary information. Write waveform 1 (WE controlled) tWC Address tAH tCW CS1 tCW CS2 tAH tBW LB, UB tAW tAS WE tWP tDW D IN Data valid tWZ DOUT tOW Data undefined Write waveform 2 (chip selects controlled) tDH High Z tWC Address tAS tAH tCW CS1 tAW tAW CS2 tCW tAS tAH tBW LB, UB tWP WE tDW DIN DOUT tCLZ High Z tWZ Data undefined tDH Data valid tOW High Z 5 AS6UA25617 Data retention characteristics (over the operating range) Parameter Sym Test conditions Min Max Unit VCC for data retention VDR 1.2V 3.6 V Data retention current ICCDR – 2 mA Chip deselect to data retention time tCDR VCC = 1.2V CS1 ≥ VCC – 0.1V or UB = LB > VCC – 0.1V VIN ≥ VCC – 0.1V or VIN ≤ 0.1V 0 – ns tRC – ns Operation recovery time tR Data retention waveform Data retention mode VCC VDR ≥ 1.2V VCC VCC tCDR CS1 VIH CS2 VIH tR VDR VIH VIH VDR tCDR tR AC test loads and waveforms VCC OUTPUT R1 R1 VCC OUTPUT 30 pF OUTPUT 5 pF Parameters R1 R2 RTH VTH R2 INCLUDING JIG AND SCOPE (a) 3.0V 1105 1550 645 1.75V VCC Typ GND 90% 10% 90% < 5 ns (b) 2.5V 16670 15380 8000 1.2V 6 10% (c) 2.0V 15294 11300 6500 0.85V Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 14 V ALL INPUT PULSES R2 INCLUDING JIG AND SCOPE Thevenin equivalent: RTH During V CC power-up, a pull-up resistor to VCC on CS1 is required to meet I SB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions. tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500 mV from steady-state voltage. This parameter is guaranteed, but not tested. WE is HIGH for read cycle. CS1 and OE are LOW and CS2 is HIGH for read cycle. Address valid prior to or coincident with CS1 transition LOW and CS2 HIGH. All read cycle timings are referenced from the last valid address to the first transitioning address. CS1 or WE must be HIGH or CS2 LOW during address transitions. Either CS1 or WE asserting HIGH terminates a write cycle. All write cycle timings are referenced from the last valid address to the first transitioning address. CE1 and CE2 have identical timing. 1.2V data retention applies to commercial and industrial temperature range operations. C = 30pF, except at HIGH Z and LOW Z parameters, where C = 5pF. Unit Ohms Ohms Ohms Volts AS6UA25617 Typical DC and AC characteristics Normalized supply current vs. supply voltage Normalized access time vs. supply voltage 1.4 Normalized standby current vs. ambient temperature 1.0 3.0 2.5 VIN = VCC typ 0.8 TA = 25 °C 0.6 0.4 0.75 Normalized ISB2 1.0 Normalized TAA Normalized ICC 1.2 TA = 25 °C 0.5 1.5 1.0 0.5 0.0 0.25 0.2 VCC = VCC typ VIN = VCC typ 2.0 –0.5 0.0 1.7 2.2 2.7 3.2 3.7 0.0 1.7 Supply voltage (V) 2.2 2.7 3.2 3.7 –55 Supply Voltage (V) Normalized standby current vs. supply voltage Normalized ICC vs. Cycle Time 1.4 1.0 Normalized ICC Normalized ISB 1.5 ISB2 1.2 25 105 Ambient temperature (°C) 0.8 0.6 0.4 1.0 VIN = V CC typ TA = 25 °C 0.50 VIN = VCC typ 0.2 TA = 25 °C 0.10 0.0 1 2.8 1.9 Supply voltage (V) 1 3.7 5 10 Supply voltage (V) 15 Package diagrams and dimensions c 44434241403938373635343332313029282726252423 e He 44-pin TSOP II 1 2 3 4 5 6 7 8 9 10111213141516171819202122 d A2 A A1 b 0–5° l A A1 A2 b c d e He E l 44-pin TSOP II Min (mm) Max (mm) 1.2 0.05 0.95 1.05 0.25 0.45 0.15 (typical) 20.85 21.05 10.06 10.26 11.56 11.96 0.80 (typical) 0.40 0.60 E 7 AS6UA25617 48-ball FBGA Bottom View 6 5 4 3 Top View 2 Ball #A1 index Ball #A1 1 A B C D SRAM Die C1 C E F A G H Elastomer A B B1 Detail View Side View A E2 D E E2 Y E Die Die E1 A B B1 C C1 D E E1 E2 Y 8 0.3/Typ Minimum – 6.90 – 10.90 – 0.30 – – 0.22 – Typical 0.75 7.00 3.75 11.00 5.25 0.35 – 0.68 0.25 – Maximum – 7.10 – 11.10 – 0.40 1.20 – 0.27 0.08 Notes 1. Bump counts: 48 (8 row × 6 column). 2. Pitch: (x,y) = 0.75 mm × 0.75 mm (typ). 3. Units: millimeters. 4. All tolerances are ±0.050 unless otherwise specified. 5. Typ: typical. 6. Y is coplanarity: 0.08 (max). AS6UA25617 Ordering codes Speed (ns) Ordering Code Package Type 55/70/100 AS6UA25617-BC AS6UA25617-TC AS6UA25617-BI A6UA25617-TI 48-ball fine pitch BGA 44-pin TSOP II 48-ball fine pitch BGA 44-pin TSOP II Operating Range Commercial Industrial Part numbering system AS6UA 25617 SRAM Intelliwatt™ prefix Device number B, T Package: B: CSP BGA T: TSOP II C, I Temperature range: C: Commercial: 0° C to 70° C I: Industrial: -40° C to 85° C 9 Copyright ©2000 Alliance Semiconductor Corporation (Alliance)'s three-point logo, our name, and Intelliwatt™ are trademarks or r egistered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this web site and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this web site. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to fitness