PDM41256 256K Static RAM 32K x 8-Bit Description Features n n n n n The PDM41256 is a high-performance CMOS static RAM organized as 32,768 x 8 bits. Writing to this device is accomplished when the write enable (WE) and the chip enable (CE) inputs are both LOW. Reading is accomplished when WE remains HIGH and CE and OE are both LOW. High-speed access times Com’l: 7, 8, 10, 12 and 15ns Ind’l: 8, 10, 12 and 15ns (use 15ns for slower designs) Low power operation (typical) - PDM41256SA Active: 475 mW Standby: 100 mW - PDM41256LA Active: 425mW Standby: 25 mW The PDM41256 operates from a single +5V power supply and all the inputs and outputs are fully TTLcompatible. The PDM41256 comes in two versions: the standard power version PDM41256SA and the low power version PDM41256LA. Both versions are functionally the same and differ only in their power consumption. Single +5V (±10%) power supply TTL-compatible inputs and outputs Packages Plastic SOJ (300 mil) - SO Plastic TSOP (I) - T The PDM41256 is available in a 28-pin plastic TSOP (I) and a 28-pin 300-mil plastic SOJ. Addresses I/O 0 • A0 • • • • • A 14 Decoder • • • • • • Memory 4 5 8 Matrix 9 • • • • • Input Data Control Column I/O 10 • 11 • CE 3 7 • I/O 7 2 6 Functional Block Diagram • 12 WE OE Rev. 4.4 - 4/29/98 1 1 PDM41256 SOJ Pin Configurations Pin Description TSOP (I) OE A11 A9 A8 A13 WE Vcc A14 A12 A7 A6 A5 A4 A3 21 20 19 18 17 16 15 14 13 12 11 10 9 8 22 23 24 25 26 27 28 1 2 3 4 5 6 7 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 Vss I/O2 I/O1 I/O0 A0 A1 A2 A14 1 28 Vcc A12 2 27 WE A7 3 26 A6 4 25 A5 5 24 A9 A4 6 23 A11 Name Description A13 A14-A0 Address Inputs A8 I/O7-I/O0 Data Inputs/Outputs OE Output Enable Input Write Enable Input A3 7 22 OE WE A2 8 21 A10 CE Chip Enable Input A1 9 CE VCC Power (+5V) A0 10 20 19 I/O0 11 18 I/O6 VSS Ground I/O1 12 17 I/O5 I/O2 13 14 16 I/O4 15 I/O3 Vss I/O7 Truth Table OE WE CE I/O MODE X X H Hi-Z Standby L H L DOUT Read X L L DIN Write H H L Hi-Z Output Disable NOTE: 1. H = VIH, L = VIL, X = DON’T CARE Absolute Maximum Ratings (1) Symbol Rating Com’l. Ind. Unit VTERM Terminal Voltage with Respect to Vss –0.5 to +7.0 –0.5 to +7.0 V TBIAS Temperature Under Bias –55 to +125 –65 to +135 °C TSTG Storage Temperature –55 to +125 –65 to +150 °C PT Power Dissipation 1.0 1.0 W IOUT DC Output Current 50 50 mA 125 145 °C Tj Maximum Junction Temperature (2) NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Appropriate thermal calculations should be performed in all cases and specifically for those where the chosen package has a large thermal resistance (e.g., TSOP). The calculation should be of the form: Tj = Ta + P * θja where Ta is the ambient temperature, P is average operating power and θja the thermal resistance of the package. For this product, use the following θja values: SOJ: 78 oC/W TSOP: 112 oC/W 2 Rev. 4.4 - 4/29/98 PDM41256 Recommended DC Operating Conditions Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V VSS Supply Voltage 0 0 0 V Commercial Ambient Temperature 0 25 70 °C Industrial Ambient Temperature –40 25 85 °C 1 2 3 DC Electrical Characteristics (VCC = 5.0V ± 10%) PDM41256SA PDM41256LA Unit Min. Max. Min. Max. Symbol Parameter Test Conditions ILI Input Leakage Current VCC = MAX., VIN = Vss to VCC Com’l/ Ind. –5 5 –1 1 µA ILO Output Leakage Current VCC= MAX., CE = VIH, VOUT = Vss to VCC Com’l/ Ind. –5 5 –1 1 µA VIL Input Low Voltage –0.5(1) 0.8 –0.5(1) 0.8 V VIH Input High Voltage 2.2 6.0 2.2 6.0 V VOL Output Low Voltage IOL=8 mA, VCC = Min. IOL = 10 mA, VCC = Min. — — 0.4 0.5 — — 0.4 0.5 V VOH Output High Voltage IOH = –4 mA, VCC = Min. 2.4 — 2.4 — V 4 5 6 NOTE: 1. VIL(min) = –3.0V for pulse width less than 20 ns. 7 Power Supply Characteristics -7 Symbol Parameter ICC ISB ISB1 -8 -10 Power Com’l. Com’l. Ind. -12 8 -15 Com’l. Ind. Com’l. Ind. Com’l. Ind. Units Operating Current CE = VIL SA 210 200 210 190 200 170 180 150 160 mA f = fMAX = 1/tRC VCC = Max IOUT = 0 mA LA 190 180 190 170 180 150 160 130 140 mA Standby Current CE = VIH SA 90 80 80 70 70 60 60 50 50 mA f = fMAX = 1/tRC VCC = Max LA 90 80 80 70 70 60 60 50 50 mA Full Standby Current CE ≥ VCC – 0.2V SA 20 20 20 20 20 20 20 20 20 mA f=0 VCC = Max VIN ≥ VCC – 0.2V or ≤ 0.2V LA 5 5 5 5 5 5 5 5 5 mA 9 10 11 12 SHADED AREA = PRELIMINARY DATA NOTE:All values are maximum guaranteed values. Rev. 4.4 - 4/29/98 3 PDM41256 Capacitance(1) (TA = +25°C, f = 1.0 MHz) Symbol Parameter Max. Unit CIN Input Capacitance 8 pF COUT Output Capacitance 8 pF NOTE: 1. This parameter is determined by device characterization but is not production tested. AC Test Conditions Input pulse levels VSS to 3.0V Input rise and fall times 3 ns Input timing reference levels 1.5V Output reference levels 1.5V Output load See Figures 1 and 2 +5V +5V 480Ω 480Ω DOUT DOUT 255Ω 255Ω 30 pF Delta tAA - nS Figure 1. Output Load Equivalent 5 pF Figure 2. Output Load Equivalent (for tLZCE, tHZCE, tLZWE, tHZWE, tLZOE, tHZOE) Typical Delta tAA vs Capacitive Loading 5 4 3 2 1 0 0 30 60 90 120 Additional Lumped Capacitive Loading (pF) Figure 3. 4 Rev. 4.4 - 4/29/98 PDM41256 Read Cycle No. 1(1) 1 t RC ADDR t AA t OH DOUT 2 DATA VALID PREVIOUS DATA VALID 3 Read Cycle No. 2(2) 4 tRC ADDR tAA tACE 5 CE tHZCE tLZCE OE tLZOE 6 tHZOE DOUT DATA VALID tAOE 7 AC Electrical Characteristics --7(6) Description READ Cycle Sym READ cycle time tRC --8(6) -10(6) -12 8 -15 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 7 8 10 12 15 ns Address access time tAA 7 8 10 12 15 ns Chip enable access time tACE 7 8 10 12 15 ns Output hold from address change (3, 4, 5) Chip enable to output in low Z Chip disable to output in high Z (3, 4, 5) Chip enable to power up time(4) Chip disable to power down time tOH 3 3 3 3 3 ns tLZCE 5 5 5 5 5 ns tHZCE tPU (4) Output enable access time Output enable to output in low Z(4, 5) Output disable to output in high Z (4, 5) 5 0 6 0 6 0 6 0 6 0 ns 7 8 10 12 15 ns tAOE 5 5 5 6 8 ns tHZOE 0 0 5 0 6 0 6 0 6 10 ns tPD tLZOE 9 11 ns 6 ns 12 SHADED AREA = PRELIMINARY DATA. Notes referenced are after Data Retention Table. Rev. 4.4 - 4/29/98 5 PDM41256 Write Cycle No. 1 (Write Enable Controlled) t WC ADDR t AW t AH t CW CE t t WP AS WE t DH t DS DIN DATA VALID t HZWE t LZWE HIGH Z DOUT Write Cycle No. 2 (Chip Enable Controlled) t WC ADDR t AW tCW tAS CE t AH t WP UNDEFINED WE t DS DIN t DH DON'T CARE DATA VALID AC Electrical Characteristics -7(6) Description WRITE Cycle Sym -8(6) -10(6) -12 -15 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units WRITE cycle time tWC 7 8 10 12 15 ns Chip enable to end of write tCW 7 8 10 10 12 ns Address valid to end of write tAW 7 8 10 10 12 ns Address setup time tAS 0 0 0 0 0 ns Address hold from end of write tAH 0 0 0 0 0 ns Write pulse width tWP 7 8 8 8 11 ns Data setup time tDS 6 7 7 7 7 ns ns Data hold time tDH 0 0 0 0 0 Write disable to output in low Z(4, 5) tLZWE 0 0 0 0 0 Write enable to output in high Z(4, 5) tHZWE 3 3 3 3 ns 3 ns SHADED AREA = PRELIMINARY DATA 6 Rev. 4.4 - 4/29/98 PDM41256 Low VCC Data Retention Waveform 1 Data Retention Mode V CC 4.5V 4.5V VDR t CDR VIH CE V IL 2 tR VDR 3 DON'T CARE 4 5 Data Retention Electrical Characteristics (LA Version Only) Symbol Parameter VDR VCC for Retention Data ICCDR Data Retention Current tCDR Chip Deselect to Data Retention Time tR(4) Operation Recovery Time Test Conditions CE ≥ VCC – 0.2V VIN ≥ VCC – 0.2V or ≤ 0.2V Min. Typ. Max. Unit 2 — — V VCC = 2V — 95 500 µA VCC = 3V — 350 750 µA 0 — — ns tRC — — ns 6 7 NOTES: (For three previous Electrical Characteristics tables) 1. The device is continuously selected. Chip Enable is held in its active state. 2. The address is valid prior to or coincident with the latest occuring Chip Enable. 3. At any given temperature and voltage condition, tHZCE is less than tLZCE. 4. This parameter is sampled. 5. The parameter is tested with CL = 5 pF as shown in Figure 2. Transition is measured ±200 mV from steady state voltage 6. Vcc = 5V ± 5%. 8 9 10 11 12 Rev. 4.4 - 4/29/98 7 PDM41256 Ordering Information XXXXX X Device Type Power XX Speed X X X Package Type Process Temp. Range Preferred Shipping Container Blank Tubes TR Tape & Reel TY Tray Blank Commercial (0° to +70°C) I Industrial (–40°C to +85°C) A Automotive ( –40°C to +105°C) SO T 28-pin 300-mil Plastic SOJ 28-pin Plastic TSOP (I) Commercial Only 7 8 10 12 15 (use 15ns for slower designs) SA LA Standard Power Low Power PDM41256- 256K (32Kx8) Static RAM Faster Memories for a Faster World ™ 8 Rev. 4.4 - 4/29/98