Revised May 2005 MM74HC245A Octal 3-STATE Transceiver General Description Features The MM74HC245A 3-STATE bidirectional buffer utilizes advanced silicon-gate CMOS technology, and is intended for two-way asynchronous communication between data buses. It has high drive current outputs which enable high speed operation even when driving large bus capacitances. This circuit possesses the low power consumption and high noise immunity usually associated with CMOS circuitry, yet has speeds comparable to low power Schottky TTL circuits. ■ Typical propagation delay: 13 ns ■ Wide power supply range: 2–6V ■ Low quiescent current: 80 PA maximum (74 HC) ■ 3-STATE outputs for connection to bus oriented systems ■ High output drive: 6 mA (minimum) ■ Same as the 645 This device has an active LOW enable input G and a direction control input, DIR. When DIR is HIGH, data flows from the A inputs to the B outputs. When DIR is LOW, data flows from the B inputs to the A outputs. The MM74HC245A transfers true data from one bus to the other. This device can drive up to 15 LS-TTL Loads, and does not have Schmitt trigger inputs. All inputs are protected from damage due to static discharge by diodes to VCC and ground. Ordering Code: Order Number Package Number MM74HC245AWM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC245ASJ MM74HC245AMTC MM74HC245AN MTC20 N20A Package Description 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table Pin Assignments for DIP, SOIC, SOP and TSSOP Control Inputs G Operation DIR L L B data to A bus L H A data to B bus H X Isolation H HIGH Level L LOW Level X Irrelevant Top View © 2005 Fairchild Semiconductor Corporation DS005165 www.fairchildsemi.com MM74HC245A Octal 3-STATE Transceiver September 1983 MM74HC245A Logic Diagram www.fairchildsemi.com 2 Recommended Operating Conditions Supply Voltage (VCC) DC Input Voltage DIR and G pins (VIN) DC Input/Output Voltage (VIN , VOUT) Clamp Diode Current (ICD) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) 0.5 to 7.0V 1.5 to VCC 1.5V 0.5 to VCC 0.5V r20 mA r35 mA r70 mA 65qC to 150qC Supply Voltage (VCC) 600 mW S.O. Package only 500 mW (VIN, VOUT) Operating Temperature Range (TA) (tr, tf) Symbol VIH VIL VOH Parameter VCC V 85 qC VCC 2.0V 1000 ns VCC 4.5V 500 ns VCC 6.0V 400 ns Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package: 12 mW/qC from 65qC to 85qC. VCC TA 25qC Typ TA 40 to 85qC TA 55 to 125qC Guaranteed Limits Units Minimum HIGH Level Input 2.0V 1.5 1.5 1.5 V Voltage 4.5V 3.15 3.15 3.15 V V 6.0V 4.2 4.2 4.2 Maximum LOW Level Input 2.0V 0.5 0.5 0.5 V Voltage 4.5V 1.35 1.35 1.35 V 6.0V 1.8 1.8 1.8 V Minimum HIGH Level Output VIN Voltage |IOUT| d 20 PA VIH or VIL 2.0V 2.0 1.9 1.9 1.9 V 4.5V 4.5 4.4 4.4 4.4 V 6.0V 6.0 5.9 5.9 5.9 V |IOUT| d 6.0 mA 4.5V 4.2 3.98 3.84 3.7 V |IOUT| d 7.8 mA 6.0V 5.7 5.48 5.34 5.2 V VIH or VIL Maximum LOW Level Output VIN Voltage |IOUT| d 20 PA Input Leakage VIH or VIL 2.0V 0 0.1 0.1 0.1 V 4.5V 0 0.1 0.1 0.1 V 6.0V 0 0.1 0.1 0.1 V |IOUT| d 6.0 mA 4.5V 0.2 0.26 0.33 0.4 V |IOUT| d 7.8 mA 6.0V 0.2 0.26 0.33 0.4 V VIN 6.0V r0.1 r1.0 r1.0 PA 6.0V r0.5 r5.0 r10 PA 6.0V 8.0 80 160 PA VIN IIN 0 40 (Note 4) Conditions VIN VOL V Note 1: Maximum Ratings are those values beyond which damage to the device may occur. 260qC DC Electrical Characteristics Units 6 Input Rise/Fall Times Lead Temperature (TL) (Soldering 10 seconds) Max 2 DC Input or Output Voltage Power Dissipation (PD) (Note 3) Min VIH or VIL VCC to GND Current (G and DIR) IOZ ICC Maximum 3-STATE Output VOUT Leakage Current Enable G Maximum Quiescent Supply VIN Current IOUT VCC or GND VIH VCC or GND 0 PA Note 4: For a power supply of 5V r10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. 3 www.fairchildsemi.com MM74HC245A Absolute Maximum Ratings(Note 1) (Note 2) MM74HC245A AC Electrical Characteristics VCC 25qC, tr 5V, TA Symbol tf 6ns Parameter Conditions Guaranteed Typ Units Limit tPHL, tPLH Maximum Propagation Delay CL 45 pF 12 17 ns tPZH, tPZL Maximum Output Enable RL 1 k: 24 35 ns Time CL 45 pF Maximum Output Disable RL 1 k: 18 25 ns Time CL 5 pF tPHZ, tPLZ AC Electrical Characteristics VCC 2.0V to 6.0V, CL Symbol 50 pF, tr tf 6ns (unless otherwise specified) Parameter Conditions VCC TA 25qC Typ TA 40 to 85qC TA 55 to 125qC Units Guaranteed Limits tPHL, Maximum Propagation CL 50 pF 2.0V 31 90 113 135 ns tPLH Delay CL 150 pF 2.0V 41 96 116 128 ns CL 50 pF 4.5V 13 18 23 27 ns CL 150 pF 4.5V 17 22 28 33 ns CL 50 pF 6.0V 11 15 19 23 ns CL 150 pF 6.0V 14 19 23 28 ns tPZH, Maximum Output Enable RL 1 k: tPZL Time CL 50 pF 2.0V 71 190 240 285 ns CL 150 pF 2.0V 81 240 300 360 ns CL 50 pF 4.5V 26 38 48 57 ns CL 150 pF 4.5V 31 48 60 72 ns CL 50 pF 6.0V 21 32 41 48 ns CL 150 pF 6.0V 25 41 51 61 ns tPHZ, Maximum Output Disable RL 1 k: 2.0V 39 135 169 203 ns tPLZ Time CL 50 pF 4.5V 20 27 34 41 ns ns tTLH, tTHL Output Rise and Fall Time CL 50 pF 6.0V 18 23 29 34 2.0V 20 60 75 90 ns 4.5V 6 12 15 18 ns 5 10 13 15 6.0V CPD Power Dissipation G VIL Capacitance (Note 5) G VIH 50 ns pF 5 pF CIN Maximum Input Capacitance 5 10 10 10 pF CIN/OUT Maximum Input/Output 15 20 20 20 pF Capacitance, A or B Note 5: CPD determines the no load dynamic power consumption, PD CPD VCC2 fICC VCC, and the no load dynamic current consumption, IS CPD VCC fICC. www.fairchildsemi.com 4 MM74HC245A Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com MM74HC245A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 MM74HC245A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.com MM74HC245A Octal 3-STATE Transceiver Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8