Revised June 2005 SSTV16857 • SSTVN16857 14-Bit Register with SSTL-2 Compatible I/O and Reset General Description Features The SSTV16857 is a 14-bit register designed for use with 184 and 232 pin PC1600, 2100, and 2700 DDR DIMM applications. The SSTVN16857 is a 14-bit register designed for use with 184 and 232 pin PC3200 DDR DIMM applications. These devices have a differential input clock, SSTL-2 compatible data inputs and a LVCMOS compatible RESET input. These devices have been designed for compliance with the JEDEC DDR module and register specifications. ■ Compliant with DDR-I registered module specifications ■ Operates at 2.5V r 0.2V VDD ■ SSTL-2 compatible input and output structure ■ Differential SSTL-2 compatible clock inputs ■ Low power mode when device is reset ■ Industry standard 48 pin TSSOP package The devices are fabricated on an advanced submicron CMOS process and are designed to operate at power supplies of less than 3.6V’s. Ordering Code: Package Number Package Description SSTV16857MTD Order Number MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide SSTVN16857MTD (Preliminary) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Name Description Q1-Q14 SSTL-2 Compatible Output D1-D14 SSTL-2 Compatible Inputs RESET Asynchronous LVCMOS Reset Input CK Positive Master Clock Input CK Negative Master Clock Input VREF Voltage Reference Pin for SSTL Level Inputs VDDQ Power Supply Voltage for Output Signals VDD Power Supply Voltage for Inputs Truth Table RESET Dn CK CK Qn L X or Floating X or Floating X or Floating L H L H H n n p p L H H X L H Qn H X H L Qn L Logic LOW H Logic HIGH X Don’t Care, but not floating unless noted n LOW-to-HIGH Clock Transition p HIGH-to-LOW Clock Transition © 2005 Fairchild Semiconductor Corporation DS500387 www.fairchildsemi.com SSTV16857 • SSTVN16857 14-Bit Register with SSTL-2 Compatible I/O and Reset September 2000 SSTV16857 • SSTVN16857 Functional Description RESET is removed, the system designer must insure the clock and data inputs to the device are stable during the rising transition of the RESET signal. The SSTV16857 and SSTVN16587 are 14-bit registers with SSTL-2 compatible inputs and outputs. Input data is captured by the register on the positive edge crossing of the differential clock pair. The SSTL-2 data inputs transition based on the value of VREF. VREF is a stable system reference used for setting the trip point of the input buffers of the SSTV16857/ SSTVN16857 and other SSTL-2 compatible devices. When the LV-CMOS RESET signal is asserted LOW, all outputs and internal registers are asynchronously placed into the LOW logic state. In addition, the clock and data differential comparators are disabled for power savings. Output glitches are prevented by disabling the internal registers more quickly than the input comparators. When The RESET signal is a standard CMOS compatible input and is not referenced to the VREF signal. Logic Diagram www.fairchildsemi.com 2 Supply Voltage (VDDQ) Supply Voltage (VDD) Reference Voltage (VREF) Input Voltage (VI) Recommended Operating Conditions (Note 3) 0.5V to 3.6V 0.5V to 3.6V 0.5V to 3.6V 0.5V to VDD 0.5V Power Supply (VDDQ) Output Voltage (VO) SSTV16857 2.3V to 2.7V SSTVN16857 2.5V to 2.7V Power Supply (VDD) Outputs Active (Note 2) 0.5V to VDDQ 0.5V Operating Range DC Input Diode Current (IIK) VI 0V 50 mA 50 mA VI ! VDD DC Output Diode Current (IOK) VO ! VDD SSTV16857 1.15 to 1.35 SSTVN16857 1.25 to 1.35 50 mA 50 mA Input Voltage VREF r 40 mV r50 mA Output Current IOH/IOL 0V to VDD Output Voltage (VO) DC Output Source/Sink Current Output in Active States (IOH/IOL) DC VDD or Ground Current Storage Temperature Range (Tstg) VDDQ/2) Termination Voltage (VTT) VO 0V per Supply Pin (IDD or Ground) VDDQ to 2.7V Reference Supply (VREF r100 mA 65qC to 150qC 0V to VDDQ VDD 2.3V to 2.7V SSTV16857 VDD 2.5V to 2.7V SSTVN16857 Free Air Operating Temperature (TA) r20 mA r20 mA 0qC to 70qC Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the “Electrical Characteristics” table are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: IO Absolute Maximum Rating must be observed. Note 3: The RESET input of the device must be held at VDD or GND to ensure proper device operation. The differential inputs must not be floating, unless RESET is asserted LOW. DC Electrical Characteristics (SSTV16857) (2.3V d VDD d 2.7V) Symbol Parameter Conditions VDD (V) Min Max Units VIKL Input LOW Clamp Voltage II 18 mA 2.3 1.2 V VIKH Input HIGH Clamp Voltage II 18 mA 2.3 3.5 V VREF310mV VIH-AC AC HIGH Level Input Voltage Data Inputs VIL-AC AC LOW Level Input Voltage Data Inputs VIH-DC DC HIGH Level Input Voltage Data Inputs VIL-DC DC LOW Level Input Voltage Data Inputs VIH HIGH Level Input Voltage RESET VIL LOW Level Input Voltage RESET VICR Common Mode Input Voltage Range CLK, CLK 0.97 VI(PP) Peak to Peak Input Voltage CLK, CLK 360 VOH HIGH Level Output Voltage IOH 100 PA 2.3 to 2.7 VDD 0.2 IOH 16 mA 2.3 1.95 IOL 100 PA 2.3 to 2.7 0.2 IOL 16 mA 2.3 0.35 2.7 r5.0 PA 10 PA 25 mA VOL LOW Level Output Voltage VREF150mV VREF150mV Input Leakage Current VI Static Standby RESET VDD or GND GND, IO Static Operating RESET VDD, IO 0 0 VIH(AC) or VIL(AC) 3 V V 0.7 II V V 1.7 IDD VI V VREF310mV 1.53 V V mV V V 2.7 www.fairchildsemi.com SSTV16857 • SSTVN16857 Absolute Maximum Ratings(Note 1) SSTV16857 • SSTVN16857 DC Electrical Characteristics (SSTV16857) Symbol Parameter Conditions (Continued) VDD Min Max Units 90 PA/MHz 15 PA/MHz (V) IDDD Dynamic Operating Current RESET Clock Only VI VDD, IO 0 VIH(AC) or VIL(AC) CK, CK Duty Cycle 50% Dynamic Operating Current RESET per Data Input VI VDD, IO 0 2.7 VIH(AC) or VIL(AC) CK, CK Duty Cycle 50% Data Input ½ Clock Rate 50% Duty Cycle ROH Output HIGH On Resistance IOH 20 mA 2.3 to 2.7 7 20 : ROL Output LOW On Resistance IOL 20 mA 2.3 to 2.7 7 20 : RO' | ROH - ROL | IO 4 : Max Units 20 mA, TA 25qC 2.5 DC Electrical Characteristics (SSTVN16857) (2.5V d VDD d 2.7V) Symbol Parameter Conditions VDD (V) Min VIKL Input LOW Clamp Voltage II 18 mA 2.5 1.2 V VIKH Input HIGH Clamp Voltage II 18 mA 2.5 3.5 V VIH-AC AC HIGH Level Input Voltage Data Inputs VIL-AC AC LOW Level Input Voltage Data Inputs VIH-DC DC HIGH Level Input Voltage Data Inputs VREF310mV V VREF310mV VREF150mV V V VREF150mV VIL-DC DC LOW Level Input Voltage Data Inputs VIH HIGH Level Input Voltage RESET VIL LOW Level Input Voltage RESET VICR Common Mode Input Voltage Range CLK, CLK 0.97 VI(PP) Peak to Peak Input Voltage CLK, CLK 360 VOH HIGH Level Output Voltage IOH 100 PA 2.5 to 2.7 VDD 0.2 IOH 16 mA 2.5 1.95 IOL 100 PA 2.5 to 2.7 0.2 IOL 16 mA 2.5 0.35 2.7 r5.0 PA 10 PA 25 mA 90 PA/MHz 15 PA/MHz VOL LOW Level Output Voltage 1.7 0.7 II Input Leakage Current VI IDD Static Standby RESET GND, IO Static Operating RESET VDD, IO VI IDDD VDD or GND 0 0 Dynamic Operating Current RESET VI VDD, IO 1.53 V V mV V V 2.7 VIH(AC) or VIL(AC) Clock Only V V 0 VIH(AC) or VIL(AC) CK, CK Duty Cycle 50% Dynamic Operating Current RESET per Data Input VI VDD, IO 0 2.7 VIH(AC) or VIL(AC) CK, CK Duty Cycle 50% Data Input ½ Clock Rate 50% Duty Cycle ROH Output HIGH On Resistance IOH 20 mA 2.5 to 2.7 7 20 : ROL Output LOW On Resistance IOL 20 mA 2.5 to 2.7 7 20 : RO' | ROH - ROL | IO 4 : www.fairchildsemi.com 20 mA, TA 25qC 4 2.5 TA Symbol VDD Parameter 0qC to 70qC, CL 30 pF, RL 50: 2.5V r 0.2V; VDDQ 2.5V r 0.2V Min Max Units fMAX Maximum Clock Frequency 200 MHz tW Pulse Duration, CK, CK HIGH or LOW (Figure 2) 2.5 ns tACT Differential Inputs Activation Time, (Note 5) data inputs must be LOW after RESET HIGH (Figure 3) 22 ns tINACT Differential Inputs De-activation Time, (Note 5) data and clock inputs must be held at valid levels 22 ns (not floating) after RESET LOW tS tH Setup Time, Fast Slew Rate (Note 6)(Note 7) (Figure 5) 0.65 Setup Time, Slow Slew Rate (Note 7)(Note 8) (Figure 5) 0.9 Hold Time, Fast Slew Rate (Note 6)(Note 8) (Figure 5) 0.75 Hold Time, Slow Slew Rate (Note 7)(Note 8) (Figure 5) 0.9 tREM Reset Removal Time (Figure 7) 10 tPHL, tPLH Propagation Delay CLK, CLK to Qn (Figure 4) 1.1 tPHL tSK(Pn-Pn) ns ns ns 2.8 ns Propagation Delay RESET to Qn (Figure 6) 5.0 ns Output to Output Skew 200 ps Note 4: Refer to Figure 1 through Figure 7. Note 5: This parameter is not production tested. Note 6: For data signal input slew rate t 1 V/ns. Note 7: For data signal input slew rate t 0.5 V/ns and 1 V/ns. Note 8: For CK, CK signals input slew rates are t 1 V/ns. AC Electrical Characteristics (SSTVN16857) (Note 9) TA Symbol VDD Parameter 0qC to 70qC, CL 30 pF, RL 50: 2.5V r 0.2V; VDDQ 2.5V r 0.2V Min Max Units fMAX Maximum Clock Frequency 220 MHz tW Pulse Duration, CK, CK HIGH or LOW (Figure 2) 2.5 ns tACT Differential Inputs Activation Time, (Note 5) data inputs must be LOW after RESET HIGH (Figure 3) 22 ns 22 ns tINACT Differential Inputs De-activation Time, (Note 5) Data and Clock Inputs must be held at valid levels (not floating) after RESET LOW tS tH Setup Time, Fast Slew Rate (Note 9)(Note 12) (Figure 5) 0.65 Setup Time, Slow Slew Rate (Note 12)(Note 13) (Figure 5) 0.75 Hold Time, Fast Slew Rate (Note 11)(Note 13) (Figure 5) 0.75 ns ns Hold Time, Slow Slew Rate (Note 12)(Note 13) (Figure 5) 0.9 tREM Reset Removal Time (Figure 7) 10 tPHL, tPLH Propagation Delay CLK, CLK to Qn (Figure 4) 1.1 tPSS Propagation Delay Simultaneous Switching CLK, CLK to Qn (Note 14) 2.7 ns tPHL Propagation Delay RESET to Qn (Figure 6) 5.0 ns tSK(Pn-Pn) Output to Output Skew 200 ps ns 2.4 ns Note 9: Refer to Figure 1 through Figure 7. Note 10: This parameter is not production tested. Note 11: For data signal input slew rate t 1 V/ns. Note 12: For data signal input slew rate t 0.5 V/ns and 1 V/ns. Note 13: For CK, CK signals input slew rates are t 1 V/ns. Note 14: Simultaneous Switching is guaranteed by characterization. 5 www.fairchildsemi.com SSTV16857 • SSTVN16857 AC Electrical Characteristics (SSTV16857) (Note 4) SSTV16857 • SSTVN16857 Capacitance (Note 15) Symbol CIN Note 15: TA Max Units Data Pin Input Capacitance Parameter 2.0 3.0 pF VDD 2.5V, VI CK, CK - Input Capacitance 2.5 3.5 pF VDD 2.5V, VICR RESET 2.5 3.5 pF VDD 2.5V, VI 25qC, f Min Typ Conditions VREF r 350 mV 1.25V, VI(PP) 360 mV VDD to GND 1 MHz, Capacitance is characterized but not tested. AC Loading and Waveforms (See Notes A through F below) Note: CL includes probe and jog capacitance FIGURE 2. Voltage Waveforms - Pulse Duration FIGURE 1. AC Test Circuit Note: IDD tested with clock and data inputs held at VDD or GND, and IO 0 mA. FIGURE 3. Voltage and Current Waveforms Inputs Active and Inactive Times FIGURE 4. Voltage Waveforms Propagation Delay Times FIGURE 5. Voltage Waveforms - Setup and Hold Times FIGURE 6. Voltage Waveforms RESET Propagation Delay Times Note A: All input pulses are supplied by generators having the following characteristics: PRR d 10 MHz, Z0 50:, input slew rate 1V/ns r 20% (unless otherwise specified). Note B: The outputs are measured one at a time with one transition per measurement. Note C: VTT VREF VDD/2. Note D: VIH VREF 310 mV (AC voltage levels) for differential inputs. VIH VDD for LVCMOS input. Note E: VIL VREF 310 mV (AC voltage levels) for differential inputs. VIL GND for LVCMOS input. Note F: Removal time (tREM) is tested with one data input held active HIGH. The propagation time from CK to the corresponding output must meet valid timing specifications for the measurement to be accurate. FIGURE 7. Voltage Waveforms RESET Removal Delay Times www.fairchildsemi.com 6 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com SSTV16857 • SSTVN16857 14-Bit Register with SSTL-2 Compatible I/O and Reset 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48