Dual Input Network Clock
Generator/Synchronizer
AD9549
Preliminary Technical Data
FEATURES
APPLICATIONS
Flexible Reference Inputs
Input frequencies 8 kHz to 750 MHz
Two reference inputs
Loss of Reference indicators
Auto and Manual Holdover modes
Auto and Manual Switchover modes
Smooth A to B phase transition on outputs
Excellent stability in holdover mode
Programmable 16+1-bit Input Divider, R
Differential HSTL Clock Output
Output frequencies to 750 MHz
Low Jitter clock doubler for frequencies > 400 MHz
Single-ended CMOS output; frequencies < 50MHz
Programmable Digital Loop Filter (< 1 Hz to ~100 kHz)
High Speed Digitally Controlled Oscillator (DCO) core
DDS with integrated 14 bit DAC
Excellent Dynamic Performance
Programmable 16+1-bit Feedback Divider, S
Software controlled power-down
64-lead LFCSP package
Network Synchronization
Reference Clock Jitter Cleanup
SONET/SDH Clocks up to OC-192, Including FEC
Stratum 3/3E Reference Clocks
Wireless Base Stations, Controllers
Cable Infrastructure
Data Communications
GENERAL DESCRIPTION
The AD9549 provides synchronization for many systems
including synchronous optical networks (SONET/SDH). The
AD9549 generates an output clock, synchronized to one of two
external input references. The external references may contain
significant time jitter, also specified as phase noise. Using a
digitally controlled loop and holdover circuitry, the AD9549
continues to generate a clean (low jitter), valid output clock
during a ‘loss of reference’ condition, even when both references
have failed.
The AD9549 operates over an industrial temperature range,
spanning -40°C to +85°C.
Figure 1: Basic Block Diagram
Rev. PrA
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Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
AD9549
Preliminary Technical Data
SAMPLE APPLICATION CIRCUIT
Figure 2: AD9549 + AD9514 Precision Clock Distribution Circuit
Features:
Input Frequencies Down to 8 kHz. Output Frequencies Up to 400 MHz.
Programmable Loop Bandwidth Down to < 1 Hz
Automatic Redundant Clock Switchover with User Selectable Rate of Phase Adjustment.
Automatic Stratum 2/3/3E Clock Holdover, Depending on Configuration.
Phase Noise (Fc=122.3 MHz & 100 Hz loop BW): 100 Hz offset: -107 dBc/Hz. 1 KHz offset: -142 dBc/Hz. 100 kHz offset: -157 dBc/Hz.
Two Zero-delay Outputs with Programmable Post-Divider and Synchronization.
Two Additional Outputs (non-zero delay) on AD9549.
Programmable Skew Adjustment on One AD9514 Output.
Rev. PrA | Page 2 of 78
Preliminary Technical Data
AD9549
TABLE OF CONTENTS
Features...............................................................................................1
Phase Lock Detection.............................................................31
Applications .......................................................................................1
Frequency Lock Detection ....................................................32
General Description..........................................................................1
Reference Monitors ....................................................................33
Sample Application Circuit..............................................................2
Loss of Reference ....................................................................33
DC Specifications ..............................................................................5
Reference Frequency Monitor...............................................33
AC Specifications ..............................................................................7
Reference Switchover .................................................................34
Typical Performance Characteristics ............................................13
Use of Line Card Mode to Eliminate Runt Pulses..............35
Absolute Maximum Ratings ..........................................................17
Holdover ......................................................................................36
ESD Caution ................................................................................17
Holdover Control....................................................................36
Pin Configuration and Function Descriptions ...........................18
Holdover & Reference Switchover State Machine..............36
Input / Output Termination Recommendations.........................21
Reference Recovery Timers...................................................37
Theory of Operation .......................................................................22
Holdover Operation ...............................................................38
Overview ......................................................................................22
Holdover Sampler and Averager...........................................39
PLL Core (DPLLC) .....................................................................23
Output Frequency Range Control ............................................39
Feedforward Divider (Divide-by-R).....................................23
Reconstruction Filter..................................................................39
Feedback Divider (Divide-by-S) ...........................................23
Use of Narrowband Filter for High Performance...............40
Forward and Reverse FEC Clock Scaling ............................24
FDBK Inputs................................................................................41
Phase Detector.........................................................................24
Reference Inputs .........................................................................41
Digital Loop Filter...................................................................24
Reference Clock Receiver ......................................................41
Direct Digital Synthesizer ......................................................26
SysClk Inputs...............................................................................42
DAC Output.............................................................................27
Functional Description ..........................................................42
Phase Detector.............................................................................27
Bipolar Edge Detector ............................................................42
Coarse Phase Detector ...........................................................27
SysClk PLL Multiplier ............................................................42
Fine Phase Detector................................................................27
External Loop Filter (SysClk PLL) .......................................43
Phase Detector Gain Matching .............................................28
Detail of SysClk Differential Inputs .....................................43
Phase Detector Pin Connections ..........................................28
Harmonic Spur Reduction.........................................................45
Digital Loop Filter Coefficients ................................................28
Output Clock Drivers & 2x frequency Multiplier ..................46
Closed Loop Phase Offset..........................................................30
Primary 1.8V Differential HSTL Driver..............................46
Lock Detection ............................................................................31
2x Frequency Multiplier.........................................................46
Rev. PrA | Page 3 of 78
AD9549
Preliminary Technical Data
Single-Ended CMOS Output................................................ 46
Read ......................................................................................... 54
Frequency Slew Limiter............................................................. 46
The Instruction Word (16 Bits)................................................ 54
Frequency Estimator.................................................................. 47
MSB/LSB First Transfers ........................................................... 54
Status and Warnings .................................................................. 48
I/O Register Map ............................................................................ 58
1
Status Pins ............................................................................... 48
Types of Registers:................................................................ 65
Reference Monitor Status ...................................................... 49
I/O Register Description ............................................................... 66
Default DDS Output Frequency on Power-Up .................. 49
Serial Port Configuration (0000 – 0005)............................. 66
Interrupt Request (IRQ)........................................................ 49
Power Down and Reset ......................................................... 66
Power-On Reset.......................................................................... 51
System Clock........................................................................... 67
AD9549 Power Up and Programming Sequence................... 51
Digital PLL Control and Dividers........................................ 68
Power Management........................................................................ 52
Digital PLL Loop Filter.......................................................... 69
3.3V Supplies............................................................................... 52
Free-Run (Single-Tone) Mode.............................................. 70
1.8V Supplies............................................................................... 52
Reference Selector / Holdover .............................................. 70
Serial Control Port.......................................................................... 53
Doubler and Output Drivers ................................................ 71
Serial Control Port Pin Descriptions....................................... 53
Monitor.................................................................................... 72
Operation of Serial Control Port.............................................. 53
Calibration (User Accessible Trim) ..................................... 75
Framing a Communication Cycle with CSB ...................... 53
Harmonic Spur Reduction.................................................... 77
Communication Cycle—Instruction Plus Data ................. 53
Outline Dimensions ....................................................................... 78
Write......................................................................................... 53
Ordering Guide............................................................................... 78
Rev. PrA | Page 4 of 78
Preliminary Technical Data
AD9549
DC SPECIFICATIONS
Unless otherwise noted, AVDD=1.8±5%, AVDD3=3.3±5%, DVDD=1.8±5%, DVDD_I/O=3.3±5%.
Table 1.
Parameter
SUPPLY VOLTAGE
DVDD_I/O (pin 1)
DVDD (pin 3, 5, 7)
AVDD3 (pin 14, 46, 47, 49)
AVDD3 (pin 37)
AVDD (pin 11,19, 23-26,29,30,36,42,44,45,53)
SUPPLY CURRENT
I-AVDD3 (pin 14)
I-AVDD3 (pin 37)
I-AVDD3 (pin 46, 47, 49)
I-AVDD (pin 36)
I-AVDD (pin 42)
I-AVDD (pin 11)
I-AVDD (pin 19, 23-26, 29, 30, 44, 45)
I-AVDD (pin 53)
I-DVDD (pin 3, 5, 7)
I-DVDD_I/O (pin 1)
LOGIC INPUTS (Except Pin 32)
Input High Voltage (VIH)
Input Low Voltage (VIL)
Input Current (IINH, IINL)
Maximum Input Capacitance (CIN)
CLKMODESEL (Pin 32) LOGIC INPUT
Input High Voltage (VIH)
Input Low Voltage (VIL)
Input Current (IINH, IINL)
Maximum Input Capacitance (CIN)
LOGIC OUTPUTS
Output High Voltage (VOH)
Output Low Voltage (VOL)
REFERENCE INPUTS
Input Capacitance
Input Resistance
Common Mode Input Voltage1
Differential Input Voltage Swing1
Input Voltage High (VIH)
Input Voltage Low (VIL)
Input Current
Internal Bias Voltage
FDBK INPUT
Input Capacitance
Input Resistance
Common Mode Input Voltage2
Differential Input Voltage Swing2
Min
Typ
Max
Unit
3.135
1.71
3.135
1.71
1.71
3.30
1.80
3.30
3.30
1.80
3.465
1.89
3.465
3.465
1.89
V
V
V
V
V
6
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
0.8
±100
V
V
µA
pF
0.4
±100
V
V
µA
pF
25
8
10
10
170
35
200
3
2.0
±30
3
Test Conditions/Comments
(with respect to DVSS)
(with respect to DVSS)
(with respect to AVSS)
(with respect to AVSS)
(with respect to AVSS)
REFA, REFB Buffers
CMOS Output Clock Driver at 3.3V
DAC output current source
HSTL Output Clock Driver
FDBK
SYSCLK
aggregate analog supply
DAC Power Supply
Digital Core
Digital I/O (varies dynamically)
Pins 56-61, 64, 9, 10, 54, 55, 63
At Vin=0V and Vin=DVDD_I/O
Pin 32 only.
1.4
±30
3
2.7
0.4
3
16
AVDD31600
AVDD3800
AVDD3400
V
V
pF
KΩ
V
mV
V
V
mA
mV
At Vin=0V and Vin=DVDD_I/O
Pin 62, & bi-dir. pins 9, 10, 54, 55, 63
IOH = 1 mA w/ VOH =DVDD_I/O-0.4V
IOL = 1mA w/ VOL =0.4V
Pins 12, 13, 15, 16
Differential at Vbias=AVDD3-800mV
differential operation
differential operation
single-ended operation
single-ended operation
single-ended operation
programmable (see text)
Pins 40, 41
3
30
Rev. PrA | Page 5 of 78
pF
KΩ
V
mV
Differential
differential operation
differential operation
AD9549
SYSTEM CLOCK INPUT
SYSCLK PLL BYPASSED
Input Capacitance (DC)
Input Impedance (DC)
Common Mode Input Voltage3
Differential Input Voltage Swing3
Input Voltage High (VIH)
Input Voltage Low (VIL)
Input Current
SYSCLK PLL ENABLED
Input Capacitance (DC)
Input Impedance (DC)
Common Mode Input Voltage3
Differential Input Voltage Swing3
Input Voltage High (VIH)
Input Voltage Low (VIL)
Input Current
CRYSTAL RESONATOR WITH SYSCLK PLL ENABLED
Motional Resistance
CLOCK OUTPUT DRIVERS
HSTL OUTPUT DRIVER
Differential Output Voltage Swing4
Common Mode Output Voltage4
Continuous Output Current
CMOS OUTPUT DRIVER
Output Voltage High (VOH)
Output Voltage Low (VOL)
Output High Current (IOH)
Output Low Current (IOL)
TOTAL POWER DISSIPATION
All Blocks Running
Power-Down Mode
Preliminary Technical Data
1.5
1
pF
KΩ
single-ended, each pin
differential
differential operation
differential operation
single-ended operation
single-ended operation
single-ended operation
3
2
pF
KΩ
single-ended, each pin
differential
differential operation
differential operation
single-ended operation
single-ended operation
single-ended operation
kΩ
TBD
700
mV
TBD
0.9
7.2
V
mA
0.4
V
V
µA
µA
TBD
TBD
TBD
TBD
mW
mW
Default with SysClk PLL Enabled
TBD
TBD
mW
Default with SysClk PLL Disabled
TBD
TBD
mW
TBD
TBD
TBD
TBD
TBD
mW
mW
mW
mW
mW
- with Digital Power Down
- with REFA or REFB Power Down
- with HSTL Clock Driver Power Down
- with CMOS Clock Driver Power Down
- with HSTL 2x Freq. Multiplier Power
Down
Must be ≤ 0V relative to AVDD3 (pin 14) and ≥ 0V relative to AVSS (pins 33, 43).
Must be ≤ 0V relative to AVDD (pin 42) and ≥ 0V relative to AVSS (pins 33, 43).
Relative to AVSS (pins 33, 43).
4
Must be ≤ 0V relative to AVDD (pin 36) and ≥ 0V relative to AVSS (pins 33, 43).
5
See “Power Management” Section for details about power profiles.
1
2
3
Rev. PrA | Page 6 of 78
Both pins AC-coupled using 0.01uF,
then 50Ω to GND,
TBD
Using either the Power Down
Register or PWRDOWN pin.
After reset or power up with fS=1GHz,
S4=0, S1-S3=1, fSYSCLK=25MHz
After reset or power up with fS=1GHz,
S4-S4=1, & Sysclk PLL powered down.
One reference still powered up.
Preliminary Technical Data
AD9549
AC SPECIFICATIONS
Unless otherwise noted: fS=1GHz. DAC RSET=10KΩ. Power supply pins within the range specified in “DC SPECIFICATIONS.”
Table 2.
Parameter
REFERENCE INPUTS
Frequency Range
Minimum Slew Rate
Minimum Pulse Width High
Minimum Pulse Width Low
FDBK INPUT
Input Frequency Range
Min
Typ
.008
Max
Unit
750
MHz
V/ns
ps
ps
MHz
Minimum Slew Rate
Minimum Differential Input Level
SYSTEM CLOCK INPUT
SYSCLK PLL BYPASSED
Input Frequency Range
Minimum Pulse Width High
Minimum Pulse Width Low
Minimum Differential Input Level
SYSCLK PLL ENABLED
VCO Frequency Range – Low Band
VCO Frequency Range – High Band
Maximum Input Rate of PFD
Without Bipolar Edge Detector
Input Frequency Range
Multiplication Range
Minimum Pulse Width High
Minimum Pulse Width Low
Minimum Differential Input Level
With Bipolar Edge Detector
Input Frequency Range
Multiplication Range
Input Duty Cycle
Minimum Differential Input Level
CRYSTAL RESONATOR WITH SYSCLK PLL ENABLED
Crystal Resonator Frequency Range
Maximum Crystal Motional Resistance
V/ns
V
TBD
1000
MHz
ps
ps
V
700
800
850
1000
100
MHz
MHz
MHz
TBD
8
TBD
66
MHz
TBD
132
40+
TBD
Rev. PrA | Page 7 of 78
peak-to-peak (xxxdBm into 50Ω)
Pins 27, 28
peak-to-peak (xxxdBm into 50Ω)
peak-to-peak (xxxdBm into 50Ω)
MHz
integer multiples of 4
%
V
10
Pins 40, 41
sinusoidal (without degrading phase
noise performance)
integer multiples of 2
ps
ps
V
TBD
16
Test Conditions/Comments
Pins 12, 13, 15, 16
MHz
peak-to-peak (xxxdBm into 50Ω)
fundamental mode resonator
see text for recommendations
AD9549
CLOCK DRIVERS
HSTL OUTPUT DRIVER
Toggle Rate
Output Duty Cycle
Output Rise/Fall Time
JITTER
HSTL OUTPUT DRIVER WITH 2X MULTIPLIER
Output Frequency Range
Duty Cycle
Sub-harmonic Spur Level
JITTER
CMOS OUTPUT DRIVER (AVDD3/PIN 37) @3.3V
Toggle Rate
Duty Cycle
Output Rise/Fall Time
JITTER
CMOS OUTPUT DRIVER AT (AVDD3/PIN 37) @1.8V
Toggle Rate
Duty Cycle
Output Rise/Fall Time
JITTER
HOLDOVER
Frequency Accuracy (XTAL)
Variation Over Temperature range
Variation Over Supply range
Frequency Accuracy (TCXO)
Variation Over Temperature range
Variation Over Supply range
OUTPUT FREQUENCY SLEW LIMITER
Slew Rate Resolution
Slew Rate Range
REFERENCE MONITORS
LOSS OF REFERENCE MONITOR
Operating Frequency Range
Minimum Frequency Error for Continuous
“REF” Present” Indication
Minimum Frequency Error for Continuous
“REF” Present” Indication
Maximum Frequency Error for Continuous
“REF Lost” Indication
Maximum Frequency Error for Continuous
“REF Lost” Indication
REFERENCE QUALITY MONITOR
Operating Frequency Range
Frequency Resolution (normalized)
Frequency Resolution (normalized)
Preliminary Technical Data
TBD
48
725
52
TBD
0.6
TBD
45
TBD
55
-35
55
100
60
MHz
%
ps
ps
100Ω terminated, 5pF load
Fin=25 MHz, Fout=200 MHz
MHz
%
dBc
without correction
MHz
%
ps
see plot for maximum toggle rate
Fin=25 MHz, Fout=200 MHz
see plot for maximum toggle rate
With 20pF load and up to 50 MHz
Fin=25 MHz, Fout=50 MHz
55
50
60
MHz
%
ps
see plot for maximum toggle rate
With 20pF load and up to 50 MHz
Fin=25 MHz, Fout=50 MHz
xxxMHz, xxxppm crystal resonator at
SYSCLK pins
ppm/oC
ppm/V
TCXO at SYSCLK pins
0
0
ppm/oC
ppm/V
0.54
0
111
3x1016
Hz/sec
Hz/sec
7.63x103
167x106
-16
Hz
ppm
-19
%
-32
ppm
-35
%
0.001
16
ppm
0.002
44.9
%
VALIDATION TIMER
Rev. PrA | Page 8 of 78
P=216 for minimum; P=25 for maximum
P=216 for minimum; P=25 for maximum
fREF= 8 kHz
fREF= 155 MHz
fREF= 8 kHz
fREF= 155 MHz
fREF= 8 kHz; M=15 for minimum;
M=1 for maximum (see text)
fREF= 155 MHz; M=15 for minimum;
M=1 for maximum (see text)
Preliminary Technical Data
Timing range
Timing range
AD9549
32x10-9
65x10-6
137
2.8x105
Rev. PrA | Page 9 of 78
s
s
PIO= 5 (see text)
PIO= 16 (see text)
AD9549
DAC OUTPUT CHARACTERISTICS
DCO Frequency range (1st Nyquist zone)
Output Resistance
Output Capacitance
Full-Scale Output Current
Gain Error
Output Offset
Voltage Compliance Range
Preliminary Technical Data
10
450
50
5
10
TBD
AVSS
−0.50
+0.5V
31.7
TBD
0.6
AVSS
+0.50
MHz
Ω
pF
mA
%FS
µA
range depends on DAC RSET resistor
Outputs not DC shorted to Vss
Wideband SFDR (DC to Nyquist):
SFDR may be improved by activating
Harmonic Spur Suppression (see text)
10MHz Analog Out
40MHz Analog Out
80MHz Analog Out
120MHz Analog Out
160MHz Analog Out
Narrowband SFDR
10 MHz Analog Out (±1 MHz)
40 MHz Analog Out (±1 MHz)
80 MHz Analog Out (±1 MHz)
120 MHz Analog Out (±1 MHz)
160 MHz Analog Out (±1 MHz)
DIGITAL PLL
Minimum open-loop bandwidth
TBD
TBD
TBD
TBD
TBD
dBc
dBc
dBc
dBc
dBc
TBD
TBD
TBD
TBD
TBD
dBc
dBc
dBc
dBc
dBc
0.0001
kHz
Maximum open-loop bandwidth
100
kHz
Minimum phase margin
10
degrees
Maximum phase margin
85
degrees
PFD input frequency range
Feedforward divider ratio
Feedback divider ratio
LOCK DETECTION
PHASE LOCK DETECTOR
Time Threshold Programming Range
Time Threshold Resolution
Lock Time Programming Range
Unlock Time Programming Range
FREQUENCY LOCK DETECTOR
Normalized Frequency Threshold
Programming Range
Normalized Frequency Threshold
DPLL loop bandwidth sets lower limit
single-ended (each pin internally
terminated to AVSS)
~0.008
1
1
0
~24.5
131,070
131,070
MHz
2097
µs
ps
s
ms
0.488
32x10-9
64x10-6
68.7
16.8
0
0.0021
5x10-13
Rev. PrA | Page 10 of 78
dependent on the frequency of REFA/B,
the DAC sample rate, and the P, R, and S
divider values
dependent on the frequency of REFA/B,
the DAC sample rate, and the P, R, and S
divider values
dependent on the frequency of REFA/B,
the DAC sample rate, and the P, R, and S
divider values (not a hard limit but
bounded by 0°)
dependent on the frequency of REFA/B,
the DAC sample rate, and the P, R, and S
divider values (not a hard limit but
bounded by 90°)
1,2,..,65,535 or 2,4,..,131,070
1,2,..,65,535 or 2,4,..,131,070
FPFD_Gain=200
FPFD_Gain=200
in power-of-2 steps
in power-of-2 steps
FPFD_Gain=200; normalized to (fREF/R)2;
see text for details
FPFD_Gain=200; normalized to (fREF/R)2;
Preliminary Technical Data
Programming Resolution
Lock Time Programming Range
Unlock Time Programming Range
AD9549
32x10-9
64x10-6
68.7
16.8
Rev. PrA | Page 11 of 78
s
ms
see text for details
in power-of-2 steps
in power-of-2 steps
AD9549
Preliminary Technical Data
DIGITAL TIMING SPECIFICATIONS
Time Required to Enter Power Down
Time Req’d to Recover from Power Down
S0-4 Config Setup Time During Reset
ns
ns
ns
S0-4 Config Hold Time During Reset
ns
Reset assert to S0-4 High-Z Time
ns
Reset deassert to S0-4 Low-Z time
ns
CS to SCLK Setup Time
Period of SCLK
TDSU (Serial Data Setup Time)
TDHD (Serial Data Hold Time)
TDV (Data Valid Time)
PROPAGATION DELAY
FDBK to HSTL Output Driver
FDBK to HSTL Output Driver with 2x
Frequency Multiplier Enabled
FDBK to HSTL Output Driver with 2x
Frequency Multiplier Enabled
FDBK to CMOS Output Driver
FDBK through S-Divider to CMOS Output
Driver
TBD
10
TBD
TBD
TBD
ns
ns
ns
ns
ns
Rev. PrA | Page 12 of 78
Time S0-4 must be present before falling
edge of signal on RESET pin.
Time S0-4 must be held after falling edge
of signal on RESET pin.
Time from rising edge of RESET to High Z
on S0-4 configuration pins.
Time from falling edge of RESET to Low-Z
on S0-4 configuration pins.
Preliminary Technical Data
AD9549
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted: AVDD, AVDD3, and DVDD at nominal supply voltage; fS= 1 GHz, DAC RSET= 10kΩ.
Plot 1: Additive Phase Noise at HSTL Output Driver. Sysclk=1 GHz
(SysClk PLL Bypassed). Ref=19.44 MHz., Fout=311.04 MHz.
DPLL loop BW= 1 kHz.
Plot 2: Additive Phase Noise at HSTL Output Driver. Sysclk=1 GHz
(SysClk PLL Bypassed). Ref=19.44 MHz., Fout=622.08 MHz, DPLL
loop BW= 1 kHz. HSTL Output Doubler Enabled
Rev. PrA | Page 13 of 78
AD9549
Preliminary Technical Data
Plot 3: Additive Phase Noise at HSTL Output Driver. Sysclk = 1 GHz
(SysClk PLL Enabled and driven by 25 MHz Wenzel Oscillator.)
Ref=19.44 MHz., Fout=311.04 MHz, DPLL loop BW= 1 kHz.
Plot 5: Additive Phase Noise at HSTL Output Driver. Sysclk = 1 GHz.
(Sysclk PLL enabled and driven with 25MHz Wenzel Oscillator.)
Fin=19.44 MHz, Fout=155.52 MHz.
DPLL loop BW=1 kHz
Plot 4: Additive Phase Noise at HSTL Output Driver. Sysclk= 1 GHz
(SysClk PLL Enabled and driven by 25 MHz Wenzel Oscillator.).
Ref=19.44 MHz., Fout=622.08 MHz, DPLL loop BW= 1 kHz. HSTL
Doubler Enabled.
Rev. PrA | Page 14 of 78
Plot 6: Additive Phase Noise at HSTL Output Driver.
Sysclk = 500 MHz. Sysclk PLL disabled.
Fin=8 kHz, Fout= 155.52 MHz. DPLL loop BW= 400 Hz.
Preliminary Technical Data
AD9549
Plot 7: Additive Phase Noise at HSTL Output Driver. Sysclk = 1 GHz.
(Sysclk PLL enabled and driven with 25MHz Fox Crystal Oscillator.)
Fin=19.44 MHz, Fout=155.52 MHz.
DPLL loop BW=1 kHz.
Plot 9: SFDR vs Fout at Sysclk = 1GHz
with and w/o recon filter.
Fcut = Fout * 1.2
Plot 10: HSTL Output Amplitude vs. Toggle Rate
(100 ohms across differential pair.,)
Plot 8: Additive Phase Noise at CMOS Output Driver.
Sysclk= 500 MHz. Sysclk PLL disabled.
Fin=10.24 MHz, Fout=10.24 MHz.
DPLL loop BW=1 kHz
Rev. PrA | Page 15 of 78
AD9549
Preliminary Technical Data
AD9549 CMOS 1.8V Driver w/ 20pF Load: Amplitude vs. Frequency
Loaded with 20k Ohm Scope Probe
2.5
P k -P k ( V o lt s )
2.0
1.5
1.0
Nom Skew 25ºC 1.8V Supply DUT 2 (20pF)
0.5
Slow Skew 90ºC 1.7V Supply DUT 3 (20pF)
0.0
0
20
40
60
80
100
Output Frequency (MHz)
Plot 12: CMOS Output Driver Amplitude vs. Toggle Rate
(AVDD3 = 3.3V).
Plot 11: CMOS Output Driver Amplitude vs. Toggle Rate
(AVDD3 = 1.8 V) with 20 pF Load.
Rev. PrA | Page 16 of 78
Preliminary Technical Data
AD9549
ABSOLUTE MAXIMUM RATINGS
Table 1.
Parameter
Analog Supply Voltage (AVDD)
Digital Supply Voltage (DVDD)
Digital I/O Supply Voltage
(DVDD_I/0)
DAC Supply Voltage (DAC_VDD)
Maximum Digital Input Voltage
Storage Temperature
Operating Temperature Range
Lead Temperature Range
(Soldering 10 sec)
Junction Temperature
1
Thermal Resistance (ΘJA)
ESD CAUTION
Rating
2V
2V
3.6 V
3.6 V
−0.5 V to DVDD_I/O + 0.5 V
−65°C to +150°C
−40°C to +85°C
300°C
150°C
26°C/W typ.
ESD (electrostatic discharge)
sensitive device. Electrostatic
charges as high as 4000 V readily
accumulates on the human body
and test equipment and can
discharge without detection.
Although this product features
proprietary ESD protection circuitry,
permanent damage may occur on
devices subjected to high-energy
electrostatic discharges. Therefore,
proper ESD precautions are
recommended to avoid performance
degradation or loss of functionality.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other condition s above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
1
The exposed pad on bottom of package must be soldered to ground in
order to achieve the specified thermal performance.
Rev. PrA | Page 17 of 78
AD9549
Preliminary Technical Data
SCLK
SDIO
SDO
CSB
IO_UPDATE
RESET
PWRDOWN
HOLDOVER
REFSELECT
S4
S3
AVDD
AVSS
IOUTB
IOUT
AVDD3
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DVDD_I/O
DVSS
DVDD
DVSS
DVDD
DVSS
DVDD
DVSS
S1
S2
AVDD
REFA_IN
REFA_INB
AVDD3
REFB_IN
REFB_INB
N/C
N/C
AVDD
PFD_VRB
PFD_VRT
PFD_RSET
AVDD
AVDD
AVDD
AVDD
SYSCLK
SYSCLKB
AVDD
AVDD
LOOP_FILTER
CLKMODESEL
DAC_RSET
AVDD3
AVDD3
AVDD
N/C
AVSS
AVDD
FDBK_IN
FDBK_INB
AVSS
OUT_CMOS
AVDD3
AVDD
OUT
OUTB
AVSS
Figure 3: 64-Lead LFCSP Pin Configuration
Table 2: Pin Function Descriptions
Pin No.
1
2, 4, 6, 8
3, 5, 7
9, 10, 54,
55
11, 19, 2326, 29, 30,
36, 42, 45,
53
Input/
Output
I
I
I
I/O
I
Pin
Type
Power
Power
Power
3.3V
CMOS
Power
Mnemonic
Description
DVDD_I/O
DVSS
DVDD
S1, S2, S3, S4
I/O Digital Supply
Digital Ground: Connect to Ground
Digital Supply
Configurable I/O pins: These pins are configured under program control (see “Status and
Warnings” on Page 48.
Analog Supply: Connect to a nominal 1.8V Supply
AVDD
Rev. PrA | Page 18 of 78
Preliminary Technical Data
12
I
13
I
14, 37, 46,
47, 49
15
I
I
REFB_IN
16
I
REFB_INB
22
O
N/C
PFD_VRB,
PFD_VRT
PFD_RSET
27
28
31
I
I
32
I
1.8V
CMOS
CLKMODESEL
33, 39, 43,
52
34
I
GND
AVSS
O
OUTB
35
O
38
O
1.8V
HSTL
1.8V
HSTL
3.3V
CMOS
40
Diff
Input
Diff
Input
Power
17, 18
20, 21
I set
Res
REFA_IN
REFA_INB
AVDD3
SYSCLK
SYSCLKB
LOOP_FILTER
AD9549
Frequency/Phase Reference A Input. This internally biased input is typically AC-coupled,
and when configured as such, can accept any differential signal.
Complementary Frequency/Phase Reference A Input: Complementary signal to the
input provided on pin 12
Analog Supply: Connect to a nominal 3.3V supply
Frequency/Phase Reference B Input. This internally biased input is typically AC-coupled,
and when configured as such, can accept any differential signal whose single-ended
swing is between 0.4 and 3.3V.
Complementary Frequency/Phase Reference B Input: Complementary signal to the input
provided on pin 15
No Connects: These are excess, unused pins that may be left floating
These pins must be capacitively decoupled. See the Phase Detector Pin Connections
section for details.
Connect a 5kΩ resistor from this pin to Ground
(see the Phase Detector Pin Connections section).
System Clock Input
Complementary System Clock: Complementary signal to the input provided on pin 27
System Clock Multiplier Loop Filter: When using the frequency multiplier to drive the
System Clock, an external loop filter must be constructed and attached to this pin.
Clock Mode Select. Set to GND when using a crystal. Pull up to 1.8V when using either an
oscillator or external clock source. (See the SysClk Inputs section for details on the use of
this pin).
Analog Ground: Connect to Ground. NOTE: Pin 43 is a ground shield connection.
OUT
Complementary HSTL Output: See spec table and the OUTPUT DRIVERS AND
MULTIPLIER section, under sub heading Primary (Differential) Driver, for details
HSTL Output: See specification table and the CLOCK DRIVERS section
OUT_CMOS
CMOS Output: See specification table and the CLOCK DRIVERS section
I
FDBK_INB
41
I
FDBK_IN
48
O
DAC_RSET
50
O
IOUT
51
O
IOUTB
56
I/O
3.3V
CMOS
REFSELECT
57
I/O
HOLDOVER
58
I
59
I
3.3V
CMOS
3.3V
CMOS
3.3V
CMOS
60
I
3.3V
IO_UPDATE
Complementary Feedback input: In standard operating mode, this pin is connected to
the filtered IOUTB output . This internally biased input is typically AC-coupled, and when
configured as such, can accept any differential signal.
Feedback Input: In standard operating mode, this pin is connected to the filtered IOUT
output
DAC output current setting resistor. Connect a resistor from this pin to GND . See the
“DAC Output” section.
DAC output: Output signal should be filtered and sent back on chip through FDBK_INB
input
Complimentary DAC output: Output signal should be filtered and sent back on chip
through FDBK_IN input
Reference Select input: In manual mode, the REFSELECT pin operates as a high
impedance input pin, while in automatic mode, it operates as a low impedance output
pin. Logic 0 (low) indicates/selects RefA. Logic 1 (high) indicates/selects RefB.
Holdover: (Active high) In manual holdover mode, this pin is used to force the AD9549
into holdover mode. In automatic holdover mode, it indicates holdover status.
Power Down: When this active high pin is asserted, the device becomes inactive and
enters a low power state.
Chip Reset: When this active high pin is asserted, the chip goes into reset. Note: upon
power up, a 10 us reset pulse is automatically generated when the power supplies reach
a threshold and stabilize.
I/O Update: A logic transition from 0 to 1 on this pin transfers data from the I/O port
PWRDOWN
RESET
Rev. PrA | Page 19 of 78
AD9549
Preliminary Technical Data
CMOS
61
I
3.3V
CMOS
CSB
62
O
SDO
63
I/O
64
O
3.3V
CMOS
3.3V
CMOS
3.3V
CMOS
SDIO
SCLK
registers to the control registers (see the Write subsection of the General Operation of
Serial Control Port section).
Chip Select: Active low. When programming a device, this pin must be held low. In
systems where more than one AD9549 is present this enables individual programming
of each AD9549
Serial Data Output: When the device is in three wire mode, data is read on this pin
Serial Data Input/Output: When the device is in three-wire mode, data is written via this
pin. In 2 wire mode, data reads and writes both occur on this pin
Serial Programming Clock: data clock for serial programming.
Rev. PrA | Page 20 of 78
Preliminary Technical Data
AD9549
INPUT / OUTPUT TERMINATION RECOMMENDATIONS
0.01 uF
100Ω
0.01 uF
Downstream Device
(High-Z)
AD9549
1.8V
HSTL
Output
0.01 uF
100Ω
(Opt.)
AD9549
Self-biasing
REF Input
0.01 uF
Figure 4: AC-Coupled HSTL Output Driver (Recommended)
Figure 6: Reference Input.
50Ω
AD9549
1.8V
HSTL
Output
+
AVDD/2
-
50Ω
Downstream Device
(High-Z)
0.1 uF
100Ω
AD9549
Self-biasing
FDBK Input
0.1 uF
Figure 5: DC-Coupled HSTL Output Driver
Figure 7: FDBK Input.
Rev. PrA | Page 21 of 78
AD9549
Preliminary Technical Data
THEORY OF OPERATION
CMOS
CLK_OUT
HSTL
CLK_OUT
2X
Digital PLL Core
÷S
FDBK
REF_SELECT
Freq
Est.
REF_A
÷R
PFD
FREQ
TUNING
WORD
PROG.
DIGITAL
LOOP
FILTER
SLEW
LIMIT
EXTERNAL
ANALOG
LOW-PASS
FILTER
DDS/DAC
REF_B
LOCK DETECT
INPUT
REF
MONITOR
HOLDOVER
REF_CNTRL
LOW NOISE
CLOCK
MULTIPLIER
OOL&LOR
CONTROL
LOGIC
S1-S4
IRQ & Status
Logic
AMP
SYSCLK PORT
DIGITAL
INTERFACE
HOLDOVER
SYS_CLK
Figure 8: Detailed Block Diagram
OVERVIEW
The AD9549 provides a clocking output which is directly
related in phase and frequency to the selected (active) reference
(REF_A or REF_B), but having a phase noise spectrum
primarily governed by the system clock. A wide band of
reference frequencies is supported. Jitter existent on the active
reference is greatly reduced by a programmable digital filter in
the Digital Phase Locked Loop (PLL), which is the core of this
product. The AD9549 supports both manual and automatic
holdover. While in holdover, the AD9549 will continue to
provide an output as long as the system clock is maintained.
The frequency of the output during holdover is an average of
the steady state output frequency prior to holdover. Also offered
are manual and automatic switchover modes for changing
between the two references should one become suspect or lost.
A digitally controlled oscillator (DCO) is implemented using a
Direct Digital Synthesizer (DDS) with an integrated output
DAC, clocked by the system clock. A bypassable PLL based
frequency multiplier is present enabling use of an inexpensive,
low frequency source for the system clock. For best jitter
performance, the system clock PLL should be bypassed, and a
low-noise high-frequency system clock should be provided
directly. Sampling theory sets an upper bound for the DDS
output frequency at 50% of fS (where fS is the DAC sample rate),
but a practical limitation of 40% of fS is generally recommended
to allow for the selectivity of the required off-chip
reconstruction filter. The output signal from the reconstruction
filter is fed back to the AD9549, both to complete the PLL, and
to be processed through the output circuitry. The output
circuitry includes HSTL and CMOS output buffers, as well as a
frequency doubler for systems, which need to provide
frequencies above the Nyquist level of the DDS.
The individual functional blocks are described in the following
sections.
Rev. PrA | Page 22 of 78
Preliminary Technical Data
AD9549
PLL CORE (DPLLC)
The Digital Phase Locked Loop Core (DPLLC) includes the
frequency estimation block and the digital phase lock control
block driving the DDS.
The start of the DPLLC signal chain is the reference signal, fR,
which appears on REF A or REF B inputs. The frequency of
this signal can be divided by an integer factor of R via the
feedforward divider. The output of the feedforward divider is
routed to the phase/frequency detector (PFD). Therefore, the
frequency at the input to the PFD is given by
f PFD =
fR
R
.
The PFD outputs a time series of digital words that are routed
to the digital loop filter. The digital filter implementation offers
many advantages: The filter response is determined by numeric
coefficients rather than discrete component values. There is no
aging of components and therefore, no drift of component value
over time. There is no thermal noise in the loop filter, and there
is no control node leakage current (which causes reference feed
through in a traditional analog PLL).
The output of the loop filter is a time series of digital words.
These words are applied to the frequency tuning input of a DDS
to steer the DCO frequency. The DDS provides an analog
output signal via an integrated DAC, effectively mimicking the
operation of an analog VCO.
The DPLLC can be programmed to operate in conjunction with
an internal frequency estimator to help decrease the time
required to achieve lock. When the frequency estimator is
employed, frequency acquisition is accomplished in a two-step
process:
Step 1: An estimate is made of the frequency of fPFD. The phaselock control loop is essentially inoperative during the frequency
estimation process. Once a frequency estimate is made, it is
delivered to the DDS so that its output frequency is
approximately equal to fPFD multiplied by S (the modulus of the
feedback divider).
Step 2: The phase-lock control loop becomes active and acts as a
servo to acquire and hold phase lock with the reference signal.
As mentioned in step 1) above, the DPLLC includes a feedback
divider that allows the DCO to operate at an integer multiple
(S) of fPFD. This establishes a nominal DCO frequency (fDDS)
given by:
f DDS = ( RS ) f R .
Figure 9: AD9549 Digital PLL Block Diagram
Feedforward Divider (Divide-by-R)
The feedforward divider is an integer divider allowing
frequency prescaling of the REF Source input signal while
maintaining the desired low jitter performance of the AD9549.
The feedforward divider is a programmable modulus divider
with very low jitter injection. The divider is capable of handling
input frequencies as high as 750 MHz. The divider depth is 16bits cascaded with an additional divide-by-two. The divider
therefore is capable of integer division from 1 to 65,535 (index
of 1) or 2 to 131,070 (index of 2). The divider is programmed
via the I/O Register Map to trigger on either the rising (default)
or falling edge of the REF Source input signal.
There is a lower bound on the value of R imposed by the phasefrequency detector within the DPLLC which has a maximum
operating frequency of fPFD[max] as explained in the Fine Phase
Detector section. The “R Divider /2” bit must be set when
REF_A or REF_B is greater than 400 MHz. The user must also
ensure that R is chosen so that it satisfies the inequality:
R ≥ ceil(fR / fPFD[max])
The upper bound is:
R ≤ floor(fR /8 kHz)
Where the ceil(x) function yields the nearest integer ≥ x. For
example, if fR=155 MHz and fPFD[max] =24.5 MHz, then ceil
(155/24.5) = 7, so R must be > 7.
Feedback Divider (Divide-by-S)
The feedback divider is an integer divider allowing frequency
multiplication of the REF signal that appears at the input of the
phase detector. It is capable of handling frequencies well above
the Nyquist limit of the DDS. The divider depth is 16-bits
cascaded with an additional divide-by-two. The divider is
therefore capable of integer division from 1 to 65,535 (index of
Rev. PrA | Page 23 of 78
AD9549
Preliminary Technical Data
1) or 2 to 131,070 (index of 2). The divider is programmed via
the I/O Register Map to trigger on either the rising (default) or
falling edge of the feedback signal.
condition, the phase error measurement uses the coarse phase
detector instead.
The feedback divider must be programmed within certain
boundaries. The “S Divider /2” bit must be set when FDBK_IN
is greater than 400 MHz. The upper boundary on the feedback
divider is the lesser of the maximum programmable value of S
and the maximum practical output frequency of the DDS (~
40%fS). Two formulae are given: Smax1 for a feedback divider
index of 1 and Smax2 for an index of 2:
The digital loop filter integrates and low-pass filters the digital
phase error values delivered by the phase detector. The loop
filter response mimics that of a 2nd order, R-C network used to
filter the output of a typical phase detector and charge pump
combination as shown in the diagram below.
(
= min [
)
S max 1 = min
40% f S R
fR
, 65535
S max 2
40% f S R
fR
, 131070
]
Digital Loop Filter
Loop Filter
CLK
Phase/
Frequency
Detector
or
Charge
Pump
VCO
C1
R2
C2
Where R is the modulus of the feedforward divider, fS is the
DAC sample rate, and fR is the input reference frequency.
Figure 10: Typical Analog PLL Block Diagram
The DCO has a minimum frequency (see DAC output
Characteristics section of AC specification table). This imposes
a lower bound, Smin, on the feedback divider value, as well.
((
S min = max R
f DCO min
fR
), 1)
NOTE: Reduced DCO frequencies result in worse jitter
performance (a consequence of the reduced slew rate of the
sinusoid generated by the DDS).
Forward and Reverse FEC Clock Scaling
The Feedforward (Divide-by-R) and Feedback Divider (Divideby-S) enable FEC clock scaling. For instance, to multiply the
incoming signal by 255/237, set the S- divider to 255, and the
R-divider to 237. One should be careful to abide by the
limitations on the R- and S-Dividers, and make sure the Phase
Detector input frequency is within specified limits.
Phase Detector
The phase detector is composed of two detectors: a coarse
phase detector and a fine phase detector. The two detectors
operate in parallel. Both detectors measure the duration (∆t) of
the pulses generated by a conventional 3-state phase/frequency
detector.
Together, the fine and coarse phase detectors produce a digital
word that is a time-to-digital conversion of the separation
between the edge transitions of the pre-scaled reference signal
and the feedback signal.
The building blocks implemented on the AD9549, however, are
digital. A time-to-digital converter that produces digital values
proportional to the edge timing error between the CLK and
feedback signals replaces the phase-frequency detector and
charge pump. A digital filter that processes the edge timing
error samples from the time-to-digital converter replaces the
loop filter. A DDS replaces the VCO, which produces a
frequency that is linearly related to the digital value provided by
the loop filter. This is shown in Figure 11 on Page 26 with some
additional detail.
The samples provided by the time-to-digital converter are
delivered to the loop filter at a sample rate equal to the CLK
frequency (i.e., fR/R). The loop filter is intended to oversample
the time-to-digital converter output at a rate determined by the
"P"-divider. The value of P is programmable via the I/O
Register Map. It is stored as a 5-bit number, PIO. The value of
PIO is related to P by the equation:
P = 2P
IO
(where 5 ≤ PIO ≤ 16)
Hence, the "P"-divider can provide divide ratios between 32 and
65536 in power-of-2 steps. With a DAC sample rate of 1GHz
the loop filter sample rate can range from as low as 15.26kHz to
a maximum of 31.25MHz. Coupled to the loop filter is a
cascaded comb-integrator (CCI) filter that provides a sample
rate translation between the loop filter sample rate (fS/P) and
the DDS sample rate, fS.
If the fine phase detector is able to produce a valid result, then
this result alone serves as the phase error measurement. If the
fine phase detector is either in an overflow or underflow
Rev. PrA | Page 24 of 78
Preliminary Technical Data
AD9549
The choice of P is important because it controls both the
response of the CCI filter and the sample rate of the loop filter.
In order to understand the method for determining a useful
value for P, it is first necessary to examine the transfer function
of the CCI filter:
H (ω ) CCI =
[
1− e − jωP
P (1− e − jω )
]
PIOMAX = max 5,
2
or
(
1 1− cos(ωP )
P 2 1− cos(ω )
),
ω>0
To evaluate the response in terms of absolute frequency, make
the substitution:
ω=
f S
2 fS
, floor log 2
min 16, floor log 2
80
f
3 f REF
LOOP
With a properly chosen value for P, the closed-loop response of
the digital PLL is primarily determined by the response of the
digital loop filter. Flexibility in controlling the loop filter
response translates directly into flexibility in the range of
applications satisfied by the architecture of the AD9549.
ω=0
1,
H CCI (ω ) =
define PMAX in terms of PIO, so that PIOMAX may be determined.
The condition, PIO ≤ PIOMAX, ensures that the impact of the
phase delay of the CCI filter on the phase margin of the loop
will not exceed 5°. PIOMAX may be expressed as:
2πf
fS
(where fS is the DAC sample rate and f is the frequency at which
HCCI is to be evaluated)
Analysis of this function reveals that the CCI magnitude
response follows a low pass characteristic that consists of a
series of P lobes. The lobes are bounded by null points
occurring at frequency multiples of fS/P. The peak of each
successive lobe is lower that its predecessor over the frequency
range between DC and ½fS. For frequencies greater than ½fS,
the response is a reflection about the vertical at ½fS.
Furthermore, the first lobe (which appears between DC and
fS/P) exhibits a monotonically decreasing response. That is, the
magnitude is unity at DC and it steadily decreases with
frequency until it vanishes at the first null point (fS/P).
The null points imply the existence of transmission zeros placed
at finite frequencies. While transmission zeros placed at
infinity yield minimal phase delay, zeros placed closer to DC
result in increased phase delay. Hence, the position of the first
null point has a significant impact on the phase delay
introduced by the CCI filter. This is an important
consideration, because excessive phase delay negatively impacts
the overall closed loop response. As a rule of thumb, choose a
value for P so that the frequency of the first null point (fS/P) is
the greater of:
80 times the desired loop bandwidth, or
1.5 times the frequency of CLK (fR/R)
The value of P thus calculated (PMAX) is the largest usable value
in practice. Since P is programmed as PIO, it is necessary to
Rev. PrA | Page 25 of 78
AD9549
Preliminary Technical Data
∆φ = 2π
Direct Digital Synthesizer
One of the primary building blocks of the digital PLL is a direct
digital synthesizer (DDS). The DDS behaves like a sinusoidal
signal generator. The frequency of the sinusoid generated by
the DDS is determined by a frequency tuning word (FTW),
which is a digital (i.e., numeric) value. Unlike an analog
sinusoidal generator, a DDS uses digital building blocks and
operates as a sampled system. Thus, it requires a sampling
clock (fS) that serves as the DDS's fundamental timing source.
The accumulator behaves as a modulo-248 counter with a
programmable step size (FTW). A block diagram of the DDS is
shown below.
Phase
Offset
48-bit Accumulator
48
Frequency
Tuning Word
(FTW)
48
19
D
I-Set
16
48
19
Q
Angle to
Amplitude
Conversion
14
DAC
DAC+
(14-bit)
DAC-
fS
Figure 11: DDS Block Diagram
The input to the DDS is a 48-bit FTW that provides the
accumulator with a seed value. On each cycle of fS, the
accumulator adds the value of the FTW to the running total of
its output. For example, given an FTW=5, the accumulator
would count by 5's, incrementing on each fS cycle. Over time,
the accumulator will reach the upper end of its capacity (248 in
this case). At which point it rolls over, retaining the excess. The
average rate at which the accumulator rolls over establishes the
frequency of the output sinusoid. The average rollover rate of
the accumulator is given by the formula below, and establishes
the output frequency (fDDS) of the DDS.
f DDS =
( )f
FTW
2 48
∆phase
216
)
The DDS can be operated in either open loop or closed loop
mode, via the Close Loop bit in the DPLL Register.
There are two open loop modes: Single Tone and Holdover. In
Single Tone Mode, the DDS behaves like a frequency
synthesizer, and uses the value stored in the FTW0 register to
determine its output frequency. Alternatively, the FTW and
∆phase values can be determined by the device itself using the
frequency estimator. Because Single Tone mode ignores the
reference inputs, it is very useful for generating test signals to
aid in debugging. Single Tone mode must be activated manually
via register programming.
In Holdover mode, the AD9549 uses past tuning words when
the loop was closed to determine its output frequency.
Therefore, the loop must have been successfully closed in order
for Holdover Mode to work. Switching in and out of Holdover
Mode can be either automatic or manual, depending on register
settings.
Typically, the AD9549 operates in closed loop mode. In closed
loop mode, the FTW values come from the output of the digital
loop filter and vary with time. The DDS frequency is steered in
a manner similar to a conventional VCO-based PLL.
NOTE: In "closed loop" mode, the DDS phase offset capability
is inoperative.
S
Solving this equation for FTW yields:
f
FTW = round 2 48 DDS
fS
(
For example, given that fS=1GHz and fDDS=19.44MHz, then
FTW=5,471,873,547,255 (04FA05143BF7h).
The relative phase of the sinusoid can be controlled
numerically, as well. This is accomplished using the phase offset
input to the DDS (a programmable 16-bit value (∆phase); see
the I/O Register Map). The resulting phase offset, ∆φ (radians),
is given by:
Rev. PrA | Page 26 of 78
Preliminary Technical Data
AD9549
⋅ FSC
)
I DAC _ FS = I DAC _ REF (72 + 1921024
DAC Output
The output of the digital core of the DDS is a time series of
numbers representing a sinusoidal waveform. This series is
translated to an analog signal by means of a digital-to-analog
converter (DAC).
The DAC outputs its signal to two pins driven by a balanced
current source architecture (see DAC output diagram below).
The peak output current derives from the combination of two
factors. The first is a reference current (IDAC_REF) established at
the DAC_RSET pin and the second is a scale factor
programmed into the I/O Register map.
AVDD3
49
Current
Switch
Array
IFS/2
IFS/2 + ICODE
IOUT
IOUTB
50
50
( )(2
fS
fR
PDS + 6
PDG )
The fine phase detector operates on a divided down version of fS
as its sampling time base. The sample rate of the fine phase
detector is set using a 4-bit word (PFD_Div) in the I/O Register
Map and is given by:
Fine Phase Detector Sample Rate =
50
52
fS
4 ( PFD _ Div )
The default value of PFD_Div is 5, so for fS=1GHz, the default
sample rate of the fine phase detector is 50MHz. The upper
bound on the maximum allowable input frequency to the phase
detector (fPFD[max]) is 49% of the sample rate, or:
AVSS
Figure 12: DAC Output Pins
The value of IDAC_REF is set by connecting a resistor (RDAC_REF)
between the DAC_RSET pin and ground. The DAC_RSET pin
is internally connected to a virtual voltage reference of 1.2v
nominal, so the reference current can be calculated by:
I DAC _ REF =
The coarse phase detector uses the DAC sample rate (fS) to
determine the edge timing deviation between the REF signal
and the feedback signal generated by the DDS. Hence, fS sets
the timing resolution of the coarse phase detector. At the
recommended rate of fS=1GHz, the coarse phase detector spans
a range of over 131µs (sufficient to accommodate REF signal
frequencies as low as 8 kHz).
Fine Phase Detector
IFS/2 - ICODE
CODE
51
Coarse Phase Detector
Phase GainCPD = R
Current
Switch
Array
Switch
Control
PHASE DETECTOR
The phase gain of the coarse phase detector is controlled via the
I/O Registers by means of two numeric entries. The first is a 3bit power-of-2 scale factor, PDS. The second is a 6-bit linear
scale factor, PDG.
IFS
IFS/2
Using the recommended value of RDAC_REF the full-scale DAC
output current can be set with 10-bit granularity over a range of
approximately 8.6mA to 31.7mA.
1.2
RDAC _ REF
NOTE: The recommended value of IDAC_REF is 120µA, which
leads to a recommended value of RDAC_REF of 10kΩ.
f PFD[max] =
fS
8( PFD _ Div )
Therefore, fPFD[max] is 25MHz in the example above.
The fine phase detector uses a proprietary technique to
determine the phase deviation between the REF signal and
feedback signal.
The scale factor consists of a 10-bit binary number (FSC)
programmed into the DAC FS Current register in the I/O
Register Map. The full-scale DAC output current (IDAC_FS) is
then given by:
Rev. PrA | Page 27 of 78
AD9549
Preliminary Technical Data
The phase gain of the fine phase detector is controlled by an 8bit scale factor (FPFD_Gain) in the I/O Register Map. The
nominal (default) value of FPFD_Gain is 200, and establishes
R (210107 )( FPFD _ Gain )
the phase gain as: PhaseGainFPD =
f
R
Phase Detector Gain Matching
Although the fine and coarse phase detectors use different
means to make a timing measurement, it is essential that both
have equivalent phase gain. Without proper gain matching the
closed-loop dynamics of the system cannot be properly
controlled. Hence, the goal is to make PhaseGainCPD=
PhaseGainFPD. This leads to:
S
)
(
Phase Detector Pin Connections
There are three pins associated with the phase detector that
must be connected to external components. The diagram below
shows the recommended component values and their
connections.
AD9549
PFD_VRB
)
PFD_VRT
22
10µF
Which simplifies to:
7
_ Gain
2 PDS PDG = (16⋅10 )FPFD
fS
0.1µF
Typically, FPFD_Gain is established first and then PDG and
PDS are calculated. The proper choice for PDS is given by:
[ (
PDS = round log 2
7
10 FPFD _ Gain
2 fS
10 7 FPFD _ Gain
2 PDS − 4 f S
PFD_RSET
)
The final value of PDG must satisfy 0 ≤ PDG ≤ 63. For
example, let fS=700MHz and FPFD_Gain=200, then PDS=1 and
PDG=23.
0.1µF
Figure 13: Phase Detector Pin Connections
)]
The final value of PDS must satisfy 0 ≤ PDS ≤ 7. The proper
choice for PDG is calculated using this equation:
(
21
0.1µF
2 PDS + 6 PDG = 21010 7 FPFD _ Gain
PDG = round
20
4K99
(f
Note that the AD9549 Evaluation Software will calculate
register values that have the phase detector gains already
matched.
DIGITAL LOOP FILTER COEFFICIENTS
In order to provide the desired flexibility, the loop filter has
been designed with three programmable coefficients (α, β and
γ). The coefficients along with P (where P=2Pio) completely
defines the response of the filter, which is given by:
H (ω ) LoopFilter = α
(
e jω + ( β −γ −1)
e j 2 ω + ( − γ − 2 ) e jω + (γ +1)
)
To evaluate the response in terms of absolute frequency
substitute:
ω=
2πPf
fS
Where P is the divide ratio of the "P"-divider, fS is the DAC
sample rate, and f is the frequency at which the function is to be
evaluated.
Rev. PrA | Page 28 of 78
Preliminary Technical Data
AD9549
The loop filter coefficients are determined by the AD9549
evaluation software according to three parameters:
φ:
desired closed-loop phase margin (0 < φ < π/2 rad)
desired open-loop bandwidth (Hz)
fLOOP:
desired output frequency of the DDS (Hz)
fDDS:
Note that fDDS can also be expressed as fDDS = fR(S/R).
The three coefficients are calculated according to parameters
via the equations below:
β = −4πPf C tan(φ )
γ = 12 F (φ )β
(
α = − 10
Where
238 π
7
FPFD _ Gain
)f
The quantized α coefficient is composed of three factors, where
α0, α1 and α2 are the programmed values for the α coefficient:
α
)(2α )(2−α
α quantized = (2048
0
1
2
)
The boundary values for each are 0 ≤ α0 ≤ 4095,
0 ≤ α1 ≤ 22, and 0 ≤ α2 ≤ 7. The optimal values of α0, α1 and α2
are:
α1 = max[0, min{22, ceil (log 2
2048α
4095
)}]
α 2 = max[0, min{7, floor (log 2 ( 4095
α ) + α 1 − 11)}]
DDS
α 0 = max [0, min{4095, round (α ⋅ 2α
f C F (φ ) β
F (φ ) = 1 + sin(1φ ) , f C =
f LOOP
fS
, and FPFD_Gain is
the value of the gain scale factor for the Fine Phase Detector as
programmed into the I/O Register Map.
2 −α1 +11
)}]
The magnitude of the quantized β coefficient is composed of
two factors:
β quantized = (β 0 )(2 − ( β +15 ) )
1
Where β0 and β1 are the programmed values for the β
coefficient, The boundary values for each are 0 ≤ β0 ≤ 4095 and
0 ≤ β1 ≤ 7. The optimal values of β0 and β1 are:
NOTE: The range of loop filter coefficients is limited as
follows:
0 < α < 223 (~8.39·106)
[
( ( )− 15)}]
{
β 1 = max 0, min 7, floor log 2
-0.125 < β < 0
4095
β
β 0 = max[0, min{4095, round ( β ⋅ 2 β +15 )}]
-0.125 < γ < 0
1
The above constraints on β and γ constrain the closed-loop
phase margin such that both β and γ will assume negative
values. Even though β and γ are limited to negative quantities,
the values as programmed are positive. The negative sign is
assumed internally.
NOTE: The closed-loop phase margin is limited to the range of
0° < φ < 90° because β and γ are negative.
The three coefficients are implemented as digital elements,
necessitating quantized values. Determination of the
programmed coefficient values in this context follows.
The magnitude of the quantized γ coefficient is composed of
− (γ +15 )
two factors: γ quantized = γ 0 2 1
( )(
)
Where γ0 and γ1 are the programmed values for the γ coefficient,
the boundary values for each are 0 ≤ γ0 ≤ 4095 and 0 ≤ γ1 ≤ 7.
The optimal values of γ0 and γ1 are:
[
{
( ( )− 15)}]
γ 1 = max 0, min 7, floor log 2
4095
γ
γ 0 = max[0, min{4095, round (γ ⋅ 2 γ +15 )}]
Rev. PrA | Page 29 of 78
1
AD9549
Preliminary Technical Data
The min(), max(), floor(), ceil() and round() functions are
defined as follows. The function, min(x1, x2, … xn), chooses the
smallest value in the list of arguments. The function, max(x1,
x2, … xn), chooses the largest value in the list of arguments. The
function, ceil(x), increases x to the next higher integer if x is
NOT an integer, otherwise x is unchanged. The function,
floor(x), reduces x to the next lower integer if x is NOT an
integer, otherwise x is unchanged. The function, round(x),
rounds x to the nearest integer.
To demonstrate the wide programmable range of the loop filter
bandwidth, consider the following design example. The system
clock frequency (fS) is 1GHz, the input reference frequency (fR)
is 19.44MHz, the DDS output frequency (fDDS) is 155.52MHz,
and the required phase margin (φ) is 45°. fR is within the
nominal bandwidth of the phase detector (25MHz), and fDDS/fR,
is an integer (8), so the prescalar is not required. We can
therefore use R=1 and S=8 for the feedforward and feedback
dividers, respectively.
NOTE: If fDDS/fR is a non- integer, then R and S must be chosen
such that S/R= fDDS/fR with S and R both constrained to integer
values. For example, if fR=10MHz and fDDS=155.52MHz, then
the optimal choice for S and R is 1944 and 125, respectively.
The resulting loop filter coefficients for the lower loop
bandwidth along with the necessary programming values are
shown below.
α = 0.005883404361345
β0 = 16 (10h)
α0 = 1542 (606h)
β1 = 7 (7h)
α1 = 0 (00h)
γ = -0.00000461136116
α2 = 7 (7h)
γ0 = 19 (13h)
β = -0.000003820176667
γ1 = 7 (7h)
Details on exactly how these coefficients are derived can be
obtained by contacting Analog Devices Inc. directly.
CLOSED LOOP PHASE OFFSET
The AD9549 provides for limited control over the phase offset
between the reference input signal and the output signal by
adding a constant phase offset value to the output of the phase
detector. An adder is included at the output of the phase
detector as shown in the figure below to support this. The value
of the constant (PLLOFFSET) is set via the PLL Offset register.
The open loop bandwidth range under the defined conditions
spans 9.5Hz to 257.5kHz. The wide dynamic range of the loop
filter coefficients allows for programming of any open loop
bandwidth within this range under these conditions. The
resulting closed loop bandwidth range under the same
conditions is approximately 12Hz to 359kHz.
The resulting loop filter coefficients for the upper loop
bandwidth along with the necessary programming values are
shown below.
Phase
Offset
Value
CLK
Feedback
Phase
Detector
To
CCI
Filter
Loop
Filter
Figure 14: Input Phase Offset Adder
α = 4322509.4784981
β0 = 3393 (D41h)
PLLOFFSET is a function of the phase detector gain and the
desired amount of timing offset (∆tOFFSET). It is given by:
α0 = 2111 (83Fh)
β1 = 0 (0h)
PLLOFFSET = ∆t OFFSET 21010 7 FPFD _ Gain
α1 = 22 (16h)
γ = -0.12499215775201
α2 = 0 (0h)
γ0 = 4095 (FFFh)
NOTE: FPFD_Gain is described in the Fine Phase Detector
section.
β = -0.10354689386232
γ1 = 0 (0h)
(
Rev. PrA | Page 30 of 78
)
Preliminary Technical Data
AD9549
For example, suppose that FPFD_Gain=200, fCLK=3MHz, and 1°
of phase offset is desired. First, we must find the value of
∆tOFFSET, which is:
∆t OFFSET =
deg
360
TCLK =
1
360
(
1
3 MHz
RESET
Phase
Detector
Samples
) = 925.9 ps
Absolute
Value
Control Logic
Digital
Comparator
Having determined ∆tOFFSET, we have:
(
)
Unlock
Timer
Phase
Lock
Detect
Lock
Timer
P-Divider Clock
PLLOFFSET = 925.9 ps 210 ⋅ 10 7 ⋅ 200 = 1896
3
The result has been rounded because PLLOFFSET is restricted to
integer values.
I/O Registers
Phase Lock Detect
Threshold
5
Y
X
Close
Loop
Figure 15: Phase Lock Detector Block Diagram
NOTE: The PLLOFFSET value is programmed as a 14-bit, twoscomplement number. However, the user must ensure that the
magnitude is constrained to 12 bits, such that:
11
-2 ≤ PLLOFFSET < +2
11
The above constraint yields a timing adjustment range of ±1ns.
This ensures that the phase offset remains within the bounds of
the fine phase detector.
LOCK DETECTION
Phase Lock Detection
During the phase locking process, the output of the phase
detector tends toward a value of zero, which indicates perfect
alignment of the phase detector input signals. As the control
loop works to maintain the alignment of the phase detector
input signals, the output of the phase detector wanders around
zero.
The phase lock detector tracks the absolute value of the digital
samples generated by the phase detector. These samples are
compared to the Phase Lock Detect Threshold value
programmed in the I/O Register Map. A false state at the
output of the comparator indicates the absolute value of a
sample exceeds the value in the threshold register. A true state
at the output of the comparator indicates alignment of the phase
detector input signals to the degree specified by the lock
detection threshold.
The Phase Lock Detect Threshold value (PLDT) is a 32-bit
number stored in the I/O Register Map:
(
PLDT = round ∆t ⋅ 210 ⋅ 10 7 ⋅ FPFD _ Gain
)
Where ∆t is the maximum allowable timing error between the
signals at the input to the phase detector and the value of
FPFD_Gain is as described in the Fine Phase Detector section.
For example, suppose that fR/R=3MHz, FPFD_Gain=200, and
the maximum timing deviation is given as 1°. This yields a ∆t
value of:
∆t =
1o
360o
(R ⋅ TR )⋅ = 360R f
R
=
1
360⋅ 3⋅106
(
)
The resulting phase lock detect threshold is:
2 10 ⋅10 7 ⋅ 200
= 1896
PLDT = round
6
360 3 ⋅10
(
)
Hence, 1896 (00000768h) is the value that must be stored in the
Phase Lock Detect Threshold register.
The "phase lock detect" signal is generated once the control
logic observes that the output of the comparator has been in the
true state for 2X periods of the P-Divider clock (see the Digital
Loop Filter section for a description of the P-Divider). Once the
phase lock detect signal is asserted, it remains asserted until
cleared by an "unlock" event or by a device RESET.
The duration of the lock detection process is programmable via
the Phase Lock Watchdog Timer register. The interval is
controlled by a 5-bit number, X (0 ≤ X ≤ 20). The absolute
duration of the phase lock detect interval is:
TLOCK =
Rev. PrA | Page 31 of 78
2X P
fS
AD9549
Preliminary Technical Data
The time required to declare an unlock event is programmable
via the Phase Lock Watchdog Timer register. The interval is
controlled by a 3-bit number, Y (0 ≤ Y ≤ 7). The absolute
duration of the unlock detection interval is:
Hysteresis in the phase lock detection process is controlled by
specifying the minimum duration that qualifies as an unlock
event. An unlock event is declared when the control logic
observes that the output of the comparator has been in the false
state for 2Y+1 periods of the P-Divider clock (provided that the
phase lock detect signal has been asserted). Detection of an
unlock event clears the phase lock detect signal, and the phase
lock detection process is automatically restarted.
TUNLOCK =
2Y + 1 P
fS
Figure 16 below shows the basic timing relationship between
the reference signal at the input to the phase detector, the phase
error magnitude, the output of the comparator, and the output
of the phase lock detector. The example shown here assumes
that X=3 and Y=1.
fR/R
Phase Error
Magnitude
Samples
Threshold
0
fS/P
Threshold
Comparator
8
Lock
Timer
(X=3)
8
LOCKED
4
Unlock
Timer
(Y=1)
Figure 16: Lock/Unlock Detection Timing
Frequency Lock Detection
Frequency lock detection is similar to phase lock detection,
with the exception that the difference between successive phase
samples is the source of information. A running difference of
the phase samples serves as a digital approximation to the timederivative of the phase samples, which is analogous to
frequency.
RESET
Phase
Detector
Samples
Differencer
Absolute
Value
Control Logic
Digital
Comparator
Unlock
Timer
Frequency
Lock
Detect
Lock
Timer
I/O Registers
Frequency Lock
Detect Threshold
Y
5
X
2
R
FLDT = round ∆f ⋅ 210107 FPFD _ Gain ⋅
f R
Where fR is the frequency of the active reference, R is the value
of the reference prescaler, and ∆f is the maximum frequency
deviation of fR that is considered to indicate a frequency locked
condition (∆f ≥ 0). For example, suppose that fR=3MHz, R=5,
FPFD_Gain=200, and a frequency lock threshold of 1% is
specified. Then the frequency lock detect threshold value is:
2
5
FLDT = round 1% ⋅ 3 ⋅106 ⋅ 210107 ⋅ 200 ⋅
= 170,667
6
3 ⋅10
(
P-Divider Clock
3
The formula for the Frequency Lock Detect Threshold value
(FLDT) is:
Close
Loop
Figure 17: Frequency Lock Detection
)
Hence, 170667 (00029AABh) is the value that should be stored
in the Frequency Lock Detect Threshold register.
The duration of the frequency lock/unlock detection process is
controlled in exactly the same way as the phase lock/unlock
Rev. PrA | Page 32 of 78
Preliminary Technical Data
AD9549
detection process in the previous section. However, a different
control register is used: the Frequency Lock Watchdog Timer
register.
REFERENCE MONITORS
Loss of Reference
The AD9549 can set an alert when one or both of the reference
signals are not present. Each of the two reference inputs (REFA,
REFB) has a dedicated LOR (Loss of Reference) circuit enabled
via the I/O Register Map. Detection of an LOR condition sets
the appropriate LOR bit in both a status register and an IRQ
register in the I/O Register Map. The LOR state is also
internally available to the multi-purpose "status" pins (S1:4) of
the AD9549. By setting the appropriate bit in the I/O Register
Map, the user can assign a status pin to each of the LOR flags.
This provides a means to control external hardware based on
the state of the LOR flags directly.
The LOR circuits are internal ‘watchdog’ timers with a
programmable period. The period of the timer is set via the I/O
register Map so that its period is longer than that of the
monitored reference signal. The rising edge of the reference
signal continuously resets the watchdog timer. If the timer
reaches a full count, this indicates that the reference was either
lost or its period was longer than the timer period. LOR does
not differentiate between these.
The period for each of the LOR timers is controlled by a 16-bit
word in the I/O Register Map. The period of the timer clock
(TCLK) is 2/fS. Therefore, the period of the watchdog timer
(TWD) is:
TWD = (2/fS)N
Where N is the value of the 16-bit word stored in the I/O
Register Map for the appropriate LOR circuit. Choose the value
of N so that the watchdog period is greater than the input
reference period, expressed mathematically as:
N > floor
( )
Note that when N is chosen to be
floor
( ) + 1 , the LOR
fS
2 fR
circuit is capable of indicating an LOR condition in little more
than a single input reference period. For example, if fS=1GHz
and fR=2.048MHz, then the smallest useable N value is:
(
)
10
N MIN = floor 2(2.048
+ 1 = 245
×106 )
9
Which yields values for fPRESENT and fLOST as:
f PRESENT = 2,048,816 and f LOST = 2,032,520
NOTE: N should be chosen sufficiently large to account for any
acceptable deviation in the period of the input reference signal.
Notice that the value of N is inversely proportional to the
reference frequency, meaning that as the reference frequency
goes up, the precision for adjusting the threshold goes down.
Proper operation of the LOR circuit requires that N be no less
than 3. Therefore, the highest reference frequency for which
the LOR circuit will function properly is given by: fLOR_MAX =
fS/6.
Reference Frequency Monitor
The AD9549 can set an alert whenever one or both of the
reference inputs drift in frequency beyond user-specified limits.
Each of the two references has a dedicated Out of Limits (OOL)
circuit enabled/disabled via the I/O Register Map. Detection of
an OOL condition sets the appropriate OOL bit in both a status
register and an IRQ register in the I/O Register Map. The user
can also assign a status pin (S1-S4) to each of the OOL flags by
setting the appropriate bit in the I/O Register Map. This
provides a means to control external hardware based on the
state of the OOL flags directly.
Each reference monitor contains three main building blocks: a
programmable reference divider, a 32-bit counter, and a 32-bit
digital comparator.
fS
2 fR
where fR is the frequency of the input reference. The value of N
results in establishing two frequencies. One for which the LOR
signal will never be triggered (fPRESENT), and one for which the
LOR signal will always be active (fLOST). Between these
frequencies the LOR signal will intermittently toggle between
states.
Figure 18: Reference Monitor
The values of the two frequency bounds are:
f PRESENT =
fS
2N
f LOST =
fS
2 ( N +1)
Four values are needed to calculate the correct values of the
reference monitor: The system clock frequency, fS (usually
Rev. PrA | Page 33 of 78
AD9549
Preliminary Technical Data
1 GHz), the reference input frequency, fR (in Hz), the error
bound, E (1%=0.01), and the monitor window size (W). The
monitor window size is the difference between the maximum
and minimum number of counts accumulated between adjacent
edges of the reference input. If this window is too small,
random variations will cause the OOL detector to indicate
incorrectly that a reference is out of limits. However, the time
required to determine if the reference frequency is valid
increases with window size. A window size of at least 20 is a
good starting point.
the I/O Register Map. Transition to a newly selected reference
depends on a number of factors:
The four input values mentioned above are used to calculate the
OOL Divider (D) and OOL nominal value (N), which in turn
are used to calculate the OOL Upper Limit (U), and OOL
Lower Limit (L) according to the following formulas:
A functional diagram of the reference switchover and holdover
logic is shown in Figure 19.
State of the REFSELECT pin
State of the "Ref_AB" control register bit
State of the "Enable Ref Input Override" register bit
Holdover status
f W
D = max(1, min(65535, ceil 4 * R * ))
fS E
N=
fR D
*
fS 4
L = floor ( N ) − floor (W )
U = ceil ( N ) + floor (W )
The timing accuracy is dependent on two factors. The first is
the inherent accuracy of fS, since it serves as the time base for
the Reference Monitor. As such, the accuracy of the Reference
Monitor can be no better than the accuracy of fS. Second, the
value of W, which must be sufficiently large so that the timer
resolves the deviation between a nominal value of fR and a value
that is out of limits.
As an example, let fR=10MHz, Ε=1.0%, fS=1GHz, and W=20.
The limits are then:
Lower Limit = 1980
Upper Limit = 2020
Now let Ε=0.01%, Then the limits are:
Lower Limit = 199980
Upper Limit = 200020
Notice that the number of counts (and time) required to make
this measurement has increased 100x.
REFERENCE SWITCHOVER
The AD9549 supports dual input reference clocks. Reference
switchover may be accomplished either automatically or
manually by appropriately programming the "AutoRefSel" bit in
Rev. PrA | Page 34 of 78
Preliminary Technical Data
AD9549
Active RefSel State
REF SEL
RefAB
1
0
AutoRefSel
State
Machine
0
1
Derived RefSel State
AutoHold
Derived Holdover State
To
Reference
Switching
Control
Logic
Override RefPin
Override HldPin
1
0
0
1
To
Holdover
Control
Logic
an "Enable Line Card Mode" bit is provided in the I/O Register
map. The Line Card Mode logic is shown in Figure 20 below.
When Enable Line Card bit is 0, reference switch over occurs on
command without consideration to the relative edge placement
of the references. This means that there is the possibility of an
extra pulse. However, when this bit is set to 1, the timing of the
reference switch over is executed conditionally as shown in
Figure 21 on Page 36.
REFA In
0
REFB In
1
selected reference
REF In
Enable
Line-Card
Mode
Hldovr
HOLDOVER
0
Active Holdover State
1
Q
D
From
Reference
Selection
Logic
Figure 19: Reference Switchover and Holdover Logic
In manual mode, the active reference is determined by an
externally applied logic level to the REFSELECT pin. In
automatic mode, an internal state machine determines which
reference is active, and the REFSELECT pin becomes an output
indicating which reference the state machine is using.
The user may override the active reference chosen by the
internal state machine via the "Enable Ref Input Override " bit
in the I/O Register Map. The "Ref_AB" bit in the I/O Register
Map is then used to select the desired reference. When in
override, it is important to note that the REFSELECT pin does
not indicate the physical reference selected by the "Ref_AB" bit.
Instead, it indicates the reference that the internal state machine
would select if the device were not in the override mode. This
allows the user to force a reference switchover by means of the
programming registers while monitoring the response of the
state machine via the REFSELECT pin.
0
1
Figure 20: Reference Switchover Control Logic
Note that when the line card mode is enabled, the rising edges
of the alternate reference are used to clock a latch. The latch
holds off the actual transition until the next rising edge of the
alternate reference.
Shown in Figure 21 is a timing diagram that demonstrates the
difference between reference switchover with the line card
mode enabled and disabled. If enabled, when the reference
switchover logic is given the command to switch to the alternate
reference, an actual transition does not occur until the next
rising edge of the alternate reference. This action eliminates the
spurious pulse that can occur when the line card mode is
disabled.
The same type of operation (manual/automatic and override)
also applies to the holdover function, as shown in the Reference
Switchover Logic diagram. The dashed arrows in the diagram
indicate that the state machine output is available to the
REFSELECT and HOLDOVER pins when in override mode.
Use of Line Card Mode to Eliminate Runt Pulses
When two references are not in exact phase alignment and a
transition is made from one to the other, it is possible that an
extra pulse can be generated. This depends on the relative edge
placement of the two references and the point in time that a
switch over is initiated. To eliminate the "extra pulse" problem,
Rev. PrA | Page 35 of 78
AD9549
Preliminary Technical Data
REFA In
1
REFB In
2
1
3
1=Holdover). The HOLDOVER pin is configured as a high
impedance (>100kΩ) input pin in order to accommodate
manual holdover operation.
4
2
3
4
Select REFB
From Reference
Selection Logic
Select REFA
Line Card
Mode
REF In
1
2
REF In
1
2
3
4
3
5
Disabled
4
Enabled
REF selection stalled until
next rising edge of REFB
Figure 21: Reference Switchover Timing
HOLDOVER
Holdover Control
Holdover functionality provides the user with a means of
maintaining the output clock signal even in the absence of a
reference signal at the REF A or B input. In holdover mode, the
output clock is generated from the SysClk input (via the DDS)
by directly applying a frequency tuning word to the DDS.
Transfer from normal operation to holdover mode may be
accomplished either manually or automatically by appropriately
programming the "Automatic Holdover" bit (0=Manual,
1=Auto). The actual transfer to holdover operation, however,
depends on the state of the HOLDOVER pin and the state of
control register bits "Enable Holdover Override" and "Holdover
On/Off ".
Automatic holdover is invoked when the “AutoHold" bit is a
logic 1. In automatic mode, the HOLDOVER pin is configured
as a low impedance output with its logic state indicating the
holdover state as determined by the internal state machine
(0=Normal, 1=Holdover).
In automatic holdover operation the user may override the
internal state machine by programming the "Override HldPin"
bit to a logic 1 and the "Hldovr" bit to the desired state
(0=Normal, 1=Holdover). However, the HOLDOVER pin does
not indicate the "forced" holdover state in the override
condition, but continues to indicate the holdover state as chosen
by the internal state machine (even though the state machine
choice is overridden). This allows the user to force a holdover
state by means of the programming registers while monitoring
the response of the state machine via the HOLDOVER pin.
A functional diagram of the reference switchover and holdover
logic is shown in Figure 19 on Page 35.
NOTE: The default state for the reference switchover bits is
AutoHold=0, Override HldPin=0, and Hldovr=0.
Holdover & Reference Switchover State Machine
The interplay between the input reference signals and holdover
is most readily demonstrated by means of a state diagram. In
Figure 22, the various control signals and the four states are
shown.
Manual holdover is established when the “Automatic Holdover”
bit is a logic 0 (default). In manual mode, holdover is
determined by the state of the HOLDOVER pin (0=Normal,
Rev. PrA | Page 36 of 78
Preliminary Technical Data
AD9549
Figure 22: Holdover state diagram
Abbreviation Key
RefA:
RefB:
HoldOver:
FailA:
FailB:
ValidA:
ValidB:
Reference A selected
Reference B selected
Holdover state
Reference A failed
Reference B failed
Reference A validated
Reference B validated
OvrdRefPin:
OvrdHldPin:
AutoRefSel:
AutoRcov:
AutoHold:
||
&
%
Override REF SEL pin
Override HOLDOVER pin
Automatic reference select
Automatic holdover recovery
Automatic holdover entry
Logical OR
Logical AND
Logical NOT
Figure 23: Holdover State Diagram Abbreviation Key
States 1 or 2 are in effect when the device is not in the holdover
condition, while states 3 & 4 are in effect when the holdover
condition is active. When REF A is selected as the "active"
reference, then states 1 or 3 are in effect. When REF B is
selected as the "active" reference, then states 2 or 4 are in effect.
A transition between states depends on the reference switchover
and holdover control register settings, the logic state of the
REFSELECT and HOLDOVER pins, and the occurrence of
certain events (e.g., a reference failure).
The state machine and its relationship to control register and
external pin stimuli are shown in the diagram below. The state
machine generates a "derived" reference selection and holdover
state. The actual control signal sent to the reference switchover
logic and the holdover logic, however, depends on the control
signals applied to the MUXes. The "dashed" path leading to the
REFSELECT and HOLDOVER pins is active when the "auto"
mode is selected for reference selection and/or holdover
assertion.
Reference Recovery Timers
Each of the two reference inputs has a dedicated recovery timer.
The status of these timers is used by the holdover state machine
as part of the decision making process for reverting to a
previously faulty reference. For example, suppose that a
reference fails (i.e., an LOR or OOL condition is in effect) and
Rev. PrA | Page 37 of 78
AD9549
Preliminary Technical Data
that the device is programmed to revert automatically to a valid
reference when it recovers. When a reference returns to normal
operation, the LOR and OOL conditions will no longer be true.
However, the state machine is not immediately notified of the
clearing of the LOR and OOL condition. Instead, once both the
LOR and OOL conditions are cleared, the recovery timer for
that particular reference is started. Expiration of the recovery
timer is an indication to the state machine that the reference is
now available for selection. However, even though the reference
is now flagged as "valid", actual transition to the recovered
reference depends on the programmed settings of the various
holdover control bits.
The recovery timers are controlled via the I/O Register Map.
Although there are two independent recovery timers, the
programmed information is shared among both. The desired
time interval is controlled via a 5-bit word (T) such that
0 ≤ T ≤ 31 (default is T=0). The duration of the recovery timers
is given by:
(
)
signal with the reference input signal, and will start to adjust the
phase/frequency using the holdover signal as its starting point.
The behavior of the holdover state machine when it is in
automatically exiting holdover mode is very similar. The
primary difference is that reference monitor is continuously
monitoring both reference inputs and as soon as one becomes
valid, it automatically switches to that input.
The output frequency in Holdover mode depends on the
frequency of the SysClk input source and the value of the
frequency tuning word applied to the DDS. Therefore, the
stability of the output signal is completely dependent on the
stability of the SysClk source (and the SysClk PLL Multiplier, if
enabled).
Note: It is very important to power down an unused reference
input to avoid chattering on that input. Also, the reference
validation timer must be set to at least one full cycle of the
signal coming out of the reference divider.
TRECOVER = T0 2 T +1 − 1
Where T0 is the sample rate of the digital loop filter, which has a
period of:
T0 =
2 PIO
fS
(see the Digital Loop Filter section)
A single bit, Disable Recovery Timer, causes the state machine
to ignore the status of the recovery timers. Instead, the state
machine relies on the user to validate the recovery of the faulty
reference and then to set the Validate RefA (or RefB) bit
manually in the I/O Register Map. That is, the state machine
treats the setting of the "Validate" bits as though the associated
timer had expired.
Holdover Operation
When the holdover condition is asserted, the DDS output
frequency is no longer controlled by the phase lock feedback
loop. Instead, a static frequency tuning word (FTW) is applied
to the DDS to hold it at a specified frequency. The source of the
static FTW depends on the status of the appropriate control
register bits. During normal operation, the Averager & Sampler
monitors and accumulates up to 65000 FTW values as they are
generated, and upon entering holdover, the holdover state
machine can use the averaged tuning word, or the last valid
tuning word.
Holdover mode is exited in a similar manner that it is entered. If
manual holdover control is used, then when the holdover pin is
de-asserted, the phase detector starts comparing the holdover
Rev. PrA | Page 38 of 78
Preliminary Technical Data
AD9549
Holdover Sampler and Averager
If activated via the I/O Register Map, the HSA continuously
monitors the data generated by the digital loop filter in the
background. It should be noted that the loop filter data is a
time sequence of frequency adjustments (∆f) to the DDS. The
output of the HSA is routed to a read-only register in the I/O
Register Map and to the holdover control logic.
The first of these destinations (the read-only register) serves as
a "trace buffer" that may be read by the user and the data
processed externally. The second destination (the holdover
control logic) uses the output of the HSA to "peg" the DDS at a
specific frequency upon entry into the holdover state. Hence,
the DDS will assume a frequency specified by the last value
generated by the HSA just prior to entering the holdover state.
between DC and fS/2 (with 48-bit resolution). However, the
user is given the option of placing limits on the tuning range of
the DDS via two 48-bit registers in the I/O Register Map: FTW
Upper Limit and FTW Lower Limit. If the tuning word input
exceeds the upper or lower frequency limit boundaries, the
tuning word is clipped to the appropriate value. The default
setting for these registers is fS/2 and DC, respectively.
It may be desirable to limit the output range of the DDS to a
narrow band of frequencies (for example, to achieve better jitter
performance in conjunction with a band pass filter). See “Use of
Narrowband Filter for High Performance” on Page 40 for more
information about this feature.
REF IN
R
The state of the output MUX is established by programming the
I/O Register Map. The default state is such that the ∆f values
pass through the HSA unaltered. In this mode, the output
sample rate is fS/P, the same as the sample rate of the digital loop
filter.
Phase
Detector
Loop
Filter
External
Reconstruction
Filter
S
Low Pass
Frequency
Limiter
NOTE: P is the divide ratio of the "P"-divider (see “Digital
Loop Filter” on Page 24) and fS is the DAC sample rate.
Alternatively, the MUX can be set to select the averaging path.
In this mode, a "block average" is performed on a sequence of
samples. The length of the sequence is determined by
programming the value of Y (a 4-bit number stored in the I/O
Register Map), and has a value of 2Y+1. In the "averaging" mode,
the output sample rate is given by fS/ (P∙2Y+1).
When the number of ∆f samples specified by Y has been
collected, the averaged result is delivered to a 2-stage pipeline.
The last stage of the pipeline contains the value that will be
delivered to the holdover control logic when a transition into
the holdover state occurs. The pipeline is a guarantee that the
averaged ∆f value delivered to the holdover control logic has not
been interrupted by the transition into the holdover state.
The pipeline provides an inherent delay of ∆t = P∙2Y+1/fS.
Hence, the DDS "hold" frequency is the average as it appeared
∆t to 2∆t seconds prior to entering the holdover state. Note that
the user has some control over the duration of ∆t because it is
dependent on the programmed value of Y.
OUTPUT FREQUENCY RANGE CONTROL
Under normal operating conditions, its output frequency is
dynamically changing in response to the output of the digital
loop filter. The loop filter can steer the DDS to any frequency
DDS/DAC
REF IN
R
Phase
Detector
S
Loop
Filter
DDS/DAC
External
Reconstruction
Filter
Band Pass
Figure 24: Application of the Frequency Limiter
RECONSTRUCTION FILTER
The origin of the output clock signal produced by the AD9549
is the combined DDS and DAC. The DAC output signal
appears as a sinusoid sampled at fS. The frequency of the
sinusoid is determined by the frequency tuning word (FTW)
that appears at the input to the DDS. The DAC output is
typically passed through an external reconstruction filter that
serves to remove the artifacts of the sampling process and other
spurs outside the filter bandwidth. The signal is then brought
back on-chip to be converted to a square wave that is routed
internally to the output clock driver or the 2x DLL multiplier.
Since the DAC constitutes a sampled system, its output must be
filtered so that the analog waveform accurately represents the
digital samples supplied to the DAC input. The unfiltered DAC
output contains the desired base band signal, which extends
from DC to the Nyquist frequency (fS/2). It also contains
Rev. PrA | Page 39 of 78
AD9549
Preliminary Technical Data
images of the base band signal that theoretically extend to
infinity. Notice that the odd images (shown in Figure 25 below)
are mirror images of the base band signal. Furthermore, the
entire DAC output spectrum is affected by a sin(x)/x response,
which is caused by the "sample and hold" nature of the DAC
output signal.
Magnitude
(dB)
0
-20
-40
Image 0
Image 1
primary
signal
Image 2
filter
response
Image 4
sin(x)/x
envelope
-60
-80
Image 3
spurs
f
-100
fS/2
fS
3fS/2
2fS
5fS/2
base band
Figure 25: DAC Spectrum vs. Reconstruction Filter Response
The response of the reconstruction filter should preserve the
base band signal (image 0), while completely rejecting all other
images. However, a practical filter implementation will
typically exhibit a relatively flat pass band that covers the
desired output frequency plus 20%, roll off as steeply as
possible, and then maintain significant (though not complete)
rejection of the remaining images.
Plot 14: Filtered DAC Output Using 7th order elliptical with Fc=186
MHz. Same Conditions as previous plot.
Since the DAC output signal serves as the feedback signal for
the digital PLL, the design of the reconstruction filter can have a
significant impact on the overall jitter performance. Hence,
good filter design and implementation techniques are
important for obtaining the best possible jitter results.
Use of Narrowband Filter for High Performance
A distinct advantage of the AD9549 architecture is its ability to
constrain the frequency output range of the DDS. This allows
the user to employ a narrow band reconstruction filter instead
of the low pass response shown above resulting in less jitter on
the output. For example, suppose that the nominal output
frequency of the DDS is 150MHz. One might then choose a
5MHz narrow band filter centered at 150MHz. By using the
AD9549's DDS frequency limiting feature, the user could
constrain the output frequency to 150MHz ± 4.9MHz (which
allows for a 100kHz margin at the pass band edges). This will
ensure that a feedback signal is always present for the digital
PLL. Such a design would be extremely difficult to implement
with conventional PLL architectures.
Plot 13: DAC Output without Reconstruction Filter.
fOUT=155.52 MHz. Sysclk=25 MHz.
Sysclk PLL = x40. Spur reduction disabled.
DPLL Loop Closed. Freq Span for Plot: 500 MHz.
Rev. PrA | Page 40 of 78
Preliminary Technical Data
AD9549
FDBK INPUTS
VDD
The FDBK pins serve as the input to the feedback path of the
digital PLL. Typically, these pins are used to receive the signal
generated by the DDS after it has been band-limited by the
external reconstruction filter.
FDBK_IN
Vb
~1pF
8K
REFA_IN
(or REFB_IN)
To Reference
Monitor and
Switching Logic
GND
~1pF
8K
A diagram of the FDBK input pins is provided here, which
includes some of the internal components used to bias the input
circuitry. Note that the FDBK input pins are internally biased
to a DC level of ~1V. Care should be taken to ensure that any
external connections do not disturb the DC bias, as this may
significantly degrade performance.
+
1pF
REFA_INB
(or REFB_INB)
15K
~1pF
FDBK_INB
VSS
To S-Divider
and Clock
Output Section
15K
VSS
~1pF
Figure 27: Reference Inputs
NOTE: Support for redundant reference clocks is achieved by
using the two Reference Clock receivers (REFA & REFB).
+
~1V
~2pF
VSS
Figure 26: Differential FDBK Inputs
In order to accommodate a variety of input signal conditions
the value of Vb is programmable via a pair of bits in the I/O
Register Map. Table 3 below gives the value of Vb for the bit
pattern in Register 040F.
REFERENCE INPUTS
Reference Clock Receiver
The Reference Clock receiver is the point at which the user
supplies the input clock signal that the Synchronizer will
synthesize into an output clock. The clock receiver circuit is
able to handle a relatively broad range of input levels as well as
frequencies from 8 kHz up to 750 MHz.
The following is a diagram of the REFA/B input pins, which
includes some of the internal components used to bias the input
circuitry. Note that the REF input pins are internally biased by
a DC source, Vb. Care should be taken to ensure that any
external connections do not disturb the DC bias, as this may
significantly degrade performance.
Rev. PrA | Page 41 of 78
Reference Bias Level
R040F[1:0]
Vb
00 (default)
AVDD3-800mV
01
AVDD3-400mV
10
AVDD3-1600mV
11
AVDD3-1200mV
Table 3: Setting of Input Bias Voltage (Vb)
AD9549
Preliminary Technical Data
SYSCLK INPUTS
Functional Description
The SysClk pins are where an external timebase is connected to
the AD9549 for generating the internal high frequency system
clock (fS).
The SysClk inputs can be operated in one of three modes: 1)
SysClk PLL Bypassed, 2) SysClk PLL Enabled with input signal
generated externally, or 3) Crystal Resonator with SysClk PLL
Enabled. A functional diagram of the system clock generator is
shown below.
frequency as the SysClk input signal, and the magnitude of the
sub-harmonic can be quite large. When employing the BED
care must be taken to ensure that the loop bandwidth of the
SysClk PLL Multiplier will adequately suppress the subharmonic.
The benefit offered by the BED depends on the magnitude of
the sub-harmonic, the loop bandwidth of the SysClk PLL
Multiplier, and the overall phase noise requirements of the
specific application. In many applications, the AD9549 clock
output is applied to the input of another PLL, and the subharmonic is often suppressed by the relatively narrow
bandwidth of the downstream PLL.
NOTE: Generally, the benefits of the Bipolar Edge Detector are
realized for SysClk input frequencies of 25MHz and above.
SysClk PLL Multiplier
Figure 28: System Clock Generator Block Diagram
The SysClk PLL multiplier path is enabled by a logic 0 (default)
in the PD SysClk PLL location of the I/O Register Map. The
SysClk PLL multiplier can be driven from the SysClk input pins
by one of two means depending on the logic level applied to the
1.8V CMOS CLKMODESEL pin. When CLKMODESEL=0, a
crystal can be connected directly across the SysClk pins. When
CLKMODESEL=1, the maintaining amp is disabled, and an
external frequency source (oscillator, signal generator, etc.) can
be connected directly to the SysClk input pins. Note that
CLKMODESEL=1 does not disable the system clock PLL.
When the SysClk PLL Multiplier path is employed, the
frequency applied to the SysClk input pins must be limited so as
not to exceed the maximum input frequency of the SysClk PLL
phase detector. A block diagram of the SysClk generator
appears in Figure 29 below.
When the SysClk PLL multiplier path is disabled, the AD9549
must be driven by a high frequency signal source (up to 1GHz).
The signal thus applied to the SysClk input pins becomes the
internal DAC sampling clock (fS) after passing through an
internal buffer.
Bipolar Edge Detector
The SysClk PLL Multiplier path offers an optional Bipolar Edge
Detector (BED). This block acts as a frequency doubler by
generating a pulse on each edge of the SysClk input signal. The
SysClk PLL Multiplier locks to the falling edges of this
regenerated signal.
The impetus for doubling the frequency at the input of the
SysClk PLL Multiplier is that an improvement in overall phase
noise performance can sometimes be realized. The main
drawback is that the BED output not a rectangular pulse with a
constant duty cycle even for a perfectly symmetric SysClk input
signal. This results in a sub-harmonic appearing at the same
Figure 29: Block Diagram of the SysClk PLL
The SysClk PLL Multiplier has a 1GHz VCO at its core. A
phase/frequency detector (PFD) and charge pump provide the
steering signal to the VCO in typical PLL fashion. The PFD
operates on the falling edge transitions of the input signal,
which means that the loop locks on the negative edges of the
reference signal. The charge pump gain is controlled via the
I/O Register Map by selecting one of three possible constant
current sources ranging from 125-375µA in 125µA steps. The
center frequency of the VCO is also adjustable via the I/O
Register Map and provides high/low gain selection. The
feedback path from VCO to PFD consists of a fixed divide-by-2
prescaler followed by a programmable divide-by-N block,
where 2 ≤ N ≤ 33. This limits the overall divider range to any
even integer from 4 to 66, inclusive. The value of N is
Rev. PrA | Page 42 of 78
Preliminary Technical Data
AD9549
programmed via the I/O Register Map via a 5-bit word that
spans a range of 0 to 31, but the internal logic automatically
adds a bias of 2 to the value entered, extending the range to 33.
Care should be taken when choosing these values so as to not
exceed the maximum input frequency of the Sysclk PLL phase
detector or bipolar edge detector. These values can be found in
the AC Electrical Characteristics section of this datasheet.
Sysclk
Multiplier
R1
Series
C1
Shunt
C2
<8
390Ω
1 nF
82 pF
10
470Ω
820pF
56 pF
20
1kΩ
390pF
27 pF
40 (default)
2.2kΩ
180 pF
10 pF
60
2.7kΩ
120 pF
5 pF
External Loop Filter (SysClk PLL)
The loop bandwidth of the SysClk Multiplier PLL can be
adjusted by means of three external components as shown in
the diagram below. The nominal gain of the VCO is
800MHz/V. The recommended component values are shown in
Table 4 below. They establish a loop bandwidth of
approximately 1.6MHz with the charge pump current set to
250µa. The default case is N=40, and assumes a 25MHz SysClk
input frequency and generates an internal DAC sampling
frequency (fS) of 1GHz.
Table 4: Recommended Loop Filter Values for a nominal 1.5MHz
Sysclk PLL loop Bandwidth
Detail of SysClk Differential Inputs
A diagram of the SysClk input pins is provided here. Included
are details of the internal components used to bias the input
circuitry. These components have a direct effect on the static
levels at the SysClk input pins. This information is intended to
aid in determining how best to interface to the device for a
given application.
Note that the SysClk PLL Bypassed and SysClk PLL Enabled
input paths are internally biased to a DC level of ~1V. Care
should be taken to ensure that any external connections do not
disturb the DC bias, as this may significantly degrade
performance. Generally, it is recommended that the SysClk
inputs be AC coupled to the signal source (except when using a
crystal resonator).
Figure 30: External Loop Filter for SysClk PLL
Rev. PrA | Page 43 of 78
AD9549
Preliminary Technical Data
Figure 31: Differential SysClk Inputs
Rev. PrA | Page 44 of 78
Preliminary Technical Data
AD9549
170 MHz, the 5th harmonic would normally be at 850 MHz.
However, because of the sampling process, this spur appears at
150 MHz, only 20 MHz away from the fundamental. Hence,
when attempting to reduce DAC spurs it is important to know
the actual location of the harmonic spur in the DAC output
spectrum based on the DAC sample rate so that its harmonic
number can be reduced.
HARMONIC SPUR REDUCTION
The most significant spurious signals produced by the DDS are
harmonically related to the desired output frequency of the
DDS. The source of these harmonic spurs can usually be traced
to the DAC, and the spur level is in the -60dBc range. This ratio
represents a level that is about 10 bits below the full-scale
output of the DAC (10 bits down is 2-10, or 1/1024).
The mechanics of performing harmonic spur reduction is
shown in figure below. It essentially consists of two additional
DDS cores operating in parallel with the original DDS. This
enables the user to reduce two different harmonic spurs from
the 2nd to the 15th with 9 bits of phase offset control (±π) and 8
bits of amplitude control.
To reduce such a spur would require combining the original
signal with a replica of the spur but offset in phase by 180°.
This idea is the foundation of the technique used to reduce
harmonic spurs in the AD9549. Since the DAC has 14-bit
resolution, a -60dBc spur can be synthesized using only the
lower 4 bits of the DAC full scale range. That is, the 4 LSBs can
create an output level approximately 60dB below the full scale
level of the DAC (commensurate with a -60dBc spur). This fact
gives rise to a means of digitally reducing harmonic spurs or
their aliased images in the DAC output spectrum by digitally
adding a sinusoid at the input of the DAC with similar
magnitude as the offending spur but shifted in phase to produce
destructive interference.
The dynamic range of the cancellation signal is further
augmented by a gain bit associated with each channel. When
this bit is set, the magnitude of the cancellation signal is
doubled by employing a 1-bit left-shift of the data. However,
the shift operation reduces the granularity of the cancellation
signal magnitude.
NOTE: Full-scale amplitude of a cancellation spur is
approximately -60dBc when the gain bit is a logic 0 and
approximately -54dBc when the gain bit is a logic 1.
Although the worst spurs tend to be harmonic in origin, the fact
that the DAC is part of a sampled system results in the
possibility of some harmonic spurs to appear in non-harmonic
locations in the output spectrum. For example, if the DAC is
sampled at 1 GHz and generates an output sinusoid of
DDS
DDS
Phase
O ffs e t
4 8 -b it A c c u m u la to r
Spur
C a n c e lla tio n
E n a b le
I-S e t
48
4 8 -b it
F re q u e n c y
T u n in g W o rd
(F T W )
16
48
48
19
D
Q
19
A n g le to
A m p litu d e
C o n v e rs io n
DDS+
14
0
1
14
DAC
(1 4 -b it)
DDS-
S y s C lk
C H 1 H a rm o n ic N u m b e r
C H 1 C a n c e lla tio n P h a s e O ffs e t
4
9
2 -C h a n n e l
H a rm o n ic
F re q u e n c y
G e n e ra to r
H e a d ro o m
C o rr e c tio n
0
CH1
C H 2 H a rm o n ic N u m b e r
C H 2 C a n c e lla tio n P h a s e O ffs e t
C H 2 C a n c e lla tio n M a g n itu d e
1
4
C H 1 G a in
9
0
CH2
C H 1 C a n c e lla tio n M a g n itu d e
S h ift
S h ift
1
C H 2 G a in
8
8
H a rm o n ic S p u r C a n c e lla tio n
Figure 32: Spur Reduction Technique
Rev. PrA | Page 45 of 78
AD9549
Preliminary Technical Data
OUTPUT CLOCK DRIVERS & 2X FREQUENCY
MULTIPLIER
bits in the I/O Register Map. The user may select one of two
sources under program control.
There are two output drivers provided by the AD9912. The
primary supports differential 1.8V HSTL output levels while the
secondary supports either 1.8V or 3.3V CMOS levels,
depending on whether Pin 37 is driven at 1.8 or 3.3V.
One source is the signal generated by the DDS after it has been
externally filtered and brought back on-chip. In this
configuration, the CMOS clock driver generates the same
frequency as appears at the output of the DDS.
The primary differential driver nominally provides an output
voltage with 100Ω load applied differentially (VDD-VSS=1.8V).
The source impedance of the driver is approximately 100Ω for
most of the output clock period; during transition between
levels, the source impedance reaches a maximum of about 500
ohms. The driver is designed to support output frequencies of
up to and beyond the OC-12 network rate of 622.08MHz.
NOTE: In this configuration, the DDS output frequency must
not exceed 50MHz.
The other source is the output of the feedback divider (Sdivider). In this configuration, the CMOS clock driver
generates the same frequency as the input reference after
optional prescaling by the R-divider (i.e., fCMOS=fR/R) which is
inherently limited to a maximum of 25 MHz.
The output clock may also be powered down by a control bit in
the I/O Register Map.
Primary 1.8V Differential HSTL Driver
FREQUENCY SLEW LIMITER
The DDS produces a sinusoidal clock signal that is sampled at
the system clock rate. This DDS output signal is routed off-chip
where it is passed through an analog filter and brought back onchip for buffering and, if necessary, frequency doubling. Where
possible, for the best jitter performance, it is recommended that
the upconverter be bypassed.
The AD9549 offers frequency slew limiting capability enabling
users to specify the maximum rate of frequency change that
appears at the output. The function is programmable via the
I/O Register Map. Program control a bit to enable/disable the
function (default condition is disable) and a register that sets the
desired slew rate.
The 1.8V HSTL output driver should be AC-coupled, with
100Ω termination at the destination. The driver design has low
jitter injection for frequencies in the range of 50 to 750 MHz.
Please refer to the AC Electrical Specifications for the exact
frequency limits.
The frequency slew limiter is located between the digital loop
filter and the CCI filter as shown in the diagram below.
2x Frequency Multiplier
The AD9549 may be configured (via the I/O Register Map)
with an internal 2x Delay Locked Loop (DLL) multiplier at the
input of the primary clock driver. The extra octave of frequency
gain allows the AD9549 to provide output clock frequencies
that exceed the range available from the DDS alone. These
settings are found in Registers 0010 and 0200.
The input to the DLL consists of the filtered DDS output signal
after it has been "squared up" by an integrated clock receiver
circuit. The DLL can accept input frequencies in the range of
200MHz to 400MHz.
Single-Ended CMOS Output
In addition to the high speed differential output clock driver,
the AD9549 provides an independent, single-ended output,
CMOS clock driver. It serves as a relatively low speed
(<50MHz) clock source. The origin of the signal generated by
the CMOS clock driver is determined by the appropriate control
Rev. PrA | Page 46 of 78
Figure 33: Frequency Slew Limiter
Preliminary Technical Data
AD9549
The frequency slew limiter sets a boundary on the rate of
change of the output frequency of the DDS. The frequency slew
limiting constant, KSLEW, is a 48-bit value stored in the I/O
Register Map. The value of the constant is determined by:
2 48+ PIO
K SLEW = round
2
f S
δf
δt
K MAX = floor
Where PIO is the value stored in the I/O Register Map for the
"P"-Divider, fS is the DAC sample rate, and δf/δt is the desired
frequency slew rate limitation. For example, suppose that
fS=1GHz, PIO=9 and δf/δt=5kHz/second, then:
(
)
48 + 9
K SLEW = round 2 9 2 5 ⋅ 10 3 = 721
(10 )
2
IO
( ) where
ρ=
65535
ρ
fS R
fR
R is the modulus of the feedforward divider and fR is the input
reference frequency.
The measurement error (ε) associated with the frequency
estimator depends on the choice of the measurement interval
parameter (K). These are related by:
ε=
The resulting slew rate can be calculated as:
f
δf
= K SLEW 48S+ P
δt
2
duration of the measurement, which is constrained to
Tmax=217/fS. If fS=1GHz, then this equates to ~131µs. The fact
that the measurement time is bounded by Tmax means there is a
limit to the largest value of K (KMAX) that can be used without
causing the counter to overflow. The value of KMAX is given by:
ρK
floor ( ρK )−1
−1
With a specified fractional error (ε0), only those values of K for
which ε ≤ ε0 result in a frequency estimate that meets the
requirements. A plot of ε versus K (for a given ρ) takes on the
general form shown below.
ε
The above example yields: δf/δt=5.003kHz/s
1
FREQUENCY ESTIMATOR
The AD9549 has a frequency estimation function that will
automatically set the DDS output frequency so that the
feedback frequency (fDDS/S) and the prescaled reference
frequency (fREF_IN/R) are matched within an error tolerance (ε0).
It’s primary purpose is to allow the PLL to quickly lock when
the reference frequency is not known. The error tolerance is
defined as a fractional error and is controlled by a 16-bit
programmable value (K) via the I/O Register Map.
ε bounded
by envelope
ε > ε0 for all K < K0
ε0
ε < ε0 for all K > K1
K
0
1
KLO
The precision of any frequency measurement is dependent on
two factors:
the timing resolution of the measurement device (δt)
ε < ε0 for some K
(K0 < K < K1)
K0
K1
216
KHI
Figure 34: Frequency Estimator ε vs. K
An iterative technique is necessary to determine the exact
values of K0 and K1. However, a closed form exists for a
conservative estimate of K0 (KLO) and K1 (KHI):
the duration of the measurement (Tmeas)
The frequency estimator uses fS as its measurement reference, so
δt=1/fS (i.e., δt=1ns for a 1GHz DAC sample rate). The
duration of the measurement is controlled by K, which
establishes a measurement interval that is K cycles of the
measured signal such that Tmeas=KR/fREF_IN.
[ (1 + )]
= ceil [ (1 + )]
K LO = ceil
ρ
K HI
ρ
The frequency estimator uses a 17-bit counter to accumulate
the number δt periods within the measurement interval. The
finite capacity of the counter puts an upper limit on the
Rev. PrA | Page 47 of 78
1
2
1
ε0
1
ε0
AD9549
Preliminary Technical Data
As an example, consider the system conditions specified below:
fS = 400MHz
fREF_IN = 155.52MHz
R=8
ε0=0.00005 (i.e., 50ppm)
These conditions yield KMAX=3185, which is the largest K value
that can be programmed without causing the frequency
estimator counter to overflow. With K=KMAX we find that
Tmeas=163.84µs and ε=30.2ppm. KMAX will generally (but not
always) yield the smallest value of ε, but this comes at the cost
of the largest measurement time (Tmeas).
If the measurement time must be reduced, then KHI can be used
instead of KMAX. This yields: KHI=1945, Tmeas=100.05µs, and
ε=39.4ppm.
The measurement time can be further reduced (though
marginally) by using K1 instead of KHI. K1 is found by solving
the ε ≤ ε0 inequality iteratively. To do so, start with K=KHI and
decrement K successively while evaluating the inequality for
each value of K. Stop the process the first time that the
inequality is no longer satisfied and add 1 to the value of K thus
obtained. The result is the value of K1. For the above example,
K1=1912, Tmeas=98.35µs, and ε=39.8ppm.
If a further reduction of the measurement time is necessary,
then K0 can be used. K0 is found in a manner similar to K1.
Start with K=KLO and increment K successively while evaluating
the inequality for each value of K. Stop the process the first
time that the inequality is satisfied. The result is the value of K0.
For the above example, K0=1005, Tmeas=51.70µs and ε=49.0ppm.
STATUS AND WARNINGS
Status Pins
Four pins (S1 – S4) are reserved for providing device status
information to the external environment. These four pins are
individually programmable (via the serial I/O port) as an OR'd
combination of six possible status indications. Each pin has a
dedicated group of control register bits that determine which
internal status flags are used to provide an indication on a
particular pin (as shown in the diagram below).
Internal
Status Flags
RefA LOR
0
RefA OOL
1
RefA Invalid
0
RefB LOR
1
RefB OOL
0
RefB Invalid
1
Ref LOR
Ref OOL
Ref Invalid
Phase Lock
Phase Lock Detect
Freq. Lock
Frequency Lock Detect
IRQ
IRQ
RefAB LOR
RefAB OOL
RefAB Invalid
RefAB
Phase Lock
Frequency Lock
IRQ
Status Pin Control Register
(1 of 4)
Figure 35: Status Pin Control
Rev. PrA | Page 48 of 78
Status Pin
(1 of 4)
Preliminary Technical Data
AD9549
Reference Monitor Status
In the case of reference monitoring status information, a pin
can be programmed for either RefA or RefB, but not both. In
addition, the OR'd output configuration allows the user to
combine multiple status flags into a single status indication. For
example, if both the LOR and OOL control register bits are true,
then the status pin associated with that particular control
register will give an indication if either the LOR or OOL status
flag is asserted for the selected reference (A or B).
Default DDS Output Frequency on Power-Up
The four Status Pins (S1-S4) provide a completely separate
function at power-up. They can be used to define the output
frequency of the DDS at power-up even though the I/O
Registers have not yet been programmed. This is made possible
because the status pins are designed with bi-directional drivers.
At power-up, internal logic initiates a reset pulse of about 10 ns.
During this time, S1-S4 briefly function as input pins, and can
be driven externally. Any logic levels thus applied are
transferred to a 4-bit register on the falling edge of the
internally initiated pulse. The falling edge of the pulse also
returns S1-S4 to their normal function as output pins. The same
behavior occurs when the RESET pin is asserted manually.
Setting up S1-S4 for default DDS start-up is accomplished by
connecting a resistor to each pin (either pull-up or pull-down)
to produce the desired bit pattern, yielding 16 possible states
that are used both to address an internal 8x16 ROM and to
select the SysClk Mode (see Table 5). The ROM contains eight
16-bit DDS frequency tuning words (FTWs), one of which is
selected by the state of the S1-S3 pins. The selected FTW is
transferred to the FTW0 register in the I/O Register Map
without the need for an "I/O_Update". This ensures that the
DDS generates the selected frequency even if the I/O registers
have not been programmed. The state of the S4 pin selects
whether the internal System Clock is generated by means of the
internal SysClk PLL multiplier or not (see the SysClk Input
section for details).
S4
S3
S2
S1
SysClk
Input
Mode
0
0
0
0
Xtal/PLL
0
0
0
0
1
Xtal /PLL
38.87939
0
0
1
0
Xtal /PLL
51.83411
0
0
1
1
Xtal /PLL
61.43188
0
1
0
0
Xtal /PLL
77.75879
0
1
0
1
Xtal /PLL
92.14783
0
1
1
0
Xtal /PLL
122.87903
0
1
1
1
Xtal /PLL
155.51758
1
0
0
0
Direct
0
1
0
0
1
Direct
38.87939
1
0
1
0
Direct
51.83411
1
0
1
1
Direct
61.43188
1
1
0
0
Direct
77.75879
1
1
0
1
Direct
92.14783
1
1
1
0
Direct
122.87903
1
1
1
1
Direct
155.51758
Status Pin
Output
Frequency
in MHz
Table 5: Default Power-up Frequency Options for 1 GHz System
Clock
Interrupt Request (IRQ)
The DDS output frequency listed in Table 5 assumes that the
internal DAC sampling frequency (fS) is 1GHz. These
frequencies scale 1:1 with fS, meaning that other startup
frequencies are available by varying the Sysclk frequency.
At startup, the internal frequency multiplier defaults to 40x
when the Xtal/PLL Mode is selected via the Status Pins.
Note: when using this mode, the digital PLL loop is still open,
and the AD9549 is acting as a frequency synthesizer. The
frequency dividers and DPLL loop filter must still be
programmed prior to closing the loop.
Any one of the four status pins (S1-S4) may be programmed as
an IRQ pin. If a status pin is programmed as an IRQ pin, then
the state of the internal IRQ flag appears on that pin. An IRQ
flag is internally generated based on the change of state of any
one of the internal status flags. The individual status flags are
routed to a read-only I/O register (Status Register) so that the
user may interrogate the status of any of these flags at any time.
Furthermore, each status flag is monitored for a change in state.
In some cases, only a change of state in one direction is
necessary (e.g., the Frequency Estimate Done flag), but in most
Rev. PrA | Page 49 of 78
AD9549
Preliminary Technical Data
cases, the status flags are monitored for a change of state in
either direction (see the diagram below).
Whether or not a particular state change is allowed to generate
an IRQ is dependent on the state of the bits in the IRQ Mask
Register. The user programs the mask to enable those events,
which are to constitute cause for an IRQ. If an unmasked event
occurs, it will trigger the IRQ latch and the IRQ Flag will be
asserted (active high). The state of the IRQ Flag is made
available externally via one of the programmable status pins
(see the Status Pins section of this document).
user can then read the IRQ Register any time after the
indication of an IRQ event (i.e., assertion of the IRQ Flag). By
noting the bits in the IRQ Register that is set, the cause of the
IRQ event can be determined.
Once the IRQ Register has been read, the user must set the IRQ
Reset bit in the appropriate control register via the serial I/O
port. This restores the IRQ Flag to its default state, clears the
IRQ status register, and resets the edge detection logic that
monitors the status flags in preparation for the next state
change.
The automatic assertion of the IRQ Flag causes the contents of
the Status Register to be transferred to the IRQ Register. The
IRQ Mask Register
Status
Flags
Edge
Detect
Edge
Detect
Edge
Detect
Edge
Detect
Edge
Detect
Edge
Detect
Edge
Detect
Edge
Detect
IRQ
Reg.
Edge
Detect
Edge
Detect
Edge
Detect
Status Register
IRQ Reset
Figure 36: Interrupt Request Logic
Rev. PrA | Page 50 of 78
Preliminary Technical Data
POWER-ON RESET
On initial power-up, the AD9549 internally generates a 75ns
RESET pulse. The pulse is initiated when both of the following
two conditions are met:
AD9549
The following sequence should be followed when changing
frequencies the AD9549:
1.
Open the loop and enter single tone mode via Register
0100.
The 3.3v supply is greater than 2.35± 0.1V
2.
Enter the new register settings.
The 1.8v supply is greater than 1.4± 0.05V
3.
Write 1E to Register 0012.
Less than 1 ns after RESET goes high, the S1-S4 configuration
pins go high impedance, and remain high impedance until
RESET is deactivated. This allows strapping and configuration
during RESET.
4.
Once the registered are loaded, the OOL (Out of
limits) and LOR (loss of reference) can be monitored
to insure that a valid reference signal is present on
RefA or RefB.
Because of this reset sequence, power supply sequencing isn’t
critical.
5.
If a valid reference is present, Register 0100 can be
reprogrammed to clear Single Tone Mode and lock the
loop.
6.
Automatic Holdover mode can now be used to make
the AD9549 immune to any disturbance on the
reference inputs.
AD9549 POWER UP AND PROGRAMMING
SEQUENCE
The following sequence should be followed when initializing
the AD9549:
Notes:
1.
Apply Power. The AD9549 will perform an internal
reset.
Attempting to lock the loop without a valid reference can put
the AD9549 into a state that requires a reset.
2.
IMPORTANT: Make sure the desired configuration
registers have Single Tone mode(R0100[5]) set, and
Lock Loop (R0100[0]) cleared. If the Lock Loop bit is
set on initial loading, the AD9549 will attempt to lock
the loop before it has been configured.
Automatic Holdover mode is not available unless the loop has
been successfully closed.
3.
Once the registered are loaded, the OOL (Out of
limits) and LOR (loss of reference) can be monitored
to insure that a valid reference signal is present on
RefA or RefB.
4.
If a valid reference is present, Register 0100 can be
reprogrammed to clear Single Tone Mode and lock the
loop.
5.
Automatic Holdover mode can now be used to make
the AD9549 immune to any disturbance on the
reference inputs.
If the user desires to open and close the loop manually, we
recommend writing 1E to Register 0012 prior to reclosing the
loop.
Rev. PrA
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©2007 Analog Devices, Inc. All rights reserved.
AD9549
Preliminary Technical Data
minimum, a ferrite bead should be used for isolation, with a
separate regulator being ideal.
POWER MANAGEMENT
The AD9549 features multiple power supplies, and their power
consumption varies with its configuration. This section covers
which power supplies can be grouped together, and how each
block’s power consumption varies with frequency.
The numbers quoted here are for comparison only. Please refer
to the spec table for exact numbers. With each group, bypass
caps of 1 uF in parallel with a 10 uF should be used.
The recommendations here are for typical applications, and an
application demanding the highest performance may require
additional power supply isolation.
3.3V SUPPLIES
Digital I/O (Pin 1) and VDDX_REF (Pin 14): These two 3.3V
supplies can be grouped together. The power consumption on
Pin 1 varies dynamically with serial port activity. Noise from
the serial port that couples into the reference input should be
filtered by the digital PLL.
AVDD3 (Pin 37): This is the CMOS driver supply. If the CMOS
driver will be used, this supply should be isolated from other
3.3V supplies to avoid a spur at the output frequency. The
power consumption is a function of the output frequency and
loading of this pin. If this supply will not be used, this supply
can be tied to other 3.3V supplies, and its consumption will be
less than 5 mA.
AVDD3 (Pins 46,47,49): These are 3.3V DAC power supplies
that typically consume about 25mA. At a minimum, a ferrite
bead should be used to isolate these from other 3.3V supplies,
with a separate regulator being ideal.
1.8V SUPPLIES
Digital Core (Pins 3,5,7): These Pins can be grouped together.
Their current consumption increases from about 160mA at a
system clock of 700 MHz to about 220mA a system clock of 1
GHz. There is also a slight (~5%) increase as Fout increases
from 50 MHz to 400 MHz.
VDD DAC Decoder (Pin 53): This 1.8V supply consumes about
20 to 40 mA. It is critical that this supply be well isolated from
other 1.8V supplies. At a minimum, a ferrite bead should be
used for isolation, with a separate regulator being ideal.
AVDD (Pins 11, 19, 23, 24, 36, 42, 45): These pins may be
grouped together and should be isolated from other 1.8V
supplies. At a minimum, a ferrite bead should be used for
isolation, with a separate regulator being ideal.
AVDD (Pin 25, 26, 29, 30): These pins may be grouped together
and should be isolated from other 1.8V supplies. At a
Rev. PrA | Page 52 of 78
Preliminary Technical Data
AD9549
OPERATION OF SERIAL CONTROL PORT
SERIAL CONTROL PORT
The AD9549 serial control port is a flexible, synchronous, serial
communications port that allows an easy interface with many
industry-standard microcontrollers and microprocessors. Single
or multiple byte transfers are supported, as well as MSB first or
LSB first transfer formats. The AD9549 serial control port can
be configured for a single bidirectional I/O pin (SDIO only) or
for two unidirectional I/O pins (SDIO/SDO).
SERIAL CONTROL PORT PIN DESCRIPTIONS
SCLK (serial clock) is the serial shift clock. This pin is an input.
SCLK is used to synchronize serial control port reads and
writes. Write data bits are registered on the rising edge of this
clock, and read data bits are registered on the falling edge. This
pin is internally pulled down by a 30 kΩ resistor to ground.
SDIO (serial data input/output) is a dual-purpose pin and acts
as input only or input/output. The AD9549 defaults to
bidirectional pins for I/O. Alternatively, SDIO can be used as a
unidirectional I/O pin by writing to the SDO active register at
00h<7> = 1b. In this case, SDIO is the input, and SDO is the
output.
SDO (serial data out) is used only in the unidirectional I/O
mode (00h<7> = 1) as a separate output pin for reading back
data. Bidirectional I/O mode (using SDIO as both input and
output) is active by default and (i.e. SDO enable register at
00h<7> = 0).
CSB (chip select bar) is an active low control that gates the read
and write cycles. When CSB is high, SDO and SDIO are in a
high impedance state. This pin is internally pulled up by a
100 kΩ resistor to 3.3V. It should not be left floating. See the
Operation of Serial Control Port section on the use of the CSB
in a communication cycle.
SCLK (PIN 64)
SDIO (PIN 63)
SDO (PIN 62)
CSB (PIN 61)
Framing a Communication Cycle with CSB
A communications cycle (a write or a read operation) is gated
by the CSB line. CSB must be brought low to initiate a
communication cycle.
CSB stall high is supported in modes where three or fewer bytes
of data (plus instruction data) are transferred (W1:W0 must be
set to 00, 01, or 10, see Table 6 below). In these modes, CSB can
temporarily return high on any byte boundary, allowing time
for the system controller to process the next byte. CSB can go
high on byte boundaries only and can go high during either
part (instruction or data) of the transfer. During this period, the
serial control port state machine enters a wait state until all data
has been sent. If the system controller decides to abort the
transfer before all of the data is sent, the state machine must be
reset by either completing the remaining transfer or by
returning the CSB low for at least one complete SCLK cycle (but
less than eight SCLK cycles). Raising the CSB on a non-byte
boundary terminates the serial transfer and flushes the buffer.
In the streaming mode (W1:W0 = 11b), any number of data
bytes can be transferred in a continuous stream. The register
address is automatically incremented or decremented (see the
MSB/LSB First Transfers section). CSB must be raised at the
end of the last byte to be transferred, thereby ending the stream
mode.
Communication Cycle—Instruction Plus Data
There are two parts to a communication cycle with the AD9549.
The first writes a 16-bit instruction word into the AD9549,
coincident with the first 16 SCLK rising edges. The instruction
word provides the AD9549 serial control port with information
regarding the data transfer, which is the second part of the
communication cycle. The instruction word defines whether
the upcoming data transfer is a read or a write, the number of
bytes in the data transfer, and the starting register address for
the first byte of the data transfer.
Write
AD9549
SERIAL
CONTROL
PORT
Figure 37: Serial Control Port
If the instruction word is for a write operation (I15 = 0b), the
second part is the transfer of data into the serial control port
buffer of the AD9549. The length of the transfer (1, 2, 3 bytes,
or streaming mode) is indicated by 2 bits (W1:W0) in the
instruction byte. The length of the transfer indicated by
(W1:W0) does not include the two-byte instruction. CSB can be
raised after each sequence of 8 bits to stall the bus (except after
the last byte, where it ends the cycle). When the bus is stalled, the
serial transfer resumes when CSB is lowered. Stalling on non-byte
boundaries resets the serial control port.
Rev. PrA | Page 53 of 78
AD9549
Preliminary Technical Data
There are three types of registers on the AD9549: buffered, live,
and read-only. Buffered (also referred to as mirrored) registers
require an IO_UPDATE to transfer the new values from a
temporary buffer on the chip to the actual register, and are
marked with an “M” in the column labeled “Type” of the
register map. Toggling the IO_UPDATE pin or writing a “1” to
the Register Update bit (R05h<0>) will cause the update to
occur. Since any number of bytes of data can be changed before
issuing an update command, the update simultaneously enables
all register changes since any previous update. Live registers do
not require IO_UPDATE and update immediately after being
written. Read-only registers ignore write commands, and are
marked “RO” in the “Type” column of the register map. The
“Type” column of the register map may also have an “AC,”
which indicates that the register is auto-clearing.
Read
If the instruction word is for a read operation (I15 = 1b), the
next N × 8 SCLK cycles clock out the data from the address
specified in the instruction word, where N is 1,2,3,4 as
determined by W1:W0. In this case, 4 is used for streaming
mode where 4 or more words are transferred per read. The data
read back is valid on the falling edge of SCLK.
The default mode of the AD9549 serial control port is
bidirectional mode, and the data read back appears on the
SDIO pin. It is possible to set the AD9549 to unidirectional
mode by writing the SDO enable register at 00h<7> = 0b, and in
that mode, the requested data appears on the SDO pin.
By default, a read request reads the register value that is
currently in use by the AD9549. However, setting R04h<0>=1
will cause the “buffered” registers to be read instead. The
buffered registers are the ones that will take effect during the
next IO_UPDATE.
instruction mode on power-up, and the 8-bit instruction mode
is not supported.
THE INSTRUCTION WORD (16 BITS)
The MSB of the instruction word is R/W, which indicates
whether the instruction is a read or a write. The next two bits,
W1:W0, indicate the length of the transfer in bytes. The final 13
bits are the address (A12:A0) at which to begin the read or write
operation.
For a write, the instruction word is followed by the number of
bytes of data indicated by Bits W1:W0, which is interpreted
according to Table 6.
A12:A0: These 13 bits select the address within the register map
that is written to or read from during the data transfer portion
of the communications cycle. The AD9549 uses all of the 13-bit
address space. For multi-byte transfers, this address is the
starting byte address.
W1
W0
Bytes to Transfer
(excluding the two-byte instruction)
0
0
1
0
1
2
1
0
3
1
1
Streaming Mode
Table 6: Byte Transfer Count
SDIO
SDO
CSB
SERIAL
CONTROL
PORT
UPDATE
REGISTERS
toggle
IO_UPDATE
pin
CONTROL REGISTERS
SCLK
REGISTER BUFFERS
MSB/LSB FIRST TRANSFERS
The AD9549 instruction word and byte data may be MSB first
or LSB first. The default for the AD9549 is MSB first. The LSB
first mode may be set by writing 1b to Register 00h<6>, and
requires that an I/O Update be executed. Immediately after the
LSB, first bit is set, all serial control port operations are changed
to LSB first order.
AD9549
CORE
Figure 38: Relationship Between Serial Control Port Register Buffers
and Control Registers of the AD9549
The AD9549 uses Addresses 00h to 509h. Although the
AD9549 serial control port allows both 8-bit and 16-bit
instructions, the 8-bit instruction mode provides access to five
address bits (A4 to A0) only, which restricts its use to the
address space 00h to 01F. The AD9549 defaults to 16-bit
When MSB first mode is active, the instruction and data bytes
must be written from MSB to LSB. Multi-byte data transfers in
MSB first format start with an instruction byte that includes the
register address of the most significant data byte. Subsequent
data bytes must follow in order from high address to low
address. In MSB first mode, the serial control port internal
address generator decrements for each data byte of the multibyte transfer cycle.
Rev. PrA | Page 54 of 78
Preliminary Technical Data
AD9549
When LSB_First = 1b (LSB first), the instruction and data bytes
must be written from LSB to MSB. Multi-byte data transfers in
LSB first format start with an instruction byte that includes the
register address of the least significant data byte followed by
multiple data bytes. The serial control port internal byte address
generator increments for each byte of the multi-byte transfer
cycle.
the LSB first mode is active, the serial control port register
address increments from the address just written toward 1FFFh
for multi-byte I/O operations.
Unused addresses are not skipped during multi-byte I/O
operations. The user should write the default value to a reserved
register, and should only write zeros to unmapped registers.
Note: It is more efficient to issue a new write command than
writing the default value to more than two consecutive reserved
(or unmapped) registers.
The AD9549 serial control port register address decrements
from the register address just written toward 0000h for multibyte I/O operations if the MSB first mode is active (default). If
MSB
LSB
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
R/W
W1
W0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Table 7: Serial Control Port, 16-Bit Instruction Word, MSB First
CSB
SCLK DON'T CARE
R/W W1 W0 A12 A11 A10 A9 A8
A7
A6 A5
A4 A3 A2
A1 A0
16-BIT INSTRUCTION HEADER
D7 D6 D5
D4 D3
D2 D1
REGISTER (N) DATA
D0
D7
D6 D5
D4 D3 D2
D1 D0
DON'T CARE
REGISTER (N – 1) DATA
05046-019
SDIO DON'T CARE
DON'T CARE
Figure 39: Serial Control Port Write—MSB First, 16-Bit Instruction, 2 Bytes Data
CSB
SCLK
DON'T CARE
R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
SDO DON'T CARE
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
16-BIT INSTRUCTION HEADER
REGISTER (N) DATA
REGISTER (N – 1) DATA
REGISTER (N – 2) DATA
Figure 40: Serial Control Port Read—MSB First, 16-Bit Instruction, 4 Bytes Data
Rev. PrA | Page 55 of 78
REGISTER (N – 3) DATA
DON'T
CARE
05046-020
SDIO
DON'T CARE
AD9549
Preliminary Technical Data
tDS
tHI
tS
tDH
CSB
DON'T CARE
SDIO
DON'T CARE
DON'T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
A6
A5
D4
D3
D2
D1
D0
DON'T CARE
05046-021
SCLK
tH
tCLK
tLO
Figure 41: Serial Control Port Write: MSB First, 16-Bit Instruction, Timing Measurements
CSB
SCLK
DATA BIT N
05046-022
tDV
SDIO
SDO
DATA BIT N– 1
Figure 42: Timing Diagram for Serial Control Port Register Read
CSB
SCLK DON'T CARE
A0 A1 A2 A3
A4
A5 A6 A7
A8
A9 A10 A11 A12 W0 W1 R/W D0 D1 D2 D3 D4
16-BIT INSTRUCTION HEADER
D5 D6
REGISTER (N) DATA
D7
D0
D1 D2
D3 D4 D5
D6
D7
REGISTER (N + 1) DATA
Figure 43: Serial Control Port Write—LSB First, 16-Bit Instruction, 2 Bytes Data
tS
tH
CSB
tCLK
tHI
SCLK
tLO
tDS
BI N
05046-040
tDH
SDIO
BI N + 1
Figure 44: Serial Control Port Timing—Write
Parameter
Description
Rev. PrA | Page 56 of 78
DON'T CARE
05046-023
SDIO DON'T CARE
DON'T CARE
Preliminary Technical Data
tDS
tDH
tCLK
tS
tH
tHI
tLO
AD9549
Setup time between data and rising edge of SCLK
Hold time between data and rising edge of SCLK
Period of the clock
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Table 8: Definitions of Terms Used Serial Control Port Timing Diagrams
Rev. PrA | Page 57 of 78
AD9549
Preliminary Technical Data
I/O REGISTER MAP
Table 9
Addr
(hex)
Type
1
Name
(short
description)
D7
D6
0000
D4
D3
Serial
Config
0001
Reserved
SDO
Active
LSB First
(buffered)
Soft RST
Part ID
RO
09
Serial
Options
AC
Read
Buffer
Reg
00
Register
Update
00
Digital PD
00
Power Down and Reset
Power
Down /
Enable
0011
Reserved
M, AC
Reset
M
PD HSTL
Driver
Enable
CMOS
Driver
Enable
Output
Doubler
PD
SysClk
PLL
PD RefA
PD RefB
Full PD
00
History
Reset
IRQ
Reset
FPFD
Reset
PD Fund
DDS
0020
CPFD
Reset
LF Reset
CCI
Reset
DDS
Reset
00
S Div2
Reset
R Div2
Reset
S Div
Reset
R Div
Reset
00
System Clock
0020
N-Divider
0021
Reserved
0022
PLL
Parameters
0023
PFD
Divider
N Divider [4:0]
12
00
VCO
Auto
Range
2x Reference
VCO
Range
Charge Pump Current
[1:0]
PFD Divider [3:0]
(relationship between SysClk and PFD clock)
0100
0100
18
02
0010
0013
Default
(hex)
00
0010
0012
D0
RO
0004
0005
D1
Long Inst.
Part ID
0003
D2
Serial Port Configuration and Part Identification
0000
0002
D5
04
05
DPLL
M
Single
Tone
Mode
PLL
Control
Disable
Freq.
Estimator
Enable
Freq Slew
Limiter
Loop
Polarity
Close
Loop
0101
30
00
R Divider [15:0]
0102
0103
00
R-Divider
Falling
Edge
Triggered
R Divider
/2
Rev. PrA | Page 58 of 78
00
Preliminary Technical Data
AD9549
0104
00
S Divider [15:0]
0105
00
S-Divider
Falling
Edge
Triggered
0106
0107
M
0108
M
0109
M
010A
M
010B
M
010C
M
010D
M
010E
M
010F
M
0110
M
0111
M
S Divider
/2
P-Divider
P Divider[4:0]
05
Alpha-0 [7:0]
00
Alpha-0 [11:8]
Alpha-1 [4:0]
00
00
Alpha-2 [2:0]
Beta-0 [7:0]
00
00
Beta-0 [11:8]
Loop
Coefficient
s
00
Beta-1 [2:0]
Gamma-0 [7:0]
00
00
00
Gamma-0 [11:8]
Gamma-1 [2:0]
00
00
0112
00
0113
00
0114
00
0115
RO
N/A
0116
RO
N/A
0117
RO
0118
RO
0119
RO
N/A
011A
RO
N/A
FTW
Estimate
FTW Estimate [47:0]
(read-only)
Rev. PrA | Page 59 of 78
N/A
N/A
AD9549
Preliminary Technical Data
011B
M
00
011C
M
00
011D
M
00
FTW Lower Limit [47:0]
011E
M
00
011F
M
00
0120
M
00
FTW Limits
0121
M
FF
0122
M
FF
0123
M
FF
FTW Upper Limit [47:0]
0124
M
FF
0125
M
FF
0126
M
7F
0127
M
00
0128
M
00
0129
M
00
Slew Limit
Frequency Slew Limit [47:0]
012A
M
00
012B
M
00
012C
M
00
012D
00
012E
00
Reserved
012F
00
0130
00
Rev. PrA | Page 60 of 78
Preliminary Technical Data
01A0
AD9549
Free-Run Mode
01A0
00
01A1
00
01A2
00
Reserved
01A3
00
01A4
00
01A5
00
01A6
M
00
01A7
M
00
01A8
M
FTW0
(Open Loop
Frequency
Tuning
Word)
00
FTW0 [47:0]
01A9
M
00
01AA
M
start-up
cond.
01AB
M
start-up
cond.
01AC01AD
M
Phase
(Open Loop
Only)
DDS Phase Word [15:0]
01C0
Reference Selector / Holdover
01C0
M
Automatic
Control
Holdover
Mode
01C1
M
Override
Enable
Line-Card
Mode
01C2
Averaging
Window
01C3
Reference
Validation
01C4
00
M,
AC
Disable
Recovery
Timer
Enable
Ref Input
Override
Automatic
Selector
Automatic
Recover
Automatic
Holdover
00
Ref_AB
Enable
Holdover
Override
Holdover
On/Off
00
FTW Windowed Average Size [3:0]
00
Recovery Timer [4:0]
00
Ref
Validation
(continued)
Validate
RefA *
Validate
RefB *
00
* R01C4<1> is not auto-clear, and should be cleared immediately after setting. R01C4<0> is auto clear for both validate bits.
0200
Doubler and Output Drivers
0200
HSTL Driver
0201
CMOS
Driver
OPOL
(polarity)
HSTL Output Doubler
CMOS
MUX
Rev. PrA | Page 61 of 78
05
00
AD9549
Preliminary Technical Data
0300
0300
Monitor
RO
Status
PFD Freq
too High
PFD Freq
too Low
Freq. Est.
Done
0301
RO
RefA
Valid
RefA LOR
RefA
OOL
0302
RO
PFD Freq
too High
PFD Freq
too Low
Freq. Est.
Done
RefA
Valid
RefA LOR
RefA
OOL
IRQ Status
0303
RO
Ref
Selected
Ref
Selected
0304
0305
IRQ Mask
Free Run
Ph. Lock
Detected
Freq. Lock
Detected
N/A
RefB
Valid
RefB
LOR
RefB OOL
N/A
Free Run
Ph. Lock
Detected
Freq. Lock
Detected
00
RefB
Valid
RefB
LOR
RefB OOL
00
Ref.
Changed
Leave
Free Run
Enter Free
Run
00
Freq Est
Done
Phase
Unlock
Phase
Lock
Freq.
Unlock
Freq. Lock
00
0306
RefA
Valid
!RefA
Valid
RefA LOR
!RefA
LOR
RefA
OOL
!RefA
OOL
00
0307
RefB
Valid
!RefB
Valid
RefB LOR
!RefB
LOR
RefB
OOL
!RefB
OOL
00
0308
S1 Pin
Config
Ref?
Ref? LOR
Ref? OOL
Ref? Not
Valid
Phase
Lock
Freq.
Lock
IRQ
60
0309
S2 Pin
Config
Ref?
Ref? LOR
Ref? OOL
Ref? Not
Valid
Phase
Lock
Freq.
Lock
IRQ
E0
030A
S3 Pin
Config
Ref?
Ref? LOR
Ref? OOL
Ref? Not
Valid
Phase
Lock
Freq.
Lock
IRQ
08
030B
S4 Pin
Config
Ref?
Ref? LOR
Ref? OOL
Ref? Not
Valid
Phase
Lock
Freq.
Lock
IRQ
01
030C
Control
Enable
RefA LOR
Enable
RefA
OOL
Enable
RefB LOR
Enable
RefB
OOL
Enable
Freq. Lock
Detector
A2
Enable
Phase
Lock Det.
030E
RO
N/A
030F
RO
N/A
0310
RO
HFTW
Average or Instantaneous FTW [47:0]
(read-only)
N/A
(An IO_UPDATE is required to refresh these registers.)
N/A
0311
RO
0312
RO
N/A
0313
RO
N/A
0314
M
FF
0315
M
00
Phase Lock Threshold [31:0]
0316
M
0317
M
0318
M
Phase Lock
00
00
Phase Unlock Watchdog Timer [2:0]
Rev. PrA | Page 62 of 78
Phase Lock Watchdog Timer [4:0]
FF
Preliminary Technical Data
0319
M
031A
M
031B
M
031C
M
031D
M
031E
M
AD9549
00
00
Frequency
Lock
Frequency Lock Threshold [31:0]
00
00
Frequency Unlock Watchdog Timer
[2:0]
Frequency Lock Watchdog Timer [4:0]
FF
FF
RefA LOR Divider [15:0]
031F
M
0320
M
FF
Loss of
Reference
FF
RefB LOR Divider [15:0]
0321
M
0322
M
FF
Reference
Out Of
Limits
00
RefA OOL Divider [15:0]
0323
M
00
0324
M
FF
0325
M
FF
RefA OOL Upper Limit [31:0]
0326
M
FF
0327
M
FF
0328
M
00
0329
M
00
RefA OOL Lower Limit [31:0]
032A
M
00
032B
M
00
032C
M
00
RefB OOL Divider [15:0]
032D
M
00
032E
M
FF
032F
M
FF
RefB OOL Upper Limit [31:0]
0330
M
FF
0331
M
FF
Rev. PrA | Page 63 of 78
AD9549
0332
M
0333
M
Preliminary Technical Data
00
00
RefB OOL Lower Limit [31:0]
0334
M
00
0335
M
00
0400
Calibration (User Accessible Trim)
0400
00
K Divider
K Divider [15:0]
0401
0402
00
M
CPFD Gain Scale [2:0]
00
CPFD Gain
0403
M
0404
CPFD Gain [5:0]
FPFD Gain
20
FPFD Gain [7:0]
C8
0405
00
0406
00
Reserved
0407
00
0408
00
0409
M
DPLL Phase Offset [7:0]
00
PFD Offset
040A
040B
040C
M
DPLL Phase Offset [13:8]
DAC FS
Current
00
DAC Full-scale Current [7:0]
FF
DAC Full-scale Current
[9:8]
01
040D
Reserved
00
040E
Reserved
10
040F
Ref Bias
Level
0410
Reserved
DC Input Level [1:0]
00
00
Rev. PrA | Page 64 of 78
Preliminary Technical Data
AD9549
0500
Harmonic Spur Reduction
0500
M
0501
M
0502
M
0503
M
0504
M
0505
M
0506
M
0507
M
0508
M
0509
M
1
HSR-A
Enable
Gain
Spur A Harmonic [3:0]
00
Spur A Magnitude [7:0]
00
Spur A
00
Spur A Phase [7:0]
00
Spur A
Phase [8]
HSR-B
Enable
Gain
Spur B Harmonic [3:0]
00
00
Spur B Magnitude [7:0]
00
Spur B
00
Spur B Phase [7:0]
00
Spur B
Phase [8]
Types of Registers:
M: Mirrored (also called Buffered). This type of register needs an IO_UPDATE for the new value to take effect.)
RO: Read-Only
AC: Auto-clear
Rev. PrA | Page 65 of 78
00
AD9549
Preliminary Technical Data
I/O REGISTER DESCRIPTION
Serial Port Configuration (0000 – 0005)
0000; Serial Configuration; bits D4 – D7 are mirror image of D0 – D3
[0] SDO Active: Enables SDO pin 1=SDO pin enabled (four-wire serial port mode.) 0= three-wire mode.
[1] LSB First: Sets bit order for serial port. 1=LSB first. 0=MSB first. IO_UPDATE must occur in order to take effect.
[2] Soft Reset: Resets register map except for register 0000. Setting this bit forces a soft reset, meaning that S1-S4 are not tristated, nor is their state read when this bit is cleared. The 9549 will assume the values of S1-S4 that were present during the last
hard reset. This bit is not self-clearing, and all other registers will be restored to their default values after a soft reset.
[3] Long Instruction: Read-only: this part only supports long instructions.
0001; Reserved
0002 - 0003; Part ID (read-only)
0004; Serial Options
[0] Read Buffer Register: For buffered registers, serial port read-back reads from actual (active) registers instead of the buffer.
1= Reads the buffered values that will take effect during the next IO_UPDATE.
0= Reads values that are currently in effect.
0005; Serial Options; Self Clearing
[0] Register Update: Software access to the “Register Update” pin function.
Writing a “1” to this bit is identical to performing an IO_UPDATE.
Power Down and Reset
0010; Power Down and Enables; Power up default is defined by start-up pins.
[0] Digital PD; Remove clock from most of digital section; leave serial port usable.
In contrast to Full PD, setting this bit does not de-bias inputs, allowing for quick wake-up.
[1] Full PD; Setting this bit is identical to activating the PD pin, and puts all blocks (except serial port) into power down mode.
Sysclk is turned off.
[2] PD RefB; Power down reference clock B input (and related circuits)
[3] PD RefA; Power down reference clock A input (and related circuits)
[4] PD System Clock PLL: System clock multiplier is powered down. 1= System Clock Multiplier powered down.
[5] Enable Output Doubler; Power up output clock generator doubler. Output Doubler must still be enabled in Register 0200.
[6] Enable CMOS Driver: Power up CMOS output driver. 1= CMOS Driver on.
[7] PD HSTL Driver: Power down HSTL output driver. 1 = HSTL Driver powered down.
0011; Reserved
Rev. PrA | Page 66 of 78
Preliminary Technical Data
AD9549
0012; Reset; Auto Clear; To reset the entire chip, the user may also use the (non-self clearing) Soft Reset bit in Register 0000.
Except for IRQ reset, the user normally would not need to use these.
[0] DDS (Direct Digital Synthesis) Reset
[1] CCI (Cascaded Comb Integrator) Reset
[2] LF (Loop Filter) Reset
[3] CPFD (Coarse Phase Frequency Detector) Reset
[4] FPFD (Fine Phase Frequency Detector) Reset
[5] IRQ Reset: Clear IRQ signal and IRQ status monitor
[6] Unused
[7] History Reset: Setting this bit clears the FTW monitor and pipeline.
0013; Reset (continued); NOT Auto Clear.
[0] R Divider Reset: Synchronous (to R divider prescaler output) reset for integer divider
[1] S Divider Reset: Synchronous (to S divider prescaler output) reset for integer divider
[2] R Div2 Reset: Asynchronous reset for R prescaler
[3] S Div2 Reset: Asynchronous reset for S prescalar
[7] PD Fund DDS: Setting this bit powers down the DDS fundamental output, but not the spurs. It is used during tuning of the
Spur Killer circuit.
System Clock
0020; N Divider
[4:0] N Divider: These bits set the Feedback divider for System Clock PLL. There is a fixed /2 preceding this block, as well as a
an offset of 2 added to this value. Therefore, setting this register to 00000 translates to an overall feedback divider ratio of 4. See
Figure 29: Block Diagram of the SysClk PLL on Page 42.
0021; Reserved
0022; PLL Parameters
[1:0] Charge Pump Current: 00: 250 uA , 01: 375 uA, 10: Off, 11: 125 uA
[2] VCO Range: Select low range or high range VCO. 0= low range (700 to 800 MHz). 1= high range (850 to 1000 MHz). For
System clock settings in between 800-850 MHz, use the VCO Auto Range (Bit 7) to set the correct VCO range automatically.
[3] 2x Reference: Enables a frequency doubler prior to the Sysclk PLL and can be useful in reducing jitter induced by the Sysclk
PLL. See Figure 28: System Clock Generator Block Diagram, Page 42.
[4:6] Reserved
[7] VCO Auto Range: Automatic VCO range selection. Enabling this bit allows Bit 2 of this register to be set automatically.
Rev. PrA | Page 67 of 78
AD9549
Preliminary Technical Data
0023; PFD Divider
[3:0] Divide ratio for PFD clock from system clock. This is typically varied only in cases where the designer wishes to run the
DPLL Phase detector fast while Sysclk is run relatively slowly. The ratio is equal to PFD Divider * 4. For a 1 GHz system clock,
the ADC runs at 1 GHz / 20 = 50 MHz, and the DPLL phase detector runs at half this speed , which in this case is 25 MHz).
Digital PLL Control and Dividers
0100; PLL Control
[0] Close Loop: Setting this bit closes the loop. If Bit 4 of this register is cleared, then the frequency estimator will be used. If this
bit is cleared and the loop is opened, the user should reset the CCI and LF bits of Register 0012 prior to closing the loop again.
[1] Loop Polarity: This bit reverses the polarity of the loop response.
[2] Unused
[3] Enable Frequency Slew Limiter: This bit enables the frequency slew limiter that controls how fast the tuning word can
change, and is useful for avoiding runt and stretched pulses during clock switchover and holdover transitions. These values are
set in Registers 0127-012C. See “Frequency Slew Limiter” on Page 46.
[4] Disable Frequency Estimator. The Frequency Estimator is normally not used, but is useful when the input frequency is
unknown, or needs to be qualified. This estimate appears in Registers 115-11A. The Frequency Estimator is not needed when
FTW0 (Register 01A6-01AB) is programmed. See “Frequency Estimator“ on Page 47.
[5] Single Tone Mode: Setting this bit allows the 9549 to output a tone open loop using FTW0 as DDS tuning word. This bit
must be cleared when Bit 0 (Close Loop) is set. This is very useful in debugging when the signal coming into the AD9549 is
questionable or nonexistent.
[7:6] Reserved
0101 – 0102; R Divider (DPLL Feedforward Divider)
[15:0] Feedforward Divider (also called the Reference divider) of the DPLL. Divide Ratio: 1 – 65536. See “Feedforward Divider
(Divide-by-R)” on Page 23. If the desired feedfeedforward ratio is greater than 65536, or if the reference input signal on REF_A
or REF_B is greater than 400 MHz, then Bit 0, R103 must be set.
0103; R Divider (continued)
[0] Divide by 2: Setting this bit enables an additional /2 pre-scalar, effectively doubling the range of the Feedforward Divider. If
the desired feedfeedforward ratio is greater than 65536, or if the reference input signal on REF_A or REF_B is greater than 400
MHz, then this bit must be set.
[6:1] Unused
[7] Falling Edge Triggered: Setting this bit inverts the reference clock before R divider.
0104 – 0105; S Divider (DPLL Feedback Divider)
[15:0] Feedback Divider: Divide Ratio: 1 – 65536. If the desired feedback ratio is greater than 65536, or if the feedback signal on
FDBK_IN is greater than 400 MHz, then Bit 0, R106 must be set.
Rev. PrA | Page 68 of 78
Preliminary Technical Data
AD9549
0106; S Divider (continued)
[0] Divide by 2: Setting this bit enables an additional /2 pre-scalar. See “Feedback Divider (Divide-by-S)” on Page 23. If the
desired feedback ratio is greater than 65536, or if the feedback signal on FDBK_IN is greater than 400 MHz, then this bit must
be set. An example of this case is when the PLL is locking to an image of the DAC output that is above the Nyquist frequency.
[6:1] Unused
[7] Falling Edge Triggered: Setting this bit inverts the reference clock before the S divider.
Digital PLL Loop Filter
0107; P Divider
[4:0] Divide Ratio: Controls the ratio of DAC sample rate to loop filter sample rate. See “Digital Loop Filter” on Page 24.
Loop filter sample rate = DAC Sample rate / 2^(Divide Ratio[4:0]). For the default case of 1 GHz DAC sample rate, and
P Divider [4:0] of 5, the loop filter sample rate is 31.25 MHz. Note: The DAC sample rate is the same as System Clock.
0108 – 0109; Loop Coefficients (See ”Digital Loop Filter Coefficients” on Page 28.)
(Note : The AD9549 evaluation software will derive these values.)
[11:0] Alpha-0: Linear coefficient for “alpha” coefficient
010A; Loop Coefficients (continued)
[4:0] Alpha-1: Power of 2 multiplier for “alpha” coefficient
010B; Loop Coefficients (continued)
[3:0] Alpha-2: Power of 2 divider for “alpha” coefficient
010C – 010D; Loop Coefficients (continued)
[11:0] Beta-0: Linear coefficient for “beta” coefficient
010E; Loop Coefficients (continued)
[2:0] Beta-1: Power of 2 divider for “beta” coefficient
010F – 0110; Loop Coefficients (continued)
[11:0] Gamma-0: Linear coefficient for “gamma” coefficient
0111; Loop Coefficients (continued)
[2:0] Gamma -1: Power of 2 divider for “gamma” coefficient
0112 – 0114; Reserved
0115 – 011A; FTW Estimate (Read-Only)
[47:0] FTW Estimate: This is frequency estimate from frequency estimator circuit, and is informational only. It’s useful for
verifying the input reference frequency. See “Frequency Estimator“ on Page 47 for a description.
Rev. PrA | Page 69 of 78
AD9549
Preliminary Technical Data
011B – 0120; FTW Lower Limit
[47:0] FTW Lower Limit: Lowest DDS tuning word in closed loop mode. This feature is recommended when a bandpass
reconstruction filter is used. See “Output Frequency Range Control” on Page 39.
0121 – 0126; FTW Upper Limit
[47:0] FTW Upper Limit: Highest DDS tuning word in closed loop mode. This feature is recommended when a bandpass
reconstruction filter is used. See “Output Frequency Range Control” on Page 39.
0127 – 012C; Frequency Slew Limit
[47:0] Frequency Slew Limit: See “Frequency Slew Limiter” on Page 46.
012D – 0130; Reserved
Free-Run (Single-Tone) Mode
01A0 – 01A5; Reserved
01A6 – 01AB; FTW0
[47:0] FTW0: FTW (Frequency Tuning Word) for DDS when loop is not “closed” (see register 0100 bit 0)
Also used as the initial frequency estimate when the estimator is disabled (see register 0100 bit 4)
Note: The power up default is defined by startup pins S1-S4. See “Default DDS Output Frequency on Power-Up” on Page 49.
01AC – 01AD; Phase
[15:0] DDS Phase Word: Allows user to vary the phase of the DDS output. Active only when loop is not “closed.”
Reference Selector / Holdover
01C0; Automatic Control
[0] Automatic Holdover: Setting this bit permits state-machine to enter holdover (free-run) mode.
[1] Automatic Recover: Setting this bit permits state-machine to leave holdover mode.
[2] Automatic Selector: Setting this bit permits state-machine to switch the active reference clock input.
[3] Reserved
[4] Holdover Mode: This bit determines which Frequency Tuning Word (FTW) is used in Holdover Mode.
0: Use last FTW at time of holdover. 1: Use averaged FTW at time of holdover, which is the recommended setting. The number
of averages used is set in Register 01C2.
Rev. PrA | Page 70 of 78
Preliminary Technical Data
AD9549
01C1; Override
[0] Holdover On/Off: This bit controls the status of holdover when Bit 1 of this register is set.
[1] Enable Holdover Override: Setting this bit disables automatic holdover, and allows user to enter/exit holdover manually via
Bit 0 (see above). Setting this bit overrides the HOLDOVER pin.
[2] Ref_AB: This bit selects the input when Bit 3 of this register is set. 0 equals REF_A.
[3] Enable Ref Input Override: Setting this bit disables automatic reference switchover, and allows user to switch references
manually via Bit 2 of this register. Setting this bit overrides the REFSELECT pin.
[4] Enable Line-Card Mode: Enables line-card mode of reference switch MUX, which eliminates the possibility of a runt pulse
during switchover. See “Use of Line Card Mode to Eliminate Runt Pulses” on Page 35.
01C2; Averaging Window
[3:0] FTW Windowed Average Size: This register sets the number of FTWs (frequency tuning words) that are used for
calculating the average FTW. Bit 4 in Register 01C0 enables this feature.
The number of averages equals 2(FTW Windowed Average Size [3:0]). These samples are taken at the rate of (fs / 2^PIO).
01C3; Reference Validation
[4:0] Recovery Timer: The value in this register sets the time required to validate a reference after a LOR or OOL event before
the reference can be used as the DPLL reference. This circuit uses the digital loop filter clock (see Register 0107).
Validation time = Loop filter clock period * 2(Recovery Timer[4:0] +1) -1. Assuming power-on defaults, the recovery time varies from
32 ns (00000) to 137 sec (11111). If longer validation times are required, the user can make the P divider larger.
[6:5] Unused
[7] Disable Recovery Timer: Setting these bits disables the recovery timer and requires that references be manually validated.
(see Register 01C4)
01C4; Reference Validation (continued);
[0] Validate RefB: Mark RefB as valid either prior to the recovery timer or instead of the timer, and is enabled by setting Bit 7 in
Register 01C3. This bit is self-clearing, and the self-clearing operation will clear the Validate RefA bit.
[1] Validate RefA: Mark RefA as valid either prior to the recovery timer or instead of the timer, and is enabled by setting Bit 7 in
Register 01C3. This bit is not self-clearing. The user should set this bit, and then clear it.
Doubler and Output Drivers
0200; HSTL Driver
[2:0] HSTL Output Doubler: 01: Doubler disabled. 00: Doubler enabled.
[3:2] Unused
[4] OPOL: Output polarity: Setting this bit inverts the HSTL driver output polarity.
0201; CMOS Driver
[0] User MUX control: This bit allows the user to select whether the CMOS driver output is divided by the S Divider.
0: S divider input sent to CMOS driver. 1: S divider output sent to CMOS driver.
See Figure 8: Detailed Block Diagram on Page 22.
Rev. PrA | Page 71 of 78
AD9549
Preliminary Technical Data
Monitor
0300; Status: This register contains the status of the chip. This register is read-only and live update.
[0] Frequency Lock Detect: This flag indicates that the “Frequency Lock Detect” circuit has detected frequency lock.
[1] Phase Lock Detect: This flag indicates that the “Phase Lock Detect” circuit has detected phase lock.
[2] Free Run: DPLL is in holdover mode (free-run)
[3] Reference Selected: 0: Reference A is active. 1: Reference B is active.
[4] Frequency Estimator Done: True when the “Frequency Estimator” circuit has successfully estimated the input frequency. See
“Frequency Estimator” on Page 47.
[5] PFD Frequency too Low: This flag indicates that the Frequency Estimator failed and detected too low of a PFD frequency.
This bit is only relevant if the user is relying on the Frequency Estimator to determine the input frequency.
[6] PFD Frequency too High: This flag indicates that the Frequency Estimator failed and detected too high of a PFD frequency.
This bit is only relevant if the user is relying on the Frequency Estimator to determine the input frequency.
[7] Unused
0301; Status (continued): This register contains the status of the chip. This register is read-only and live update.
[0] RefB OOL: The “OOL” (Out of Limits) circuit has determined that Reference B is out of limits.
[1] RefB LOR: A “LOR” (Loss of Reference) has occurred on Reference B.
[2] RefB Valid: The Reference Validation circuit has successfully determined that Reference B is valid.
[3] Unused
[4] RefA OOL: The “OOL” (Out of Limits) circuit has determined that Reference A is out of limits.
[5] RefA LOR: A “LOR” (Loss of Reference) has occurred on Reference A.
[6] RefA Valid: The Reference Validation circuit has successfully determined that Reference A is valid.
[7] Unused
0302 – 0303; IRQ Status; These registers contain the chip status (Registers 0300 – 0301) at the time of IRQ.
These bits are cleared with an IRQ reset (see Register 0012, Bit 5).
0304; IRQ Mask
[0] Enter Free Run: Trigger IRQ when DPLL enters free-running (holdover) mode.
[1] Leave Free Run: Trigger IRQ when DPLL leaves free-running (holdover) mode
[2] Reference Changed: Trigger IRQ when active reference clock selection changes
[7:3] Unused
Rev. PrA | Page 72 of 78
Preliminary Technical Data
AD9549
0305; IRQ Mask (continued)
[0] Frequency Lock: Trigger IRQ on rising edge of “Frequency Lock” signal
[1] Frequency Unlock: Trigger IRQ on falling edge of “Frequency Lock” signal
[2] Phase Lock: Trigger IRQ on rising edge of “Phase Lock” signal
[3] Phase Unlock: Trigger IRQ on falling edge of “Phase Lock” signal
[4] Frequency Estimator Done: Trigger IRQ when the “Frequency Estimator” is done
0306; IRQ Mask (continued)
[0] !RefA OOL: Trigger IRQ on falling edge of reference A’s OOL
[1] RefA OOL: Trigger IRQ on rising edge of reference A’s OOL
[2] !RefA LOR: Trigger IRQ on falling edge of reference A’s LOR
[3] RefA LOR: Trigger IRQ on rising edge of reference A’s LOR
[4] !RefA Valid: Trigger IRQ on falling edge of reference A’s “Valid”
[5] RefA Valid: Trigger IRQ on rising edge of reference A’s “Valid”
[7:6] Unused
0307; IRQ Mask (continued)
[0] !RefB OOL: Trigger IRQ on falling edge of reference B’s OOL
[1] RefB OOL: Trigger IRQ on rising edge of reference B’s OOL
[2] !RefB LOR: Trigger IRQ on falling edge of reference B’s LOR
[3] RefB LOR: Trigger IRQ on rising edge of reference B’s LOR
[4] !RefB Valid: Trigger IRQ on falling edge of reference B’s “Valid”
[5] RefB Valid: Trigger IRQ on rising edge of reference B’s “Valid”
[7:6] Unused
Rev. PrA | Page 73 of 78
AD9549
Preliminary Technical Data
0308; S1 Pin Configuration (See “Status and Warnings” on Page 48.)
Note: The choice of input for a given pin must be all Ref A or all Ref B, and not a combination thereof.
[0] IRQ: Select “IRQ” signal for output on this pin
[1] Reserved
[2] Frequency Lock: Select “Frequency Lock” signal for output on this pin
[3] Phase Lock: Select “Phase Lock” signal for output on this pin
[4] Ref? Not Valid: Select either RefA (0) or RefB (1) “Not Valid” signal for output on this pin
[5] Ref? OOL: Select either RefA (0) or RefB (1) “OOL” signal for output on this pin
[6] Ref?: LOR: Select either RefA (0) or RefB (1) “LOR” signal for output on this pin
[7] Ref?: Choose either RefA (0) or RefB (1) for use with bits 4 – 6
0309; S2 Pin Configuration: Same as register 0308, except applies to pin S2
030A; S3 Pin Configuration: Same as register 0308, except applies to pin S3
030B; S4 Pin Configuration: Same as register 0308, except applies to pin S4
030C; Control
[0] Enable Frequency Lock Detector. Register 0319 must be set up to use this. See “Frequency Lock Detection” on Page 32.
[1] Enable Phase Lock Detector: Register 0314h-0318h must be set up to use this. See “Phase Lock Detection” on Page 31.
[3:2] Unused
[4] Enable RefB OOL: The RefB OOL limits are set up in Registers 032C to 0335.
[5] Enable RefB LOR: The RefA LOR limits are set up in Registers 0320 to 0321.
[6] Enable RefA OOL: The RefB OOL limits are set up in Registers 0322 to 032B.
[7] Enable RefA LOR: The RefB LOR limits are set up in Registers 031E to 031F.
030D; Unused
030E – 0313; HFTW; Read-Only
[47:0] Average or Instantaneous FTW: This read-only register is the output of FTW monitor. Average or Instantaneous is
determined by “Holdover Mode” (see Bit 4, Register 01C0). These registers must be manually refreshed by issuing an
IO_UPDATE.
0314 – 0317; Phase Lock
[31:0] Phase Lock Threshold: See “Phase Lock Detection” on Page 31.
0318; Phase Lock (continued)
[7:5] Phase Unlock Watchdog Timer : See “Phase Lock Detection” on Page 31.
[4:0] Phase Lock Watchdog Timer : See “Phase Lock Detection” on Page 31.
Rev. PrA | Page 74 of 78
Preliminary Technical Data
AD9549
0319 – 031C; Frequency Lock
[31:0] Frequency Lock Threshold: See “Frequency Lock Detection” on Page 32.
031D; Frequency Lock (continued)
[7:5] Frequency Unlock Watchdog Timer: See “Frequency Lock Detection” on Page 32.
[4:0] Frequency Lock Watchdog Timer: See “Frequency Lock Detection” on Page 32.
031E – 031F; Loss of Reference
[15:0] RefA LOR Divider: See “Loss of Reference” on Page 33.
0320 – 0321; Loss of Reference (continued)
[15:0] RefB LOR Divider: See “Loss of Reference” on Page 33.
0322 – 0323; Reference Out Of Limits (OOL)
[15:0] RefA OOL Divider: See “Reference Frequency Monitor” on Page 33.
0324 – 0327; Reference OOL (continued)
[31:0] RefA OOL Upper Limit: See “Reference Frequency Monitor” on Page 33.
0328 – 032B; Reference OOL (continued)
[31:0] RefA OOL Lower Limit: See “Reference Frequency Monitor” on Page 33.
032C – 032D; Reference OOL (continued)
[15:0] RefB OOL Divider: See “Reference Frequency Monitor” on Page 33.
032E – 0331; Reference OOL (continued)
[31:0] RefB OOL Upper Limit: See “Reference Frequency Monitor” on Page 33.
0332 – 0335; Reference OOL (continued)
[31:0] RefB OOL Lower Limit: See “Reference Frequency Monitor” on Page 33.
Calibration (User Accessible Trim)
0400 – 0401; K Divider
[15:0] K Divider: The K divider alters precision of frequency estimator circuit. See “Frequency Estimator” on Page 47.
0402; CPFD Gain
[2:0] CPFD Gain Scale: This register is the coarse phase frequency power of 2 multiplier (PDS). See “Phase Detector” on
Page 27. Note that the correct value for this register will be calculated by filter design software provided with the evaluation
board.
0403; CPFD Gain (continued)
[5:0] CPFD Gain: This register is the coarse phase frequency linear multiplier (PDG). See “Phase Detector” on Page 27. Note
that the correct value for this register will be calculated by filter design software provided with the evaluation board.
Rev. PrA | Page 75 of 78
AD9549
Preliminary Technical Data
0404; FPFD Gain
[7:0] FPFD Gain: This register is the fine phase frequency detector linear multiplier (alters charge-pump current). See “Fine
Phase Detector” on Page 27. Note that the correct value for this register will be calculated by filter design software provided with
the evaluation board.
0405 – 0408; Unused
0409 – 040A; PFD Offset
[13:0] DPLL Phase Offset: This register controls the static time offset of the PFD (Phase Frequency Detector) in closed-loop
mode. It has no effect when the DPLL is open.
040B; DAC Full-scale Current:
[7:0] DAC Full-scale Current: DAC Full-scale Current [7:0]. See “DAC Output” on Page 27.
040C; DAC Full-scale Current
[1:0] DAC Full-scale Current: DAC Full-scale Current [9:8]. See Register 040B.
040D – 040E; Unused
040F; Reference Bias Level
[1:0] DC Input Level for VDDX @ 3.3 V: This register sets the DC bias level for the reference inputs. The value should be chosen
such that VIH is as close as possible to (but not exceeding) 3.3V.
00: VDD3 – 800 mV
01: VDD3 – 400 mV
10: VDD3 – 1.6 V
11: VDD3 – 1.2 V
[7:2] Reserved
0410; Unused
Rev. PrA | Page 76 of 78
Preliminary Technical Data
AD9549
Harmonic Spur Reduction
0500; Spur A: See “Harmonic Spur Reduction” on Page 77.
[3:0] Spur A Harmonic 1 – 15
[5:4] Unused
[6] Amplitude Gain x2
[7] Harmonic Spur Reduction A Enable (HSR-A Enable)
0501 – 0502; Spur A (continued)
[7:0] Spur A Magnitude: Linear multiplier for Spur A magnitude
0503 – 0504; Spur A (continued)
[8:0] Spur A Phase: Linear offset for Spur A phase
0505; Spur B
[3:0] Spur B Harmonic: 1 – 15
[5:4] Unused
[6] Amplitude Gain x2
[7] Harmonic Spur Reduction B Enable (HSR-B Enable)
0506 – 0507; Spur B (continued)
[7:0] Spur B Magnitude: Linear multiplier for Spur B magnitude
0508 – 0509; Spur B (continued)
[8:0] Spur B Phase: Linear offset for Spur B phase
Rev. PrA | Page 77 of 78
AD9549
Preliminary Technical Data
OUTLINE DIMENSIONS
64-Lead Lead Frame Chip Scale Package [LFCSP]
9 x 9 mm Body
(CP-64-1)
Dimensions shown in millimeters
a
9.00
BSC SQ
0.60 MAX
0.60 MAX
8.75
BSCSQ
TOP
VIEW
1
33
32
PIN 1
INDICATOR
4.85
4.70 SQ*
4.55
EXPOSED PAD
(BOTTOM VIEW)
0.45
0.40
0.35
12 MAX
64
49
48
PIN 1
INDICATOR
1.00
0.85
0.80
0.30
0.25
0.18
16
17
7.50
REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
0.50 BSC
SEATING
PLANE
0.20REF
* COMPLIANT TO JEDEC STANDARDS MO-220-VMMD
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 45: Outline Dimensions
ORDERING GUIDE
Model
AD9549BCPZ1(when released)
AD9549XCPZ1 (prototypes)
1
Temperature Range
-40 to +85
-40 to +85
Z = Pb-free part.
©2007 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the property
of their respective owners.
PR06744-0-3/07(PrA)
Rev. PrA | Page 78 of 78
Package Description
64-lead LFCSP
64-lead LFCSP
Package Option