1 CY2081 Three-PLL General-Purpose EPROM-Programmable Clock Generator Features • Factory-EPROM configurable for quick availability and prototyping • General purpose clock synthesizer for all applications – such as modems, disk drives, CD-ROM drives, Video CD players, games, set-top boxes, data/telecommunications, etc. • Three independent configurable clock outputs • Outputs ranging from 500 kHz to 100 MHz (5V) and up to 80 MHz for 3.3V operation • Configurable output control pin (pin 8) can be used as an output enable, power-down, suspend or select line. • Phase-locked loop oscillator input derived from external crystal (10 MHz to 25 MHz) or external reference clock (1 MHz to 30 MHz) • 3.3V or 5V operation (factory configured) • 8-pin 150-mil packaging achieves minimum footprint for space-critical applications • Sophisticated internal loop filter requires no external components or manufacturing tweaks as commonly required with external filters Functional Description The CY2081 is a general-purpose clock synthesizer designed for use in applications such as modems, disk drives, CD-ROM drives, Video CD players, games, set-top boxes and data/telecommunications. This devices offers three configurable clock outputs in an 8-pin 150-mil SOIC package and can be config- ured to operate off either a 3.3V or 5V power supply. The on-chip reference oscillator is designed for 10 MHz to 25 MHz crystals. Alternatively, a reference clock between 1 MHz and 30 MHz can be used. The CY2081 also features an output control pin (pin 8), which can be configured as an output enable, power down, frequency select, or suspend input. This gives the user the ability to three-state the output, power down the device, change the CLKA output frequency during operation, or suspend any of the outputs. Asserting the PD input will result in all the PLLs and the outputs being shut down. The PLLs will have to re-lock when the PD input is deasserted. The CY2081 outputs three clocks: CLKA, CLKB, and CLKC, whose frequencies can possess any value within the specified range. Additionally, the reference frequency can be obtained on any output. Custom configurations with user-defined features and frequencies can be obtained by filling out the custom configuration form located at the back of this data sheet and contacting your local Cypress representative. The CY2081 can replace multiple Metal Can Oscillators (MCO) in a synchronous system, providing cost and board space savings to manufacturers. Hence, this device is ideally suited for applications that require multiple, accurate, and stable clocks synthesized from low-cost generators in small packages. A hard disk drive is an example of such an application. In this case, CLKA drives the PLL in the Read Controller, while CLKB and CLKC drive the MCU and associated sequencers. Consider using the CY2291, CY2292, or CY2907 for applications that require more than three output clocks. Logic Block Diagram Pin Configuration SOIC Top View CLKA GND XTALIN XTALOUT XTALIN Reference Oscillator 1 8 2 7 3 6 4 5 CLKA PLL 1 XTALOUT PLL 2 OE/PD/FS/SUSPEND VDD CLKC CLKB EPROMConfigurable Multiplexer and Divide Logic CLKB CLKC PLL 3 OE/PD/FS/SUSPEND Cypress Semiconductor Corporation Document #: 38-07136 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised September 26, 2001 CY2081 Pin Summary Name Number Description CLKA 1 Configurable Clock Output GND 2 Ground XTALIN[1] 3 Reference Crystal Input or External Reference Clock Input 4 Reference Crystal Feedback CLKB 5 Configurable Clock Output CLKC 6 Configurable Clock Output VDD 7 Voltage Supply XTALOUT [1,2] OE / PD / FS / SUSPEND 8 Output control pin; either active-HIGH Output Enable, active-LOW power down, CLKA Frequency Select, or active-LOW Suspend input Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Supply Voltage ............................................... –0.5V to +7.0V Junction Temperature...................................................150°C DC Input Voltage......................................–0.5V to VDD+0.5V Static Discharge Voltage ........................................... >2000V (per MIL-STD-883, Method 3015) Operating Conditions[3] Parameter Description VDD Supply Voltage TA Operating Temperature, Ambient CL Max. Load Capacitance per output fREF External Reference Crystal fREF Min. Max. Unit 4.5 (3.0) 5.5 (3.6) V 70 °C 25 (15) pF 10.0 25.0 MHz 1.0 30.0 MHz 0 [4, 5] External Reference Clock Electrical Characteristics VDD = 5V (3.3V) ±10%, TA = 0°C to +70°C Parameter Description Conditions VOH HIGH-Level Output Voltage IOH = –4.0 mA VOL LOW-Level Output Voltage IOL = 4.0 mA VIH HIGH-Level Input Voltage[6] Except Crystal Pins [6] VIL LOW-Level Output Voltage Except Crystal Pins IIH Input HIGH Current VIN = VDD – 0.5V IIL Input LOW Current VIN = 0.5V IOZ Output Leakage Current Three State Outputs [7] IDD VDD Supply Current IDDS VDD Power Supply Current in Power-down Mode VDD = VDD max. 5V (3.3V) operation, CL = 25 pF (15 pF) Min. Typ. Max. 2.4 Unit V 0.4 2.0 V V 0.8 V <100 150 µA <100 150 µA 250 µA 40 (24) 60 (40) mA 100 200 µA Power-down Active, 5V Operation Notes: 1. For best accuracy, use a parallel-resonant crystal, CL=17 pF. 2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to an external crystal). 3. Electrical parameters are guaranteed with these operating conditions. Values for 3.3V operation are shown in parentheses. 4. External input reference clock must have a duty cycle between 40% and 60%, measured at VDD/2. 5. Please refer to application note “Crystal Oscillator Topics” for information on AC-coupling the external input reference clock. 6. Xtal inputs have CMOS thresholds. 7. Load = max, typical configuration, fREF = 14.318 MHz. Specific configurations may vary. Document #: 38-07136 Rev. ** Page 2 of 6 CY2081 Switching Characteristics[8] Parameter Name Description Min. Typ. Max. Unit t1 Output Period Clock output range, 5V operation 10 [100 MHz] 2000 [500 KHz] ns t1 Output Period Clock output range, 3.3V operation 12.5 [80 MHz] 2000 [500 KHz] ns t1A Clock Jitter[9] Peak-to-peak period jitter,% of clock period (fOUT ≤ 4 MHz) <0.5 1 % t1B Clock Jitter[9] Peak-to-peak period jitter (4 MHz ≤ fOUT ≤ 16 MHz) <0.7 1 ns t1C Clock Jitter[9] Peak-to-peak period jitter (16 MHz < fOUT ≤ 50 MHz) <400 500 ps t1D Clock Jitter[9] Peak-to-peak period jitter (fOUT > 50 MHz) <250 350 ps Output Duty Cycle[10] Duty cycle for outputs, defined as t2 ÷ t1[11] fOUT > 66.67 MHz 40% 50% 60% Duty cycle for outputs, defined as t2 ÷ t1[11] fOUT ≤ 66.67 MHz 45% 50% 55% t3 Rise time Output clock rise time[12] at CL=25 pF (15 pF at 3.3V operation) 3 5 ns t4 Fall time Output clock fall time[12] at CL=25 pF (15 pF at 3.3V operation) 2.5 4 ns t5 Frequency Slew Rate Rate of change of frequency of CLKA 5 40 MHz/ ms t6 Power Up Stabilization Time < 25 50 ms Output clock stable time after power up 1 Switching Waveforms All Outputs Duty Cycle and Rise/Fall Time t1 t2 OUTPUT 2.4V 0.4V t3 2.4V 0.4V 3.3V 0V t4 Notes: 8. Guaranteed by design, not 100% tested. 9. Jitter varies with configuration. All standard configurations sample tested at the factory conform to this limit. For more information on jitter, please refer to the application note: “Jitter in PLL-Based Systems.” 10. Reference Output duty cycle depends on XTALIN duty cycle. 11. Measured at 1.4V. 12. Measured between 0.4V and 2.4V. Document #: 38-07136 Rev. ** Page 3 of 6 CY2081 Test Circuit VDD 7 0.1 µF OUTPUTS CLK output CLOAD 2 GND Customer Configuration Request Procedure The CY2081 is programmed at the wafer level, and is therefore only available as a factory programmed device. There is no field programming for the CY2081. For CY2081 programmed configurations, design opportunities must be 50 Ku per year in production. If the design opportunity does not meet the factory minimums, the design can be implemented using the CY2292 (3-PLLs, 16-SOIC, field programmable), or the CY22381 (3-PLLs, 8-SOIC, field programmable). For factory programmed samples, all requests must be submitted to your local Cypress FAE or sales representative. The method to use to request factory configurations is: Use CyClocks software. This software automatically calculates the output frequencies that can be generated by the CY2081 and provides a printout of final pinout. Output frequencies requested will be matched as closely as the internal PLL divider and multiplier options allow. This printout and the design entry file produced by CyClocks (<filename>.ENT) can be submitted (in electronic format) to your local FAE or sales representative. CyClocks software is available free of charge from the Cypress website (http://www.cypress.com) or from your local FAE or sales representative. Once the custom request has been processed you will receive a part number with a three-digit extension (e.g., CY2081SC-357) specific to the frequencies and pinout of your device. This will be the part number used for samples requests and production orders. Ordering Information Ordering Code Package Name Package Type Operating Range CY2081SC-XXX S8 8-Pin (150-Mil) SOIC 5.0V, Commercial[13] CY2081SL-XXX S8 8-Pin (150-Mil) SOIC 3.3V, Commercial[13] Note: 13. 0°C to +70°C CyClocks is a trademark of Cypress Semiconductor Corporation. Document #: 38-07136 Rev. ** Page 4 of 6 CY2081 Package Diagram 8-Lead (150-Mil) SOIC S8 51-85066-A Document #: 38-07136 Rev. ** Page 5 of 6 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY2081 Document Title: CY2081 Three-PLL General Purpose EPROM-Programmable Clock Generator Document Number: 38-07136 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 110245 10/28/01 SZV Change from Spec number: 38-00463 to 38-07136 Document #: 38-07136 Rev. ** Page 6 of 6