CYPRESS CY2213ZC-1

CY2213
High-Frequency Programmable PECL
Clock Generator
1CY2213
Features
Benefits
• Jitter peak-peak (TYPICAL) = 35 ps
High-accuracy clock generation
• LVPECL output
One pair of differential output drivers
• Default Select option
Phase-locked loop (PLL) multiplier select
• Serially-configurable multiply ratios
Eight-bit feedback counter and six-bit reference counter for high accuracy
• Output edge-rate control
Minimize electromagnetic interference (EMI)
• 16-pin TSSOP
Industry-standard, low-cost package saves on board space
• High frequency
125- to 400-MHz (-1) or to 500-MHz (-2) extended output range for high-speed
applications
• 3.3V operation
Enables application compatibility
Block Diagram
XIN
Xtal
Oscillator
XOUT
OE
PLL
CLK
xM
CLKB
S
SER CLK
SER DATA
Pin Configuration
CY2213
16-pin TSSOP
VDDX
1
16
S
VSSX
2
15
VDD
XOUT
3
14
VSS
XIN
4
13
CLK
VDD
5
12
CLKB
OE
6
11
VSS
VSS
7
10
VDD
8
9
SER CLK
SER DATA
Cypress Semiconductor Corporation
Document #: 38-07263 Rev. *E
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised May 23, 2003
CY2213
Pin Description
Pin Name
Pin Number
Pin Description
VDDX
1
3.3V Power Supply for Crystal Driver
VSSX
2
Ground for Crystal Driver
XOUT
3
Reference Crystal Feedback
XIN
4
Reference Crystal Input
VDD
5
3.3 V Power Supply (all VDD pins must be tied directly on board)
OE
6
Output Enable, 0 = output disable, 1 = output enable (no internal pull-up)
VSS
7
Ground
SER CLK
8
Serial Interface Clock
SER DATA
9
Serial Interface Data
VDD
10
3.3V Power Supply (all VDD pins must be tied directly on board)
VSS
11
Ground
CLKB
12
LVPECL Output Clock (complement)
CLK
13
LVPECL Output Clock
VSS
14
Ground
VDD
15
3.3V Power Supply (all VDD pins must be tied directly on board)
S
16
PLL Multiplier Select Input, Pull-up Resistor Internal
Frequency Table
S
0
1
M (PLL Multiplier)
x16
x8
Example Input Crystal Frequency
25 MHz
400 MHz
31.25 MHz
500 MHz
15.625 MHz
125 MHz
CY2213 Two-Wire Serial Interface
Introduction
The CY2213 has a two-wire serial interface designed for data
transfer operations, and is used for programming the P and Q
values for frequency generation. Sclk is the serial clock line
controlled by the master device. Sdata is a serial bidirectional
data line. The CY2213 is a slave device and can either read or
write information on the dataline upon request from the master
device.
Figure 1 shows the basic bus connections between master
and slave device. The buses are shared by a number of
devices and are pulled high by a pull-up resistor.
Serial Interface Specifications
Figure 2 shows the basic transmission specification. To begin
and end a transmission, the master device generates a start
signal (S) and a stop signal (P). Start (S) is defined as
switching the Sdata from HIGH to LOW while the Sclk is at
HIGH. Similarly, stop (P) is defined as switching the Sdata from
LOW to HIGH while holding the Sclk HIGH. Between these two
signals, data on Sdata is synchronous with the clock on the Sclk.
Data is allowed to change only at LOW period of clock, and
must be stable at the HIGH period of clock. To acknowledge,
drive the Sdata LOW before the Sclk rising edge and hold it
LOW until the Sclk falling edge.
Document #: 38-07263 Rev. *E
CLK,CLKB
Serial Interface Format
Each slave carries an address. The data transfer is initiated by
a start signal (S). Each transfer segment is 1 byte in length.
The slave address and the read/write bit are first sent from the
master device after the start signal. The addressed slave
device must acknowledge (Ack) the master device. Depending
on the Read/Write bit, the master device will either write data
into (logic 0) or read data (logic 1) from the slave device. Each
time a byte of data is successfully transferred, the receiving
device must acknowledge. At the end of the transfer, the
master device will generate a stop signal (P).
Serial Interface Transfer Format
Figure 2 shows the serial interface transfer format used with
the CY2213. Two dummy bytes must be transferred before the
first data byte. The CY2213 has only three bytes of latches to
store information, and the third byte of data is reserved. Extra
data will be ignored.
Page 2 of 10
CY2213
Rp
S d a ta
S clk
V DD
Rp
S d ata _ C
S d a ta _ C
S clk _ C
S d ata _ in
S clk _ in
S d ata _ in
S c lk _ in
M a ste r D e vice
S lav e D ev ice
Figure 1. Device Connections
S clk
S data
Start (S)
valid data
Stop (P)
Acknowledge
Figure
Serial Interface
Fig. 2.
2 Serial
Interface Specifications
Specifications
1 bit
7 bits
S
Slave Address
Data 1
1 bit
Ack
8 bits
R/W
1 bit
8 bits
Ack
1 bit
Dummy Byte 0
8 bits
1 bit
Ack Dummy Byte 1 Ack
8 bits
1 bit
Data 0
Ack
P
1 bit
Figure 3. CY2213 Transfer Format
Serial Interface Address for the CY2213
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
0
1
0
1
0
Serial Interface Programming for the CY2213
b7
b6
b5
b4
b3
b2
b1
b0
Data0
QCNTBYP
SELPQ
Q<5>
Q<4>
Q<3>
Q<2>
Q<1>
Q<0>
Data1
P<7>
P<6>
P<5>
P<4>
P<3>
P<2>
P<1>
P<0>
Data2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
To program the CY2213 using the two-wire serial interface, set
the SELPQ bit HIGH. The default setting of this bit is LOW. The
P and Q values are determined by the following formulas:
Pfinal = (P7..0 + 3) * 2
Qfinal = Q5..0 + 2.
Document #: 38-07263 Rev. *E
If the QCNTBYP bit is set HIGH, then Qfinal defaults to a value
of 1. The default setting of this bit is LOW.
If the SELPQ bit is set LOW, the PLL multipliers will be set
using the values in the Select Function Table.
CyberClocks™ has been developed to generate P and Q
values for stable PLL operation. This software is downloadable
from www.cypress.com.
Page 3 of 10
CY2213
PLL Frequency = Reference x P/Q = Output
Reference
Q
Φ
Output
VCO
P
PLL
Figure 4. PLL Block Diagram
Absolute Maximum Conditions
The following table reflects stress ratings only, and functional
operation at the maximums are not guaranteed.
Parameter
Description
Min.
Max.
Unit
VDD,ABS
Max. voltage on VDD, or VDDX with respect to ground
–0.5
4.0
V
VI, ABS
Max. voltage on any pin with respect to ground
–0.5
VDD+0.5
V
Min.
Max.
Unit
10
31.25
MHz
Min.
Max.
Unit
3.00
3.60
V
Crystal Requirements
Requirements to use parallel mode fundamental xtal. External
capacitors are required in the crystal oscillator circuit. Please
refer to the application note entitled Crystal Oscillator Topics
for details.
Parameter
XF
Description
Frequency
DC Electrical Specifications
Parameter
Description
VDD
Supply voltage
TA
Ambient operating temperature
VIL
Input signal low voltage at pin S
VIH
Input signal high voltage at pin S
RPUP
Internal pull-up resistance
tPU
Power-up time for all VDDs to reach minimum specified voltage
(power ramps must be monotonic)
0
70
°C
0.35
VDD
0.65
VDD
10
100
kΩ
0.05
500
ms
Min.
Max.
Unit
AC Electrical Specifications
Parameter
Description
fIN
Input frequency with driven reference
1
133
MHz
fXTAL,IN
Input frequency with crystal input
10
31.25
MHz
CIN,CMOS
Input capacitance at S pin[1]
10
pF
3.3V DC Device Characteristics (Driving load, Figure 5)
Min.
Typ.
Max.
Unit
VOH
Parameter
Output high voltage, referenced to VDD
Description
–1.02
–0.95
–0.88
V
VOL
Output low voltage, referenced to VDD
–1.81
–1.70
–1.62
V
3.3V DC Device Characteristics (Driving load, Figure 6)
Min.
Typ.
Max.
Unit
VOH
Parameter
Output high voltage
Description
1.1
1.2
1.3
V
VOL
Output low voltage
0
0
0
V
Note:
1. Capacitance measured at freq. = 1 MHz, DC Bias = 0.9V, and VAC < 100 mV.
Document #: 38-07263 Rev. *E
Page 4 of 10
CY2213
State Transition Characteristics
Specifies the maximum settling time of the CLK and CLKB
outputs from device power-up. For VDD and VDDX any
sequences are allowed to power-up and power-down the
CY2213.
From
To
Transition Latency
Description
3 ms
Time from VDD/VDDX is applied and settled to CLK/CLKB outputs settled.
VDD/VDDX On CLK/CLKB Normal
AC Device Characteristics
Parameter
Description
tCYCLE
Clock cycle time
tJCRMS
Cycle-to-cycle RMS jitter
Min.
Max.
Unit
2.50 (400 MHz)
8.00 (125 MHz)
ns
0.25%
% tCYCLE
20
ps
At 125-MHz frequency
tJCPK
At 400-/500-MHz frequency
6.25/5
ps
Cycle-to-cycle jitter (pk-pk)
1.75%
% tCYCLE
At 125-MHz frequency
140
ps
At 200-MHz frequency, XF = 25 MHz
55
ps
At 400-/500-MHz frequency
tJPRMS
Period jitter RMS
At 125-MHz frequency
tJPPK
20
ps
ps
Period jitter (pk-pk)
2.0%
% tCYCLE
160
ps
65
ps
At 400-/500-MHz frequency
50/40
ps
Long term RMS Jitter (P < 20)
1.75%
% tCYCLE
140
ps
At 125-MHz frequency
At 400-/500-MHz frequency
Long term RMS Jitter (20 < P < 40)
At 125-MHz frequency
At 400-/500-MHz frequency
tJLT
% tCYCLE
6.25/5
At 200-MHz frequency, XF = 25 MHz
tJLT
ps
0.25%
At 400-/500-MHz frequency
At 125-MHz frequency
tJLT
43.75/35
Long-term RMS Jitter (40 < P < 60)
At 125-MHz frequency
At 400-/500-MHz frequency
Phase Noise
Phase Noise at 10 kHz (x8 mode) @ 125 MHz
DC
Long-term average output duty cycle
tDC,ERR
Cycle-cycle duty cycle error at x8 with
15.625-MHz input
tCR, tCF
Output rise and fall times (measured at 20% –
80% of VOHmin and VOLmax)
BWLOOP
PLL Loop Bandwidth
Document #: 38-07263 Rev. *E
43.75/35
ps
2.5%
% tCYCLE
200
ps
62.5/50
ps
3.5%
% tCYCLE
280
ps
87.5/70
ps
–107
–92
dBc
45
55
%
70
ps
100
400
ps
50 kHz (–3 dB)
8 MHz (–20 dB)
Page 5 of 10
CY2213
Functional Specifications
Crystal Input
The CY2213 receives its reference from an external crystal.
Pin XIN is the reference crystal input, and pin XOUT is the
reference crystal feedback. The parameters for the crystal are
given on page 5 of this data sheet. The oscillator circuit
requires external capacitors. Please refer to the application
note entitled Crystal Oscillator Topics for details.
Select Input
There is only one select input, pin S. This pin selects the
frequency multiplier in the PLL, and is a standard LVCMOS
input. The S pin has an internal pull-up resistor. The multiplier
selection is given on page 2 of this data sheet.
PECL Clock Output Driver
Figure 5 and Figure 6 show the clock output driver.
VDD
82Ω
82Ω
130Ω
Measurement Point
50Ω
PECL
Differential
Driver
50Ω
130Ω
130Ω
130Ω
Measurement Point
Figure 5. Output Driving Load (-1)
Measurement Point
62Ω
45Ω
PECL
Differential
Driver
45Ω
62Ω
45Ω
45Ω
Measurement Point
Figure 6. Output Driving Load (-2)
An alternative termination scheme can be used to drive a
standard PECL fanout buffer
VDD
135Ω
79Ω
Measurement Point
135Ω
50Ω
PECL
Differential
Driver
50Ω
79Ω
79Ω
79Ω
Measurement Point
Figure 7. Output Driving Load(-3)
Document #: 38-07263 Rev. *E
Page 6 of 10
CY2213
The PECL differential driver is designed for low-voltage,
high-frequency operation. It significantly reduces the transient
switching noise and power dissipation when compared to
conventional CMOS drivers. The nominal value of the channel
impedance is 50Ω. The pull-up and pull-down resistors provide
matching channel termination. The combination of the differential driver and the output network determines the voltage
swing on the channel. The output clock is specified at the
measurement point indicated in Figure 5 and Figure 6.
Input and Output voltage waveforms are defined as shown in
Figure 8. Rise and fall times are defined as the 20% and 80%
measurement points of VOHmin – VOLmax.
The device parameters are defined in Table 1. Figure 9 shows
the definition of long-term duty cycle, which is simply the CLK
waveform high-time divided by the cycle time (defined at the
crossing point). Long-term duty cycle is the average over
many (> 10,000) cycles. DC is defined as the output clock
long-term duty cycle.
Signal Waveforms
A physical signal that appears at the pins of the device is
deemed valid or invalid depending on its voltage and timing
relations with other signals. This section defines the voltage
and timing waveforms for the input and output pins of the
CY2213. The Device Characteristics tables list the specifications for the device parameters that are defined here.
Table 1. Definition of Device Parameters
Parameter
Definition
VOH, VOL
Clock output high and low voltages
VIH, VIL
VDD LVCMOS input high and low voltages
tCR, tCF
Clock output rise and fall times
VOHmin
80%
V(t)
20%
VOLmax
tCF
tCR
Figure 8. Voltage Waveforms
CLK
CLKB
tPW+
tCYCLE
DC = tPW+/tCYCLE
Figure 9. Duty CycleJitter
Jitter
This section defines the specifications that relate to timing
uncertainty (or jitter) of the input and output waveforms.
Figure 10 shows the definition of period jitter with respect to
the falling edge of the CLK signal. Period jitter is the difference
between the minimum and maximum cycle times over many
cycles (typically 12800 cycles at 400 MHz). Equal require-
Document #: 38-07263 Rev. *E
ments apply for rising edges of the CLK signal. tJP is defined
as the output period jitter.
Figure 11 shows the definition of cycle-to-cycle jitter with
respect to the falling edge of the CLK signal. Cycle-to-cycle
jitter is the difference between cycle times of adjacent cycles
over many cycles (typically 12800 cycles at 400 MHz). Equal
requirements apply for rising edges of the CLK signal. tJC is
defined as the clock output cycle-to-cycle jitter.
Page 7 of 10
CY2213
Figure 12 shows the definition of cycle-to-cycle duty cycle
error. Cycle-to-cycle duty cycle error is defined as the
difference between high-times of adjacent cycles over many
cycles (typically 12800 cycles at 400 MHz). Equal requirements apply to the low-times. tDC,ERR is defined as the clock
output cycle-to-cycle duty cycle error.
Figure 13 shows the definition of long-term jitter error.
Long-term jitter is defined as the accumulated timing error over
many cycles (typically 12800 cycles at 400 MHz). It applies to
both rising and falling edges. tJLT is defined as the long-term
jitter.
CLK
CLKB
tCYCLE
tJP = tCYCLE,max – tCYCLE, min. over many cycles
Figure 10. Period Jitter
CLK
CLKB
tCYCLE,i
tCYCLE, i+1
tJC = tCYLCE,i – tCYCLE,i+1 over many consecutive cycles
Figure 11. Cycle-to-cycle Jitter
CLK
Cycle i
Cycle i+1
CLKB
tPW+,i+1
tCYCLE,i+1
tPW+,i
tCYCLE, i+1
tDC,ERR = tPW+,i – tPW+,i+1 over many consecutive cycles
Figure 12. Cycle-to-cycle Duty Cycle Error
CLK
CLKB
tmin
tmax
tJLT = tmax – tmin over many cycles
Figure 13. Long-term Jitter
Document #: 38-07263 Rev. *E
Page 8 of 10
CY2213
Ordering Information
Ordering Code
Package Type
Operating Range
Operating Voltage
CY2213ZC-1
16-lead TSSOP
Commercial, to 400 MHz
3.3V
CY2213ZC-1T
16-lead TSSOP – Tape and Reel Commercial, to 400 MHz
3.3V
CY2213ZC-2
16-lead TSSOP
Commercial, to 500 MHz
3.3V
CY2213ZC-2T
16-lead TSSOP – Tape and Reel Commercial, to 500 MHz
3.3V
Package Drawing and Dimensions
16-Lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16
51-85091-**
CyberClocks is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the
trademarks of their respective holders.
Document #: 38-07263 Rev. *E
Page 9 of 10
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY2213
Document History Page
Document Title: CY2213 High-Frequency Programmable PECL Clock Generator
Document Number: 38-07263
REV.
Orig. of
ECN NO. Issue Date Change
Description of Change
**
113090
02/06/02
DSG
Change from Spec number: 38-01100 to 38-07263
*A
113512
05/24/02
CKN
Added PLL Block Diagram (Figure 4) and PLL frequency equation
*B
121882
12/14/02
RBI
Power-up requirements added to Operating Conditions
*C
123215
12/19/02
LJN
Previous revision was released with incorrect *A numbering in footer; *A should have
been *B (and was changed accordingly)
*D
124012
03/05/03
CKN
Added -2 to data sheet; edited line 3 of Benefits
*E
126557
05/27/03
RGL
Added 200-MHz Jitter Spec.
Added optional output termination
Document #: 38-07263 Rev. *E
Page 10 of 10