LINER LT3487EDD

LT3487
Boost and Inverting
Switching Regulator
for CCD Bias
DESCRIPTIO
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FEATURES
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The LT®3487 dual channel switching regulator generates
positive and negative outputs for biasing CCD imagers.
The device delivers up to –8V at 90mA and 15V at 45mA
from a lithium-ion cell, providing bias for many popular
CCD imagers. The boost regulator incorporates output
disconnect technology to eliminate the DC current path
from VIN to the output load that is present in standard
boost configurations. The 2MHz switching frequency
allows CCD solutions using tiny, low profile capacitors
and inductors and generates low noise outputs that are
easy to filter. Schottky diodes are internal and the output
voltages are set with one resistor per channel, reducing
the external component count.
Generates 15V at 45mA, –8V at 90mA from a
Li-Ion Cell
Output Disconnect
Sequencing: Positive Output Reaches Regulation
Before Negative Channel Begins Switching
Internal Schottky Diodes
2MHz Constant Switching Frequency
Requires Only One Resistor per Channel to Set
Output Voltages
VIN Range: 2.3V to 16V
Output Voltage Up to 28V
Short-Circuit Robust
Capacitor Programmable Soft-Start
Separate VBAT Pin Allows Separate Sources for
Power and Control Circuitry
Available in 10-Lead (3mm × 3mm) DFN Package
Intelligent soft-start allows sequential soft-start of the two
channels with a single capacitor. The soft-start is sequenced
such that the output ramp of the negative channel begins
after the ramp of the positive channel. Internal sequencing
circuitry also disables the negative channel until the positive
channel has reached 87% of its final value, ensuring that
the sum of the two outputs is always positive.
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APPLICATIO S
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CCD Bias
TFT LCD Bias
OLED Bias
±Rail Generation for Op Amps
The LT3487 is available in a 10-pin 3mm × 3mm DFN
package.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
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TYPICAL APPLICATIO
Conversion Efficiency
15µH
80
SWN
VBAT
VIN
1µF
SWP
70
CAP
FBP
47pF
4.7µF
15µH
22µF
100nF
549k
LT3487
DN
VNEG
–8V
90mA
POS CHANNEL AT CAP
75
EFFICIENCY (%)
2.2µF
VIN
3V TO 12V
10µH
POS CHANNEL
AT VPOS
65
NEG CHANNEL
60
55
50
FBN
324k
RUN/SS
100nF
RUN/SS
VPOS
15V
45mA
VPOS
GND
3487 TA01a
45
40
VIN = 3.6V
0
20
40
80
60
LOAD CURRENT (mA)
100
3487 TA01b
3487f
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LT3487
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ABSOLUTE
AXI U RATI GS
(Note 1)
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PACKAGE/ORDER I FOR ATIO
VIN Voltage ............................................................... 16V
VBAT Voltage ............................................................. 16V
SWP, SWN Voltage................................................... 32V
CAP, VPOS .................................................................30V
DN Voltage ............................................................. –32V
RUN/SS Voltage ..........................................................8V
FBP Voltage................................................................ 6V
FBN Voltage ................................................ –0.2V to 6V
Maximum Junction Temperature .......................... 125°C
Operating Temperature Range ................. –40°C to 85°C
Storage Temperature Range................... –65°C to 125°C
TOP VIEW
10 VPOS
CAP
1
SWP
2
VBAT
3
SWN
4
7 FBN
DN
5
6 VIN
9 FBP
11
8 RUN/SS
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
θJA = 43°C/W, θJC = 3°C/W
EXPOSED PAD (PIN 11) IS GND, MUST BE CONNECTED TO PCB
ORDER PART NUMBER
DD PART MARKING
LT3487EDD
LBXB
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, VBAT = 3.6V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
Operating Voltage Range
2.3
Quiescent Current
RUN/SS = 3V, Not Switching
RUN/SS = 0V
RUN/SS Voltage Threshold (Full Current)
(Note 3)
3.7
5.3
MAX
RUN/SS = 0V (Note 4)
UNITS
16
V
5
8
mA
µA
1.6
●
RUN/SS Voltage Threshold (Shutdown)
RUN/SS Pin Current
TYP
V
100
160
1
1.4
2
mV
µA
V
FBP (Positive Channel) Pin Voltage
●
1.19
1.23
1.27
FBN (Negative Channel) Pin Voltage
●
–7
3
12
FBP Pin Voltage Line Regulation
0.007
FBN Pin Voltage Line Regulation
mV
%/V
0.001
mV/V
FBP Pin Bias Current
●
24.4
25
25.6
µA
FBN Pin Bias Current
●
24.4
25
25.6
µA
87
90
%
2
2.15
FBP Threshold (Percent of Final Value)
to Start Negative Channel
Switching Frequency
1.85
MHz
●
87
93
%
Positive Channel Switch Current Limit
(Note 5)
●
750
920
mA
Negative Channel Switch Current Limit
(Note 5)
●
900
1090
mA
Positive Channel VCESAT
ISWP = 400mA
280
mV
Negative Channel VCESAT
ISWN = 600mA
340
mV
Maximum Duty Cycle
3487f
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LT3487
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, VBAT = 3.6V, unless otherwise noted.
PARAMETER
CONDITIONS
Schottky DP Forward Drop
ISWP = 400mA
MIN
1045
mV
Schottky DN Forward Drop
ISWN = 600mA
980
mV
Disconnect PNP VCE
IVPOS = 50mA
205
mV
MAX
UNITS
Disconnect Current Limit
VCAP = 15V, VPOS = 0V
VCAP – VBAT to Disconnect
VBAT = 3.6V, VPOS = 0V, ICAP < 100µA
1.2
1.6
V
Disconnect Leakage
VBAT = 3.6V, CAP = 3.6V, VPOS = 0V
0.1
1.0
µA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3487E is guaranteed to meet specified performance from
0°C to 85°C. Specifications over the –40°C to 85°C operating range are
assured by design, characterization and correlation with statistical process
controls.
100
TYP
155
mA
Note 3: Guaranteed by design, not directly tested.
Note 4: Current flows out of pin.
Note 5: Current limit guaranteed by design and/or correlation to static test.
Slope compensation reduces current limit at higher duty cycle.
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TYPICAL PERFOR A CE CHARACTERISTICS
Shutdown Quiescent Current
Positive Output to Enable Inverter
100
8
6
4
2
0
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
3487 G01
FBP Voltage
1.300
90
1.275
80
VFBP (V)
PERCENTAGE OF FINAL FBP VOLTAGE (%)
QUIESCENT CURRENT (µA)
10
1.250
70
1.225
60
50
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
3487 G02
1.200
–50
–25
75
0
25
50
TEMPERATURE (°C)
100
125
3487 G03
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LT3487
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TYPICAL PERFOR A CE CHARACTERISTICS
FBN Voltage
FBP Bias Current
10.0
FBN Bias Current
26.0
26.0
25.5
25.5
7.5
0
IFBN (µA)
2.5
IFBP (µA)
VFBN (mV)
5.0
25.0
25.0
–2.5
24.5
24.5
–5.0
–7.5
–10.0
–50 –25
0
50
75
25
TEMPERATURE (°C)
100
24.0
–50
125
–25
75
0
25
50
TEMPERATURE (°C)
3487 G04
300
200
100
100
200
300
400
500
SWITCH CURRENT (mA)
500
400
300
200
100
0
0 100 200 300 400 500 600 700 800 900
SWITCH CURRENT (mA)
600
3487 G07
100
500
400
300
200
100
0
600 650 700 750 800 850 900 950 1000
SCHOTTKY FORWARD DROP (mV)
3487 G09
Output Disconnect Voltage Drop
(50mA Load)
Maximum Disconnect Current
300
800
125
600
3487 G08
Negative Channel Schottky I-V
Characteristic
140
700
VCAP – VPOS = 500mV
TA = 25°C
120
250
500
400
300
100
ICAP (mA)
600
VCAP – VPOS (mV)
NEGATIVE SCHOTTKY FORWARD CURRENT (mA)
75
0
25
50
TEMPERATURE (°C)
Positive Channel Schottky I-V
Characteristic
POSITIVE SCHOTTKY FORWARD CURRENT (mA)
NEGATIVE SWITCH SATURATION VOLTAGE (mV)
POSITIVE SWITCH SATURATION VOLTAGE (mV)
400
–25
3487 G06
Negative Channel Switch VCE(SAT)
500
0
24.0
–50
125
3487 G05
Positive Channel Switch VCE(SAT)
0
100
200
60
40
150
200
80
20
100
0
600 650 700 750 800 850 900 950 1000
SCHOTTKY FORWARD DROP (mV)
3487 G10
100
–50
–25
75
0
25
50
TEMPERATURE (°C)
100
125
0
0
2.5
5
7.5
10
12.5
VCAP – VBAT (V)
3487 G11
3487 G20
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LT3487
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TYPICAL PERFOR A CE CHARACTERISTICS
Output Disconnect Current Limit
1150
CURRENT LIMITS (mA)
150
125
1100
1050
1000
950
POS CHANNEL
900
–25
75
0
25
50
TEMPERATURE (°C)
100
800
–50 –25
125
800
P0S CHANNEL
600
400
200
850
100
–50
NEG CHANNEL
1000
NEG CHANNEL
175
CURRENT LIMIT (mA)
1200
1200
VCAP = 15V
VBAT = 3.6V
VPOS = 0V
CURRENT LIMITS (mA)
200
Switch Current Limits
vs Duty Cycle
Switch Current Limits
0
0
50
75
25
TEMPERATURE (°C)
100
3487 G12
0
125
20
40
60
DUTY CYCLE (%)
100
80
3487 G14
3487 G13
Switch Current Limits vs RUN/SS
Voltage (at 55% Duty Cycle)
RUN/SS Pin Current
vs VIN in Shutdown
RUN/SS Pin Current in Shutdown
1000
2.0
3.0
NEG CHANNEL
IRUN/SS (µA)
P0S CHANNEL
600
400
2.0
1.5
1.0
200
0
250
500
750 1000
RUN/SS (mV)
1250
1500
0
–50 –25
1.0
0.5
0
50
25
75
0
TEMPERATURE (°C)
100
3487 G15
125
2
4
6
8
10
VIN (V)
UVLO Voltage
12
14
16
3487 G17
3487 G16
RUN/SS Shutdown Threshold
2.5
300
250
2.4
VRUN/SS (mV)
0
1.5
0.5
UVLO (V)
CURRENT LIMITS (mA)
RUN/SS PIN CURRENT (µA)
2.5
800
2.3
2.2
200
150
100
2.1
2.0
–50
50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
3487 G18
0
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
125
3487 G19
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LT3487
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PI FU CTIO S
CAP (Pin 1): Disconnect-PNP Emitter and Positive Schottky
Cathode. Acts as an intermediate positive (boost) output.
Connect boost output capacitor to this pin.
VBAT (Pin 3): Battery Voltage. Connect this pin to the supply voltage for the boost inductor. The disconnect drive
current is returned to this pin. The disconnect operates
until CAP falls to 1.2V above VBAT.
RUN/SS (Pin 8): Run/Soft-Start Pin. Connect to an opendrain transistor. The transistor must sink 1.4µA from
RUN/SS. Pull RUN/SS below 100mV to shut down the chip.
Connect a capacitor from RUN/SS to ground to program
soft-start functionality. The soft-start will slowly bring the
boost channel into regulation and then slowly bring up
the inverter. RUN/SS must be above 1.6V to allow both
channels to reach full current. If soft-start is not required,
this pin can be driven with a logic signal, but the RUN/SS
voltage must remain below VIN.
SWN (Pin 4): Switch Pin for Negative (Inverter) Channel. Connect inverter input inductor and flying capacitor
here.
FBP (Pin 9): Feedback Pin for Boost. Connect boost
feedback resistor R1 from FBP to CAP. Choose R1 according to:
SWP (Pin 2): Switch Pin and Schottky Anode for Positive
Channel. Connect boost inductor to this pin.
DN (Pin 5): Anode of Internal Schottky for Inverter. Connect
inverter output inductor and flying capacitor here.
VIN (Pin 6): Input Supply Pin. VIN is used to power the
control circuitry of the LT3487. This pin must be locally
bypassed with an X5R or X7R type ceramic capacitor.
FBN (Pin 7): Feedback Pin for Inverter. Connect feedback
resistor R2 from this pin to VNEG. Choose R2 according
to:
R2 = –
VNEG
25µA
R1=
VPOS – 1.23
25µA
Pin voltage = 1.23V when regulated.
VPOS (Pin 10): Output Pin for Boost Channel. VPOS is
the collector of the output disconnect PNP. Connect the
boost load to VPOS. Connect capacitor C5 between CAP
and VPOS for stability.
Exposed Pad (Pin 11): GND. Tie directly to ground plane
through multiple vias under the package for optimum
thermal performance.
Pin voltage = 0V when regulated.
3487f
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LT3487
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BLOCK DIAGRA
L1
VBAT
CAP
2
R1
9
SWP
–
FBP
49.2k
+
A1
–
VCP
+
A2
DP
R
S
VBAT
6
CAP
X1
Q
Q1
VIN
DISCONNECT
PNP
Q3
C4
VBAT
C1
VREF
1.23V
VPOS
Σ
1.4µA
GND
RAMP
GENERATOR
49.2k
+
M1
8
RUN
RUN/SS
–
+
1
ANTISAT
C5
3
+
10
11
2MHz
OSCILLATOR
160mV
1.25V
C6
7
C7
R2
FBN
VBAT
+
–
A3
–
VCN
+
VNEG
L2
A4
SWN
R
X2
S
Q
4
Q2
C2
Σ
DN
DN
RAMP
GENERATOR
L3
VNEG
5
C3
3487 BD
Figure 1. Block Diagram
3487f
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LT3487
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APPLICATIO S I FOR ATIO
Operation
The LT3487 uses a constant frequency, current mode control scheme to provide excellent line and load regulation.
Operation can be best understood by referring to the Block
Diagram in Figure 1. At the start of each oscillator cycle,
the SR latch X1 is set, which turns on the power switch
Q1. A voltage proportional to the switch current is added
to a stabilizing ramp and the resulting sum is fed into the
positive terminal of the PWM comparator A2. When this
voltage exceeds the level at the negative input of A2, the
SR latch X1 is reset, turning off the power switch Q1. The
level at the negative input of A2 is set by the error amplifier
A1, and is simply an amplified version of the difference
between the feedback voltage and the reference voltage
of 1.23V. In this manner, the error amplifier sets the correct peak current level to keep the output in regulation.
If the error amplifier’s output increases, more current is
delivered to the output; if it decreases, less current is
delivered. The second channel is an inverting converter.
The basic operation is the same as the positive channel.
The SR latch X2 is also set at the start of each oscillator
cycle. The power switch Q2 is turned on at the same time
as Q1. Q2 turns off based on its own feedback loop, which
consists of error amplifier A3 and PWM comparator A4.
The reference voltage of this negative channel is ground.
Voltage clamps on VCP and VCN (not shown) enforce current
limit. Switching waveforms with typical load conditions
are shown in Figure 2.
The PNP Q3 is used as an output disconnect pass transistor.
Q3 disconnects the load from the input during shutdown.
The anti-sat driver keeps Q3 at the edge of saturation as
VSWP
20V/DIV
ILI
100mA/DIV
VSWN
20V/DIV
ISWN
100mA/DIV
VIN = 3.6V
VPOS = 15V, 25mA
VNEG = –8V, 50mA
200ns/DIV
Figure 2. Switching Waveforms
3487 F02
long as CAP is typically 1.2V and worst-case 1.6V (cold)
above the VBAT voltage. The drive current for the output
disconnect PNP is returned to the VBAT pin. This allows
the pass transistor to turn off when the CAP voltage
falls to less than 1.2V above VBAT. The VBAT pin allows
applications in which the power (inductors L1 and L2)
and internal control circuitry (VIN pin) are powered from
different sources.
Inductor Selection
A 10μH inductor is recommended for the LT3487 boost
channel. The inverting channel can use uncoupled 15μH
inductors, or coupled 10μH inductors. Small size and
high efficiency are the major concerns for most LT3487
applications. Inductors with low core losses and small
DCR (copper wire resistance) at 2MHz are good choices
for LT3487 applications. The inductor DCR should be on
the order of half of the switch on-resistance for its channel. Some inductors in this category with small size are
listed in Table 1.
Table 1. Recommended Inductors
PART NUMBER
DB318C-A997AS100M
CDRH3D18-100
CDRH2D18HP-100
CDRH3D23-100
CDRH2D18/HP-150
CDRH3D18-150
CDRH3D23-150
INDUCTANCE DCR
(μH)
(Ω)
10
0.18
10
10
10
15
15
15
0.205
0.245
0.117
0.345
0.301
0.191
CURRENT
RATING
(mA)
MANUFACTURER
580
Toko
www. tokoam.com
Sumida
900
www.sumida.com
850
850
700
750
700
Capacitor Selection
The small size of ceramic capacitors makes them suitable
for LT3487 applications. X5R and X7R types of ceramic
capacitors are recommended because they retain their
capacitance over wider voltage and temperature ranges
than other types such as Y5V or Z5U. A 1μF input capacitor is sufficient for most LT3487 applications. The output
capacitors required for stability depend on the application.
For the typical Li-Ion to +15V, –8V application, the positive
channel requires a 4.7μF output capacitor and the negative
channel requires at least 10μF of capacitance.
3487f
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LT3487
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APPLICATIO S I FOR ATIO
where L is the inductance, r is the resistance of the inductor
and C is the output capacitance. For low DCR inductors,
which is usually the case for this application, the peak
inrush current can be simplified as follows:
Table 2. Recommended Ceramic Capacitor Manufacturers
MANUFACTURER
Taiyo Yuden
Murata
Kemet
PHONE
(408) 573-4150
(814) 237-1431
(408) 986-0424
URL
www.t-yuden.com
www.murata.com
www.kemet.com
⎛ α π⎞
Inrush Current
The LT3487 uses internal Schottky diodes. When a supply voltage is abruptly applied to the VIN pin, the voltage
difference between VIN and VCAP generates inrush current
flowing from the input through the inductor L1 and the
internal Schottky diode DP to charge the boost output
capacitor C4. For the inverting channel, there is a similar
inrush current flowing from the input through the inductor
L2 path, charging the flying capacitor C2 and returning
through the internal Schottky diode DN. The maximum
current the Schottky diodes in the LT3487 can sustain is
2A. The selection of inductor and capacitor values should
ensure that the peak inrush current is below 2A. The peak
inrush current can be calculated as follows:
α
V – 0.6 ⎜⎝ – ω • 2 ⎟⎠
IP = IN
•e
L•ω
Table 3 gives inrush peak currents for some component
selections. Note that inrush current is not a concern if the
input voltage rises slowly.
Table 3. Inrush Peak Current
VIN (V)
5
5
3.6
3.6
3.6
R (Ω)
0.18
0.235
0.18
0.245
0.345
L (μH)
10
15
10
10
15
C (μF)
4.7
2.2
4.7
4.7
2.2
IP (A)
1.44
1.06
0.979
0.958
0.704
External Diode Selection
As stated previously, the LT3487 has internal Schottky
diodes. The Schottky diode, DP, is sufficient for most
step-up applications. However, for high current inverter
applications, a properly selected external Schottky diode in
parallel with DN can improve efficiency. For external diode
selection, both forward voltage drop and diode capacitance
need to be considered. Schottky diodes rated for higher
current usually have lower forward voltage drops and
larger capacitance, which can cause significant switching
losses at a 2MHz switching frequency. Some recommended
Schottky diodes are listed in Table 4.
⎛ ω⎞
V – 0.6 – ω •arctan⎜⎝ α ⎟⎠
⎡
⎛ ω⎞⎤
IP = IN
•e
• SIN ⎢ arctan ⎜ ⎟ ⎥
⎝ α⎠⎦
L•ω
⎣
r + 1.5
2 •L
1
r
ω=
–
L • C 4 • L2
α=
Table 4. Recommended Schottky Diodes
PART NUMBER
PMEG2010AEB
FORWARD CURRENT (mA)
1000
FORWARD VOLTAGE DROP (V)
0.51
DIODE CAPACITANCE
(pF at 10V)
7.5
CMDSH2-3
200
0.49
15
RSX051VA-30
500
0.35
30
ZHCS400
400
0.425
18
MANUFACTURER
Philips
www.semiconductors.
philips.com
Central Semiconductor
www.centralsemi.com
ROHM
www.rohm.com
Zetex
www.zetex.com
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LT3487
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APPLICATIO S I FOR ATIO
Setting the Output Voltages
Start Sequencing
The LT3487 has an accurate internal feedback resistor
that is trimmed to set the feedback currents to 25µA for
each channel. Only one resistor is needed to set the output
voltage for each channel. The output voltage can be set
according to the following formulas:
The LT3487 also has internal sequencing circuitry that
inhibits the negative channel from operating until the
feedback voltage of the boost channel reaches about 1.1V
(87% of the final voltage), ensuring that the sum of the
two outputs is always positive.
⎛ V – 1.23 ⎞
R1= ⎜ POS
⎝ 25µA ⎟⎠
R2 =
– VNEG
25µA
In order to maintain accuracy, high precision resistors are
preferred (1% is recommended).
Soft-Start
The LT3487 has a single soft-start control for both channels. The RUN/SS pin is fed by a 1.4μA current source.
The soft-start ramp can be programmed by connecting a
capacitor from the RUN/SS pin to ground. An open-drain
transistor should be used to pull the pin low to shut down
the LT3487. Once the transistor stops sinking the 1.4μA,
the capacitor begins to charge. The chip starts up when
the RUN/SS pin charges to 160mV. The VCP node voltage
follows the RUN/SS voltage as it continues to ramp up
to ensure slow start-up on the positive channel. The VCN
node follows the ramp voltage, down a VBE. This ensures
that the negative channel starts up after the positive, but
still has a slow ramping output to avoid large start-up
currents.
VRUN/SS
2V/DIV
VRUN/SS
2V/DIV
IIN
1A/DIV
VPOS
10V/DIV
IIN
500mA/DIV
VPOS
10V/DIV
VNEG
10V/DIV
VNEG
10V/DIV
500µs/DIV
3487 F03a
Figure 3a. VRUN/SS, VPOS, VNEG,
IIN with No Soft-Start Capacitor
There are two ways in which the negative channel may
start up, depending on the size of the soft-start capacitor.
If there is no soft-start capacitor, or a very small capacitor,
then the negative channel will start up when the positive
output reaches 87% of its final value. If a large enough
soft-start capacitor is used, then the RUN/SS voltage will
continue to clamp the negative channel past the point
where the positive channel is in regulation. Figure 3 shows
the start-up sequencing without soft-start, with a small
soft-start capacitor, and a large soft-start capacitor.
Output Disconnect
The output disconnect uses a PNP transistor with circuitry
that varies the base current such that the transistor is
consistently at the edge of saturation, thus yielding the
best compromise between VCE(SAT) and low quiescent
current. To remain stable, this circuit requires a bypass
capacitor connected between the VPOS pin and the CAP pin
or between the VPOS pin and ground. A ceramic capacitor
with a value of at least 0.1μF is a good choice. Figure 4
shows that the PNP can support load currents of 50mA
with a VCE less than 210mV. The disconnect transistor is
current limited to provide a maximum of 155mA in short
circuit.
VRUN/SS
2V/DIV
IIN
200mA/DIV
VPOS
10V/DIV
VNEG
10V/DIV
2ms/DIV
3487 F03b
Figure 3b. VRUN/SS, VPOS, VNEG,
IIN with a 10nF Soft-Start Capacitor
10ms/DIV
3487 F03c
Figure 3c. VRUN/SS, VPOS, VNEG, IIN
with a 100nF Soft-Start Capacitor
3487f
10
LT3487
U
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W
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APPLICATIO S I FOR ATIO
Choosing a Feedback Node
The positive channel feedback resistor, R1, may be connected to the VPOS pin or to the CAP pin (see Figure 5).
Regulating the VPOS pin eliminates the output offset resulting from the voltage drop across the output disconnect.
However, in the case of a short-circuit fault at the VPOS
pin, the LT3487 will switch continuously because the FBP
pin is low. While operating in this open-loop condition, the
rising voltage at the CAP pin is limited only by the current
limit of the output disconnect. Given worst-case parameters
this voltage may reach 18V in a Li-Ion application. Care
must be taken in high VIN applications when regulating
from the VPOS pin. When the short-circuit is removed, the
VPOS pin will bounce up to the voltage on the CAP pin,
potentially exceeding the programmed output voltage until
DISCONNECT SATURATION VOLTAGE (mV)
300
the capacitor voltages fall back into regulation. While this
is harmless to the LT3487, this should be considered in
the context of the external circuitry if short-circuit events
are expected. Regulating the CAP pin ensures that the
voltage on the VPOS pin never exceeds the set output voltage after a short-circuit event. However, this setup does
not compensate for the voltage drop across the output
disconnect, resulting in an output voltage that is slightly
lower than the voltage set by the feedback resistor. This
voltage drop (VDISC) can be accounted for when using
the CAP pin as the feedback node by setting the output
voltage according to the following formula (using VDISC
from Figure 4):
R1=
VPOS + VDISC – 1.23
25µA
VBAT
250
The VBAT pin is a new innovation in the LT3487 that allows
output disconnect operation in a wide range of applications. The VBAT pin allows the part to stay on until CAP is
less than 1.2V above VBAT. This ensures that the positive
bias doesn’t fall before the negative bias discharges. In
some applications it may be useful to power the inductors
from a different source than VIN. In this case, connect
VBAT to the source powering the inductors to allow proper
operation of the disconnect. For example, in an automotive
system there may already be a buck regulator producing
3.3V from a 12V battery. The LT3487 enables the user
to power VIN from the 3.3V rail, but power the VBAT pin
200
150
100
50
0
0
20
40
60
80
DISCONNECT CURRENT (mA)
100
2400 G31
Figure 4. VCE vs I of Output Disconnect
SWN
VBAT
VIN
SWP
SWN
CAP
VIN
FBP
DN
LT3487
DN
VBAT
SWP
CAP
LT3487
FBN
FBP
FBN
RUN/SS
VPOS
GND
VPOS
RUN/SS
VPOS
VPOS
GND
3487 F05
Figure 5. Feedback Connection Using the VPOS and CAP Pins
3487f
11
LT3487
U
W
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APPLICATIO S I FOR ATIO
and the inductors directly from the battery for higher efficiency. When the part goes into shutdown, the output
load is isolated from the 12V source as soon as the CAP
node falls to below VBAT plus 1.2V (13.2V in this case).
The VBAT pin is also useful in a system using a 2V supply
(such as a 2-cell alkaline battery), below the operating
range of the LT3487. A boost converter designed for low
voltage operation can provide 3.3V for the LT3487 VIN pin,
while the inductors and VBAT can still be powered from the
2V supply. In shutdown, the 3.3V supply will turn off, but
the output disconnect will still decouple the output load
as soon as CAP falls below 3.2V .
Board Layout Consideration
As with all switching regulators, careful attention must be
paid to the PCB board layout and component placement.
To maximize efficiency, switch rise and fall times are made
as short as possible. To prevent electromagnetic interference (EMI) problems, proper layout of the high frequency
switching path is essential. The voltage signals of the
SWP and SWN pins have rise and fall times of a few ns.
Minimize the length and area of all traces connected to
the SWP and SWN pins and always use a ground plane
under the switching regulator to minimize interplane
coupling. Recommended component placement is shown
in Figure 6.
VBAT
CAP
L1
C2
R2
C7
U1
R1
C8
C5
VNEG
C1
VPOS
C6
L3
FBP
C4
L1
M1
3487 F06
VIN
RUN
Figure 6. Recommended Component Placement
3487f
12
LT3487
U
TYPICAL APPLICATIO
+15V and –8V Boost and Inverting CCD Bias
L2
15µH
C2
2.2µF
VIN
3V TO 12V
SWN
L1
10µH
VBAT
SWP
CAP
VIN
C1
1µF
R1
549k
LT3487
DN
C5
100nF
FBP
C7 47pF
L3
15µH
VNEG
–8V
90mA
C4
4.7µF
FBN
R2 324k
RUN/SS
C3
22µF
RUN/SS
C6
100nF
VPOS
15V
45mA
VPOS
GND
3487 TA02a
C1: TAIYO YUDEN EMK212BJ105MG
C2: TAIYO YUDEN TMK212BJ225MG
C3: TAIYO YUDEN TMK325BJ226MM
C4: TAIYO YUDEN TMK316BJ475ML-TR
L1: TOKO DB318C-A997AS-100M
L2, L3: SUMIDA CDRH2D18/HP-150NC
VPOS Load Step Response
VNEG Load Step Response
VNEG
20mV/DIV
AC-COUPLED
VPOS
100mV/DIV
AC-COUPLED
–50mA
INEG
–90mA
IPOS 45mA
15mA
VIN = 3.6V
3487 TA02b
100µs/DIV
VIN = 3.6V
100µs/DIV
3487 TA02c
The positive channel’s response is stable, but slightly
underdamped. A phase lead capacitor (C8) can be added
to provide more ideal phase margin.
VPOS Load Step Response (with Phase Lead Capacitor)
VPOS
100mV/DIV
AC-COUPLED
CAP
C8
10pF
FBP
3487 TA02e
R2
549k
IPOS 45mA
15mA
VIN = 3.6V
100µs/DIV
3487 TA02d
3487f
13
LT3487
U
TYPICAL APPLICATIO S
+15V and –8V Low VIN CCD Bias
L2
15µH
C2
2.2µF
VIN
2.7V TO 5V
SWN
L1
10µH
VBAT
SWP
CAP
VIN
C1
1µF
C8
15pF
LT3487
DN
R1
549k
C5
100nF
FBP
C7 33pF
L3
15µH
VNEG
–8V
80mA
C4
4.7µF
FBN
R2 324k
RUN/SS
C3
22µF
RUN/SS
VPOS
15V
40mA
VPOS
C6
100nF
GND
3487 TA03
C1: TAIYO YUDEN EMK212BJ105MG
C2: TAIYO YUDEN EMK212BJ225MD-TR
C3: TAIYO YUDEN TMK325BJ226MM
C4: TAIYO YUDEN TMK316BJ475ML-TR
L1: TOKO DB318C-A997AS-100M
L2, L3: SUMIDA CDRH2D18/HP-150NC
+15V and –8V Boost and Charge Pump CCD Bias
L2
15µH
C2
2.2µF
VIN
3V TO 12V
SWN
L1
10µH
VBAT
C1
1µF
VNEG
–8V
90mA
R1
549k
LT3487
DN
D1
SWP
CAP
VIN
C5
100nF
FBP
C7 20pF
C4
4.7µF
FBN
R2 324k
RUN/SS
C3
10µF
RUN/SS
C6
100nF
VPOS
15V
45mA
VPOS
GND
3487 TA04
C1: TAIYO YUDEN EMK212BJ105MG
C2: TAIYO YUDEN TMK212BJ225MG
C3: TAIYO YUDEN EMK316BJ106ML
C4: TAIYO YUDEN TMK316BJ475ML-TR
D1: PHILIPS PMEG2010AEB
L1: TOKO DB318C-A997AS-100M
L2, L3: SUMIDA CDRH2D18/HP-150NC
3487f
14
LT3487
U
PACKAGE DESCRIPTIO
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
0.675 ±0.05
3.50 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
PACKAGE
OUTLINE
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
TYP
6
3.00 ±0.10
(4 SIDES)
0.38 ± 0.10
10
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
(DD10) DFN 1103
5
0.200 REF
1
0.75 ±0.05
0.00 – 0.05
0.25 ± 0.05
0.50 BSC
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
3487f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LT3487
U
TYPICAL APPLICATIO
+24V and –16V LCD Bias
L2
22µH
C2
2.2µF
VIN
3V TO 6V
SWN
L1
15µH
VBAT
CAP
VIN
C1
1µF
C8
15pF
LT3487
DN
R1
931k
C5
100nF
FBP
C7 33pF
L3
22µH
VNEG
–16V
26mA
SWP
C4
10µF
FBN
R2 640k
RUN/SS
C3
22µF
RUN/SS
C6
100nF
VPOS
24V
24mA
VPOS
GND
3487 TA05
C1: TAIYO YUDEN EMK212BJ105MG
C2: TAIYO YUDEN TMK212BJ225MG
C3: TAIYO YUDEN TMK325BJ226MM
C4: TAIYO YUDEN TMK316BJ106KL-T
L1: SUMIDA CDRH2D18/HP-150NC
L2, L3: TOKO D53LC-A915AY-220M
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PART NUMBER
DESCRIPTION
COMMENTS
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Dual Output 350mA/100mA ISW, Constant Off-Time,
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VIN: 1.2V to 15V, VOUT(MAX) = 34V, IQ = 20µA, ISD < 1µA, 10-Lead
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LT1945
Dual Output, Boost/Inverter, 350mA ISW, Constant Off-Time,
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Triple Output, 550kHz, High Efficiency DC/DC Converter
VIN: 1.4V to 4.6V, VOUT(MAX) = ±15V, IQ = 75µA, ISD < 2µA,
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LT3463/LT3463A
Dual Output, Boost/Inverter, 250mA ISW, Constant Off-Time,
High Efficiency DC/DC Converter with Integrated Schottkys
VIN: 2.2V to 16V, VOUT(MAX) = ±40V, IQ = 2.8mA, ISD < 1µA,
DFN Package
LT3471
Dual Output, Boost/Inverter, 1.3A ISW, 1.2MHz, High
Efficiency DC/DC Converter
VIN: 2.4V to 16V, VOUT(MAX) = ±40V, IQ = 2.5mA, ISD < 1µA,
DFN Package
LT3472/LT3472A
Dual Output, Boost/Inverter, 350mA/400mA ISW, 1.2MHz,
High Efficiency DC/DC Converter with Integrated Schottkys
VIN: 2.3V to 15V, VOUT(MAX) = ±40V, IQ = 40µA, ISD < 1µA,
DFN Package
3487f
16 Linear Technology Corporation
LT 0406 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
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© LINEAR TECHNOLOGY CORPORATION 2006