Sep 2006 J-FET-Based DC/DC Converter Starts and Runs from 300mV Supply

L DESIGN IDEAS
J-FET-Based DC/DC Converter Starts
and Runs from 300mV Supply by Jim Williams
A J-FET’s self-biasing characteristic
can be utilized to construct a DC/DC
converter powered from as little as
300mV. Solar cells, thermopiles and
single stage fuel cells, all with outputs below 600mV, are typical power
sources for such a converter.
Figure 1, an N-channel J-FET I-V
plot, shows drain-source conduction
under zero bias (gate and source tied
together) conditions. This property can
be exploited to produce a self-starting
DC/DC converter that runs from 0.3V
to 1.6V inputs.
Figure 2 shows the circuit. Q1 and
T1 form an oscillator with T1’s secondary providing regenerative feedback
to Q1’s gate. When power is applied,
Q1’s gate is at zero volts and its drain
conducts current via T1’s primary. T1’s
phase inverting secondary responds by
going negative at Q1’s gate, turning
it off. T1’s primary current ceases,
its secondary collapses and oscillation commences. T1’s primary action
causes positive going “flyback” events
10mA/DIV
100mV/DIV
Figure 1. Zero volt biased JFET I-V curve
shows 10mA conduction at 100mV, rising
above 40mA at 500mV. Characteristic enables
construction of DC/DC converter powered
from 300mV supply.
at Q1’s drain, which are rectified and
filtered. Q2’s approximately 2V turnon potential isolates the load, aiding
start-up. When Q2 turns on, circuit
output heads towards 5V. C1, powered
from Q2’s source, enforces output
regulation by comparing a portion of
the output with its internal voltage
reference. C1’s switched output controls Q1’s on-time via Q3, forming a
control loop.
VIN
0.3V TO 1.6V
Waveforms for the circuit include
the AC coupled output (Figure 3, trace
A), C1’s output (trace B) and Q1’s drain
flyback events (trace C). When the
output drops below 5V, C1 goes low,
turning on Q1. Q1’s resultant flyback
events continue until the 5V output is
restored. This pattern repeats, maintaining the output.
The 5V output can supply up to
2mA, sufficient to power circuitry or
supply bias to a higher power switching regulator when more current is
required. The circuit will start into
loads of 300µA at 300mV input; 2mA
loading requires a 475mV supply.
Figure 4 plots minimum input voltage vs output current over a range
of loads.
A
0.1V/DIV
AC COUPLED
B
5V/DIV
C
5V/DIV
1.18V REF OUT
5ms/DIV
Figure 3. J-FET based DC/DC converter
waveforms. When supply output (trace A)
decays, C1 (trace B) switches, allowing Q1 to
oscillate. Resultant flyback events at Q1 drain
(trace C) restore supply output.
–
C1
LTC1440
+
0.01µF
100Ω
T1
3
3.83M*
7
Q2
TP-0610L
6 1N5817
Q1
0.001µF
6.8µF
+
+
VOUT
5V
2mA
100µF
BAT85
Q3
VN2222L
T1: COILTRONICS VP-1-1400
TIE WINDINGS (1,12)(2,4)
(8,10)(9,11)
*1% METAL FILM RESISTOR
Q1: PHILIPS BF-162, 2 DEVICES
IN PARALLEL
Figure 2. J-FET based DC/DC converter runs from 300mV input. Q1-T1 oscillator output is
rectified and filtered. Load is isolated until Q2 source arrives at approximately 2V, aiding startup. Comparator and Q3 close loop around oscillator, controlling Q1’s on-time to stabilize 5V
output.
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MINIMUM INPUT VOLTAGE
TO MOUNTAIN VOUT = 5V (V)
5
0.6
1.21M*
0.5
WITH QUIESCENT CONTROL
CIRCUITRY (FIGURE 5)
0.4
WITHOUT QUIESCENT CONTROL
CIRCUITRY (FIGURE 2)
0.3
0.2
0.1
0
0
400
800
1200
1600
OUTPUT CURRENT (µA)
2000
Figure 4. J-FET based DC/DC converter of
Figure 2 starts and runs into 100µA load at
VIN = 275mV. Regulation to 2mA is possible,
although required VIN rises to 500mV.
Quiescent current control circuitry of Figure
5 slightly increases input voltage required to
support load at VIN < 500mV.
Linear Technology Magazine • September 2006
DESIGN IDEAS L
VIN
0.3V TO 1.6V
1.18V REF OUT
–
C1
LTC1440
+
Q4
0.01µF
1M
1.21M*
51Ω
5
T1
3
3.83M*
10M
7
Q2
TP-0610L
6 1N5817
Q1
470k
Q3
VN2222L
6.8µF
+
6.8V
1N4692
+
+
VOUT
5V
2mA
100µF
1µF T1: COILTRONICS VP-1-1400
TIE WINDINGS (1,12)(2,4)
(8,10)(9,11)
* 1% METAL FILM RESISTOR
Q1, Q4: PHILIPS BF-162, Q1 IS
2 DEVICES IN PARALLEL
1N4148
Q3’s shunt control of Q1 is simple
and effective, but results in a 25mA
quiescent current drain. Figure 5’s
modifications reduce this figure to 1mA
by series switching T1’s secondary.
Here, Q3 switches series-connected
Q4, more efficiently controlling Q1’s
gate drive. Negative turn-off bias for
Q4 is bootstrapped from T1’s secondary; the 6.8V zener holds off bias
supply loading during initial power
application, aiding start-up. Figure
4 shows minimal penalty imposed by
the added quiescent current control
circuitry. L
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the latest information
on LTC products,
visit
www.linear.com
Figure 5. Adding Q3, Q4 and bootstrapped negative bias generator reduces quiescent current.
Comparator directed Q3 switches Q4, more efficiently controlling Q1’s gate drive. Q2 and zener
diode isolate all loading during Q1 start-up.
LT3487, continued from page 13
until the positive side reaches 87% of
its final voltage. The output disconnect
is also designed so that both channels
can collapse together gently when the
chip is shut down.
Output Disconnect
In a standard boost regulator, the
inductor and Schottky diode provide a
DC current path from the input to the
output, even when the regulator is shut
down. Any load at the output when
the chip is shut down can continue
to drain the VIN source. The LT3487
addresses this issue with an on-chip
output disconnect. The output disconnect is a PNP pass transistor that
eliminates the DC loss path. The pass
transistor is controlled by a circuit
that varies its base current to keep it
at the edge of saturation, yielding the
best compromise between voltage drop
across the PNP and quiescent current.
The disconnect in the LT3487 can
support loads of 50mA with a VCE of
less than 210mV.
VBAT Pin
The VBAT pin is an innovation that
allows output disconnect operation
in a wide range of applications. VBAT
monitors the voltage at the input of the
boost inductor and allows the positive
output to stay active until the CAP node
falls to 1.2V above VBAT. This ensures
that output disconnect continues operating even after the part goes into
shutdown. Since output disconnect
continues to work, the positive output
doesn’t fall sharply to ground before
the negative bias discharges. The
VBAT pin allows the inductors to be
powered from a different source than
VIN while still maintaining the disconnect operation. This can be useful in
VRUN/SS
2V/DIV
IIN
200mA/DIV
VRUN/SS
2V/DIV
IIN
1A/DIV
VPOS
10V/DIV
VPOS
10V/DIV
VNEG
10V/DIV
VNEG
10V/DIV
500µs/DIV
Figure 3. Startup without
soft-start capacitor
Linear Technology Magazine • September 2006
10ms/DIV
Figure 4. Startup with 100nF
soft-start capacitor
a system using a 2-cell supply where
a low voltage boost provides 3.3V for
the VIN supply. By connecting VBAT
as well as the inductors to the 2-cell
supply, the positive output is able to
stay on as long as possible when the
part goes into shutdown.
Applications
The LT3487 can be used in a CCD
bias as well as other applications
that require a positive and negative
bias such as ±12V data acquisition
systems. The boost channel can produce voltages up to 30V as long as
the part can meet the required duty
cycle. Similarly, the inverting channel
can produce voltages down to –30V.
This high voltage capability allows
the LT3487 to be used in many LCD
applications.
Conclusion
The LT3487 simplifies and shrinks
CCD bias supplies without compromising on performance or features.
The soft-start and output disconnect
features ensure that the input battery
doesn’t encounter current spikes or
shutdown leakage. The high current
capability satiates even the most power-hungry video applications. L
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