LTC3577/LTC3577-1 Highly Integrated 6-Channel Portable PMIC DESCRIPTION FEATURES n n n n n n n n n n n n n Full Featured Li-Ion/Polymer Charger/PowerPath™ Control with Instant-On Operation Triple Adjustable High Efficiency Step-Down Switching Regulators (800mA, 500mA, 500mA IOUT) 6μA Battery Drain Current in Hard Reset Bat-Track™ Control for External HV Buck DC/DCs I2C Adjustable SW Slew Rates for EMI Reduction High Temperature Battery Voltage Reduction Improves Safety and Reliability Overvoltage Protection for USB (VBUS)/Wall Inputs Provides Protection to 30V Integrated 40V Series LED Backlight Driver with 60dB Brightness Control and Gradation via I2C 1.5A Maximum Charge Current with Thermal Limiting Battery Float Voltage: 4.2V (LTC3577) 4.1V (LTC3577-1) Pushbutton On/Off Control with System Reset Dual 150mA Current Limited LDOs Small 4mm × 7mm 44-Pin QFN Package APPLICATIONS n n n n PNDs, DMB/DVB-H; Digital/Satellite Radio; Media Players Portable Industrial/Medical Products Universal Remotes, Photo Viewers Other USB-Based Handheld Products The LTC®3577 is a highly integrated power management IC for single cell Li-Ion/Polymer battery applications. It includes a PowerPath manager with automatic load prioritization, a battery charger, an ideal diode, input overvoltage protection and numerous other internal protection features. The LTC3577 is designed to accurately charge from current limited supplies such as USB by automatically reducing charge current such that the sum of the load current and the charge current does not exceed the programmed input current limit (100mA or 500mA modes). The LTC3577 reduces the battery voltage at elevated temperatures to improve safety and reliability. Efficient high current charging from supplies up to 38V is available using the on-chip Bat-Track controller. The LTC3577 also includes a pushbutton input to control the three synchronous step-down switching regulators and system reset. The onboard LED backlight boost circuitry can drive up to 10 series LEDs and includes versatile digital dimming via I2C input. The I2C input also controls two 150mA LDOs as well as other operating modes and status read back. The LTC3577 is available in a low profile 4mm × 7mm × 0.75mm 44-pin QFN package. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. PowerPath and Bat-Track are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 6522118, 6700364, 7511390, 5481178, 6580258. Other Patents Pending. TYPICAL APPLICATION HV SUPPLY 8V TO 38V (TRANSIENTS TO 60V) LED Driver Efficiency 10 LEDs HIGH VOLTAGE BUCK DC/DC 90 OPTIONAL 80 100mA/500mA 1000mA 70 VOUT OVERVOLTAGE PROTECTION 0V CC/CV CHARGER LTC3577/LTC3577-1 CHARGE 2 I2C PORT + NTC 0.8V to 3.6V/150mA 0.8V to 3.6V/150mA DUAL LDO REGULATORS UP TO 10 LED BOOST LED BACKLIGHT WITH DIGITALLY CONTROLLED DIMMING PB TRIPLE HIGH EFFICIENCY STEP-DOWN SWITCHING REGULATORS WITH PUSHBUTTON CONTROL SINGLE CELL Li-Ion 0.8V to 3.6V/800mA 0.8V to 3.6V/500mA 0.8V to 3.6V/500mA EFFICIENCY (%) USB 60 MAX PWM 50 CONSTANT CURRENT 40 30 20 10 0 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 LED CURRENT (A) 1.E-01 3577 TA01b 3577 TA01a 3577f 1 LTC3577/LTC3577-1 TABLE OF CONTENTS FEATURES/APPLICATIONS ..........................................................................................................................................1 ABSOLUTE MAXIMUM RATINGS .................................................................................................................................3 PACKAGE/ORDER INFORMATION ................................................................................................................................3 ELECTRICAL CHARACTERISTICS .......................................................................................................................... 4-10 TYPICAL PERFORMANCE CHARACTERISTICS .................................................................................................... 10-15 PIN FUNCTION ..................................................................................................................................................... 15-18 BLOCK DIAGRAM ......................................................................................................................................................18 PowerPath OPERATION ....................................................................................................................................... 19-29 LOW DROPOUT LINEAR REGULATOR OPERATION ............................................................................................. 29-30 STEP-DOWN SWITCHING REGULATOR OPERATION .......................................................................................... 30-33 LED BACKLIGHT/BOOST OPERATION.................................................................................................................. 33-36 I2C OPERATION ................................................................................................................................................... 37-42 PUSHBUTTON INTERFACE OPERATION ............................................................................................................... 42-46 LAYOUT AND THERMAL CONSIDERATIONS........................................................................................................ 47-48 TYPICAL APPLICATION ........................................................................................................................................ 49-50 PACKAGE DESCRIPTION ............................................................................................................................................51 RELATED PARTS ........................................................................................................................................................52 3577f 2 LTC3577/LTC3577-1 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1, 2, 3) 44 CHRG 43 CLPROG 42 VC 41 ACPR 40 VBUS 39 VOUT 38 BAT TOP VIEW ILIM0 1 ILIM1 2 LED_FS 3 WALL 4 SW3 5 VIN3 6 FB3 7 OVSENS 8 LED_OV 9 DVCC 10 SDA 11 SCL 12 OVGATE 13 PWR_ON 14 ON 15 45 37 IDGATE 36 PROG 35 NTC 34 NTCBIAS 33 SW1 32 VIN12 31 SW2 30 VINLD02 29 LDO2 28 LDO1 27 LDO1_FB 26 FB1 25 FB2 24 LDO2_FB 23 VINLDO1 PBSTAT 16 WAKE 17 SW 18 SW 19 SW 20 PG_DCDC 21 ILED 22 VSW ............................................................ –0.3V to 45V VBUS, VOUT , VIN12, VIN3, VINLDO1, VINLDO2, WALL t < 1ms and Duty Cycle < 1% .................. –0.3V to 7V Steady State............................................. –0.3V to 6V CHRG, BAT, LED_FS, LED_OV, PWR_ON, WAKE, PBSTAT, PG_DCDC, FB1, FB2, FB3, LDO1, LDO1_FB, LDO2, LDO2_FB, DVCC, SCL, SDA ............... –0.3V to 6V NTC, PROG, CLPROG, ON, ILIM0, ILIM1 (Note 4)............................................–0.3V to VCC + 0.3V IVBUS, IVOUT , IBAT ........................................................2A ISW3 (Continuous) ................................................850mA ISW2, ISW1 (Continuous) .......................................600mA ILDO1, ILDO2 (Continuous).....................................200mA ICHRG, IACPR, IWAKE, IPBSTAT, IPG_DCDC ....................75mA IOVSENS...................................................................10mA ICLPROG, IPROG, ILED_FS, ILED_OV ...............................2mA Junction Temperature ........................................... 110°C Operating Temperature Range.................. –40°C to 85°C Storage Temperature Range................... –65°C to 125°C UFF PACKAGE 44-LEAD (7mm s 4mm) PLASTIC QFN TJMAX = 110°C, θJA = 45°C/W EXPOSED PAD (PIN 45) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3577EUFF#PBF LTC3577EUFF#TRPBF 3577 44-Lead (4mm × 7mm) Plastic QFN –40°C to 85°C LTC3577EUFF-1#PBF LTC3577EUFF-1#TRPBF 35771 44-Lead (4mm × 7mm) Plastic QFN –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3577f 3 LTC3577/LTC3577-1 ELECTRICAL CHARACTERISTICS Power Manager. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VBUS = 5V, VBAT = 3.8V, ILIM0 = ILIM1 = WALL = 0V, VINLDO1 = VINLDO2 = VIN12 = VIN3 = VOUT, RPROG = 2k, RCLPROG = 2.1k, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 90 475 950 100 500 1000 mA mA mA 0.42 0.042 0.1 mA mA Input Power Supply VBUS Input Supply Voltage IBUS(LIM) Total Input Current (Note 5) ILIM0 = 0V, ILIM1 = 0V (1x Mode) ILIM0 = 5V, ILIM1 = 5V (5x Mode) ILIM0 = 5V, ILIM1 = 0V (10x Mode) 4.35 IBUSQ Input Quiescent Current, POFF State 1x, 5x, 10x Modes ILIM0 = 0V, ILIM1 = 5V (Suspend Mode) hCLPROG Ratio of Measured VBUS Current to CLPROG Program Current VCLPROG CLPROG Servo Voltage in Current Limit 1x Mode 5x Mode 10x Mode VUVLO VBUS Undervoltage Lockout Rising Threshold Falling Threshold l l l 80 450 900 5.5 1000 mA/mA 0.2 1.0 2.0 3.5 V V V V 3.8 3.7 3.9 V V 100 mV mV VDUVLO VBUS to VOUT Differential Undervoltage Rising Threshold Lockout Falling Threshold 50 –50 RON_ILIM Input Current Limit Power FET OnResistance (Between VBUS and VOUT) 200 mΩ Battery Charger VFLOAT VBAT Regulated Output Voltage ICHG Constant-Current Mode Charge Current RPROG = 1k, Input Current Limit = 2A RPROG = 2k, Input Current Limit = 1A RPROG = 5k, Input Current Limit = 0.4A IBATQ_HR Battery Drain Current, Hard Reset VBUS = 0V, IOUT = 0μA 7 15 μA IBATQ_OFF Battery Drain Current, POFF State VBAT = 4.3V, Charger Time Out VBUS = 0V 6 40 27 100 μA μA IBATQ_ON Battery Drain Current, PON State LDOs, and LED Backlight Disabled VBUS = 0V, IOUT = 0μA, No Load on Supplies, Burst Mode Operation (Note 10) 90 160 μA VPROG,CHG PROG Pin Servo Voltage VBAT > VTRKL 1.000 V VBAT < VTRKL 0.100 V 1000 mA/mA VPROG,TRKL PROG Pin Servo Voltage in Trickle Charge LTC3577 LTC3577, 0 ≤ TA ≤ 85°C LTC3577-1 LTC3577-1, 0 ≤ TA ≤ 85°C l l l 4.179 4.165 4.079 4.065 4.200 4.200 4.100 4.100 4.221 4.235 4.121 4.135 V V V V 950 465 180 1000 500 200 1050 535 220 mA mA mA hPROG Ratio of IBAT to PROG Pin Current ITRKL Trickle Charge Current VBAT < VTRKL 40 50 60 mA VTRKL Trickle Charge Rising Threshold Trickle Charge Falling Threshold VBAT Rising VBAT Falling 3.0 2.5 2.85 2.75 V V ΔVRECHRG Recharge Battery Threshold Voltage Threshold Voltage Relative to VFLOAT –75 –100 –125 mV tTERM Safety Timer Termination Period Timer Starts when VBAT = VFLOAT – 50mV 3.2 4 4.8 Hour tBADBAT Bad Battery Termination Time VBAT < VTRKL 0.4 0.5 0.6 Hour hC/10 End-of-Charge Indication Current Ratio (Note 6) 0.085 0.1 0.11 mA/mA RON_CHG Battery Charger Power FET OnResistance (Between VOUT and BAT) 200 mΩ TLIM Junction Temperature in Constant Temperature Mode 110 °C 3577f 4 LTC3577/LTC3577-1 ELECTRICAL CHARACTERISTICS Power Manager. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VBUS = 5V, VBAT = 3.8V, ILIM0 = ILIM1 = WALL = 0V, VINLDO1 = VINLDO2 = VIN12 = VIN3 = VOUT, RPROG = 2k, RCLPROG = 2.1k, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS NTC, Battery Discharge Protection VCOLD Cold Temperature Fault Threshold Voltage Rising NTC Voltage Hysteresis 75 76 1.3 77 %VNTCBIAS %VNTCBIAS VHOT Hot Temperature Fault Threshold Voltage Falling NTC Voltage Hysteresis 34 35 1.3 36 %VNTCBIAS %VNTCBIAS V2HOT NTC Discharge Threshold Voltage Falling NTC Voltage Hysteresis 24.5 25.5 50 26.5 %VNTCBIAS mV INTC NTC Leakage Current VNTC = VBUS = 5V –50 IBAT2HOT BAT Discharge Current VBAT = 4.1V, NTC < VTOO_HOT 180 mA VBAT2HOT BAT Discharge Threshold IBAT < 0.1mA, NTC < VTOO_HOT 3.9 V VFWD Forward Voltage Detection IOUT = 10mA RDROPOUT Diode On-Resistance, Dropout IOUT = 200mA 200 mΩ IMAX Diode Current Limit (Note 7) 3.6 A 50 nA Ideal Diode 5 15 25 mV Overvoltage Protection VOVCUTOFF Overvoltage Protection Threshold Rising Threshold, ROVSENS = 6.2k 6.10 6.35 6.70 V VOVGATE OVGATE Output Voltage Input Below VOVCUTOFF Input Above VOVCUTOFF 1.88 • VOVSENS 0 12 V V IOVSENSQ OVSENS Quiescent Current VOVSENS = 5V 40 μA tRISE OVGATE Time to Reach Regulation COVGATE = 1nF 2.5 ms ACPR Pin Output High Voltage ACPR Pin Output Low Voltage IACPR = 0.1mA IACPR = 1mA Absolute Wall Input Threshold Voltage VWALL Rising VWALL Falling Wall Adapter VACPR VW ΔVW Differential Wall Input Threshold Voltage VWALL – VBAT Falling VWALL – VBAT Rising IQWALL Wall Operating Quiescent Current IWALL + IVOUT , IBAT = 0mA, WALL = VOUT = 5V VOUT – 0.3 3.1 0 VOUT 0 4.3 3.2 25 75 0.3 4.45 100 440 V V V V mV mV μA Logic (ILIM0, ILIM1 and CHRG) VIL Input Low Voltage ILIM0, ILIM1 VIH Input High Voltage ILIM0, ILIM1 IPD Static Pull-Down Current ILIM0, ILIM1; VPIN = 1V VCHRG CHRG Pin Output Low Voltage ICHRG = 10mA ICHRG CHRG Pin Input Current VBAT = 4.5V, VCHRG = 5V 0.4 1.2 V V 2 μA 0.15 0.4 V 0 1 μA 3577f 5 LTC3577/LTC3577-1 ELECTRICAL CHARACTERISTICS I2C Interface. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. DVCC = 3.3V, VOUT = 3.8V, unless otherwise noted. SYMBOL PARAMETER DVCC Input Supply Voltage IDVCC DVCC Supply Current VDVCC,UVLO DVCC UVLO CONDITIONS MIN TYP 1.6 SCL = 400kHz SCL = SDA = 0kHz MAX UNITS 5.5 V 1 0.4 μA μA 1.0 V VIH Input HIGH Voltage VIL Input LOW Voltage 50 IIH Input HIGH Leakage Current SDA = SCL = DVCC = 5.5V –1 1 μA IIL Input LOW Leakage Current SDA = SCL = 0V, DVCC = 5.5V –1 1 μA VOL SDA Output LOW Voltage ISDA = 3mA 0.4 V 400 kHz 30 70 50 %DVCC %DVCC Timing Characteristics (Note 8) (All Values are Referenced to VIH and VIL) fSCL SCL Clock Frequency tLOW LOW Period of the SCL Clock 1.3 μs tHIGH HIGH Period of the SCL Clock 0.6 μs tBUF Bus Free Time Between Stop and Start Condition 1.3 μs tHD,STA Hold Time After (Repeated) Start Condition 0.6 μs tSU,STA Setup Time for a Repeated Start Condition 0.6 μs tSU,STO Stop Condition Set-Up Time 0.6 μs tHD,DATO Output Data Hold Time 0 tHD,DATI Input Data Hold Time 0 tSU,DAT Data Set-Up Time tSP Input Spike Suppression Pulse Width 900 ns ns 100 ns 50 ns Step-Down Switching Regulators. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VOUT = VIN12 = VIN3 = 3.8V, all regulators enabled unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Step-Down Switching Regulators (Buck1, Buck2 and Buck3) VIN12, VIN3 Input Supply Voltage (Note 9) VOUT UVLO VOUT Falling VOUT Rising VIN12 and VIN3 Connected to VOUT Through Low Impedance. Switching Regulators are Disabled Below VOUT UVLO fOSC l 2.7 2.5 Oscillator Frequency 1.91 5.5 2.7 V V 2.8 2.9 V 2.25 2.59 MHz 800mA Step-Down Switching Regulator 3 (Buck3 – Pushbutton Enabled, Third in Sequence) IVIN3Q Pulse-Skipping Mode Input Current (Note 10) Burst Mode Input Current (Note 10) 100 Shutdown Input Current μA 17 μA 0.01 μA ILIM3 Peak PMOS Current Limit (Note 7) VFB3 Feedback Voltage Pulse-Skipping Mode Burst Mode Operation IFB3 FB3 Input Current (Note 10) –0.05 D3 Max Duty Cycle FB3 = 0V 100 RP3 RDS(ON) of PMOS 0.3 Ω RN3 RDS(ON) of NMOS 0.4 Ω l l 1000 1400 1700 mA 0.78 0.78 0.8 0.8 0.82 0.824 V V 0.05 μA % 3577f 6 LTC3577/LTC3577-1 ELECTRICAL CHARACTERISTICS Step-Down Switching Regulators. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VOUT = VIN12 = VIN3 = 3.8V, all regulators enabled unless otherwise noted. SYMBOL PARAMETER CONDITIONS RSW3_PD SW3 Pull-Down in Shutdown POFF State MIN TYP MAX UNITS 10 kΩ 100 μA 500mA Step-Down Switching Regulator 2 (Buck2 – Pushbutton Enabled, Second in Sequence) IVIN12Q Pulse-Skipping Mode Input Current (Note 10) Burst Mode Input Current (Note 10) Shutdown Input Current ILIM2 Peak PMOS Current Limit (Note 7) Pulse-Skipping Mode Burst Mode Operation l l 17 μA 0.01 μA 650 900 1200 mA 0.78 0.78 0.8 0.8 0.82 0.824 V V 0.05 μA VFB2 Feedback Voltage IFB2 FB2 Input Current (Note 10) –0.05 D2 Max Duty Cycle FB2 = 0V 100 RP2 RDS(ON) of PMOS ISW2 = 100mA 0.6 RN2 RDS(ON) of NMOS ISW2 = –100mA 0.6 Ω RSW2_PD SW2 Pull-Down in Shutdown POFF State 10 kΩ % Ω 500mA Step-Down Switching Regulator 1 (Buck1 – Pushbutton Enabled, First in Sequence) IVIN12Q Pulse-Skipping Mode Input Current (Note 10) 100 μA Burst Mode Input Current (Note 10) 17 μA Shutdown Input Current 0.01 μA ILIM1 Peak PMOS Current Limit (Note 7) VFB1 Feedback Voltage Pulse-Skipping Mode Burst Mode Operation IFB1 FB1 Input Current (Note 10) –0.05 D1 Max Duty Cycle FB1 = 0V 100 RP1 RDS(ON) of PMOS ISW1 = 100mA 0.6 RN1 RDS(ON) of NMOS ISW1 = –100mA 0.6 Ω RSW1_PD SW1 Pull-Down in Shutdown POFF State 10 kΩ l l 650 900 1200 mA 0.78 0.78 0.8 0.8 0.82 0.824 V V 0.05 μA % Ω LDO Regulators. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VINLDO1 = VINLDO2 = VOUT = VBAT = 3.8V, LDO1 and LDO2 enabled unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS LDO Regulator 1 (LDO1 – Enabled Via I2C) VINLDO1 Input Voltage Range VINLDO1 ≤ VOUT + 0.3V VOUT_UVLO VOUT Falling VOUT Rising LDO1 is Disabled Below VOUT UVLO IQLDO1_VO IQLDO1_VI LD01 VOUT Quiescent Current LD01 VINLDO1 Quiescent Current LDO1 Enabled, PON State, ILDO1 = 0mA LDO1 Enabled, PON State, ILDO1 = 0mA IVINLDO1 Shutdown Current LDO1 Disabled, PON or POFF State VLDO1_FB LDO1_FB Regulated Feedback Voltage ILDO1 = 1mA LDO1_FB Line Regulation (Note 11) ILDO1 = 1mA, VIN = 1.65V to 5.5V LDO1_FB Load Regulation (Note 11) ILDO1 = 1mA to 150mA ILDO1_FB LDO1_FB Input Current LDO1_FB = 0.8V ILDO1_OC Available Output Current l 1.65 2.5 l 0.78 5.5 V 2.7 2.8 2.9 V V 18 0.1 30 2 μA μA 0.01 1 μA 0.8 0.82 V 0.4 mV/V 5 –50 l 150 μV/mA 50 nA mA 3577f 7 LTC3577/LTC3577-1 ELECTRICAL CHARACTERISTICS LDO Regulators. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VINLDO1 = VINLDO2 = VOUT = VBAT = 3.8V, LDO1 and LDO2 enabled unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP ILDO1_SC Short-Circuit Output Current VDROP1 Dropout Voltage (Note 12) ILDO1 = 150mA, VINLDO1 = 3.6V ILDO1 = 150mA, VINLDO1 = 2.5V ILDO1 = 75mA, VINLDO1 = 1.8V 160 200 170 RLDO1_PD Output Pull-Down Resistance in Shutdown LDO1 Disabled 10 MAX 270 UNITS mA 260 320 280 mV mV mV kΩ LDO Regulator 2 (LDO2 – Enabled Via I2C) VINLDO2 Input Voltage Range VINLDO2 ≤ VOUT + 0.3V VOUT_UVLO VOUT Falling VOUT Rising LDO2 is Disabled Below VOUT UVLO IQLDO2_VO IQLDO2_VI LDO2 VOUT Quiescent Current LDO2 VINLDO2 Quiescent Current IVINLDO2 VLDO2_FB l 1.65 5.5 V 2.7 2.8 2.9 V V LDO2 Enabled, PON State, ILDO2 = 0mA LDO2 Enabled, PON State, ILDO2 = 0mA 18 0.1 30 2 μA μA Shutdown Current LDO2 Disabled, PON or POFF State 0.01 1 μA LDO2_FB Regulated Output Voltage ILDO2 = 1mA 0.8 0.82 LDO2_FB Line Regulation (Note 11) ILDO2 = 1mA, VIN = 1.65V to 5.5V LDO2_FB Load Regulation (Note 11) ILDO2 = 1mA to 150mA LDO2_FB = 0.8V 2.5 l 0.78 mV/V 5 μV/mA ILDO2_FB LDO2_FB Input Current ILDO2_OC Available Output Current –50 ILDO2_SC Short-Circuit Output Current VDROP2 Dropout Voltage (Note 12) ILDO2 = 150mA, VINLDO2 = 3.6V ILDO2 = 150mA, VINLDO2 = 2.5V ILDO1 = 75mA, VINLDO1 = 1.8V 160 200 170 RLDO2_PD Output Pull-Down Resistance in Shutdown LDO2 Disabled 14 l V 0.4 50 150 nA mA 270 mA 260 320 280 mV mV mV kΩ LED Boost Switching Regulator. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN3 = VOUT = 3.8V, ROV = 10M, RLED_FS = 20k, boost regulator disabled unless otherwise noted. SYMBOL PARAMETER CONDITIONS VIN3, VOUT Operating Supply Range (Note 9) IVOUT_LED Operating Quiescent Current Shutdown Quiescent Current (Notes 10, 14) VLED_OV LED_OV Overvoltage Threshold LED_OV Rising LED_OV Falling MIN l TYP 2.7 MAX 5.5 560 0.01 UNITS V μA μA 1.0 0.85 1.25 0.6 V V ILIM Peak NMOS Switch Current 800 1000 1200 mA ILED_FS ILED Pin Full-Scale Operating Current 18 20 22 mA ILED_DIM ILED Pin Full-Scale Dimming Range RNSWON RDS(ON) of NMOS Switch INSWOFF NMOS Switch-Off Leakage Current fOSC Oscillator Frequency 64 Steps 60 dB 240 VSW = 5.5V VLED_FS LED_FS Pin Voltage ILED_OV LED_OV Pin Current RLED_FS = 20k DBOOST Maximum Duty Cycle ILED = 0 VBOOSTFB Boost Mode ILED Feedback Voltage mΩ 0.01 1 μA 0.95 1.125 1.3 MHz l 780 800 820 mV l 3.8 4 4.2 μA l 775 800 825 mV 97 % 3577f 8 LTC3577/LTC3577-1 ELECTRICAL CHARACTERISTICS Pushbutton Controller. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VOUT = 3.8V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Pushbutton Pin (ON) l VOUT Pushbutton Operating Supply Range (Note 9) VOUT UVLO VOUT Falling VOUT Rising Pushbutton is Disabled Below VOUT UVLO VON_TH ON Threshold Rising ON Threshold Falling ION ON Input Current VON = VOUT VON = 0V 2.7 2.5 2.7 2.8 0.4 0.8 0.7 –1 –4 –9 0.4 0.8 0.7 5.5 V 2.9 V V 1.2 V V 1 –14 μA μA 1.2 V V Power-On Input Pin (PWR_ON) VPWR_ON IPWR_ON PWR_ON Threshold Rising PWR_ON Threshold Falling PWR_ON Input Current VPWR_ON = 3V –1 1 μA –1 1 μA 0.1 0.4 V 1 μA 0.1 0.4 V 1 μA Status Output Pins (PBSTAT, WAKE, PG_DCDC) IPBSTAT PBSTAT Output High Leakage Current VPBSTAT = 3V VPBSTAT PBSTAT Output Low Voltage IPBSTAT = 3mA IWAKE Wake Output High Leakage Current VWAKE = 3V VWAKE Wake Low Output Voltage IWAKE = 3mA IPG_DCDC PG_DCDC Output High Leakage Current VPG_DCDC = 3V VPG_DCDC PG_DCDC Output Low Voltage IPG_DCDC = 3mA 0.1 VTHPG_DCDC PG_DCDC Threshold Voltage (Note 13) –8 % –1 –1 0.4 V Pushbutton Timing Parameters tON_PBSTAT1 ON Low Time to PBSTAT Low WAKE High 50 ms tON_PBSTAT2 ON High to PBSTAT High PBSTAT Low > tPBSTAT_PW 900 μs tON_WAKE ON Low Time to WAKE High WAKE Low > tPWR_ONBK2 tON_HR ON Low to Hard Reset Hard Reset = All Supplies Disabled 400 4.2 40 ms 5 5.8 50 60 Seconds tPBSTAT_PW PBSTAT Minimum Pulse Width tWAKE_EXTP WAKE High from USB or Wall Present WAKE Low > tPWR_ONBK2 100 ms tWAKE_DCDC WAKE High to Buck1 Enable WAKE Low > tPWR_ONBK2 5 μs tPWR_ONH PWR_ON High to WAKE High WAKE Low > tPWR_ONBK2 50 ms tPWR_ONL PWR_ON Low to WAKE Low WAKE High > tPWR_ONBK1 50 ms tPWR_ONBK1 PWR_ON Power-Up Blanking WAKE Rising Until PWR_ON Low Recognized 5 Seconds tPWR_ONBK2 PWR_ON Power-Down Blanking WAKE Falling Until PWR_ON High Recognized 1 Seconds tPG_DCDCH Bucks in Regulation to PG_DCDC High All Bucks Within PG_DCDC Threshold Voltage 230 ms tPG_DCDCL Bucks Disabled to PG_DCDC Low All Bucks Disabled 44 μs Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3577E/LTC3577E-1 are guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. ms Note 3: This IC includes over temperature protection that is intended to protect the device during momentary overload conditions. Junction temperatures will exceed 110°C when over temperature protection is active. Continuous operation above the specified maximum operating junction temperature may result in device degradation or failure. 3577f 9 LTC3577/LTC3577-1 ELECTRICAL CHARACTERISTICS Note 4: VCC is the greater of VBUS, VOUT or BAT. Note 5: Total input current is the sum of quiescent current, IBUSQ, and measured current given by VCLPROG/RCLPROG • (hCLPROG + 1). Note 6: hC/10 is expressed as a fraction of measured full charge current with indicated PROG resistor. Note 7: The current limit features of this part are intended to protect the IC from short term or intermittent fault conditions. Continuous operation above the specified maximum pin current rating may result in device degradation or failure. Note 8: The serial port is tested at rated operating frequency. Timing parameters are tested and/or guaranteed by design. Note 9: VOUT not in UVLO. Note 10: FB high, not switching. Note 11: Measured with the LDO running unity gain with output tied to feedback pin. Note 12: Dropout voltage is the minimum input to output voltage differential needed for an LDO to maintain regulation at a specified output current. When an LDO is in dropout, its output voltage will be equal to VIN – VDROP . Note 13: PG_DCDC threshold is expressed as a percentage difference from the Buck1-3 regulation voltages. The threshold is measured from Buck1-3 output rising. Note 14: IVOUT_LED is the sum of VOUT and VIN3 current due to LED driver. Note 15: The IBATQ specifications represent the total battery load assuming VINLDO1, VINLDO2, VIN12 and VIN3 are tied directly to VOUT. TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise specified Input Supply Current vs Temperature 0.7 0.10 VBUS = 5V 1x MODE 400 NO LOAD ON SUPPLIES, LDOS AND LED 350 BOOST DISABLED. VBAT = 3.8V, VBUS = 0V PON STATE 300 PULSE-SKIPPING MODE VBUS = 5V 0.08 0.6 0.5 IVBUS (mA) IVBUS (mA) Battery Drain Current vs Temperature 0.4 0.3 0.06 IBAT (μA) 0.8 Input Supply Current vs Temperature (Suspend Mode) 0.04 250 200 150 PON STATE Burst Mode OPERATION 100 0.2 0.02 POFF STATE 50 0.1 HARD RESET STATE 0 –50 –25 75 50 25 TEMPERATURE (°C) 0 100 0 –50 125 –25 50 25 0 75 TEMPERATURE (°C) 100 Input Current Limit vs Temperature 1000 VBUS = 5V RCLPROG = 2.1k 300 280 10x MODE 700 220 RON (mΩ) IVBUS (mA) 240 5x MODE 500 400 VBUS = 4.5V 400 VBUS = 5V 180 VBUS = 5.5V 160 1x MODE 100 –25 50 25 0 75 TEMPERATURE (°C) 100 100 100 125 3577 G04 0 –50 300 200 120 200 0 –50 500 140 300 125 600 IOUT = 400mA 260 800 100 Charge Current vs Temperature (Thermal Regulation) Input RON vs Temperature 900 600 50 25 0 75 TEMPERATURE (°C) 3577 G03 IBAT (mA) 1100 –25 3577 G02 3577 G01 1200 0 –50 125 –25 50 25 0 75 TEMPERATURE (°C) 100 125 3577 G05 VBUS = 5V 10x MODE RPROG = 2k 0 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 3577 G06 3577f 10 LTC3577/LTC3577-1 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise specified Battery Current and Voltage vs Time Battery Regulation (Float) Voltage vs Temperature 6 600 5 3 200 SAFETY TIMER 2 TERMINATION 1450mAhr CELL 100 VBUS = 5V RPROG = 2k RCLPROG = 2k 0 0 2 1 C/10 4.14 4.12 LTC3577-1 4.10 IBAT 5 6 100 4.04 –50 –25 0 75 50 25 TEMPERATURE (°C) 0 100 0 2.0 125 0.25 RCLPROG = 2.1k RPROG = 2k 500 VBUS = 5V 10x MODE 40 VBUS = 0V TA = 25°C 4.0 4.4 VBAT = 3.8V VBUS = 0V TA = 25°C 35 VBAT = 3.2V 30 VBAT = 3.6V 400 VBAT = 4.2V VFWD (V) 0.15 FALLING VBAT 3.2 3.6 VBAT (V) Forward Voltage vs Ideal Diode Current (with Si2333DS External FET) 0.20 300 2.8 3577 G09 Forward Voltage vs Ideal Diode Current (No External FET) 600 2.4 3577 G08 LTC3577-1 IBAT vs VBAT IBAT (mA) FALLING VBAT 4.06 3577 G07 0.10 200 RISING VBAT 25 20 15 10 0.05 100 0 RISING VBAT 300 200 4.08 1 3 4 TIME (HOUR) 400 4.16 VFWD (mV) IBAT (mA) 300 4.18 IBAT (mA) 4 400 LTC3577 4.20 VBAT AND VCHRG (V) VBAT VBAT (V) 500 RCLPROG = 2.1k RPROG = 2k 500 VBUS = 5V 10x MODE IBAT = 2mA 4.22 CHRG LTC3577 IBAT vs VBAT 600 4.24 5 2.0 2.4 2.8 3.2 3.6 VBAT (V) 4.0 4.4 0 0 0 0.2 0.4 0.6 IBAT (A) 0.8 3577 G10 1.0 1.2 Input Disconnect Waveform 0.6 IBAT (A) 0.8 1.0 Switching from 1x to 5x Mode VBUS 5V/DIV VOUT 5V/DIV VOUT 5V/DIV IBUS 0.5A/DIV IBUS 0.5A/DIV IBUS 0.5A/DIV IBAT 0.5A/DIV IBAT 0.5A/DIV IBAT 0.5A/DIV 3577 G13 0.4 3577 G12 VBUS 5V/DIV 1ms/DIV 0.2 3577 G11 Input Connect Waveform VBAT = 3.75V IOUT = 100mA RCLPROG = 2k RPROG = 2k 0 ILIM0/ILIM1 5V/DIV VBAT = 3.75V IOUT = 100mA RCLPROG = 2k RPROG = 2k 1ms/DIV 3577 G14 VBAT = 3.75V IOUT = 50mA RCLPROG = 2k RPROG = 2k 1ms/DIV 3577 G15 3577f 11 LTC3577/LTC3577-1 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise specified Switching from Suspend Mode to 5x Mode WALL Connect Waveform WALL Disconnect Waveform ILIM0 5V/DIV WALL 5V/DIV WALL 5V/DIV VOUT 5V/DIV IBUS 0.5A/DIV VOUT 5V/DIV IWALL 0.5A/DIV VOUT 5V/DIV IWALL 0.5A/DIV IBAT 0.5A/DIV IBAT 0.5A/DIV IBAT 0.5A/DIV VBAT = 3.75V IOUT = 100mA RCLPROG = 2k RPROG = 2k ILIM1 = 5V 3577 G16 100μs/DIV VBAT = 3.75V IOUT = 100mA RPROG = 2k Oscillator Frequency vs Temperature 100 Burst Mode 90 OPERATION 80 2.2 VIN = 5V 70 2.1 2.0 1.9 VIN = 2.9V 1.8 90 80 PULSE-SKIPPING MODE 60 50 40 EFFICIENCY (%) VIN = 3.8V EFFICIENCY (%) 2.3 30 VIN = 2.7V 3577 G18 1ms/DIV Step-Down Switching Regulator 2 1.8V Output Efficiency vs IOUT2 100 2.4 Burst Mode OPERATION 70 60 PULSE-SKIPPING MODE 50 40 30 1.7 20 VOUT1 = 3.3V 20 VOUT2 = 1.8V 1.6 10 VIN12 = 3.8V VIN12 = 5V 10 VIN12 = 3.8V VIN12 = 5V –25 50 25 0 75 TEMPERATURE (°C) 100 0 0.01 125 0.1 1 10 IOUT (mA) 100 Step-Down Switching Regulator 3 1.2V Output Efficiency vs IOUT3 50 40 20 VOUT3 = 1.2V VIN3 = 3.8V VIN3 = 5V 10 0.1 1 10 IOUT (mA) 100 1000 70 PULSE-SKIPPING MODE 60 50 40 3577 G22 20 VOUT3 = 2.5V VIN3 = 3.8V VIN3 = 5V 10 0 0.01 1000 1400 30 30 0 0.01 EFFICIENCY (%) PULSE-SKIPPING MODE 100 1500 Burst Mode 90 OPERATION 80 Burst Mode OPERATION 60 1 10 IOUT (mA) Step-Down Switching Regulator Short-Circuit Current vs Temperature 100 70 0.1 3577 G21 Step-Down Switching Regulator 3 2.5V Output Efficiency vs IOUT3 100 80 1000 3577 G20 3577 G19 90 0 0.01 0.1 1 10 IOUT (mA) 100 1000 3577 G23 SHORT-CIRCUIT CURRENT (mA) 1.5 –50 EFFICIENCY (%) VBAT = 3.75V IOUT = 100mA RPROG = 2k Step-Down Switching Regulator 1 3.3V Output Efficiency vs IOUT1 2.5 fOSC (MHz) 3577 G17 1ms/DIV 1300 800mA BUCK 1200 1100 1000 900 500mA BUCK 800 700 VINx = 3.8V VINx = 5V 600 500 –50 –25 0 50 75 25 TEMPERATURE (°C) 100 125 3577 G24 3577f 12 LTC3577/LTC3577-1 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise specified Step-Down Switching Regulator Output Transient (Burst Mode Operation) Step-Down Switching Regulator Output Transient (Pulse-Skipping Mode) VOUT1 50mV/DIV (AC) VOUT2 50mV/DIV (AC) VOUT3 100mV/DIV (AC) 500mA 500mA IOUT3 IOUT3 5mA VOUT1 = 3.3V 50μs/DIV IOUT1 = 10mA VOUT2 = 1.8V IOUT2 = 20mA VOUT3 = 1.2V VOUT = VBAT = 3.8V 3577 G25 0.9 VINX = 3.2V 0.8 SWITCH IMPEDANCE (Ω) VOUT1 50mV/DIV (AC) VOUT2 50mV/DIV (AC) VOUT3 100mV/DIV (AC) Step-Down Switching Regulator Switch Impedance vs Temperature 5mA VOUT1 = 3.3V 50μs/DIV IOUT1 = 30mA VOUT2 = 1.8V IOUT2 = 20mA VOUT3 = 1.2V VOUT = VBAT = 3.8V 0.7 0.6 500mA NMOS 500mA PMOS 0.5 0.4 800mA PMOS 0.3 800mA NMOS 0.2 3577 G26 0.1 0 –50 –25 0 25 75 50 TEMPERATURE (°C) 100 125 3577 G27 500mA Step-Down Switching Regulator Feedback Voltage vs Output Current 800mA Step-Down Switching Regulator Feedback Voltage vs Output Current 0.85 0.85 0.84 0.84 0.83 0.83 0.81 0.82 Burst Mode OPERATION FEEDBACK (V) FEEDBACK (V) 0.82 0.80 0.79 PULSE-SKIPPING MODE 0.79 0.78 0.77 0.75 0.1 1 10 100 OUTPUT CURRENT (mA) 1000 Burst Mode OPERATION LDO2 20mV/DIV (AC) 0.80 0.77 3.8V 5V LDO1 50mV/DIV (AC) 0.81 0.78 0.76 LDO Load Step PULSE-SKIPPING MODE IOUT1 5mA 1 10 100 OUTPUT CURRENT (mA) 1000 3577 G29 3577 G28 OVP Protection Waveform OVP Connection Waveform OVP Reconnection Waveform VBUS 5V/DIV VBUS 5V/DIV 3577 G30 LDO1 = 1.2V 20μs/DIV LDO2 = 2.5V ILDO2 = 40mA VOUT = VBAT = 3.8V 3.8V 5V 0.76 0.75 0.1 100mA VBUS 5V/DIV OVGATE 5V/DIV OVGATE 5V/DIV OVP INPUT VOLTAGE 0V TO 5V STEP 5V/DIV OVP INPUT VOLTAGE 5V TO 10V STEP 5V/DIV 500μs/DIV 3577 G31 500μs/DIV 3577 G32 OVGATE 5V/DIV OVP INPUT VOLTAGE 10V TO 5V STEP 5V/DIV 500μs/DIV 3577 G33 3577f 13 LTC3577/LTC3577-1 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise specified Rising Overvoltage Threshold vs Temperature OVSENS Quiescent Current vs Temperature VOVSENS = 5V OVSENS CONNECTED TO INPUT THROUGH 10 6.2k RESISTOR 6.275 33 31 8 OVGATE (V) 35 6.270 6.265 –15 35 10 TEMPERATURE (°C) 60 85 2 0 6.255 –40 –15 35 10 TEMPERATURE (°C) 60 Input and Battery Current vs Load Current LED Driver Efficiency 10 LEDs IIN 400 EFFICIENCY (%) ILOAD 300 IBAT (CHARGING) 200 100 90 85 85 80 80 75 70 65 3V 3.6V 4.2V 4.8V 5.5V –100 0 100 55 IBAT (DISCHARGING) WALL = 0V 200 400 300 ILOAD (mA) 500 4 6 INPUT VOLTAGE (V) 50 0 600 2 4 6 75 70 65 3V 3.6V 4.2V 4.8V 5.5V 60 55 50 8 10 12 14 16 18 20 ILED (mA) 0 2 4 6 8 10 12 14 16 18 20 ILED (mA) 3577 G38 3577 G37 LED Driver Efficiency 6 LEDs 35773 G39 LED Boost Current Limit vs Temperature LED Driver Efficiency 4 LEDs 90 90 85 85 80 80 8 LED Driver Efficiency 8 LEDs 90 60 0 2 3577 G36 EFFICIENCY (%) RPROG = 2k RCLPROG = 2k 500 0 85 3577 G35 3577 G34 600 6 4 6.260 29 27 –40 CURRENT (mA) OVGATE vs OVSENS 12 6.280 OPV THRESHOLD (V) QUIESCENT CURRENT (μA) 37 1200 1100 75 70 65 3V 3.6V 4.2V 4.8V 5.5V 60 55 50 0 2 4 6 8 10 12 14 16 18 20 ILED (mA) 3577 G40 75 70 65 3V 3.6V 4.2V 4.8V 5.5V 60 55 50 0 2 4 6 8 10 12 14 16 18 20 ILED (mA) 3577 G41 CURRENT LIMIT (mA) EFFICIENCY (%) EFFICIENCY (%) 1000 900 800 700 600 500 400 300 200 100 0 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 3577 G42 3577f 14 LTC3577/LTC3577-1 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise specified DAC Code vs LED Current LED Boost Maximum Duty Cycle vs Temperature LED Boost Start-Up Transient 70 96.6 60dB = 20mA 0dB = 20μA 60 RLED_FS = 20k 96.5 ILED 10mA/DIV 40 MAX DUTY CYCLE (%) CURRENT (dB) 50 96.4 VBOOST 20V/DIV 30 20 IL 200mA/DIV 96.3 96.2 96.1 96.0 3V 3.6V 4.2V 5.5V 95.9 10 95.8 0 0 10 20 40 30 DAC CODE 50 60 70 2ms/DIV 3577 G44 95.7 –50 –25 25 0 50 75 TEMPERATURE (°C) 3577 G43 Battery Discharge vs Temperature 90 MAX PWM 50 CONSTANT CURRENT 40 30 20 10 180 175 VBUS = 5V 140 125 VBUS = 0V 100 75 1.E-04 1.E-03 1.E-02 LED CURRENT (A) 1.E-01 120 100 80 60 50 VBAT = 4.1V VNTC < VTOO_HOT 5x MODE IVOUT = 0mA 25 0 1.E-05 VNTC < VTOO_HOT VBUS = 0V 160 150 IBAT (mA) BATTERY DISCHARGE CURRENT (mA) EFFICIENCY (%) 60 0 1.E-06 Too Hot BAT Discharge 200 200 70 125 3577 G45 LED PWM vs Constant Current Efficiency 80 100 50 60 40 20 90 100 80 TEMPERATURE (°C) 70 3577 G46 110 120 3577 G47 0 3.8 3.9 4.0 VBAT (V) 4.1 4.2 3577 G48 PIN FUNCTIONS ILIM0, ILIM1 (Pins 1, 2): Input Current Control Pins. ILIM0 and ILIM1 control the input current limit. See Table 1 in “USB PowerPath Controller” section. Both pins are pulled low by a weak current sink. SW3 (Pin 5): Power Transmission (Switch) Pin for StepDown Switching Regulator 3 (Buck 3). LED_FS (Pin 3): A resistor between this pin and ground sets the full-scale output current of the ILED pin. FB3 (Pin 7): Feedback Input for Step-Down Switching Regulator 3 (Buck 3). This pin servos to a fixed voltage of 0.8V when the control loop is complete. WALL (Pin 4): Wall Adapter Present Input. Pulling this pin above 4.3V will disconnect the power path from VBUS to VOUT . The ACPR pin will also be pulled low to indicate that a wall adapter has been detected. VIN3 (Pin 6): Power Input for Step-Down Switching Regulator 3. This pin should be connected to VOUT . OVSENSE (Pin 8): Overvoltage Protection Sense Input. OVSENSE should be connected through a 6.2k resistor to the input power connector and the drain of an external 3577f 15 LTC3577/LTC3577-1 PIN FUNCTIONS N-channel MOS pass transistor. When the voltage on this pin exceeds a preset level, the OVGATE pin will be pulled to GND to disable the pass transistor and protect downstream circuitry. LED_OV (Pin 9): A resistor between this pin and the boosted LED backlight voltage sets the overvoltage limit on the boost output. If the boost voltage exceeds the programmed limit the LED boost converter will be disabled. DVCC (Pin 10): Supply Voltage for I2C Lines. This pin sets the logic reference level of the LTC3577. A UVLO circuit on the DVCC pin forces all registers to all 0s whenever DVCC is <1V. Bypass to GND with a 0.1μF capacitor. SDA (Pin 11): I2C Data Input. Serial data is shifted one bit per clock to control the LTC3577. The logic level for SDA is referenced to DVCC. SCL (Pin 12): I2C Clock Input. The logic level for SCL is referenced to DVCC. OVGATE (Pin 13): Overvoltage Protection Gate Output. Connect OVGATE to the gate pin of an external N-channel MOS pass transistor. The source of the transistor should be connected to VBUS and the drain should be connected to the product’s DC input connector. In the absence of an overvoltage condition, this pin is connected to an internal charge pump capable of creating sufficient overdrive to fully enhance this transistor. If an overvoltage condition is detected, OVGATE is brought rapidly to GND to prevent damage. OVGATE works in conjunction with OVSENSE to provide this protection. PWR_ON (Pin 14): Logic Input Used to Keep Buck DC/DCs Enabled After Power-Up. May also be used to enable the buck DC/DCs directly (sequence = buck1 → buck2 → buck3). See “Pushbutton Interface Operation” section for more information. ON (Pin 15): Pushbutton Input. A weak internal pull-up forces ON high when left floating. A normally open pushbutton is connected from ON to ground to force a low state on this pin. PBSTAT (Pin 16): Open-drain output is a de-bounced and buffered version of ON to be used for processor interrupts. WAKE (Pin 17): Open-Drain Output. The WAKE pin indicates the operating state of the buck DC/DCs. If WAKE is Hi-Z, the BUCK DC/DCs are enabled and either up or powering up. A low on WAKE indicates that the buck DC/DCs are either powered down or are powering down. See “Pushbutton Interface Operation” section for more information. SW (Pins 18,19,20): Power Transmission (Switch) Pin for LED Boost Converter. See “LED Backlight/Boost Operation” section for circuit hook-up and component selection. I2C is used to control LED driver enable. I2C default is LED driver off. PG_DCDC (Pin 21): Open-Drain Output. PG_DCDC goes high impedance 230ms after all buck DC/DCs are in regulation (within 8% of final value). ILED (Pin 22): Series LED Backlight Current Sink Output. This pin is connected to the cathode end of the series LED backlight string. The current drawn through the series LEDs can be programmed via a 6-bit 60dB DAC and dimmed via an internal 4-bit PWM function. I2C is used to control LED driver enable, brightness, gradation (soft on/soft off). I2C default is LED driver off, current = 0mA. VINLDO1 (Pin 23): Input Supply of Low Dropout Linear Regulator 1 (LDO1). This pin should be bypassed to ground with a 1μF or greater ceramic capacitor. LDO2_FB (Pin 24): Feedback Voltage Input for Low Dropout Linear Regulator 2 (LDO2). LDO2 output voltage is set using an external resistor divider between LDO2 and LDO2_FB. FB2 (Pin 25): Feedback Input for Step-Down Switching Regulator 2 (Buck 2). This pin servos to a fixed voltage of 0.8V when the control loop is complete. FB1 (Pin 26): Feedback Input for Step-Down Switching Regulator 1 (Buck 1). This pin servos to a fixed voltage of 0.8V when the control loop is complete. LDO1_FB (Pin 27): Feedback Voltage Input for Low Dropout Linear Regulator 1 (LDO1). LDO1 output voltage is set using an external resistor divider between LDO1 and LDO1_FB. LDO1 (Pin 28): Output of Low Dropout Linear Regulator 1. This pin must be bypassed to ground with a 1μF or greater ceramic capacitor. 3577f 16 LTC3577/LTC3577-1 PIN FUNCTIONS LDO2 (Pin 29): Output of Low Dropout Linear Regulator 2. This pin must be bypassed to ground with a 1μF or greater ceramic capacitor. VINLDO2 (Pin 30): Input Supply of Low Dropout Linear Regulator 2 (LDO2). This pin should be bypassed to ground with a 1μF or greater ceramic capacitor. SW2 (Pin 31): Power Transmission (Switch) Pin for StepDown Switching Regulator 2 (Buck 2). VIN12 (Pin 32): Power Input for Step-Down Switching Regulators 1 and 2. This pin will generally be connected to VOUT . SW1 (Pin 33): Power Transmission (Switch) Pin for StepDown Switching Regulator 1 (Buck 1). either deliver system power to VOUT through the ideal diode or be charged from the battery charger. VOUT (Pin 39): Output Voltage of the PowerPath Controller and Input Voltage of the Battery Charger. The majority of the portable product should be powered from VOUT . The LTC3577 will partition the available power between the external load on VOUT and the internal battery charger. Priority is given to the external load and any extra power is used to charge the battery. An ideal diode from BAT to VOUT ensures that VOUT is powered even if the load exceeds the allotted input current from VBUS or if the VBUS power source is removed. VOUT should be bypassed with a low impedance multilayer ceramic capacitor. NTCBIAS (Pin 34): Output Bias Voltage for NTC. A resistor from this pin to the NTC pin will bias the NTC thermistor. VBUS (Pin 40): USB Input Voltage. VBUS will usually be connected to the USB port of a computer or a DC output wall adapter. VBUS should be bypassed with a low impedance multilayer ceramic capacitor. NTC (Pin 35): The NTC pin connects to a battery’s thermistor to determine if the battery is too hot or too cold to charge. If the battery’s temperature is out of range, charging is paused until it drops back into range. A low drift bias resistor is required from NTCBIAS to NTC and a thermistor is required from NTC to ground. ACPR (Pin 41): Wall Adapter Present Output (Active Low). A low on this pin indicates that the wall adapter input comparator has had its input pulled above its input threshold (typically 4.3V). This pin can be used to drive the gate of an external P-channel MOSFET to provide power to VOUT from a power source other than a USB port. PROG (Pin 36): Charge Current Program and Charge Current Monitor Pin. Connecting a resistor from PROG to ground programs the charge current: ICHG = 1000V (A) RPROG If sufficient input power is available in constant current mode, this pin servos to 1V. The voltage on this pin always represents the actual charge current. IDGATE (Pin 37): Ideal Diode Gate Connection. This pin controls the gate of an optional external P-channel MOSFET transistor used to supplement the internal ideal diode. The source of the P-channel MOSFET should be connected to VOUT and the drain should be connected to BAT. It is important to maintain high impedance on this pin and minimize all leakage paths. BAT (Pin 38): Single Cell Li-Ion Battery Pin. Depending on available power and load, a Li-Ion battery on BAT will VC (Pin 42): High Voltage Buck Regulator Control Pin. This pin can be used to drive the VC pin of an approved external high voltage buck switching regulator. The VC pin is designed to work with the LT®3480, LT3653 and LT3505. Consult factory for additional approved high voltage buck regulators. See “External HV Buck Control through the VC Pin” section for operating information. CLPROG (Pin 43): Input Current Program and Input Current Monitor Pin. A resistor from CLPROG to ground determines the upper limit of the current drawn from the VBUS pin (i.e., the input current limit). A precise fraction of the input current, hCLPROG, is sent to the CLPROG pin. The input PowerPath delivers current until the CLPROG pin reaches 2V (10x mode), 1V (5x mode) or 0.2V (1x mode). Therefore, the current drawn from VBUS will be limited to an amount given by hCLPROG and RCLPROG. In USB applications the resistor RCLPROG should be set to no less than 2.1k. 3577f 17 LTC3577/LTC3577-1 PIN FUNCTIONS CHRG (Pin 44): Open-Drain Charge Status Output. The CHRG pin indicates the status of the battery charger. If CHRG is high then the charger is near the float voltage (charge current less than 1/10th programmed charge current) or charging is complete and charger is disabled. A low on CHRG indicates that the charger is enabled. For more information see the “Charge Status Indication” section. Exposed Pad (Pin 45): Ground. The exposed package pad is ground and must be soldered to the PC board for proper functionality and for maximum heat transfer. BLOCK DIAGRAM 8 13 OVSENS 4 OVERVOLTAGE PROTECTON 40 43 34 35 1 2 44 41 WALL OVGATE 42 ACPR VC WALL DETECT VC CONTROL VOUT VBUS INPUT CURRENT LIMIT CLPROG NTCBIAS NTC BATTERY TEMP MONITOR IDEAL DIODE – + OVERTEMP BATTERY SAFETY DISCHARGE ILIM LOGIC EN 500mA, 2.25MHz BUCK REGULATOR 15 16 10 11 12 BAT VIN12 SW1 CHRG 0.8V FB1 PG 17 15mV IDGATE PROG CHRGE STATUS 14 + – HRST UVLO ILIM0 ILIM1 CC/CV CHARGER 21 ON EN PUSHBUTTON INPUT 36 32 33 26 500mA, 2.25MHz BUCK REGULATOR SW2 0.8V FB2 PG DVCC I2C LOGIC SDA SCL EN 800mA, 2.25MHz BUCK REGULATOR VIN3 SW3 31 25 6 5 PG_DCDC 230ms FALLING DELAY LED_OV FB3 PG VINLD01 EN 0.8V 40V LED BACKLIGHT BOOST CONVERTER LDO1 150mA LDO1 LDO1_FB DAC 3 38 PBSTAT SW 18,19,20 22 37 PWR_ON WAKE 0.8V 21 39 ILED VINLD02 EN 0.8V LED_FS 0.8V 150mA LDO2 LDO2 LDO2_FB 7 23 28 27 30 29 24 GND 45 3577 BD 3577f 18 LTC3577/LTC3577-1 OPERATION PowerPath OPERATION Introduction The LTC3577 is a highly integrated power management IC that features: – PowerPath controller – Battery charger – Ideal diode – Input overvoltage protection – Pushbutton controller – Three step-down switching regulators – High voltage buck regulator VC controller – Two low dropout linear regulators – 40V LED backlight controller Designed specifically for USB applications, the PowerPath controller incorporates a precision input current limit which communicates with the battery charger to ensure that input current does not violate the USB average input current specification. The ideal diode from BAT to VOUT guarantees that ample power is always available to VOUT even if there is insufficient or absent power at VBUS. The LTC3577 also has the ability to receive power from a wall adapter or other non-current-limited power source. Such a power supply can be connected to the VOUT pin of the LTC3577 through an external device such as a power Schottky or FET as shown in Figure 1. The LTC3577 has the unique ability to use the output, which is powered by an external supply, to charge the battery while providing power to the load. A comparator on the WALL pin is configured to detect the presence of the wall adapter and shut off the connection to the USB. This prevents reverse conduction from VOUT to VBUS when a wall adapter is present. The LTC3577 provides a VC output pin which can be used to drive the VC pin of an external high voltage buck switching regulator such as the LT3480, LT3653 or LT3505 to provide power to the VOUT pin. The VC control circuitry adjusts the regulation point of the switching regulator to FROM AC ADAPTER (OR HIGH VOLTAGE BUCK OUTPUT) 42 4.3V (RISING) 3.2V (FALLING) 4 – + VC OPTIONAL CONTROL FOR HIGH VOLTAGE BUCK REGS LT3480, LT3481 OR LT3505 ACPR WALL 41 + – FROM USB + – 40 VBUS 75mV (RISING) 25mV (FALLING) ENABLE VOUT VOUT 39 SYSTEM LOAD USB CURRENT LIMIT IDEAL DIODE CONSTANT CURRENT CONSTANT VOLTAGE BATTERY CHARGER + – – + IDGATE OPTIONAL EXTERNAL IDEAL DIODE PMOS 37 15mV BAT BAT 38 3577 F01 + Li-Ion Figure 1. Simplified PowerPath Block Diagram 3577f 19 LTC3577/LTC3577-1 OPERATION a small voltage above the BAT pin voltage. This control method provides a high input voltage, high efficiency battery charger and PowerPath function. The LTC3577 also includes a pushbutton input to control the three synchronous step-down switching regulators and system reset. The three 2.25MHz constant frequency current mode step-down switching regulators provide 500mA, 500mA and 800mA each and support 100% duty cycle operation as well as Burst Mode operation for high efficiency at light load. No external compensation components are required for the switching regulators. The onboard LED backlight boost circuitry can drive up to 10 series LEDs and includes versatile digital dimming via the I2C input. The I2C input also controls two 150mA low dropout (LDO) linear regulators. current. When a programming resistor is connected from CLPROG to GND, the voltage on CLPROG represents the input current: IVBUS =IBUSQ + where IBUSQ and hCLPROG are given in the Electrical Characteristics table. The input current limit is programmed by the ILIM0 and ILIM1 pins. The LTC3577 can be configured to limit input current to one of several possible settings as well as be deactivated (USB suspend). The input current limit will be set by the appropriate servo voltage and the resistor on CLPROG according to the following expression: All regulators can be programmed for a minimum output voltage of 0.8V and can be used to power a microcontroller core, microcontroller I/O, memory or other logic circuitry. IVBUS =IBUSQ + USB PowerPath Controller IVBUS =IBUSQ + The input current limit and charge control circuits of the LTC3577 are designed to limit input current as well as control battery charge current as a function of IVOUT . VOUT drives the combination of the external load, the three step-down switching regulators, two LDOs, LED backlight and the battery charger. If the combined load does not exceed the programmed input current limit, VOUT will be connected to VBUS through an internal 200mΩ P-channel MOSFET. If the combined load at VOUT exceeds the programmed input current limit, the battery charger will reduce its charge current by the amount necessary to enable the external load to be satisfied while maintaining the programmed input current. Even if the battery charge current is set to exceed the allowable USB current, the average input current USB specification will not be violated. Furthermore, load current at VOUT will always be prioritized and only excess available current will be used to charge the battery. The current out of the CLPROG pin is a fraction (1/hCLPROG) of the VBUS VCLPROG •h RCLPROG CLPROG IVBUS =IBUSQ + 0.2V RCLPROG 1V RCLPROG 2V RCLPROG • h CLPROG (1x Mode) • h CLPROG ( 5x Mode) • h CLPROG (10x Mode) Under worst-case conditions, the USB specification for average input current will not be violated with an RCLPROG resistor of 2.1k or greater. Table 1 shows the available settings for the ILIM0 and ILIM1 pins: Table 1. Controlled Input Current Limit ILIM1 ILIM0 IBUS(LIM) 0 0 100mA (1x) 0 1 1A (10x) 1 0 Suspend 1 1 500mA (5x) Notice that when ILIM0 is high and ILIM1 is low, the input current limit is set to a higher current limit for increased charging and current availability at VOUT . This mode is typically used when there is a higher power, non-USB source available at the VBUS pin. 3577f 20 LTC3577/LTC3577-1 OPERATION Ideal Diode from BAT to VOUT The LTC3577 has an internal ideal diode as well as a controller for an optional external ideal diode. Both the internal and the external ideal diodes respond quickly whenever VOUT drops below BAT. If the load increases beyond the input current limit, additional current will be pulled from the battery via the ideal diodes. Furthermore, if power to VBUS (USB) or VOUT (external wall power or high voltage regulator) is removed, then all of the application power will be provided by the battery via the ideal diodes. The ideal diodes are fast enough to keep VOUT from dropping significantly with just the recommended output capacitor (see Figure 2). The ideal diode consists of a precision amplifier that enables an on-chip P-channel MOSFET whenever the voltage at VOUT is approximately 15mV (VFWD) below the voltage at BAT. The resistance of the internal ideal diode is approximately 200mΩ. If this is sufficient for the application, then no external components are necessary. However, if lower resistance is needed, an external P-channel MOSFET can be added from BAT to VOUT. The IDGATE pin of the LTC3577 drives the gate of the external P-channel MOSFET for automatic ideal diode control. The source of the MOSFET should be connected to VOUT and the drain should be connected to BAT. Capable of driving a 1nF load, the IDGATE pin can control an external P-channel MOSFET having extremely low on-resistance. Using the WALL Pin to Detect the Presence of an External Power Source The WALL input pin can be used to identify the presence of an external power source (particularly one that is not subject to a fixed current limit like the USB VBUS input). Typically, such a power supply would be a 5V wall adapter output or the low voltage output of a high voltage buck regulator (specifically, LT3480, LT3653 or LT3505). When the wall adapter output (or buck regulator output) is connected directly to the WALL pin, and the voltage exceeds the WALL pin threshold, the USB power path (from VBUS to VOUT) will be disconnected. Furthermore, the ACPR pin will be pulled low. In order for the presence of an external power supply to be acknowledged, both of the following conditions must be satisfied: 1. The WALL pin voltage must exceed approximately 4.3V. 2. The WALL pin voltage must be greater than 75mV above the BAT pin voltage. The input power path (between VBUS and VOUT) is reenabled and the ACPR pin is pulled high when either of the following conditions is met: 1. The WALL pin voltage falls to within 25mV of the BAT pin voltage. 2. The WALL pin voltage falls below 3.2V. Each of these thresholds is suitably filtered in time to prevent transient glitches on the WALL pin from falsely triggering an event. 4.0V VOUT 3.8V 3.6V External HV Buck Control Through the VC Pin 500mA CHARGE IBAT 0 DISCHARGE –500mA IVOUT LOAD 1A 0A VBAT = 3.8V VBUS = 5V 5x MODE COUT = 10μF 10μs/DIV 3577 F02 Figure 2. Ideal Diode Transient Response The WALL, ACPR and VC pins can be used in conjunction with an external high voltage buck regulator such as the LT3480, LT3505 or LT3653 to provide power directly to the VOUT pin as shown in Figures 3 to 5 (Consult factory for complete list of approved high voltage buck regulators). When the WALL pin voltage exceeds 4.3V, VC pin control circuitry is enabled and drives the VC pin of the LT3480, LT3505 or LT3653. The VC pin control circuitry is designed so that no compensation components are required on the VC node. The voltage at the VOUT pin is regulated to the larger of (BAT + 300mV) or 3.6V as shown in Figure 6. 3577f 21 LTC3577/LTC3577-1 OPERATION HVIN 8V TO 38V (TRANSIENTS TO 60V) 4 68nF 4.7μF VIN BOOST 2 0.47μF 150k LT3480 5 3 RUN/SS SW 10 RT 40.2k 1 7 NC BD 8 6 NC FB GND VC 11 LT3480 HIGH VOLTAGE BUCK CIRCUITRY 6.8μH DFLS240L 499k 22μF 100k 9 Si2333DS 42 4 UP TO 2A VOUT 41 COUT VC WALL ACPR 39 VOUT 37 LTC3577 IDGATE 38 BAT Si2333DS (OPT) + BAT Li-Ion 3577 F03 Figure 3. LT3480 Buck Control Using VC (800kHz Switching) 3 HVIN 8V TO 36V 1μF 68nF 150k 4 VIN BOOST 1N4148 1 LT3505 2 SW SHDN BZT52C16T 0.1μF 6.8μH MBRM140 49.9k 10μF 20k 806k 6 RT GND LT3505 HIGH VOLTAGE BUCK CIRCUITRY 5, 9 FB VC 10.0k 7 8 Si2333DS 42 4 UP TO 1.2A VOUT 41 VC WALL ACPR 39 VOUT 37 LTC3577 IDGATE 38 BAT COUT Si2333DS (OPT) + BAT Li-Ion 3577 F04 Figure 4. LT3505 Buck Control Using VC (2.2MHz Switching with Frequency Foldback) 3577f 22 LTC3577/LTC3577-1 OPERATION HVIN 7.5V TO 30V (TRANSIENTS TO 60V) 1 4.7μF 60V BOOST VIN SW 7 0.1μF 4.7μH 10V 8 DFLS240L LT3653 324k 4 9 ILIM ISENSE GND VOUT 6 5 VC HVOK 3 2 UP TO 1.2A HIGH VOLTAGE BUCK CIRCUITRY 42 4 VOUT 41 COUT VC WALL ACPR 39 VOUT 37 LTC3577 IDGATE 38 BAT Si2333DS (OPT) + BAT Li-Ion 3577 F05 Figure 5. LT3653 Buck Control Using VC 5.0 VOUT (V) 4.5 4.0 3.5 IO = 0.0A IO = 0.75A IO = 1.5A BAT 3.0 2.5 2.5 3 3.5 4 BAT (V) 4.5 3577 F06 Figure 6. VOUT Voltage vs Battery Voltage (LT3480) 5.0 VOUT (V) 4.5 4.0 3.5 3.0 2.5 2.5 IO = 0.0A IO = 0.6A BAT 3 3.5 BAT (V) 4 4.5 3577 F07 Figure 7. VOUT Voltage vs Battery Voltage (LT3505) 3577f 23 LTC3577/LTC3577-1 OPERATION The feedback network of the high voltage buck regulator should be set to generate an output voltage higher than 4.4V (be sure to include the output voltage tolerance of the buck regulator). The VC control of the LTC3577 overdrives the local VC control of the external high voltage buck. Therefore, once the VC control is enabled, the output voltage is set independent of the buck regulator feedback network. This technique provides a significant efficiency advantage over the use of a 5V buck to drive the battery charger. With a simple 5V buck output driving VOUT , battery charger efficiency is approximately: ηCHARGER = ηBUCK • VBAT 5V where ηBUCK is the efficiency of the high voltage buck regulator and 5V is the output voltage of the buck regulator. With a typical buck efficiency of 87% and a typical battery voltage of 3.8V, the total battery charger efficiency is approximately 66%. Assuming a 1A charge current, this works out to nearly 2W of power dissipation just to charge the battery! With the VC control technique, battery charger efficiency is approximately: ηCHARGER = ηBUCK • VBAT 0.3V + VBAT With the same assumptions as above, the total battery charger efficiency is approximately 81%. This example works out to just 900mW of power dissipation. For applications, component selection and board layout information beyond those listed here please refer to the respective high voltage buck regulator data sheet. Suspend Mode When ILIM0 is pulled low and ILIM1 is pulled high the LTC3577 enters suspend mode to comply with the USB specification. In this mode, the power path between VBUS and VOUT is put in a high impedance state to reduce the VBUS input current to 50μA. If no other power source is available to drive WALL and VOUT , the system load connected to VOUT is supplied through the ideal diodes connected to BAT. 24 VBUS Undervoltage Lockout (UVLO) and Undervoltage Current Limit (UVCL) An internal undervoltage lockout circuit monitors VBUS and keeps the input current limit circuitry off until VBUS rises above the rising UVLO threshold (3.8V) and at least 50mV above VOUT . Hysteresis on the UVLO turns off the input current limit if VBUS drops below 3.7V or 50mV below VOUT . When this happens, system power at VOUT will be drawn from the battery via the ideal diode. To minimize the possibility of oscillation in and out of UVLO when using resistive input supplies, the input current limit is reduced as VBUS falls below 4.45V (typ). Battery Charger The LTC3577 includes a constant-current/constant-voltage battery charger with automatic recharge, automatic termination by safety timer, low voltage trickle charging, bad cell detection and thermistor sensor input for out of temperature charge pausing. When a battery charge cycle begins, the battery charger first determines if the battery is deeply discharged. If the battery voltage is below VTRKL, typically 2.85V, an automatic trickle charge feature sets the battery charge current to 10% of the programmed value. If the low voltage persists for more than one-half hour, the battery charger automatically terminates. Once the battery voltage is above 2.85V, the battery charger begins charging in full power constant current mode. The current delivered to the battery will try to reach 1000V/RPROG. Depending on available input power and external load conditions, the battery charger may or may not be able to charge at the full programmed rate. The external load will always be prioritized over the battery charge current. The USB current limit programming will always be observed and only additional current will be available to charge the battery. When system loads are light, battery charge current will be maximized. Charge Termination The battery charger has a built-in safety timer. When the battery voltage approaches the float voltage, the charge current begins to decrease as the LTC3577 enters constant voltage mode. Once the battery charger detects that it has entered constant voltage mode, the four hour safety 3577f LTC3577/LTC3577-1 OPERATION timer is started. After the safety timer expires, charging of the battery will terminate and no more current will be delivered. Automatic Recharge After the battery charger terminates, it will remain off drawing only microamperes of current from the battery. If the portable product remains in this state long enough, the battery will eventually self discharge. To ensure that the battery is always topped off, a charge cycle will automatically begin when the battery voltage falls below VRECHRG (typically 4.0V for LTC3577-1 and 4.1V for LTC3577). In the event that the safety timer is running when the battery voltage falls below VRECHRG, the timer will reset back to zero. To prevent brief excursions below VRECHRG from resetting the safety timer, the battery voltage must be below VRECHRG for more than 1.3ms. The charge cycle and safety timer will also restart if the VBUS UVLO cycles low and then high (e.g., VBUS, is removed and then replaced). Charge Current The charge current is programmed using a single resistor from PROG to ground. 1/1000th of the battery charge current is delivered to PROG which will attempt to servo to 1.000V . Thus, the battery charge current will try to reach 1000 times the current in the PROG pin. The program resistor and the charge current are calculated using the following equations: RPROG = 1000V 1000V , ICHG = ICHG RPROG In either the constant-current or constant-voltage charging modes, the PROG pin voltage will be proportional to the actual charge current delivered to the battery. Therefore, the actual charge current can be determined at any time by monitoring the PROG pin voltage and using the following equation: IBAT = VPROG • 1000 R PROG In many cases, the actual battery charge current, IBAT , will be lower than ICHG due to limited input current available and prioritization with the system load drawn from VOUT. Thermal Regulation To prevent thermal damage to the IC or surrounding components, an internal thermal feedback loop will automatically decrease the programmed charge current if the die temperature rises to approximately 110°C. Thermal regulation protects the LTC3577 from excessive temperature due to high power operation or high ambient thermal conditions and allows the user to push the limits of the power handling capability with a given circuit board design without risk of damaging the LTC3577 or external components. The benefit of the LTC3577 thermal regulation loop is that charge current can be set according to actual conditions rather than worst-case conditions with the assurance that the battery charger will automatically reduce the current in worst-case conditions. Charge Status Indication The CHRG pin indicates the status of the battery charger. An open-drain output, the CHRG pin can drive an indicator LED through a current limiting resistor for human interfacing or simply a pull-up resistor for microprocessor interfacing. When charging begins, CHRG is pulled low and remains low for the duration of a normal charge cycle. When charging is complete, i.e., the charger enters constant voltage mode and the charge current has dropped to one-tenth of the programmed value, the CHRG pin is released (high impedance). The CHRG pin does not respond to the C/10 threshold if the LTC3577 is in input current limit. This prevents false end-of-charge indications due to insufficient power available to the battery charger. Even though charging is stopped during an NTC fault, the CHRG pin will stay low indicating that charging is not complete. Battery Charger Stability Considerations The LTC3577’s battery charger contains both a constantvoltage and a constant-current control loop. The constantvoltage loop is stable without any compensation when a battery is connected with low impedance leads. Excessive lead length, however, may add enough series inductance to require a bypass capacitor of at least 1μF from BAT to GND. Furthermore, a 4.7μF capacitor in series with a 0.2Ω to 1Ω resistor from BAT to GND is required to keep ripple voltage low when the battery is disconnected. 3577f 25 LTC3577/LTC3577-1 OPERATION High value, low ESR multilayer ceramic chip capacitors reduce the constant-voltage loop phase margin, possibly resulting in instability. Ceramic capacitors up to 22μF may be used in parallel with a battery, but larger ceramics should be decoupled with 0.2Ω to 1Ω of series resistance. In constant-current mode, the PROG pin is in the feedback loop rather than the battery voltage. Because of the additional pole created by any PROG pin capacitance, capacitance on this pin must be kept to a minimum. With no additional capacitance on the PROG pin, the battery charger is stable with program resistor values as high as 25k. However, additional capacitance on this node reduces the maximum allowed program resistor. The pole frequency at the PROG pin should be kept above 100kHz. Therefore, if the PROG pin has a parasitic capacitance, CPROG, the following equation should be used to calculate the maximum resistance value for RPROG: RPROG ≤ 1 2π • 100kHz • C PROG NTC Thermistor and Battery Voltage Reduction The battery temperature is measured by placing a negative temperature coefficient (NTC) thermistor close to the battery pack. To use this feature connect the NTC thermistor, RNTC, between the NTC pin and ground and a bias resistor, RNOM, from NTCBIAS to NTC. RNOM should be a 1% resistor with a value equal to the value of the chosen NTC thermistor at 25°C (R25). The LTC3577 will pause charging when the resistance of the NTC thermistor drops to 0.54 times the value of R25 or approximately 54k (for a Vishay “Curve 1” thermistor, this corresponds to approximately 40°C). If the battery charger is in constant voltage (float) mode, the safety timer also pauses until the thermistor indicates a return to a valid temperature. As the temperature drops, the resistance of the NTC thermistor rises. The LTC3577 is also designed to pause charging when the value of the NTC thermistor increases to 3.17 times the value of R25. For a Vishay “Curve 1” thermistor this resistance, 317k, corresponds to approximately 0°C. The hot and cold comparators each have approximately 3°C of hysteresis to prevent oscillation about the trip point. The typical NTC circuit is shown in Figure 8. NTCBIAS NTC BLOCK 34 RNOM 100k NTC 0.76 • NTCBIAS LTC3577 – TOO_COLD 35 + RNTC 100k – TOO_HOT 0.35 • NTCBIAS 0.26 • NTCBIAS + + BATTERY OVERTEMP – 3577 F08 Figure 8. Typical NTC Thermistor Circuit To improve safety and reliability the battery voltage is reduced when the battery temperature becomes excessively high. When the resistance of the NTC thermistor drops to about 0.35 times the value of R25 or approximately 35k (for a Vishay “Curve 1” thermistor, this corresponds to approximately 50°C) the NTC enables circuitry to monitor the battery voltage. If the battery voltage is above the battery discharge threshold (about 3.9V) then the battery discharge circuitry is enabled and draws about 140mA from the battery when VBUS = 0V and about 180mA when VBUS = 5V. As the battery voltage approaches the discharge threshold the discharge current is linearly reduced until it reaches 0mA at which point the discharge circuitry is disabled. Reducing the discharge current in this fashion keeps the circuit from causing oscillations on VBAT due to battery ESR. When the charger is disabled an internal watchdog timer samples the NTC thermistor for about 150μs every 150ms and will enable the battery monitoring circuitry if the battery temperature exceeds the NTC TOO_HOT threshold. If adding a capacitor to the NTC pin for filtering the time constant must be much less than 150μs so that the NTC pin can settle to its final value during the sampling period. A time constant of less than 10μs is recommended. Once the battery monitoring circuitry is enabled it will remain enabled and monitoring the battery voltage until the battery 3577f 26 LTC3577/LTC3577-1 OPERATION temperature falls back below the discharge temperature threshold. The battery discharge circuitry is only enabled if the battery voltage is greater than the battery discharge threshold. NTCBIAS RNOM 105k NTC Alternate NTC Thermistors and Biasing NTC thermistors have temperature characteristics which are indicated on resistance-temperature conversion tables. The Vishay-Dale thermistor NTHS0603N011-N1003F, used in the following examples, has a nominal value of 100k and follows the Vishay “Curve 1” resistance-temperature characteristic. In the following explanation, this notation is used. R25 = Value of the thermistor at 25°C RNTC|COLD = Value of thermistor at the cold trip point RNTC|HOT = Value of the thermistor at the hot trip point rCOLD = Ratio of RNTC|COLD to R25 rHOT= Ratio of RNTC|HOT to R25 RNOM = Primary thermistor bias resistor (see Figure 9) R1 = Optional temperature range adjustment resistor (see Figure 9) 0.76 • NTCBIAS LTC3577 – TOO_COLD + 35 R1 12.7k The LTC3577 provides temperature qualified charging if a grounded thermistor and a bias resistor are connected to NTC. By using a bias resistor whose value is equal to the room temperature resistance of the thermistor (R25) the upper and lower temperatures are pre-programmed to approximately 40°C and 0°C, respectively (assuming a Vishay “Curve 1” thermistor). The upper and lower temperature thresholds can be adjusted by either a modification of the bias resistor value or by adding a second adjustment resistor to the circuit. If only the bias resistor is adjusted, then either the upper or the lower threshold can be modified but not both. The other trip point will be determined by the characteristics of the thermistor. Using the bias resistor in addition to an adjustment resistor, both the upper and the lower temperature trip points can be independently programmed with the constraint that the difference between the upper and lower temperature thresholds cannot decrease. Examples of each technique follows. NTC BLOCK 34 – RNTC 100k TOO_HOT 0.35 • NTCBIAS 0.26 • NTCBIAS + + BATTERY OVERTEMP – 3577 F09 Figure 9. NTC Thermistor Circuit with Additional Bias Resistor The trip points for the LTC3577’s temperature qualification are internally programmed at 0.35 • VNTC for the hot threshold and 0.76 • VNTC for the cold threshold. Therefore, the hot trip point is set when: RNTC|HOT RNOM + RNTC|HOT • NTCBIAS = 0.35 • NTCBIAS and the cold trip point is set when: RNTC|COLD RNOM + RNTC|COLD • NTCBIAS = 0.76 • NTCBIAS Solving these equations for RNTC|COLD and RNTC|HOT results in the following: RNTC|HOT = 0.538 • RNOM and RNTC|COLD = 3.17 • RNOM By setting RNOM equal to R25, the above equations result in rHOT = 0.538 and rCOLD = 3.17. Referencing these ratios to the Vishay Resistance-Temperature Curve 1 chart gives a hot trip point of about 40°C and a cold trip point of about 0°C. The difference between the hot and cold trip points is approximately 40°C. 3577f 27 LTC3577/LTC3577-1 OPERATION By using a bias resistor, RNOM, different in value from R25, the hot and cold trip points can be moved in either direction. The temperature span will change somewhat due to the non-linear behavior of the thermistor. The following equations can be used to easily calculate a new value for the bias resistor: r RNOM = HOT • R25 0.538 r RNOM = COLD • R25 3.17 Overvoltage Protection (OVP) The LTC3577 can protect itself from the inadvertent application of excessive voltage to VBUS or WALL with just two external components: an N-channel FET and a 6.2k resistor. The maximum safe overvoltage magnitude will be determined by the choice of the external NMOS and its associated drain breakdown voltage. Consider an example where a 60°C hot trip point is desired. From the Vishay Curve 1 R-T characteristics, rHOT is 0.2488 at 60°C. Using the above equation, RNOM should be set to 46.4k. With this value of RNOM, the cold trip point is about 16°C. Notice that the span is now 44°C rather than the previous 40°C. This is due to the decrease in “temperature gain” of the thermistor as absolute temperature increases. The overvoltage protection module consists of two pins. The first, OVSENS, is used to measure the externally applied voltage through an external resistor. The second, OVGATE, is an output used to drive the gate pin of an external FET. The voltage at OVSENS will be lower than the OVP input voltage by (IOVSENS • 6.2k) due to the OVP circuit’s quiescent current. The OVP input will be 200mV to 400mV higher than OVSENS under normal operating conditions. When OVSENS is below 6V, an internal charge pump will drive OVGATE to approximately 1.88 • OVSENS. This will enhance the N-channel FET and provide a low impedance connection to VBUS or WALL which will, in turn, power the LTC3577. If OVSENS should rise above 6V (6.35V OVP input) due to a fault or use of an incorrect wall adapter, OVGATE will be pulled to GND, disabling the external FET to protect downstream circuitry. When the voltage drops below 6V again, the external FET will be re-enabled. The upper and lower temperature trip points can be independently programmed by using an additional bias resistor as shown in Figure 9. The following formulas can be used to compute the values of RNOM and R1: –r r RNOM = COLD HOT • R25 2.714 R1= 0.536 • RNOM – rHOT • R25 In an overvoltage condition, the OVSENS pin will be clamped at 6V. The external 6.2k resistor must be sized appropriately to dissipate the resultant power. For example, a 1/10W 6.2k resistor can have at most √PMAX • 6.2kΩ = 24V applied across its terminals. With the 6V at OVSENS, the maximum overvoltage magnitude that this resistor can withstand is 30V. A 1/4W 6.2k resistor raises this value to 45V. For example, to set the trip points to 0°C and 45°C with a Vishay Curve 1 thermistor choose The charge pump output on OVGATE has limited output drive capability. Care must be taken to avoid leakage on this pin, as it may adversely affect operation. where rHOT and rCOLD are the resistance ratios at the desired hot and cold trip points. Note that these equations are linked. Therefore, only one of the two trip points can be chosen, the other is determined by the default ratios designed in the IC. RNOM = 3.266 – 0.4368 • 100k = 104.2k 2.714 the nearest 1% value is 105k. R1 = 0.536 • 105k – 0.4368 • 100k = 12.6k the nearest 1% value is 12.7k. The final solution is shown in Figure 9 and results in an upper trip point of 45°C and a lower trip point of 0°C. Dual Input Overvoltage Protection It is possible to protect both VBUS and WALL from overvoltage damage with several additional components, as shown in Figure 10. Schottky diodes D1 and D2 pass the larger of V1 and V2 to R1 and OVSENS. If either V1 or V2 exceeds 6V plus VF(SCHOTTKY), OVGATE will be pulled to GND and both the WALL and USB inputs will be protected. 3577f 28 LTC3577/LTC3577-1 OPERATION MN1 MP1 USB/WALL ADAPTER WALL V1 MN1 VBUS OVGATE LTC3577 LTC3577 V2 D2 D1 MN2 C1 D1 R1 500k VBUS R2 6.2k OVGATE OVSENS C1 3577 F11 D1: 5.6V ZENER MP1: Si2323DS, BVDSS = 20V VBUS POSITIVE PROTECTION UP TO BVDSS OF MN1 VBUS NEGATIVE PROTECTION UP TO BVDSS OF MP1 R1 OVSENS 3577 F10 Figure 10. Dual Input Overvoltage Protection Each input is protected up to the drain-source breakdown, BVDSS, of MN1 and MN2. R1 must also be rated for the power dissipated during maximum overvoltage. See the “Overvoltage Protection” section for an explanation of this calculation. Table 2 shows some NMOS FETs that are suitable for overvoltage protection. Figure 11. Dual Polarity Voltage Protection VINLDOx LDOxEN 0 MP LDOx 1 LDOx OUTPUT R1 LDOx_FB Table 2. Recommended Overvoltage FETs NMOS FET BVDSS RON PACKAGE Si1472DH 30V 82mΩ SC70-6 Si2302ADS 20V 60mΩ SOT-23 Si2306BDS 30V 65mΩ SOT-23 Si2316BDS 30V 80mΩ SOT-23 IRLML2502 20V 35mΩ SOT-23 Reverse Input Voltage Protection The LTC3577 can also be easily protected against the application of reverse voltage as shown in Figure 10. D1 and R1 are necessary to limit the maximum VGS seen by MP1 during positive overvoltage events. D1’s breakdown voltage must be safely below MP1’s BVGS. The circuit shown in Figure 11 offers forward voltage protection up to MN1’s BVDSS and reverse voltage protection up to MP1’s BVDSS. LOW DROPOUT LINEAR REGULATOR OPERATION LDO Operation and Voltage Programming The LTC3577 contains two 150mA adjustable output LDO regulators. To enable the LDOs write a 1 to the LDO1EN and/or LDO2EN I2C registers. The LDOs can be disabled three ways: 1) Write a 0 to the LDO1EN and LDO2EN registers; 2) Bring DVCC below the DVCC undervoltage threshold; 3) Enter the power-down pushbutton state. 0.8V GND COUT R2 3577 F12 Figure 12. LDO Application Circuit The LDOs are further disabled if VOUT falls below the VOUT UVLO threshold and cannot be enabled until the UVLO condition is removed. When disabled all LDO circuitry is powered off leaving only a few nanoamps of leakage current on the LDO supply. The LDO outputs are individually pulled to ground through internal resistors when disabled. The power good status bits of LDO1 and LDO2 are available in I2C through the read-back registers PGLDO[1] and PGLDO[2] for LDO1 and LDO2 respectively. The power good comparators for both LDOs are sampled when the I2C port receives the correct I2C read address. Figure 12 shows the LDO application circuit. The fullscale output voltage for each LDO is programmed using a resistor divider from the LDO output (LDO1 or LDO2) connected to the feedback pins (LDO1_FB or LDO2_FB) such that: ⎛ R1 ⎞ VLDOx = 0.8V • ⎜ + 1⎟ ⎝ R2 ⎠ 3577f 29 LTC3577/LTC3577-1 OPERATION For stability, each LDO output must be bypassed to ground with a minimum 1μF ceramic capacitor (COUT). the specified operating range as operation is not guaranteed beyond this range. LDO Operating as a Current Limited Switch Output Voltage Programming The LDO can be used as a current limited switch by simply connecting the LDOx_FB input to ground. In this case the LDOx output will be pulled up to VINLDOx through the LDO’s internal current limit (about 300mA). Enabling the LDO via the I2C interface effectively connects LDOx and VINLDOx, while disabling the LDO disconnected LDOx from VINLDOx. Figure 13 shows the step-down switching regulator application circuit. The full-scale output voltage for each step-down switching regulator is programmed using a resistor divider from the step-down switching regulator output connected to the feedback pins (FB1, FB2 and FB3) such that: STEP-DOWN SWITCHING REGULATOR OPERATION Introduction The LTC3577 includes three 2.25MHz constant frequency current mode step-down switching regulators providing 500mA, 500mA and 800mA each. All step-down switching regulators can be programmed for a minimum output voltage of 0.8V and can be used to power a microcontroller core, microcontroller I/O, memory or other logic circuitry. All step-down switching regulators support 100% duty cycle operation (low dropout mode) when the input voltage drops very close to the output voltage and are also capable of Burst Mode operation for highest efficiencies at light loads. Burst Mode operation is individually selectable for each step-down switching regulator through the I2C register bits BK1BRST, BK2BRST and BK3BRST. The step-down switching regulators also include soft-start to limit inrush current when powering on, short-circuit current protection, and switch node slew limiting circuitry to reduce EMI radiation. No external compensation components are required for the switching regulators. The regulators are sequenced up and down together through the pushbutton interface (see “Pushbutton Interface” section for more information). It is recommended that the step-down switching regulator input supplies (VIN12 and VIN3) be connected to the system supply pin (VOUT). This is recommended because the undervoltage lockout circuit on the VOUT pin (VOUT UVLO) disables the stepdown switching regulators when the VOUT voltage drops below the VOUT UVLO threshold. If driving the step-down switching regulator input supplies from a voltage other than VOUT the regulators should not be operated outside 30 ⎛ R1 ⎞ VOUTx = 0.8V • ⎜ + 1⎟ ⎝ R2 ⎠ Typical values for R1 are in the range of 40k to 1M. The capacitor CFB cancels the pole created by feedback resistors and the input capacitance of the FB pin and also helps to improve transient response for output voltages much greater than 0.8V. A variety of capacitor sizes can be used for CFB but a value of 10pF is recommended for most applications. Experimentation with capacitor sizes between 2pF and 22pF may yield improved transient response. VIN EN MODE PWM SLEW CONTROL MP SWx MN L VOUTx CFB R1 COUT FBx 0.8V GND R2 3577 F13 Figure 13. Step-Down Switching Regulator Application Circuit PG_DCDC Operation The PG_DCDC pin is an open-drain output used to indicate that all step-down switching regulators are enabled and have reached their final regulation voltage. A 230ms delay is included from the time all switching regulators reach 92% of their regulation value to allow a system controller ample time to reset itself. PG_DCDC may be used as a power-on reset to a microprocessor powered by the step-down switching regulators. PG_DCDC is an 3577f LTC3577/LTC3577-1 OPERATION open-drain output and requires a pull-up resistor to an appropriate power source. Optimally the pull-up resistor is connected to one of the step-down switching regulator output voltages so that power is not dissipated while the regulators are disabled. Operating Modes The step-down switching regulators include two possible operating modes to meet the noise/power needs of a variety of applications. In pulse-skipping mode, an internal latch is set at the start of every cycle, which turns on the main P-channel MOSFET switch. During each cycle, a current comparator compares the peak inductor current to the output of an error amplifier. The output of the current comparator resets the internal latch, which causes the main P-channel MOSFET switch to turn off and the N-channel MOSFET synchronous rectifier to turn on. The N-channel MOSFET synchronous rectifier turns off at the end of the 2.25MHz cycle or if the current through the N-channel MOSFET synchronous rectifier drops to zero. Using this method of operation, the error amplifier adjusts the peak inductor current to deliver the required output power. All necessary compensation is internal to the step-down switching regulator requiring only a single ceramic output capacitor for stability. At light loads in pulse-skipping mode, the inductor current may reach zero on each pulse which will turn off the N-channel MOSFET synchronous rectifier. In this case, the switch node (SW1, SW2 or SW3) goes high impedance and the switch node voltage will “ring.” This is discontinuous operation, and is normal behavior for a switching regulator. At very light loads in pulse-skipping mode, the step-down switching regulators will automatically skip pulses as needed to maintain output regulation. At high duty cycle (VOUTX approaching VINX) it is possible for the inductor current to reverse at light loads causing the stepped down switching regulator to operate continuously. When operating continuously, regulation and low noise output voltage are maintained, but input operating current will increase to a few milliamps. In Burst Mode operation, the step-down switching regulators automatically switch between fixed frequency PWM operation and hysteretic control as a function of the load current. At light loads the step-down switching regulators control the inductor current directly and use a hysteretic control loop to minimize both noise and switching losses. While operating in Burst Mode operation, the output capacitor is charged to a voltage slightly higher than the regulation point. The step-down switching regulator then goes into sleep mode, during which the output capacitor provides the load current. In sleep mode, most of the switching regulator’s circuitry is powered down, helping conserve battery power. When the output voltage drops below a pre-determined value, the step-down switching regulator circuitry is powered on and another burst cycle begins. The sleep time decreases as the load current increases. Beyond a certain load current point (about 1/4 rated output load current) the step-down switching regulators will switch to a low noise constant frequency PWM mode of operation, much the same as pulse-skipping operation at high loads. For applications that can tolerate some output ripple at low output currents, Burst Mode operation provides better efficiency than pulse-skipping at light loads. The step-down switching regulators allow mode transition on-the-fly, providing seamless transition between modes even under load. This allows the user to switch back and forth between modes to reduce output ripple or increase low current efficiency as needed. Burst Mode operation is individually selectable for each step-down switching regulator through the I2C register bits BK1BRST, BK2BRST and BK3BRST. Shutdown The step-down switching regulators are shut down when the pushbutton circuitry is in the power-down, power off or hard reset states. In shutdown all circuitry in the step-down switching regulator is disconnected from the switching regulator input supply leaving only a few nanoamps of leakage current. The step-down switching regulator outputs are individually pulled to ground through internal 10k resistors on the switch pin (SW1, SW2 or SW3) when in shutdown. Dropout Operation It is possible for a step-down switching regulator’s input voltage to approach its programmed output voltage (e.g., a battery voltage of 3.4V with a programmed output voltage of 3.3V). When this happens, the PMOS switch duty cycle 3577f 31 LTC3577/LTC3577-1 OPERATION increases until it is turned on continuously at 100%. In this dropout condition, the respective output voltage equals the regulator’s input voltage minus the voltage drops across the internal P-channel MOSFET and the inductor. Soft-Start Operation Soft-start is accomplished by gradually increasing the peak inductor current for each step-down switching regulator over a 500μs period. This allows each output to rise slowly, helping minimize inrush current required to charge up the switching regulator output capacitor. A soft-start cycle occurs whenever a given switching regulator is enabled. A soft-start cycle is not triggered by changing operating modes. This allows seamless output transition when actively changing between operating modes. Slew Rate Control The step-down switching regulators contain new patent pending circuitry to limit the slew rate of the switch node (SW1, SW2 and SW3). This new circuitry is designed to transition the switch node over a period of a few nanoseconds, significantly reducing radiated EMI and conducted supply noise while maintaining high efficiency. Since slowing the slew rate of the switch nodes causes efficiency loss, the slew rate of the step-down switching regulators is adjustable via the I2C registers SLEWCTL1 and SLEWCTL2. This allows the user to optimize efficiency or EMI as necessary with four different slew rate settings. The power-up default is the fastest slew rate (highest efficiency) setting. 100 Figures 14 and 15 show the efficiency and power loss graph for Buck3 programmed for 1.2V and 2.5V outputs. Note that the power loss curves remain fairly constant for both graphs yet changing the slew rate has a larger effect on the 1.2V output efficiency. This is mainly because for a given output current the 2.5V output is delivering more than 2x the power than the 1.2V output. Efficiency will always decrease and show more variation to slew rate as the programmed output voltage is decreased. Low Supply Operation An undervoltage lockout circuit on VOUT (VOUT UVLO) shuts down the step-down switching regulators when VOUT drops below about 2.7V. It is recommended that the stepdown switching regulator input supplies (VIN12, VIN3) be connected to the power path output (VOUT) directly. This UVLO prevents the step-down switching regulators from operating at low supply voltages where loss of regulation or other undesirable operation may occur. If driving the step-down switching regulator input supplies from a voltage other than the VOUT pin, the regulators should not be operated outside the specified operating range as operation is not guaranteed beyond this range. Inductor Selection Many different sizes and shapes of inductors are available from numerous manufacturers. Choosing the right inductor from such a large selection of devices can be overwhelming, but following a few basic guidelines will make the selection 100 1.00E+00 90 90 80 60 1.00E-02 50 Burst Mode OPERATION VIN = 3.8V SW[1:0] = 00 01 10 11 40 30 20 10 1.00E-0.3 IOUT3 (mA) 1.00E-01 1.00E-03 1.00E-04 1.00e-01 70 60 1.00E-02 50 Burst Mode OPERATION VIN = 3.8V SW[1:0] = 00 01 10 11 40 30 20 10 1.00E-05 3577 F14 Figure 14. VOUT3 (1.2V) Efficiency and Power Loss vs IOUT3 0 1.00E-05 1.00E-0.3 IOUT3 (mA) 1.00E-01 1.00E-03 POWER LOSS (W) 70 EFFICIENCY (%) 1.00e-01 POWER LOSS (W) EFFICIENCY (%) 80 0 1.00E-05 1.00E+00 1.00E-04 1.00E-05 3577 F15 Figure 15. VOUT3 (2.5V) Efficiency and Power Loss vs IOUT3 3577f 32 LTC3577/LTC3577-1 OPERATION Table 3. Recommended Inductors for Step-Down Switching Regulators INDUCTOR TYPE DB318C D312C DE2812C CDRH3D16 CDRH2D11 CLS4D09 SD3118 SD3112 SD12 SD10 LPS3015 L (μH) MAX IDC (A) MAX DCR (Ω) SIZE in mm (L × W × H) 4.7 3.3 4.7 3.3 4.7 3.3 1.07 1.20 0.79 0.90 1.15 1.37 0.1 0.07 0.24 0.20 0.13* 0.105* 3.8 × 3.8 × 1.8 3.8 × 3.8 × 1.8 3.6 × 3.6 × 1.2 3.6 × 3.6 × 1.2 3.0 × 2.8 × 1.2 3.0 × 2.8 × 1.2 Toko www.toko.com 4.7 3.3 4.7 3.3 4.7 0.9 1.1 0.5 0.6 0.75 0.11 0.085 0.17 0.123 0.19 4 × 4 × 1.8 4 × 4 × 1.8 3.2 × 3.2 × 1.2 3.2 × 3.2 × 1.2 4.9 × 4.9 × 1 Sumida www.sumida.com 4.7 3.3 4.7 3.3 4.7 3.3 4.7 3.3 1.3 1.59 0.8 0.97 1.29 1.42 1.08 1.31 0.162 0.113 0.246 0.165 0.117* 0.104* 0.153* 0.108* 3.1 × 3.1 × 1.8 3.1 × 3.1 × 1.8 3.1 × 3.1 × 1.2 3.1 × 3.1 × 1.2 5.2 × 5.2 × 1.2 5.2 × 5.2 × 1.2 5.2 × 5.2 × 1.0 5.2 × 5.2 × 1.0 Cooper www.cooperet.com 4.7 3.3 1.1 1.3 0.2 0.13 3.0 × 3.0 × 1.5 3.0 × 3.0 × 1.5 Coil Craft www.coilcraft.com MANUFACTURER *Typical DCR process much simpler. The step-down switching regulators are designed to work with inductors in the range of 2.2μH to 10μH. For most applications a 4.7μH inductor is suggested for step-down switching regulators providing up to 500mA of output current while a 3.3μH inductor is suggested for step-down switching regulators providing up to 800mA. Larger value inductors reduce ripple current, which improves output ripple voltage. Lower value inductors result in higher ripple current and improved transient response time, but will reduce the available output current. To maximize efficiency, choose an inductor with a low DC resistance. For a 1.2V output, efficiency is reduced about 2% for 100mΩ series resistance at 400mA load current, and about 2% for 300mΩ series resistance at 100mA load current. Choose an inductor with a DC current rating at least 1.5 times larger than the maximum load current to ensure that the inductor does not saturate during normal operation. If output short-circuit is a possible condition, the inductor should be rated to handle the maximum peak current specified for the step-down converters. Different core materials and shapes will change the size/current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or Permalloy materials are small and don’t radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. Inductors that are very thin or have a very small volume typically have much higher core and DCR losses, and will not give the best efficiency. The choice of which style inductor to use often depends more on the price versus size, performance, and any radiated EMI requirements than on what the step-down switching regulators requires to operate. The inductor value also has an effect on Burst Mode operation. Lower inductor values will cause Burst Mode switching frequency to increase. Table 3 shows several inductors that work well with the step-down switching regulators. These inductors offer a good compromise in current rating, DCR and physical size. Consult each manufacturer for detailed information on their entire selection of inductors. Input/Output Capacitor Selection Low ESR (equivalent series resistance) ceramic capacitors should be used at both step-down switching regulator outputs as well as at each step-down switching regulator input supply. Only X5R or X7R ceramic capacitors should be used because they retain their capacitance over wider voltage and temperature ranges than other ceramic types. A 10μF output capacitor is sufficient for the step-down switching regulator outputs. For good transient response 3577f 33 LTC3577/LTC3577-1 OPERATION and stability the output capacitor for step-down switching regulators should retain at least 4μF of capacitance over operating temperature and bias voltage. Each switching regulator input supply should be bypassed with a 2.2μF capacitor. Consult with capacitor manufacturers for detailed information on their selection and specifications of ceramic capacitors. Many manufacturers now offer very thin (<1mm tall) ceramic capacitors ideal for use in height-restricted designs. Table 4 shows a list of several ceramic capacitor manufacturers. Table 4. Ceramic Capacitor Manufacturers AVX www.avxcorp.com Murata www.murata.com Taiyo Yuden www.t-yuden.com Vishay Siliconix www.vishay.com TDK www.tdk.com LED BACKLIGHT/BOOST OPERATION Introduction The LED driver uses a constant frequency, current mode boost converter to supply power to up to 10 series LEDs. As shown in Figure 16 the series string of LEDs is connected from the output of the boost converter (BOOST) to the ILED pin. Under normal operation the boost converter BOOST output will be driven to a voltage where the ILED pin regulates at 300mV. The ILED pin is a constant-current sink that is programmed via I2C “LED DAC register”. The LED can be further controlled using I2C to program brightness levels and soft turn-on/turn-off effects. See the “I2C Interface” section for more information on programming the ILED current. The boost converter also includes an overvoltage protection feature to limit the BOOST output voltage as well as variable slew rate control of the SW pin to reduce EMI. LED Boost Operation The LED boost converter is designed for very high duty cycle operation and can boost from 3V to 40V for load currents up to 20mA. The boost converter also features an overvoltage protection feature to protect the output in case of an open circuit in the LED string. The overvoltage protection threshold is set by adjusting R1 in Figure 16 such that: BOOST(MAX) = 800mV • R1 +LED_ OV 10 •R2 where LED_OV is about 1.0V. In the case of Figure 16 BOOST(MAX) is set to 40V for a 10-LED string. Capacitor C3 provides soft-start, limiting the inrush current when the boost converter is first enabled. C3 provides feedback to the ILED pin. This feedback limits the rise time of output voltage and the inrush current while the output capacitor, C2, is charging. The boost converter will be operated in either continuous conduction mode, discontinuous conduction mode or pulse-skipping mode depending on the inductor current required for regulation. C1 22μF VOUT 39 LTC3577 18 SW 19 SW 20 SW LED_OV ILED_FS ILED L1 10μH LPS4018-103ML D12 ZLLS400 BOOST R1 9 10M 3 C2 1μF 50V R2 20k 22 D1 D2 C3 22nF 50V D10 D9 D3 D4 D5 D8 D7 D6 3577 F16 Figure 16. LED Boost Application Circuit LED Constant Current Sink The LED driver uses a precision current sink to regulate the LED current up to 20mA. The current sink is programmed via I2C “LED DAC Register” and utilizes a 6-bit 60dB exponential DAC. This DAC provides accurate current control from 20μA to 20mA with approximately 1dB per step for ILED(FS) = 20mA. The LED current can be approximated by the following equations: ILED =ILED(FS) • 10 DAC – 63 ⎞ ⎛ ⎜⎝ 3 • ⎟⎠ 63 0.8V ILED(FS) = • 500 R2 (1) 3577f 34 LTC3577/LTC3577-1 OPERATION where DAC is the decimal value programmed into the I2C “LED DAC register”. For example with ILED(FS) = 20mA and DAC[5:0] = 000000 (0 decimal) ILED equates to 20μA, while DAC[5:0] = 111111 (63 decimal) ILED equates to 20mA. As a final example DAC[5:0] = 101010 is 42 decimal and equates to ILED = 2mA for ILED(FS) = 20mA. The DAC approximates the Equation 1 using the nominal values in Table 5. The differences between the approximation equation and the table are due to design of the DAC using eight linear segments that approximate the exponential function. Table 5. LED DAC Codes to Output Current DAC Codes 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Output Current 20.0μA 23.5μA 27.0μA 30.5μA 34.0μA 37.6μA 41.1μA 44.6μA 48.1μA 56.5μA 65.0μA 73.4μA 81.9μA 90.3μA 98.7μA 107μA 116μA 136μA 156μA 177μA 197μA 217μA 237μA 258μA 278μA 327μA 376μA 424μA 473μA 522μA 571μA 620μA DAC Codes 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Output Current 668μA 786μA 903μA 1.02mA 1.14mA 1.26mA 1.37mA 1.49mA 1.61mA 1.89mA 2.17mA 2.45mA 2.74mA 3.02mA 3.30mA 3.58mA 3.86mA 4.54mA 5.22mA 5.90mA 6.58mA 7.26mA 7.93mA 8.61mA 9.29mA 10.8mA 12.4mA 13.9mA 15.4mA 17.0mA 18.5mA 20.0mA The full-scale LED current is set using a resistor (R2 in Figure 16) connected between the LED_FS pin and ground. Typically R2 should be set to 20k to give 20mA of LED current at full-scale. The resistance may be increased to decrease the current or the resistance may be decreased to increase the LED current. The DAC has been optimized for best performance at 20mA full-scale. The full-scale current may be adjusted but the accuracy of the output current will be degraded the further it is programmed from 20mA. The LED_FS pin is current limited and will only source about 80μA. This protects the pin and limits the ILED current in a case where LED_FS is shorted to ground, it is not recommended to program the LED current above 25mA. LED Gradation The LED driver features an automatic gradation circuit. The gradation circuit ramps the LED current up when the LED driver is enabled and ramps the current down when the LED driver is disabled. The DAC is enabled and disabled with the EN bit of the I2C “LED control register.” The gradation function is automatic when enabling and disabling the LED driver; only the gradation speed needs to be programmed to use this function. The gradation speed is set by the GR1 and GR2 bits of the I2C “LED control register” which allows transitions times of approximately 15ms, one-half second, one second and two seconds. See the “I2C Interface” section for more information. The gradation function allows the LEDs to turn on and off gradually as opposed to an abrupt step. LED PWM vs Constant Current Operation The LED driver provides both linear LED current mode as well as PWM LED current mode. These modes are selected through the MD1 and MD2 bits of the I2C “LED control register.” When both bits are 0 the LED boost converter is in constant current (CC) mode and the ILED current sink is constant whose value is set by the DAC[5:0] bits of the I2C “LED DAC register.” Setting MD1 to 0 and MD2 to 1 selects the LED PWM mode. In this mode the LED driver is pulsed using an internally generated PWM signal. The PWM mode may be used to reduce the LED intensity for a given programmed current. 3577f 35 LTC3577/LTC3577-1 OPERATION When dimming via PWM the LED driver and boost converter are both turned on and off together. This allows some degree of additional control over the LED current, and in some cases may offer a more efficient method of dimming since the boost could be operated at an optimal efficiency point and then pulsed for the desired LED intensity. The PWM mode, if enabled, is set up using 3 values; PWMNUM[3:0] and PWMDEN[3:0] in the I2C “LED PWM Register” and PWMCLK, set by PWMC2 and PWMC1 in the I2C “LED Control Register.” PWMNUM PWMDEN PWMCLK Frequency = PWMDEN Duty Cycle = Table 6. PWM Clock Frequency PWMC2 PWMC1 PWMCLK 0 0 8.77kHz 0 1 4.39kHz 1 0 2.92kHz 1 1 2.19kHz Using the PWM control, a 4-bit internally generated PWM is possible as additional dimming. Using these control bits a number of PWM duty cycles and frequencies are available in the 100Hz to 500Hz range. This range was selected to be below the audio range and above the frequency where the PWM is visible. For example, given PWMC2 = 1, PWMC1 = 0, PWMNUM[3:0] = 0111 and PWMDEN[3:0] = 1100 then the duty cycle will be 58.3% and PWM frequency will be 243Hz. If PWMNUM is set to 0 then the duty cycle will be 0% and the current sink will effectively be off. If PWMNUM is programmed to a value larger than PWMDEN the duty cycle will be 100% and the current sink will effectively be constant. PWMDEN and PWMNUM may both be changed to result in 73 different duty cycle possibilities and 41 different PWM frequencies between 8.77kHz and 100Hz. When PWM mode is enabled, a small (2μA) standby current source is always enabled on the ILED pin. The purpose of this is to have some current flowing in the LEDs at all times. This helps to reduce the magnitude of the voltage swing on the ILED pin as the current is pulsed on and off. Fixed Boost Output Setting MD1 to 1 and MD2 to 0 selects the fixed high voltage boost mode. This mode can be used to generate output voltages at or greater than VOUT . When configured as a boost converter the ILED pin becomes the feedback pin, and will regulate the output voltage such that the voltage on the ILED pin is 800mV. Figure 17 shows a fixed 12V output generated using the boost converter in the fixed high voltage boost mode. Any output voltage up to 40V may be programmed by selecting appropriate values for the R1 and R2 voltage divider from the equation: ⎛ R1 ⎞ VBOOST = 0.8V • ⎜ + 1⎟ ⎝ R2 ⎠ Values for R2 should be kept below 24.3k to keep the pole at ILED beyond cross over. The boost is designed primarily as a high voltage, high duty cycle converter. When operating with a lower boost ratio, a larger output capacitor, 10μF, should be used. Operating with a very low duty cycle will cause cycle skipping which will increase ripple. C1 22μF VOUT ILED_FS 39 3 LTC3577 SW SW SW ILED LED_OV 18 19 20 22 9 L4 10μH LPS4018-103ML D12 ZLLS400 800mV VREF R1 301k BOOST C2 10μF 10V R2 21.5k 3577 F17 Figure 17. Fixed 12V/75mA Boost Output Application 3577f 36 LTC3577/LTC3577-1 OPERATION To keep the average steady-state inductor current below 300mA the maximum output current is reduced as programmed output voltage increases. The output current available is given by: IBOOST(MAX) = 300mA • VOUT(MIN) VBOOST Note that the maximum boost output current must be set by the minimum VOUT operating voltage. If the boost converter is allowed to operate down to the VOUT UVLO then 2.5V must be assumed as the minimum operating VOUT voltage. Diode Selection When boosting to increasingly higher voltages, parasitic capacitance at the switch pin becomes an increasing large component of the switching loses. For this reason it is important to minimize the capacitance on the switch node. The diode selected should be sized to handle the peak inductor current and the average output current. At high boost voltages a diode with the lowest possible junction capacitance will often result in a more efficient solution than one with a lower forward drop. I2C OPERATION Inductor Selection I2C Interface The LED boost converter is designed to work with a 10μH inductor. The inductor must be able to handle a peak current of 1A and should have a low ESR value for good efficiency. Table 7 shows several inductors that work well with the LED boost converter. These inductors offer a good compromise in current rating, DCR and physical size. Consult each manufacturer for detailed information on their entire selection of inductors. The LTC3577 may communicate with a bus master using the standard I2C 2-wire interface. The Timing Diagram shows the relationship of the signals on the bus. The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources, such as the LTC1694 SMBus accelerator, are required on these lines. The LTC3577 is both a slave receiver and slave transmitter. The I2C control signals, SDA and SCL are scaled internally to the DVCC supply. DVCC should be connected to the same power supply as the bus pull-up resistors. The I2C port has an undervoltage lockout on the DVCC pin. When DVCC is below approximately 1V , the I2C serial port is cleared, the LTC3577 is set to its default configuration of all zeros. Table 7. Recommended Inductors for Boost Switching Reguators L (μH) MAX IDC (A) MAX DCR (Ω) SIZE in mm (L × W × H) DB62LCB 10 1.22 0.118 6.2 × 6.2 × 2 CDRH4D16NP-100M 10 10.5 0.155 4.8 × 4.8 × 1.8 Sumida www.sumida.com SD18-100-R 10 1.28 0.158* 5.2 × 5.2 × 1.8 Cooper www.cooperet.com LPS4018-103 10 1.1 0.200 4.0 × 4.0 × 1.8 Coil Craft www.coilcraft.com INDUCTOR TYPE MANUFACTURER Toko www.toko.com *Typical 3577f 37 LTC3577/LTC3577-1 OPERATION I2C Timing Diagram DATA BYTE A ADDRESS DATA BYTE B WR A7 0 0 0 1 0 0 1 0 SDA 0 0 0 1 0 0 1 0 ACK SCL 1 2 3 4 5 6 7 8 9 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 START STOP ACK 1 2 3 4 5 6 7 8 9 ACK 1 2 3 4 5 6 7 8 9 SDA tSU, STA tSU, DAT tLOW tHD, STA tHD, DAT tBUF tSU, STO 3577 TD SCL tHIGH tHD, STA START CONDITION tr tSP tf REPEATED START CONDITION STOP CONDITION START CONDITION I2C Bus Speed I2C Acknowledge The I2C port is designed to be operated at speeds of up to 400kHz. It has built-in timing delays to ensure correct operation when addressed from an I2C compliant master device. It also contains input filters designed to suppress glitches should the bus become corrupted. The acknowledge signal is used for handshaking between the master and the slave. When the LTC3577 is written to (write address), it acknowledges its write address as well as the subsequent two data bytes. When it is read from (read address), the LTC3577 acknowledges its read address only. The bus master should acknowledge receipt of information from the LTC3577. I2C START and STOP Conditions A bus master signals the beginning of communications by transmitting a START condition. A START condition is generated by transitioning SDA from HIGH to LOW while SCL is HIGH. The master may transmit either the slave write or the slave read address. Once data is written to the LTC3577, the master may transmit a STOP condition which commands the LTC3577 to act upon its new command set. A STOP condition is sent by the master by transitioning SDA from LOW to HIGH while SCL is HIGH. The bus is then free for communication with another I2C device. I2C Byte Format Each byte sent to or received from the LTC3577 must be 8 bits long followed by an extra clock cycle for the acknowledge bit. The data should be sent to the LTC3577 most significant bit (MSB) first. An acknowledge (active LOW) generated by the LTC3577 lets the master know that the latest byte of information was received. The acknowledge related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the acknowledge clock cycle. The LTC3577 pulls down the SDA line during the write acknowledge clock pulse so that it is a stable LOW during the HIGH period of this clock pulse. When the LTC3577 is read from, it releases the SDA line so that the master may acknowledge receipt of the data. Since the LTC3577 only transmits one byte of data, a master not acknowledging the data sent by the LTC3577 has no I2C specific consequence on the operation of the I2C port. 3577f 38 LTC3577/LTC3577-1 OPERATION I2C Slave Address The LTC3577 responds to a 7-bit address which has been factory programmed to b’0001001[R/W]’. The LSB of the address byte, known as the read/write bit, should be 0 when writing data to the LTC3577 and 1 when reading data from it. Considering the address an eight bit word, then the write address is 0x12 and the read address is 0x13. The LTC3577 will acknowledge both its read and write address. I2C Sub-Addressed Writing The LTC3577 has four command registers for control input. They are accessed by the I2C port via a subaddressed writing system. Each write cycle of the LTC3577 consists of exactly three bytes. The first byte is always the LTC3577’s write address. The second byte represents the LTC3577’s sub-address. The sub address is a pointer which directs the subsequent data byte within the LTC3577. The third byte consists of the data to be written to the location pointed to by the subaddress. The LTC3577 contains control registers at only four sub-address locations: 0x00, 0x01, 0x02 and 0x03. Writing to sub-addresses outside the four sub-addresses listed is not recommended as it can cause data in one of the four listed sub-addresses to be overwritten. I2C Bus Write Operation The master initiates communication with the LTC3577 with a START condition and the LTC3577’s write address. If the address matches that of the LTC3577, the LTC3577 returns an acknowledge. The master should then deliver the sub-address. Again the LTC3577 acknowledges and the cycle is repeated for the data byte. The data byte is transferred to an internal holding latch upon the return of its acknowledge by the LTC3577. This procedure must be repeated for each sub-address that requires new data. After one or more cycles of [ADDRESS][SUB-ADDRESS][DATA], the master may terminate the communication with a STOP condition. Alternatively, a REPEAT-START condition can be initiated by the master and another chip on the I2C bus can be addressed. This cycle can continue indefinitely and the LTC3577 will remember the last input of valid data that it received. Once all chips on the bus have been addressed and sent valid data, a global STOP can be sent and the LTC3577 will update its command latches with the data that it had received. I2C Bus Read Operation The bus master reads the status of the LTC3577 with a START condition followed by the LTC3577 read address. If the read address matches that of the LTC3577, the LTC3577 returns an acknowledge. Following the acknowledgement of its read address the LTC3577 returns one bit of status information for each of the next 8 clock cycles. A STOP command is not required for the bus read operation. I2C Input Data There are 4 bytes of data that can be written to on the LTC3577. The bytes are accessed through the subaddresses 0x00 to 0x03. At first power application (VBUS, WALL or BAT) all bits default to 0. Additionally all bits are cleared to 0 when DVCC drops below its undervoltage lock out or if the pushbutton enters the power-down (PDN1 or PDN2) state. Table 8. LDO and Buck Control Register LDO and BUCK CONTROL REGISTER ADDRESS: 00010010 SUB-ADDRESS: 00000000 BIT NAME FUNCTION B0 LDO1EN Enable LDO 1 B1 LDO2EN Enable LDO 2 B2 BK1BRST Buck1 Burst Mode Enable B3 BK2BRST Buck2 Burst Mode Enable B4 BK3BRST Buck2 Burst Mode Enable B5 SLEWCTL1 B6 SLEWCTL2 Buck SW Slew Rate: 00 = 1ns, 01 = 2ns, 10 = 4ns, 11 = 8ns B7 N/A Not Used—No Effect on Operation Table 8 shows the first byte of data that can be written to at sub-address 0x00. This byte of data is referred to as the “LDO and buck control register.” Bits B0 and B1 enable and disable the LDOs. Writing 1 to B0 or B1 will enable LDO1 or LDO2 respectively, while writing a 0 will disable the respective LDO. 3577f 39 LTC3577/LTC3577-1 OPERATION Bits B2, B3, and B4 set the operating modes of the stepdown switching regulators (bucks). Writing 1 to any of these three registers will put that respective buck converter in the high efficiency Burst Mode operation, while a 0 will enable the low noise pulse-skipping mode operation. The B5 and B6 bits adjust the slew rate of all SW pins together so they all slew at the same rate. It is recommended that the fastest slew rate (B6:B5 = 00) be used unless EMI is an issue in the application as slower slew rates cause reduced efficiency. Table 9. I2C LED Control Register LED CONTROL REGISTER BIT ADDRESS: 00010010 SUB-ADDRESS: 00000001 NAME FUNCTION B0 EN Enable: 1 = Enable 0 = Off B1 GR2 B2 GR1 Gradation GR[2:1]: 00 = 15ms, 01 = 460ms, 10 = 930ms, 11 = 1.85s B3 MD1 B4 MD2 B5 PWMC1 B6 PWMC2 PWM CLK PWMC[2:1]: 00 = 8.77kHz, 01 = 4.39kHz, 10 = 2.92kHz, 11 = 2.19kHz B7 SLEWLED LED SW Slew Rate: 0/1 = Fast/Slow Mode MD[2:1]: 00 = CC Boost, 10 = PWM Boost; 01 = HV Boost Table 9 shows the second byte of data that can be written to at sub-address 0x01. This byte of data is referred to as the “LED control register.” Bit B0 enables and disables the LED boost circuitry. Writing a 1 to B0 enables the LED boost circuitry, while writing a 0 disables the LED boost circuitry. Bits B5 and B6 set the PWM clock speed as shown in Table 9 of the “LED Backlight / Boost Operation” section. Bit B7 sets the slew rate of the LED boost SW pin. Setting B7 to 0 results in the fastest slew rate and provides the most efficient mode of operation. Setting B7 to 1 should only be used in cases where EMI due to SW slewing is an issue as the slower slew rate causes a loss in efficiency. See “LED Backlight/Boost Operation” section for more detailed operating information. Table 10 shows the third byte of data that can be written to at sub-address 0x02. This byte of data is referred to as the “LED DAC register.” The LED current source utilizes a 6-bit 60dB exponential DAC. This DAC provides accurate current control from 20μA to 20mA with approximately 1dB per step with ILED(FS) programmed to 20mA. The LED current can be approximated by the following equation: ILED =ILED(FS) • 10 DAC – 63 ⎞ ⎛ ⎜⎝ 3 • ⎟⎠ 63 where DAC is the decimal value programmed into the I2C “LED DAC register.” For example with ILED(FS) = 20mA and DAC[5:0] = 101010 (42 decimal) ILED equates to 2mA. Table 10. I2C LED DAC Register LED DAC REGISTER ADDRESS: 00010010 SUB-ADDRESS: 00000010 BIT NAME FUNCTION B0 DAC[0] 6-Bit Log DAC Code B1 DAC[1] Bits B1 and B2 are the LED gradation which sets the ramp up and down time of the LED current when enabled or disabled. The gradation function allows the LEDs to turn on/off gradually as opposed to an abrupt step. B2 DAC[2] B3 DAC[3] B4 DAC[4] B5 DAC[5] Bits B3 and B4 set the operating mode of the LED boost circuitry. The operating modes are: B4:B3 = 00 LED constant current (CC) boost operation; B4:B3 = 10 LED PWM boost operation; B4:B3 = 01 fixed high voltage (HV) output boost operation; B4:B3 = 11 not supported, do not use. See the “LED Backlight/Boost Operation” section for more information on the operating modes. B6 N/A Not Used—No Effect On Operation B7 N/A Not Used—No Effect On Operation 3577f 40 LTC3577/LTC3577-1 OPERATION Table 11 shows the final byte of data that can be written to at sub-address 0x03. This byte of data is referred to as the “LED PWM register”. See the “LED PWM vs Constant Current Operation” section for detailed information on how to set the values of this register. Table 11. LED PWM Register LED PWM REGISTER ADDRESS: 00010010 SUB-ADDRESS: 00000011 BIT NAME FUNCTION B0 PWMDEN[0] PWM DENOMINATOR B1 PWMDEN[1] B2 PWMDEN[2] B3 PWMDEN[3] B4 PWMNUM[0] B5 PWMNUM[1] B6 PWMNUM[2] B7 PWMNUM[3] PWM NUMERATOR I2C Output Data One status byte may be read from the LTC3577. Table 12 represents the status byte information. A 1 read back in the any of the bit positions indicates that the condition is true. For example, 1 read back from bit A3 indicate that LDO1 is enabled and regulating correctly. A status read from the LTC3577 captures the status information when the LTC3577 acknowledges its read address. Table 12. I2C READ Register STATUS REGISTER ADDRESS: 00010011 SUB-ADDRESS: None BIT NAME FUNCTION A0 CHARGE Charge Status (1 = Charging) A1 STAT[0] A2 STAT[1] STAT[1:0]; 00 = No Fault 01 = TOO COLD/HOT 10 = BATTERY OVERTEMP 11 = BATTERY FAULT A3 PGLDO[1] LDO1 Power Good A4 PGLDO[2] LDO2 Power Good A5 PGBCK[1] Buck1 Power Good A6 PGBCK[2] Buck2 Power Good A7 PGBCK[3] Buck3 Power Good Bit A7 shows the power good status of buck3. A 1 indicates that buck3 is enabled and is regulating correctly. A 0 indicates that either buck3 is not enabled, or that the buck3 is enabled, but is out of regulation by more than 8%. Bit A6 shows the power good status of buck2. A 1 indicates that buck2 is enabled and is regulating correctly. A 0 indicates that either buck2 is not enabled, or that the buck2 is enabled, but is out of regulation by more than 8%. Bit A5 shows the power good status of buck1. A 1 indicates that buck1 is enabled and is regulating correctly. A 0 indicates that either buck1 is not enabled, or that the buck1 is enabled, but is out of regulation by more than 8%. Bit A4 shows the power good status of LDO2. A 1 indicates that LDO2 is enabled and is regulating correctly. A 0 indicates that either LDO2 is not enabled, or that the LDO2 is enabled, but is out of regulation by more than 8%. Bit A3 shows the power good status of LDO1. A 1 indicates that LDO1 is enabled and is regulating correctly. A 0 indicates that either LDO1 is not enabled, or that the LDO1 is enabled, but is out of regulation by more than 8%. Bits A2 and A1 indicate the fault status of the charger circuit and are decoded in Table 12. The “too cold/hot” state indicates that the thermistor temperature is out of the valid charging range (either below 0°C or above 40°C for a curve 1 thermistor) and that charging has paused until a return to valid temperature. The battery overtemp state indicates that the battery’s thermistor has reached a critical temperature (above 50°C for a curve 1 thermistor) and that long-term battery capacity may be seriously compromised if the condition persists. The battery fault state indicates that an attempt was made to charge a low battery (typically < 2.85V) but that the low voltage condition persisted for more than 1/2 hour. In this case charging has terminated. Bit A0 indicates the status of the battery charger. A 1 indicates that the charger is enabled and is in the constant current charge state. In this case the battery is being charged unless the NTC thermistor is outside its valid charge range in which case charging is temporarily suspended but not complete. Charging will continue once the 3577f 41 LTC3577/LTC3577-1 OPERATION battery has returned to a valid charging temperature. A 0 in bit A0 indicates that charging has entered the end-ofcharge state (hC/10) and is near VFLOAT or that charging has been terminated. Charging can be terminated by reaching the end of the charge timer or by a battery fault as described previously. I2C WRITE REGISTER MAP (see “I2C Input Data” section for more details, all registers default to 0 when reset) LDO and BUCK CONTOL REGISTER BIT NAME B0 LDO1EN B1 LDO2EN B2 BK1BRST B3 BK2BRST B4 BK3BRST B5 SLEWCTL1 B6 SLEWCTL2 B7 N/A ADDRESS: 00010010 SUB-ADDRESS: 00000000 FUNCTION Enable LDO 1 Enable LDO 2 Buck1 Burst Mode Enable Buck2 Burst Mode Enable Buck2 Burst Mode Enable Buck SW Slew Rate: 00 = 1ns, 01 = 2ns, 10 = 4ns, 11 = 8ns LED CONTROL REGISTER BIT NAME B0 EN B1 GR2 B2 GR1 B3 MD1 B4 MD2 B5 PWMC1 B6 PWMC2 B7 SLEWLED ADDRESS: 00010010 SUB-ADDRESS: 00000001 FUNCTION Enable: 1= Enable 0 = Off LED DAC REGISTER BIT NAME B0 DAC[0] B1 DAC[1] B2 DAC[2] B3 DAC[3] B4 DAC[4] B5 DAC[5] B6 N/A B7 N/A Not Used—No Effect On Operation Gradation GR[2:1]: 00 = 15ms, 01 = 460ms, 10 = 930ms, 11 = 1.85 Seconds Mode MD[2:1]: 00 = CC Boost, 10 = PWM Boost, 01 = HV Boost ADDRESS: 00010010 SUB-ADDRESS: 00000011 FUNCTION PWM Denominator LED PWM REGISTER BIT NAME B0 PWMDEN[0] B1 PWMDEN[1] B2 PWMDEN[2] B3 PWMDEN[3] B4 PWMNUM[0] B5 PWMNUM[1] B6 PWMNUM[2] B7 PWMNUM[3] PWM Numerator PUSHBUTTON INTERFACE OPERATION State Diagram/Operation Figure 18 shows the LTC3577 pushbutton state diagram. Upon first application of power (VBUS, WALL or BAT) an internal power-on reset (POR) signal places the pushbutton circuitry into the power-down (PDN1) state. One second after entering the PDN1 state the pushbutton circuitry will transition into the hard reset (HR) state. The following events cause the state machine to transition out of HR into the power-up (PUP1) state: 1) ON input low for 400ms (PB400MS) 2) Application of external power (EXTPWR) 3) PWR_ON input going high (PWR_ON) PWM CLK PWMC[2:1]: 00 = 8.77kHz, 01 = 4.39kHz, 10 = 2.92kHz, 11 = 2.19kHz LED SW Slew rate: 0/1 = Fast/Slow ADDRESS: 00010010 SUB-ADDRESS: 00000010 FUNCTION 6-Bit Log DAC Code HR PB400MS + EXTPWR + PWR_ON PUP2 PB400MS + EXTPWR + PWR_ON PUP1 5SEC POFF 1SEC Not Used—No Effect On 0peration Not Used—No Effect On 0peration PON PWR_ON +UVLO PDN2 5SEC HRST HRST HRST PDN1 1SEC POR Figure 18. Pushbutton State Diagram 3577f 42 LTC3577/LTC3577-1 OPERATION Upon entering the PUP1 state, the pushbutton circuitry will sequence up the three step-down switching regulators in numerical order. LDO1, LDO2 and LED backlight are enabled via I2C and do not take part in the power-up sequence of the pushbutton. Five seconds after entering the PUP1 state, the pushbutton circuitry will transition into the power-on (PON) state. Note that the PWR_ON input must be brought high before entering the PON state if the part is to remain in the PON state. PWR_ON going low, or VOUT dropping to its undervoltage lockout (VOUT UVLO) threshold will cause the state machine to leave the PON state and enter the power-down (PDN2) state. The PDN1 and PDN2 states reset the I2C registers effectively shutting down the LDOs and LED backlight as well as disable all switching regulators together. The one second delay before leaving either power-down state allows all LTC3577 generated supplies to power down completely before they can be re-enabled. The same three events used to exit HR are also used to exit the POFF state and enter PUP2 state. The PUP2 state operates in the same manner as the PUP1 state previously described. The hard reset (HRST) event is generated by pressing and holding the pushbutton (ON input low) for 5 seconds. For a valid HRST event to occur the initial pushbutton application must start in the PUP1, PUP2 or PON state, but can end in any state. If a valid HRST event is present in PON, PDN2 or POFF, then the state machine will transition to the PDN1 state and subsequently transition to the HR state one second later. In the HR state all supplies are disabled and the PowerPath circuitry is placed in an ultralow quiescent state to minimize battery drain. If no external charging supply is present (WALL or VBUS) then the ideal diode is shut down disconnecting VOUT from BAT to further minimize battery drain. The ultralow power consumption in the HR state makes it ideal for shipping or long term storage, minimizing battery drain. Power-Up via Pushbutton Timing The timing diagram, Figure 19, shows the LTC3577 powering up through application of the external pushbutton. For this example the pushbutton circuitry starts in the POFF or HR state with a battery connected and all buck disabled. Pushbutton application (ON low) for 400ms transitions the pushbutton circuitry into the PUP state which brings WAKE Hi-Z for 5 seconds. WAKE going Hi-Z sequences buck1-3 up in numerical order. WAKE will stay Hi-Z if PWR_ON is driven high before the 5 seconds PUP period is over. If PWR_ON is low or goes low after the 5 second period, WAKE will go low and buck1-3 will be shut down together. PG_DCDC is asserted once all enabled bucks are within 8% of their regulation voltage for 230ms. PBSTAT does not go low impedance with ON going low during the power-up pushbutton application. PBSTAT will go low impedance with ON on subsequent pushbutton applications once in the PUP1, PUP2 or PON states. The LDOs and LED backlight can be enabled and disabled at any time via I2C once in the PUP1, PUP2 or PON states. The PWR_ON input can be driven via a μP/μC or by one of the buck outputs through a high impedance (100kΩ typ) to keep the bucks enabled as described above. BAT VBUS ON (PB) PBSTAT 400ms WAKE BUCKS SEQUENCE UP 123 230ms BUCK1-3 PG_DCDC 5SEC PWR_ON STATE POFF/HR PUP2/PUP1 PON 3755 F19 Figure 19. Power-Up via Pushbutton Timing 3577f 43 LTC3577/LTC3577-1 OPERATION Power-Up via External Power Timing Power-Up via PWR_ON Timing The timing diagram, Figure 20, shows the LTC3577 powering up through application of the external power (VBUS or WALL). For this example the pushbutton circuitry starts in the POFF or HR state with a battery connected and all buck disabled. 100ms after WALL or VBUS application the WAKE output goes Hi-Z for 5 seconds. The 100ms delay time allows the applied supply to settle. WAKE going Hi-Z sequences buck1-3 up in numerical order. WAKE will stay Hi-Z if the PWR_ON input is driven high before the 5 seconds PUP period is over. If PWR_ON is low or goes low after the 5 second period, WAKE will go low and buck1-3 will be shut down together. PG_DCDC is asserted once all enabled bucks are within 8% of their regulation voltage for 230ms. The timing diagram, Figure 21, shows the LTC3577 powering up by driving PWR_ON high. For this example the pushbutton circuitry starts in the POFF or HR state with a battery connected and all bucks disabled. 50ms after PWR_ON goes high the WAKE output goes Hi-Z for 5 seconds. WAKE going Hi-Z sequences buck1-3 up in numerical order. WAKE will stay Hi-Z as long as PWR_ON is high at the end of the 5 second PUP period. If PWR_ON is low or goes low after the 5 second period, WAKE will go low and buck1-3 will be shut down together. PG_DCDC is asserted once all enabled bucks are within 8% of their regulation voltage for 230ms. The LDOs and LED backlight can be enabled and disabled via I2C any time after entering the PUP1, PUP2 or PON state. The PWR_ON input can be driven via a μP/μC or one of the buck outputs through a high impedance (100kΩ typ) to keep the bucks enabled as described above. Without a battery present initial power application causes a power on reset which puts the pushbutton circuitry in the PDN2 state and subsequently the HR state 1 second later. In this case the pushbutton must be applied to enter the PUP1 state after initial power application. The LDOs and LED backlight can be enabled and disabled via I2C any time after entering the PUP1, PUP2 or PON state. Powering up via PWR_ON is useful for applications containing an always on μC. This allows the μC to power the application up and down for house keeping and other activities outside the user’s control. BAT ON (PB) PBSTAT 5SEC PWR_ON 5Oms WAKE BAT BUCKS SEQUENCE UP 123 BUCK1-3 VBUS 230ms PG_DCDC ON (PB) STATE PBSTAT POFF/HR PUP2/PUP1 PON 100ms 3577 F21 WAKE BUCKS SEQUENCE UP 123 230ms BUCK1-3 Figure 21. Power-Up via PWR_ON Timing PG_DCDC 5SEC PWR_ON STATE POFF/HR PUP2/PUP1 PON 3755 F20 Figure 20. Power-Up via External Power Timing 3577f 44 LTC3577/LTC3577-1 OPERATION Power-Down via Pushbutton Timing UVLO Minimum Off-Time Timing (Low Battery) The timing diagram, Figure 22, shows the LTC3577 powering down by μC/μP control. For this example the pushbutton circuitry starts in the PON state with a battery connected and all bucks enabled. In this case the pushbutton is applied (ON low) for at least 50ms, which generates a low impedance on the PBSTAT output. After receiving the PBSTAT the μC/μP will drive the PWR_ON input low. 50ms after PWR_ON goes low the WAKE output will go low and the pushbutton circuitry will enter the PDN2 state. The bucks are disabled together at once upon entering the PDN2 state. Once entering the PDN2 state a 1 second wait time is initiated before entering the POFF state. During this 1 second time ON and PWR_ON inputs as well as external power application are ignored to allow all LTC3577 generated supplies to go low. Though the above assumes a battery present, the same operation would take place with a valid external supply (VBUS or WALL) with or without a battery present. The timing diagram, Figure 23, assumes the battery is either missing or at a voltage below the VOUT UVLO threshold and the application is running via external power (VBUS or WALL). A glitch on the external supply causes VOUT to drop below the VOUT UVLO threshold temporarily. The VOUT UVLO condition will cause the pushbutton circuitry to transition from the PON state to the PDN2 state. Upon entering the PDN2 state WAKE and PG_DCDC will go low while the bucks, LDOs and LED backlight power down together. If the external supply recovers after entering the PND2 state such that VOUT is no longer in UVLO then the LTC3577 will transition back into the PUP2 state once the PDN2 one second delay is complete. Though not shown in Figure 23, the pushbutton logic briefly visits the POFF state when transitioning between PDN2 and PUP2. Entering the PUP2 state will cause the bucks to sequence up as described previously in the power-up sections. The LDOs and LED backlight must be re-enabled via I2C once device is powered back up. Upon entering the PDN2 state the LDOs and LED backlight I2C registers are cleared effectively disabling both. If this is not desirable the LDOs and LED backlight should be disabled via I2C prior to entering the PDN2 state. Holding ON low through the 1 second power-down period will not cause a power-up event at end of the 1 second period. The ON input must be brought high following the power-down event and then go low again to establish a valid power-up event. BAT VBUS/WALL ON (PB) PBSTAT 5SEC PWR_ON 1SEC WAKE BUCKS SEQUENCE UP 123 230ms BUCKS PG_DCDC BAT STATE PON VBUS/WALL PDN2 PUP2 PON 3577 F23 1SEC ON (PB) Figure 23. UVLO Minimum Off-Time 50ms PBSTAT μC/μP CONTROL PWR_ON 50ms WAKE ALL BUCKS LOW BUCK1-3 PG_DCDC STATE PON PDN2 POFF 3577 F22 Figure 22. Power-Down va Pushbutton Timing 3577f 45 LTC3577/LTC3577-1 OPERATION Hard Reset Timing Power-Up Sequencing Hard reset provides an ultralow power-down state for shipping or long-term storage as well as a way to power down the application in case of a software lock-up. In the case of software lock-up ON is brought low by the user applying the pushbutton. If the user holds the pushbutton for 5 seconds a hard reset event (HRST) will occur placing the pushbutton circuitry in the PDN1 state. At this point the bucks, LDOs and LED backlight will all be shut down and WAKE and PG_DCDC will both go low. Following a 1 second power-down period the pushbutton circuitry will enter the hard reset state (HR). Figure 25 shows the actual power-up sequencing of the LTC3577. Buck1, buck2 and buck3 are all initially disabled (0V). Once the pushbutton has been applied (ON low) for 400ms, WAKE goes high and buck1 is enabled. Buck1 slews up and enters regulation once enabled. The actual slew rate is controlled by the soft-start function of buck1 in conjunction with output capacitance and load (see “Step-Down Switching Regulator Operation” section for more information). When buck1 is within about 8% of final regulation, buck2 is enabled and slews up into regulation. Finally when buck2 is within about 8% of final regulation, buck3 is enabled and slews up into regulation. 230ms after buck3 is within 8% of final regulation the PG_DCDC output will go high impedance (not shown in Figure 25). The regulators in Figure 25 are slewing up with nominal output capacitors and no load. Adding a load or increasing output capacitance on any of the outputs will reduce the slew rate and lengthen the time it takes the regulator to get into regulation. Reducing the slew rate also pushes out the time until the next regulator is enabled proportionally. Holding ON low through the 1 second power-down period will not cause a power-up event at end of the 1second period. The ON must be brought high following the power-down event and then go low for again for 400ms to establish a valid power up event as shown in Figure 24. BAT 5SEC 1 ON (PB) WAKE PBSTAT 0 400ms WAKE BUCK1 2V/DIV 123 BUCKS 1SEC PWR_ON 0V PG_DCDC STATE 0V BUCK2 1V/DIV PON PDN1 HR PUP 3577 F24 Figure 24. Hard Reset Timing BUCK3 1V/DIV 0V 50μs/DIV 3577 F23 Figure 25. Power-Up Sequencing 3577f 46 LTC3577/LTC3577-1 OPERATION LAYOUT AND THERMAL CONSIDERATIONS Printed Circuit Board Power Dissipation In order to be able to deliver maximum charge current under all conditions, it is critical that the exposed ground pad on the backside of the LTC3577 package is soldered to a ground plane on the board. Correctly soldered to 2500mm2 ground plane on a double-sided 1oz. copper board the LTC3577 has a thermal resistance (θJA) of approximately 45°C/W. Failure to make good thermal contact between the Exposed Pad on the backside of the package and a adequately sized ground plane will result in thermal resistances far greater than 45°C/W. The conditions that cause the LTC3577 to reduce charge current due to the thermal protection feedback can be approximated by considering the power dissipated in the part. For high charge currents with a wall adapter applied to VOUT, the LTC3577 power dissipation is approximately: PD = (VOUT – BAT) • IBAT + PDREGS where, PD is the total power dissipated, VOUT is the system supply voltage, BAT is the battery voltage, and IBAT is the battery charge current. PDREGS is the sum of power dissipated on-chip by the step-down switching, LDO and LED boost regulators. The power dissipated by a step-down switching regulator can be estimated as follows: PD(SWx) = (BOUTx •IOUT ) • 100 – Eff 100 where BOUTx is the programmed output voltage, IOUT is the load current and Eff is the % efficiency which can be measured or looked up on an efficiency table for the programmed output voltage. The power dissipated on chip by a LDO regulator can be estimated as follows: PDLDOx = (VINLDOx – LOUTx) • IOUT where LOUTx is the programmed output voltage, VINLDOx is the LDO supply voltage and IOUT is the LDO output load current. Note that if the LDO supply is connected to one of the buck output, then its supply current must be added to the buck regulator load current for calculating the buck power loss. The power dissipated by the LED boost regulator can be estimated as follows: ⎛ BOOST ⎞ PDLED =ILED • 0.3V + RNSWON • ⎜ ILED • V – 1⎟⎠ ⎝ 2 OUT where BOOST is the output voltage driving the top of the LED string, RNSWON is the on-resistance of the SW N-FET (typically 330mΩ), ILED is the LED programmed current sink. Thus the power dissipated by all regulators is: PDREGS = PDSW1 + PDSW2 + PDSW3 + PDLDO1 + PDLDO2 + PDLED It is not necessary to perform any worst-case power dissipation scenarios because the LTC3577 will automatically reduce the charge current to maintain the die temperature at approximately 110°C. However, the approximate ambient temperature at which the thermal feedback begins to protect the IC is: TA = 110°C – PD • θJA Example: Consider the LTC3577 operating from a wall adapter with 5V (VOUT) providing 1A (IBAT) to charge a Li-Ion battery at 3.3V (BAT). Also assume PDREGS = 0.3W, so the total power dissipation is: PD = (5V – 3.3V) • 1A + 0.3W = 2W The ambient temperature above which the LTC3577 will begin to reduce the 1A charge current, is approximately TA = 110°C – 2W • 45°C/W = 20°C 3577f 47 LTC3577/LTC3577-1 OPERATION The LTC3557 can be used above 20°C, but the charge current will be reduced below 1A. The charge current at a given ambient temperature can be approximated by: PD = 110°C – TA = ( VOUT – BAT ) •IBAT + PD(REGS) θ JA Thus: (110°C − TA ) − PDREGS θ JA IBAT = VOUT – BAT Consider the above example with an ambient temperature of 55°C. The charge current will be reduced to approximately: 110°C – 55°C − 0.3W 45°C/W IBAT = 5V – 3.3V 1.22W – 0.3W = 542mA 1.7V If an external buck switching regulator controlled by the LTC3577 VC pin is used instead of a 5V wall adapter we see a significant reduction in power dissipated by the LTC3577. This is because the external buck switching regulator will drive the PowerPath output (VOUT) to about 3.6V with the battery at 3.3V. If you go through the example above and substitute 3.6V for VOUT we see that thermal regulation does not kick in until about 83°C. Thus, the external high voltage buck regulator not only allows higher charging currents, but lower power dissipation means a cooler running application. IBAT = Printed Circuit Board Layout When laying out the printed circuit board, the following list should be followed to ensure proper operation of the LTC3577: 1. The Exposed Pad of the package (Pin 45) should connect directly to a large ground plane to minimize thermal and electrical impedance. 2. The step-down switching regulator input supply pins (VIN12 and VIN3) and their respective decoupling capacitors should be kept as short as possible. The GND side of these capacitors should connect directly to the ground plane of the part. These capacitors provide the AC current to the internal power MOSFETs and their drivers. It’s important to minimizing inductance from these capacitors to the pins of the LTC3577. Connect VIN12 and VIN3 to VOUT through a short low impedance trace. 3. The switching power traces connecting SW1, SW2, and SW3 to their respective inductors should be minimized to reduce radiated EMI and parasitic coupling. Due to the large voltage swing of the switching nodes, sensitive nodes such as the feedback nodes (FBx, LDOx_FB and LED_OV) should be kept far away or shielded from the switching nodes or poor performance could result. 4. Connections between the step-down switching regulator inductors and their respective output capacitors should be kept should be kept as short as possible. The GND side of the output capacitors should connect directly to the thermal ground plane of the part. 5. Keep the buck feedback pin traces (FB1, FB2, and FB3) as short as possible. Minimize any parasitic capacitance between the feedback traces and any switching node (i.e. SW1, SW2, SW3, and logic signals). If necessary shield the feedback nodes with a GND trace. 6. Connections between the LTC3577 PowerPath pins (VBUS and VOUT) and their respective decoupling capacitors should be kept as short as possible. The GND side of these capacitors should connect directly to the ground plane of the part. 7. The boost converter switching power trace connecting SW to the inductor should be minimized to reduce radiated EMI and parasitic coupling. Due to the large voltage swing of the SW node, sensitive nodes such as the feedback nodes (FBx, LDOx_FB and LED_OV) should be kept far away or shielded from this switching node or poor performance could result. 3577f 48 LTC3577/LTC3577-1 TYPICAL APPLICATION USB Plus 5V Adapter Input Charger, Multi-Channel Power Supply and PowerPath Controller 5V WALL ADAPTER Si2333DS Si2306BDS D3 42 R1 13 6.2k 8 VC 4 WALL ACPR OVGATE VINLDO2 OVSENSE VOUT OPTIONAL OVERVOLTAGE/ REVERSE VOLTAGE PROTECTION VIN12 40 USB VBUS VIN3 10μF 2.1k 43 2k 36 CLPROG PROG Si2333DS 41 VOUT SYSTEM LOAD 30 10μF 39 2.2μF 32 2.2μF 1k 6 44 CHRG 37 IDGATE 38 BAT 34 100k NTCBIAS 35 NTC Si2333DS (OPT) BAT + Li-Ion 20μF 100k NTC 10μH LTC3577 10 DVCC 11 SDA 12 SCL DVCC SDA SCL 499k μC/μP WAKE PBSTAT PWR_ON RST LED_OV 1 ILIM0 2 ILIM1 ILIM0 ILIM1 15 VLDO2 2.5V 150mA 28 1μF 464k 232k 27 29 1μF 470k 18,19,20 9 22 ILED 499k 3 17 LED_FS WAKE 16 21 PBSTAT PG_DCDC 14 PWR_ON SW1 PUSHBUTTON VLDO1 1.2V 75mA ZLLS400 SW FB1 ON VINLDO1 SW2 LDO1 LDO1_FB FB2 SW3 LDO2 1.00M 24 LDO2_FB GND FB3 33 1μF 50V 6M 22nF 6-LED BACKLIGHT 20k 100k 4.7μH 10pF 26 1.02M 324k 10μF VOUT1 3.3V 500mA 23 31 4.7μH 10pF 25 5 7 806k 649k 10μF 3.3μH 10pF 232k 464k 10μF VOUT2 1.8V 500mA VOUT3 1.2V 800mA 45 3577 TA02 3577f 49 LTC3577/LTC3577-1 TYPICAL APPLICATION USB Plus HV Input Charger, Multi-Channel Power Supply and PowerPath Controller HVIN 8V TO 38V (TRANSIENTS TO 60V) 4 150k 68nF 4.7μF 5 40.2k 10 6 NC 7 NC LT3480 RUN/SS OPTIONAL HIGH VOLTAGE BUCK INPUT 2 BOOST VIN 0.47μF 6.8μH 3 SW 499k DFLS240L RT SYNC BD PG GND 22μF 1 100k 8 FB VC 11 9 Si2333DS 42 VC 4 41 WALL ACPR VINLDO2 Si2306BDS 40 USB VBUS VOUT 10μF VIN12 13 6.2k 8 OPTIONAL OVERVOLTAGE PROTECTION 2.1k 43 2k 36 VIN3 OVGATE OVSENSE CLPROG PROG VOUT SYSTEM LOAD 30 10μF 39 2.2μF 32 2.2μF 1k 6 44 CHRG 37 IDGATE 38 BAT 34 100k NTCBIAS 35 NTC Si2333DS (OPT) BAT + Li-Ion 20μF 100k NTC 10μH LTC3577 10 DVCC 11 SDA 12 SCL DVCC SDA SCL 499k μC/μP WAKE PBSTAT PWR_ON RST LED_OV 1 ILIM0 2 ILIM1 ILIM0 ILIM1 15 VLDO2 2.5V 150mA 28 1μF 464k 470k 9 SW1 FB1 ON VINLDO1 SW2 LDO1 33 1μF 50V 10M 10-LED BACKLIGHT 22nF 20k 100k 4.7μH 10pF 26 LDO1_FB FB2 SW3 LDO2 1.00M 24 LDO2_FB GND FB3 324k 10μF 4.7μH 10pF 27 1.02M VOUT1 3.3V 400mA 23 31 232k 29 1μF 18,19,20 22 ILED 499k 3 17 LED_FS WAKE 16 21 PBSTAT PG_DCDC 14 PWR_ON PUSHBUTTON VLDO1 1.2V 75mA ZLLS400 SW 806k 25 5 7 649k 10μF 3.3μH 10pF 232k 464k 10μF VOUT2 1.8V 400mA VOUT3 1.2V 600mA 45 3577 TA03 3577f 50 LTC3577/LTC3577-1 PACKAGE DESCRIPTION UFF Package Variation: UFFMA 44-Lead Plastic QFN (4mm × 7mm) (Reference LTC DWG # 05-08-1762 Rev Ø) 1.48 ±0.05 0.70 ±0.05 1.70 ±0.05 2.56 ±0.05 4.50 ±0.05 3.10 ±0.05 2.40 REF 2.02 ±0.05 2.76 ±0.05 2.64 ±0.05 0.98 ±0.05 PACKAGE OUTLINE 0.20 ±0.05 5.60 REF 6.10 ±0.05 7.50 ±0.05 0.40 BSC RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 p0.10 0.75 p0.05 PIN 1 NOTCH R = 0.30 TYP OR 0.35 s 45o CHAMFER 2.40 REF 43 0.00 – 0.05 44 0.40 p0.10 1 2 PIN 1 TOP MARK (SEE NOTE 6) 2.64 ±0.10 2.56 ±0.10 7.00 p0.10 5.60 REF 1.70 ±0.10 2.76 ±0.10 R = 0.10 TYP 0.74 ±0.10 R = 0.10 TYP 0.74 ±0.10 (UFF44MA) QFN REF Ø 1107 0.200 REF R = 0.10 TYP 0.98 ±0.10 0.20 p0.05 0.40 BSC BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3577f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 51 LTC3577/LTC3577-1 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3455 Dual DC/DC Converter with USB Power Manager and Li-Ion Battery Charger Seamless Transition Between Input Power Sources: Li-Ion Battery, USB and 5V Wall Adapter. Two High Efficiency DC/DC Converters: Up to 96%. Full Featured Li-Ion Battery Charger with Accurate USB Current Limiting (500mA/100mA). Pin Selectable Burst Mode Operation. Hot Swap™ Output for SDIO and Memory Cards. 24-Lead 4mm × 4mm QFN Package LTC3456 2-Cell, Multi-Output DC/DC Converter with USB Power Manager Seamless Transition Between 2-Cell Battery, USB and AC Wall Adapter Input Power Sources. Main Output: Fixed 3.3V Output, Core Output: Adjustable from 0.8V to VBATT(MIN). Hot Swap Output for Memory Cards. Power Supply Sequencing: Main and Hot Swap Accurate USB Current Limiting. High Frequency Operation: 1MHz. High Efficiency: Up to 92%. 24-Lead 4mm × 4mm QFN Package LTC3552 Standalone Linear Li-Ion Battery Charger with Adjustable Output Dual Synchronous Buck Converter Synchronous Buck Converter, Efficiency: >90%, Adjustable Outputs at 800mA and 400mA, Charge Current Programmable up to 950mA, USB Compatible, 16-Lead 5mm × 3mm DFN Package LTC3555 I2C Controlled High Efficiency USB Power Manager Plus Triple Step-Down DC/DC Maximizes Available Power from USB Port, Bat-Track, “Instant On” Operation, 1.5A Max Charge Current, 180mΩ Ideal Diode with <50mΩ Option, 3.3V/25mA Always-On LDO, Three Synchronous Buck Regulators, One 1A Buck-Boost Regulator, 4mm × 5mm QFN28 Package LTC3556 High Efficiency USB Power Manager Plus Dual Buck Plus Buck-Boost DC/DC Maximizes Available Power from USB Port, Bat-Track, “Instant On” Operation, 1.5A Max Charge Current, 180mΩ Ideal Diode with <50mΩ Option, 3.3V/25mA Always-On LDO, Two 400mA Synchronous Buck Regulators, One 1A Buck-Boost Regulator, 4mm × 5mm QFN28 Package LTC3557/ LTC3557-1 USB Power Manager with LiIon/Polymer Charger and Triple Synchronous Buck Converter Complete Multifunction ASSP: Linear Power Manager and Three Buck Regulaters Charge Current Programmable up to 1.5A from Wall Adapter Input, Thermal Regulation Synchronous Buck Efficiency: >95%, ADJ Outputs: 0.8V to 3.6V at 400mA/400mA/600mA Bat-Track Adaptive Output Control, 200m Ideal Diode, 4mm × 4mm QFN28 Package, “-1” version has 4.1V Float Voltage. LTC3566 LTC3567 Switching USB Power Manager with Li-Ion/Polymer Charger, 1A Buck-Boost Converter Plus LDO Multifunction PMIC: Switchmode Power Manager and 1A Buck-Boost Regulator + LDO, Charge Current Programmable Up to 1.5A from Wall Adapter Input, Thermal Regulation Synchronous Buck-Boost Converters Efficiency: >95%, ADJ Output: Down to 0.8V at 1A, Bat-Track Adaptive Output Control, 180mΩ Ideal Diode, LTC3567 Has I2C Interface, 4mm × 4mm QFN24 Package LTC3576/-1 Switching USB Power Manager with USB OTG + Triple Step-Down DC/DCs Complete Multi-Function PMIC: Bi-Directional Switching Power Manager + 3 Bucks + LDO, ADJ Output Down to 0.8V at 400mA/400mA/1A, Over-Voltage Protection, USB On-The-Go, Charge Current Programmable Up to 1.5A from Wall Adapter Input, Thermal Regulation, I2C, Hi-Voltage Bat-Track Buck Interface, 180mΩ Ideal Diode, 4mm × 6mm QFN-38 Package LTC3586 Switching USB Power Manager with Li-Ion/Polymer Charger Plus Dual Buck Plus Buck-Boost Plus Boost DC/DC Maximizes Available Power from USB Port, Bat-Track, “Instant On” Operation, 1.5A Max Charge Current, 180mΩ Ideal Diode with <50mΩ Option, 3.3V/25mA Always-On LDO, Two 400mA Synchronous Buck Regulators, One 1A Buck-Boost Regulator, One 600mA Boost Regulator, 4mm × 6mm 38-Pin QFN Package LTC4085/ LTC4085-1 USB Power Manager with Ideal Diode Controller and Li-Ion Charger Charges Single Cell Li-Ion Batteries Directly from a USB Port, Thermal Regulation, 200m Ideal Diode with <50m Option, 4mm × 3mm DFN14 Package, “-1” version has 4.1V Float Voltage. LTC4088 High Efficiency USB Power Manager and Battery Charger Maximizes Available Power from USB Port, Bat-Track, “Instant On” Operation, 1.5A Max Charge Current, 180mΩ Ideal Diode with <50m Option, 3.3V/25mA Always-On LDO, 4mm × 3mm DFN14 Package LTC4088-1 High Efficiency USB Power Manager and Battery Charger with Regulated Output Voltage Maximizes Available Power from USB Port, Bat-Track, “Instant-On” Operation, 1.5A Max Charge Current, 180mΩ Ideal Diode with <50mΩ Option, Automatic Charge Current Reduction Maintains 3.6V Minimum VOUT, Battery charger disabled when all logic inputs are grounded, 3mm × 4mm DFN14 Package LTC4088-2 High Efficiency USB Power Manager and Battery Charger with Regulated Output Voltage Maximizes Available Power from USB Port, Bat-Track, “Instant-On” Operation, 1.5A Max Charge Current, 180mΩ Ideal Diode with <50mΩ Option, Automatic Charge Current Reduction Maintains 3.6V Minimum VOUT, 3mm × 4mm DFN14 Package LTC4098 USB-Compatible Switchmode Power Manager with OVP High VIN : 38V Operating, 60V Transient; 66V OVP. Maximizes Available Power from USB Port, Bat-Track, “Instant-On” Operation, 1.5A Max Charge Current from Wall, 600mA Charge Current from USB, 180mΩ Ideal Diode with <50mΩ Option; 3mm × 4mm Ultra-Thin QFN20 Package Hot Swap is a trademark of Linear Technology Corporation. 3577f 52 Linear Technology Corporation LT 0709 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2009