LINER LTC3554EPD

LTC3554
Micropower USB Power
Manager with Li-Ion Charger
and Two Step-Down Regulators
DESCRIPTION
FEATURES
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The LTC®3554 is a micropower, highly integrated power
management and battery charger IC for single-cell
Li-Ion/Polymer battery applications. It includes a
PowerPath manager with automatic load prioritization,
a battery charger, an ideal diode and numerous internal
protection features. Designed speciﬁcally for USB applications, the LTC3554 power manager automatically limits
input current to a maximum of either 100mA or 500mA.
Battery charge current is automatically reduced such that
the sum of the load current and the charge current does
not exceed the selected input current limit.
10μA Standby Mode Quiescent Current (All Outputs On)
Seamless Transition Between Input Power Sources:
Li-Ion/Polymer Battery and USB
240mΩ Internal Ideal Diode Provides Low Loss
PowerPath™
Dual High Efﬁciency Step-Down Switching Regulators
(200mA IOUT) with Adjustable Output Voltages
Pushbutton On/Off Control with System Reset
Full Featured Li-Ion/Polymer Battery Charger
Programmable Charge Current with Thermal Limiting
Instant-On Operation with Discharged Battery
Compact Ultrathin 3mm × 3mm × 0.55mm 20-Pin
UTQFN Package
The LTC3554 also includes two synchronous step-down
switching regulators as well as a pushbutton controller.
With all supplies enabled in standby mode, the quiescent
current drawn from the battery is only 10μA. The LTC3554
is available in a 3mm × 3mm × 0.55mm 20-pin UTQFN
package.
APPLICATIONS
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USB-Based Handheld Products
Portable Li-Ion/Polymer Based Electronic Devices
Wearable Computers
Low Power Medical Devices
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. PowerPath is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patents, including
6522118, 6700364, 5481178, 6304066, 6570372, 6580258, 7511390.
TYPICAL APPLICATION
VBUS
10μF
100k
NTC
100k
14
LTC3554 CHRG
PROG
T
BAT
1.87k
HPWR
+
Li-Ion
BATTERY
BVIN
2.2μF
SUSP
4.7μH
PWR_ON1
10μF
649k
PGOOD
10μH
1.2V
200mA
SW2
10pF
PBSTAT
ON/OFF
2.05M
FB1
STBY
PWR_ON2
3.3V
200mA
SW1
10pF
FSEL
ON
Battery Drain Current
vs Temperature
SYSTEM
LOAD
VOUT
332k
10μF
BATTERY DRAIN CURRENT (μA)
4.35V TO 5.5V
USB INPUT
VBAT = 3.8V
STBY = 3.8V
12 REGULATORS LOAD = 0mA
BOTH REGULATORS
10 ENABLED
8
6
4
ONE REGULATOR ENABLED
BOTH REGULATORS DISABLED
2
HARD RESET
0
–75 –50 –25 0
25 50 75
TEMPERATURE (°C)
100 125
3554 TA01b
FB2
649k
3554 TA01a
3554f
1
LTC3554
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2, 3)
VBUS, VOUT, BVIN
t < 1ms and Duty Cycle < 1% .................. –0.3V to 7V
Steady State............................................. –0.3V to 6V
BAT, NTC, CHRG, SUSP, PBSTAT,
ON, PGOOD, FB1, FB2.................................. –0.3V to 6V
PWR_ON1, PWR_ON2, STBY
HPWR, FSEL (Note 4) ......................–0.3V to VCC + 0.3V
IBAT .............................................................................1A
ISW1, ISW2 (Continuous).......................................300mA
ICHRG, IPGOOD, IPBSTAT ............................................75mA
Operating Temperature Range.................. –40°C to 85°C
Junction Temperature ........................................... 110°C
Storage Temperature Range................... –65°C to 125°C
PROG
BAT
VOUT
SUSP
VBUS
TOP VIEW
20 19 18 17 16
15 NTC
HPWR 1
14 CHRG
FSEL 2
13 SW1
21
PBSTAT 3
12 BVIN
PGOOD 4
ON 5
8
9 10
FB2
PWR_ON2
PWR_ON1
STBY
7
FB1
11 SW2
6
PD PACKAGE
20-LEAD (3mm × 3mm) PLASTIC UTQFN
TJMAX = 110°C, θJA = 70°C/W
EXPOSED PAD (PIN 21) IS GND, AND MUST BE SOLDERED TO PCB GND
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3554EPD#PBF
LTC3554EPD#TRPBF
FDPT
20-Lead (3mm × 3mm) Plastic UTQFN
–40°C to 85°C
Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based ﬁnish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/
POWER MANAGER ELECTRICAL CHARACTERISTICS
The l denotes speciﬁcations that apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C,
VBUS = 5V, VBAT = 3.8V, HPWR = SUSP = PWR_ON1 = PWR_ON2 = 0V, RPROG = 1.87k, STBY = High, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
0.2
3
6.5
2
5
12
μA
μA
μA
5
8
μA
300
15
500
30
μA
μA
0.01
1.5
3
18
36
1
3
6
35
70
μA
μA
μA
μA
μA
5.5
V
90
450
100
500
mA
mA
No-Load Quiescent Currents
IBATQ
Battery Drain Current
IOUT = 0 (Note 5)
VBUS = 0V (Hard Reset)
VBUS = 0V
VBUS = 0V, PWR_ON1 = PWR_ON2 = 3.8V
IBATQC
Battery Drain Current, VBUS Available
VBAT = VFLOAT, Timer Timed Out
IBUSQ
VBUS Input Current
100mA, 500mA Modes
SUSP = 5V (Suspend Mode)
IBVINQ
BVIN Input Current
Shutdown Input Current
One Buck Enabled, Standby Mode
Both Bucks Enabled, Standby Mode
One Buck Enabled
Both Bucks Enabled
VBVIN = 3.8V, VBUS = 0V (Note 8)
PWR_ON1 = STBY = 3.8V
PWR_ON1 = PWR_ON2 = STBY = 3.8V
PWR_ON1 = 3.8V, STBY = 0V
PWR_ON1 = PWR_ON2 = 3.8V, STBY = 0V
Input Power Supply
VBUS
Input Supply Voltage
IBUS(LIM)
Total Input Current
4.35
HPWR = 0V (100mA)
HPWR = 5V (500mA)
l
l
80
400
3554f
2
LTC3554
POWER MANAGER ELECTRICAL CHARACTERISTICS
The l denotes speciﬁcations that apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C,
VBUS = 5V, VBAT = 3.8V, HPWR = SUSP = PWR_ON1 = PWR_ON2 = 0V, RPROG = 1.87k, STBY = High, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
VUVLO
VBUS Undervoltage Lockout
Rising Threshold
Falling Threshold
3.8
3.6
3.9
3.5
V
V
Rising Threshold
Falling Threshold
200
50
300
0
mV
mV
VDUVLO
RON_ILIM
VBUS to BAT Differential Undervoltage
Lockout
Input Current Limit Power FET
On-Resistance (Between VBUS and VOUT )
350
UNITS
mΩ
Battery Charger
VFLOAT
VBAT Regulated Output Voltage
0 ≤ TA ≤ 85°C
RPROG = 1.87k, 0 ≤ TA ≤ 85°C
4.179
4.165
4.2
4.2
4.221
4.235
380
400
420
V
V
ICHG
Constant-Current Mode Charge Current
mA
VPROG
VPROG,TRKL
PROG Pin Servo Voltage
PROG Pin Servo Voltage in Trickle Charge VBAT < V TRKL
1
0.1
V
V
hPROG
Ratio of IBAT to PROG Pin Current
750
mA/mA
ITRKL
Trickle Charge Current
VBAT < V TRKL
30
40
50
mA
V TRKL
Trickle Charge Threshold Voltage
VBAT Rising
VBAT Falling
3
2.6
2.9
2.75
V
V
ΔVRECHRG
Recharge Battery Threshold Voltage
Threshold Voltage Relative to VFLOAT
–75
–100
–115
mV
tTERM
Safety Timer Termination Period
Timer Starts when VBAT = VFLOAT – 50mV
3.2
4
5
tBADBAT
Bad Battery Termination Time
VBAT < V TRKL
0.4
0.5
0.63
Hour
hC/10
End-of-Charge Indication Current Ratio
(Note 6)
0.085
0.1
0.115
mA/mA
RON_CHG
Battery Charger Power FET
On-Resistance (Between VOUT and BAT)
IBAT = 200mA
TLIM
Junction Temperature in Constant
Temperature Mode
Hour
220
mΩ
110
°C
NTC
VCOLD
Cold Temperature Fault Threshold
Voltage
Rising NTC Voltage
Hysteresis
75
76
1.3
77
%VBUS
%VBUS
VHOT
Hot Temperature Fault Threshold Voltage Falling NTC Voltage
Hysteresis
34
35
1.3
36
%VBUS
%VBUS
VDIS
NTC Disable Threshold Voltage
Falling NTC Voltage
Hysteresis
1.2
1.7
50
2.2
%VBUS
mV
INTC
NTC Leakage Current
VNTC = VBUS = 5V
50
nA
VFWD
Forward Voltage Detection
(Note 12)
15
mV
RDROPOUT
Diode On-Resistance, Dropout
IOUT = 200mA, VBUS = 0V
240
mΩ
IMAX
Diode Current Limit
(Note 7)
l
–50
Ideal Diode
1
A
Logic Inputs (HPWR, SUSP)
VIL
Input Low Voltage
VIH
Input High Voltage
RPD
Internal Pull-Down Resistance
0.4
1.2
V
V
4
MΩ
Logic Output (CHRG)
VOL
Output Low Voltage
I CHRG = 5mA
65
250
mV
I CHRG
Output Hi-Z Leakage Current
VBAT = 4.5V, VCHRG = 5V
0
1
μA
3554f
3
LTC3554
SWITCHING REGULATOR ELECTRICAL CHARACTERISTICS
The l denotes speciﬁcations that apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C.
VOUT = BVIN = 3.8V, PWR_ON1 = PWR_ON2 = 0V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
BVIN
Input Supply Voltage
(Note 9)
VOUT UVLO
VOUT Falling
VOUT Rising
BVIN Connected to VOUT Through Low
Impedance. VOUT UVLO Disables the
Switching Regulators.
fOSC
Oscillator Frequency
FSEL High
FSEL Low
IFB1
IFB2
FB1 Input Current (Note 8)
FB2 Input Current (Note 8)
RSW1_PD
RSW2_PD
SW1 Pull-Down in Shutdown
SW2 Pull-Down in Shutdown
MIN
l
TYP
2.7
2.5
1.91
0.955
UNITS
5.5
V
2.6
2.8
2.9
V
V
2.25
1.125
2.59
1.295
MHz
MHz
0.05
0.05
μA
μA
–0.05
–0.05
PWR_ON1 = 0V
PWR_ON2 = 0V
MAX
10
10
kΩ
kΩ
Logic Input Pins (FSEL, STBY)
Input High Voltage
1.2
V
Input Low Voltage
Input Current
–1
0.4
V
1
μA
Switching Regulator 1 in Normal Operation (STBY Low)
ILIM1
Peak PMOS Current Limit
PWR_ON1 = 3.8V (Note 7)
PWR_ON1 = 3.8V
l
300
450
600
mA
780
800
820
mV
VFB1
Regulated Feedback Voltage
D1
Max Duty Cycle
RP1
RDS(ON) of PMOS
ISW1 = 100mA
1.1
Ω
RN1
RDS(ON) of NMOS
ISW1 = –100mA
0.7
Ω
100
%
Switching Regulator 1 in Standby Mode (STBY High)
VFB1_LOW
Feedback Voltage Threshold
ISHORT1_SB
Short-Circuit Current
VDROP1_SB
Standby Mode Dropout Voltage
PWR_ON1 = 3.8V, VFB1 Falling
l
770
800
820
mV
10
21
50
mA
25
60
mV
300
450
600
mA
780
800
820
mV
PWR_ON1 = 2.9V, ISW1 = 5mA, VFB1 = 0.77V,
VOUT = 2.9V, BVIN = 2.9V
Switching Regulator 2 in Normal Operation (STBY Low)
ILIM2
Peak PMOS Current Limit
PWR_ON2 = 3.8V (Note 7)
PWR_ON2 = 3.8V
l
VFB2
Regulated Feedback Voltage
D2
Max Duty Cycle
RP2
RDS(ON) of PMOS
ISW2 = 100mA
1.1
Ω
RN2
RDS(ON) of NMOS
ISW2 = –100mA
0.7
Ω
100
%
Switching Regulator 2 in Standby Mode (STBY High)
VFB2_LOW
Feedback Voltage Threshold
ISHORT2_SB
Short-Circuit Current
VDROP2_SB
Standby Mode Dropout Voltage
PWR_ON2 = 3.8V, VFB2 Falling
PWR_ON2 = 2.9V, ISW2 = 5mA, VFB2 = 0.77V,
VOUT = 2.9V, BVIN = 2.9V
l
770
800
820
mV
10
21
50
mA
25
60
mV
3554f
4
LTC3554
PUSHBUTTON INTERFACE ELECTRICAL CHARACTERISTICS
The l denotes speciﬁcations that apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C.
VBAT = 3.8V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Pushbutton Pin (ON)
VCC_PB
Pushbutton Operating Supply Range
VON_TH
ON Threshold Rising
ON Threshold Falling
l
(Notes 4 , 9)
2.7
5.5
V
1.2
V
V
1
μA
650
kΩ
1.2
V
V
0.4
I ON
ON Input Current
VON = VCC (Note 4)
–1
RPB_PU
Pushbutton Pull-Up Resistance
Pull-Up to VCC (Note 4)
200
400
Logic Input Pins (PWR_ON1, PWR_ON2)
VPWR_ONx
IPWR_ONx
PWR_ONx Threshold Rising
PWR_ONx Threshold Falling
0.4
PWR_ONx Input Current
–1
1
μA
–1
1
μA
Status Output Pins (PBSTAT, PGOOD)
IPBSTAT
PBSTAT Output High Leakage Current
VPBSTAT = 3V
VPBSTAT
PBSTAT Output Low Voltage
IPBSTAT = 3mA
IPGOOD
PGOOD Output High Leakage Current
VPGOOD = 3V
VPGOOD
PGOOD Output Low Voltage
IPGOOD = 3mA
0.1
V THPGOOD
PGOOD Threshold Voltage
(Note 10)
–8
%
0.1
–1
0.4
V
1
μA
0.4
V
Pushbutton Timing Parameters (Note 11)
t ON_PBSTATL
Minimum ON Low Time to Cause PBSTAT ON Brought Low During Power-On (PON) or
Low
Power-Up (PUP1, PUP2) States
50
ms
t ON_PBSTATH
Delay from ON High to PBSTAT High
Power-On (PON) State, After PBSTAT Has
Been Low for at Least tPBSTAT_PW
900
μs
t ON_PUP
Minimum ON Low Time to Enter
Power-Up (PUP1 or PUP2) State
Starting in the Hard Reset (HR) or Power-Off
(POFF) States
400
ms
t ON_HR
Minimum ON Low Time to Hard Reset
ON Brought Low During the Power-On (PON)
or Power-Up (PUP1, PUP2) States
4
5
tPBSTAT_PW
PBSTAT Minimum Pulse Width
Power-On (PON) or Power-Up (PUP1, PUP2)
States
40
50
ms
tEXTPWR
Power-Up from USB Present to Power-Up Starting in the Hard Reset (HR) or Power-Off
(PUP1 or PUP2) State
(POFF) States
100
ms
tPON_UP
Any PWR_ONx High to Power-On State
900
μs
tPON_DIS
PWR_ONx Low to Buckx Disabled
1
μs
tPUP
Power-Up (PUP1 or PUP2) State Duration
5
s
tPDN
Power-Down (PDN1 or PDN2) State
Duration
1
s
tPGOODH
Bucks in Regulation to PGOOD High
All Enabled Bucks within PGOOD Threshold
Voltage
230
ms
tPGOODL
Bucks Disabled to PGOOD Low
All Bucks Disabled
100
μs
Starting with Both PWR_ONx Low in the
Power-Off (POFF) State
Note 1. Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
6
s
Note 2. The LTC3554 is guaranteed to meet performance speciﬁcations
from 0°C to 85°C. Speciﬁcations over the –40°C to 85°C operating
temperature range are assured by design, characterization and
correlation with statistical process controls.
3554f
5
LTC3554
ELECTRICAL CHARACTERISTICS
Note 3. This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperatures will exceed 110°C when overtemperature protection is
active. Continuous operation above the speciﬁed maximum operating
junction temperature may result in device degradation or failure.
Note 4. VCC is the greater of VBUS or BAT.
Note 5. Total Battery Drain Current is the sum of IBATQ and IOUT. For
example, in applications where the buck input (BVIN pin) is connected
to the PowerPath output (VOUT pin) such that IOUT = IBVIN, total battery
drain current = IBATQ + IBVIN.
Note 6. hC/10 is expressed as a fraction of programmed full charge
current with speciﬁed PROG resistor.
Note 7. The current limit features of this part are intended to protect
the IC from short term or intermittent fault conditions. Continuous
operation above the absolute maximum speciﬁed pin current rating may
result in device degradation or failure.
Note 8. FB High, Not Switching
Note 9. VOUT not in UVLO.
Note 10. PGOOD threshold is expressed as a percentage difference from
the buck regulation voltage. The threshold is measured with the buck
feedback pin voltage rising.
Note 11. See the Operation section of this data sheet for detailed
explanation of the pushbutton state machine and the effects of each
state on switching regulator and power manager operation.
Note 12. If VBUS < VUVLO then VFWD = 0 and the forward voltage across
the ideal diode is equal to its current times RDROPOUT.
TYPICAL PERFORMANCE CHARACTERISTICS
400
VBUS Supply Current
vs Temperature (Suspend Mode)
25
VBUS = 5V
HPWR = L
14
VBUS = 5V
20
IBUS (μA)
IBUS (μA)
350
300
250
15
10
5
200
–75 –50 –25
0
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
VBAT = 3.8V
STBY = 3.8V
12 REGULATORS LOAD = 0mA
BOTH REGULATORS
10 ENABLED
8
ONE REGULATOR ENABLED
6
BOTH REGULATORS DISABLED
4
2
HARD RESET
0
–75 –50 –25 0
25 50 75
TEMPERATURE (°C)
0 25 50 75 100 125 150
TEMPERATURE (°C)
3554 G01
VBUS Current Limit
vs Temperature
500
VBUS = 5V
VBAT = 3.8V
VBUS and Battery Current
vs Load Current
600
VBUS = 5V
400
4
100 125
3554 G03
3554 G02
Battery Drain Current
vs Temperature (Suspend Mode)
5
Battery Drain Current
vs Temperature
BATTERY DRAIN CURRENT (μA)
VBUS Supply Current
vs Temperature
TA = 25°C, unless otherwise speciﬁed.
RPROG = 1.87k
500
HPWR = H
IVBUS
3
2
0
–75 –50 –25
300
200
100
1
CURRENT (mA)
IVBUS (mA)
IBAT (μA)
400
ILOAD
300
200
IBAT
(CHARGING)
100
HPWR = L
0
0 25 50 75 100 125 150
TEMPERATURE (°C)
3554 G03b
0
–75 –50 –25
0
25 50 75
TEMPERATURE (°C)
100 125
3554 G04
IBAT
(DISCHARGING)
–100
0
100
200
300
400
LOAD CURRENT (mA)
500
3554 G05
3554f
6
LTC3554
TYPICAL PERFORMANCE CHARACTERISTICS
RON from VBUS to VOUT
vs Temperature
600
480
IOUT = 200mA
0.45
IBAT (mA)
0.30
240
160
0.25
0.20
–75 –50 –25
3554 G05a
400
4
300
200
2
1
C/10
IBAT
0
1
0
3
5
4
TIME (hour)
2
7
6
4.250
0
8
3554 G07
Battery Regulation (Float)
Voltage vs Temperature
VBUS = 5V
HPWR = H
3
SAFETY TIMER
TERMINATION
3554 G06
VFLOAT Load Regulation
4.204
5
VBAT
100
80 VBUS = 5V
HPWR = H
RPROG = 1.87k
0
–75 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C)
0 25 50 75 100 125 150
TEMPERATURE (°C)
CHRG
VOLTAGE (V)
320
0.35
6
920mAhr CELL
VBUS = 5V
500 RPROG = 1.87k
400
0.40
RON (Ω)
Battery Charge Current and
Voltage vs Time
Charge Current vs Temperature
(Thermal Regulation)
BATTERY CURRENT (mA)
0.50
TA = 25°C, unless otherwise speciﬁed.
IBAT vs VBAT
500
VBUS = 5V
IBAT = 2mA
4.202
400
4.225
VBUS = 5V
HPWR = H
RPROG = 1.87k
4.198
IBAT (mA)
VFLOAT (V)
VFLOAT (V)
4.200
4.200
300
200
4.196
4.175
100
4.194
4.192
0
50 100 150 200 250 300 350 400 450
IBAT (mA)
4.150
–75 –50 –25
0
0
25 50 75
TEMPERATURE (°C)
3554 G08
100 125
2
2.4
2.8
3.2
3.6
VBAT (V)
3554 G10
3554 G08
Forward Voltage
vs Ideal Diode Current
4.4
4
VBUS Connect Waveform
VBUS Disconnect Waveform
300
VBUS
250
VBUS = 5V
VBUS
0
VOUT
VBUS = 0V
100
0
IBUS
0.5A/DIV 0A
IBAT
0.5A/DIV 0A
IBAT 0A
0.5A/DIV
50
1ms/DIV
0
0
200
400
600
800
IBAT (mA)
1000
1200
0
VOUT
0
IBUS
0.5A/DIV 0A
150
5V
5V
5V
200
VFWD (mV)
5V
VBAT = 3.75V
IOUT = 100mA
RPROG = 2k
50μs/DIV
3554 G12
3554 G13
VBAT = 3.75V
IOUT = 100mA
RPROG = 2k
3554 G11
3554f
7
LTC3554
TYPICAL PERFORMANCE CHARACTERISTICS
Switching from 100mA Mode to
500mA Mode
TA = 25°C, unless otherwise speciﬁed.
Oscillator Frequency
vs Temperature
Switching from Suspend Mode to
500mA Mode
2.6
0
0
5V
VOUT
IBUS
0.5A/DIV
0
IBUS
0A
0.5A/DIV
0A
IBAT
0.5A/DIV 0A
IBAT
0A
0.5A/DIV
3554 G14
1ms/DIV
3554 G15
1ms/DIV
VBAT = 3.75V
IOUT = 50mA
RPROG = 2k
OSCILLATOR FREQUENCY (MHz)
SUSP
5V
HPWR
5V
VBAT = 3.75V
IOUT = 50mA
RPROG = 2k
2.7V
3.8V
5.5V
2.5
2.4
2.3
2.2
2.1
2.0
1.9
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
3554 G16
100
Step-Down Switching Regulator 1
3.3V Output Efﬁciency vs IOUT1
100
FSEL = L
STBY = L
90
100
80
70
70
50
40
EFFICIENCY (%)
80
70
60
60
50
40
0
0.01
0.1
1
10
IOUT1 (mA)
100
3.8V
5V
10
0
0.01
1000
0.1
1
10
IOUT1 (mA)
100
100
35
FSEL = L
STBY = L
30
BVIN SUPPLY CURRENT (μA)
70
60
50
40
30
20
3.8V
5V
10
0
0.01
0.1
1
10
IOUT2 (mA)
100
0.1
1
10
IOUT2 (mA)
100
1000
3554 G32
3554 G31
Burst Mode ® BVIN Supply
Current Per Enabled Step-Down
Switching Regulator
Step-Down Switching Regulator 2
1.2V Output Efﬁciency vs IOUT2
80
3.8V
5V
0
0.01
1000
3554 G24a
90
40
10
1000
3554 G25
Standby Mode BVIN Supply
Current Per Enabled Step-Down
Switching Regulator
3.0
NO LOAD
STBY = L
–45°C
25°C
90°C
25
20
15
10
NO LOAD
STBY = H
2.5
–45°C
25°C
90°C
2.0
1.5
1.0
0.5
5
0
2.5
BVIN SUPPLY CURRENT (μA)
10
50
20
20
3.8V
5V
60
30
30
20
FSEL = L
STBY = L
90
80
30
EFFICIENCY (%)
Step-Down Switching Regulator 2
1.8V Output Efﬁciency vs IOUT2
FSEL = L
STBY = L
90
EFFICIENCY (%)
EFFICIENCY (%)
Step-Down Switching Regulator 1
2.5V Output Efﬁciency vs IOUT1
3
3.5
4
4.5
5
BVIN SUPPLY VOLTAGE (V)
5.5
3554 G17
0
2.5
3
3.5
4
4.5
5
BVIN SUPPLY VOLTAGE (V)
5.5
3554 G18
Burst Mode is a registered trademark of Linear Technology Corporation.
3554f
8
LTC3554
TYPICAL PERFORMANCE CHARACTERISTICS
Step-Down Switching Regulator
Short-Circuit Current
vs Temperature
TA = 25°C, unless otherwise speciﬁed.
Step-Down Switching Regulator
Output Transient
500
SHORT CIRCUIT CURRENT (mA)
STBY = L
480
VOUT2
20mV/DIV
(AC)
460
440
IOUT2
5mA
10μA
420
50μs/DIV
400
–75 –50 –25
3554 G26
VOUT2 = 1.2V
STBY = H
0 25 50 75 100 125 150
TEMPERATURE (°C)
3554 G19
Step-Down Switching
Regulator Switch Impedance
vs Temperature
Step-Down Switching Regulator
Output Transient
1.6
1.4
SWITCH IMPEDANCE (Ω)
VOUT1
100mV/DIV
(AC)
150mA
IOUT1
5mA
200μs/DIV
3554 G27
VOUT1 = 3.3V
STBY = L
BVIN = 3.2V
STBY = L
PMOS
1.2
1.0
NMOS
0.8
0.6
0.4
0.2
0
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
3554 G20
Step-Down Switching
Regulator Feedback Voltage
vs Output Current
0.820
FEEDBACK VOLTAGE (V)
0.815
Step-Down Switching Regulator
Start-Up Waveform
VOUT2
50mV/DIV
(AC)
3.8V
5V
STBY = L
0.810
VOUT1
1V/DIV
0.805
0.800
0V
IL1
100mA/DIV
0mA
PWR_ON1
0.795
0.790
100μs/DIV
0.785
0.780
0.1
1
10
100
OUTPUT CURRENT (mA)
1000
3554 G28
VOUT2 = 1.2V
IOUT2 = 50mA
ROUT1 = 22Ω
STBY = L
3554 G21
3554f
9
LTC3554
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise speciﬁed.
Step-Down Switching Regulator
Dropout Voltage in Standby Mode
vs Load Current
Step-Down Switching
Regulator Output Transient
(STBY High to Low)
Step-Down Switching
Regulator Output Transient
(FSEL Low to High)
200
DROPOUT VOLTAGE (mA)
VOUT2
20mV/DIV
(AC)
VOUT2
20mV/DIV
(AC)
STBY
FSEL
50μs/DIV
VOUT1 = 3.3V
IOUT1 = 100mA
VOUT2 = 1.2V
IOUT2 = 50mA
STBY = L
VBVIN = 2.9V
VFBx = 780mV
–45°C
25°C
90°C
STBY = H
180
VOUT1
20mV/DIV
(AC)
VOUT1
50mV/DIV
(AC)
3554 G29
50μs/DIV
VOUT1 = 3.3V
IOUT1 = 5mA
VOUT2 = 1.2V
IOUT2 = 5mA
3554 G30
160
140
120
100
80
60
40
20
0
0
2
4
6
8
10
12
LOAD CURRENT (mA)
14
3554 G23
3554f
10
LTC3554
PIN FUNCTIONS
HPWR (Pin 1): High Power Logic Input. When this pin is
low the input current limit is set to 100mA and when this
pin is driven high it is set to 500mA. The SUSP pin needs
to be low for the input current limit circuit to be enabled.
This pin has a conditional internal pull-down resistor when
power is applied to the VBUS pin.
BVIN (Pin 12): Power Input for Step-Down Switching
Regulators 1 and 2. It is recommended that this pin be
connected to the VOUT pin. It should be bypassed with a
low impedance multilayer ceramic capacitor.
FSEL (Pin 2): Buck Frequency Select. When this pin is
low the buck switching frequency is set to 1.125MHz and
when this pin is driven high it is set to 2.25MHz.
CHRG (Pin 14): Open-Drain Charge Status Output. This pin
indicates the status of the battery charger. It is internally
pulled low while charging. Once the battery charge current reduces to less than one-tenth of the programmed
charge current, this pin goes into a high impedance state.
An external pull-up resistor and/or LED is required to
provide indication.
PBSTAT (Pin 3): Pushbutton Status. This open-drain output
is a debounced and buffered version of the ON pushbutton
input. It may be used to interrupt a microprocessor.
PGOOD (Pin 4): Power Good. This open-drain output
indicates that all enabled buck regulators have been in
regulation for at least 230ms.
ON (Pin 5): Pushbutton Input. Weak internal pull-up
forces a high state if ON is left ﬂoating. A normally open
pushbutton is connected from ON to ground to force a
low state on this pin.
FB1 (Pin 6): Feedback Input for Step-Down Switching
Regulator 1. This pin servos to a ﬁxed voltage of 0.8V
when the control loop is complete.
FB2 (Pin 7): Feedback Input for Step-Down Switching
Regulator 2. This pin servos to a ﬁxed voltage of 0.8V
when the control loop is complete.
PWR_ON2 (Pin 8): Logic Input Enables Step-Down
Switching Regulator 2.
PWR_ON1 (Pin 9): Logic Input Enables Step-Down
Switching Regulator 1.
STBY (Pin 10): Standby Mode. When this pin is driven
high the part enters a very low quiescent current mode.
The buck regulators are each limited to 5mA maximum
load current in this mode.
SW2 (Pin 11): Power Transmission (Switch) Pin for StepDown Switching Regulator 2.
SW1 (Pin 13): Power Transmission (Switch) Pin for StepDown Switching Regulator 1.
NTC (Pin 15): The NTC pin connects to a battery’s thermistor to determine if the battery is too hot or too cold to
charge. If the battery’s temperature is out of range, charging
is paused until it drops back into range. A low drift bias
resistor is required from VBUS to NTC and a thermistor is
required from NTC to ground. If the NTC function is not
desired, the NTC pin should be grounded.
PROG (Pin 16): Charge Current Program and Charge
Current Monitor Pin. Connecting a resistor from PROG to
ground programs the charge current as given by:
I CHG (A)=
750V
RPROG
If sufﬁcient input power is available in constant-current
mode, this pin servos to 1V. The voltage on this pin always
represents the actual charge current.
BAT (Pin 17): Single-Cell Li-Ion Battery Pin. Depending
on available power and load, a Li-Ion battery on BAT will
either deliver system power to VOUT through the ideal
diode or be charged from the battery charger.
VOUT (Pin 18): Output Voltage of the PowerPath Controller
and Input Voltage of the Battery Charger. The majority of
the portable products should be powered from VOUT. The
3554f
11
LTC3554
PIN FUNCTIONS
LTC3554 will partition the available power between the
external load on VOUT and the internal battery charger.
Priority is given to the external load and any extra power
is used to charge the battery. An ideal diode from BAT to
VOUT ensures that VOUT is powered even if the load exceeds
the allotted input current from VBUS or if the VBUS power
source is removed. VOUT should be bypassed with a low
impedance multilayer ceramic capacitor.
SUSP (Pin 19): Suspend Mode Logic Input. If this pin
is driven high the input current limit path is disabled.
In this state the circuit draws negligible power from the
VBUS pin. Any load at the VOUT pin is provided by the
battery through the internal ideal diode. When this input
is grounded, the input current limit will be set to desired
value as determined by the state of the HPWR pin. This
pin has a conditional internal pull-down resistor when
power is applied to the VBUS pin.
VBUS (Pin 20): USB Input Voltage. VBUS will usually be
connected to the USB port of a computer or a DC output
wall adapter. VBUS should be bypassed with a low impedance multilayer ceramic capacitor.
Exposed Pad (Pin 21): Ground. The exposed package pad
is ground and must be soldered to the PC board for proper
functionality and for maximum heat transfer.
3554f
12
LTC3554
BLOCK DIAGRAM
18 VOUT
VBUS 20
HPWR
INPUT
CURRENT
LIMIT
1
SUSP 19
CC/CV
CHARGER
17 BAT
EXTPWR
NTC 15
16 PROG
UVLO
BATTERY
TEMP
MONITOR
OSC
0.8V
CHRG 14
13 SW1
CHARGE
STATUS
EN
STBY
6
FB1
200mA STEP-DOWN DC/DC
FSEL
2
2.25MHz/
1.125MHz
OSCILLATOR
12 BVIN
OSC
0.8V
11 SW2
EN
STBY
STBY 10
7
FB2
4
PGOOD
200mA STEP-DOWN DC/DC
PWR_ON1
9
PWR_ON2
8
PBSTAT
3
ON
5
PUSH BUTTON
INTERFACE
POWER GOOD
COMPARATORS
21
3554 BD1
GND
3554f
13
LTC3554
OPERATION
Introduction
The LTC3554 is a highly integrated power management
IC that includes the following features:
standby mode which can be used to power essential
keep-alive circuitry while draining ultralow current from
the battery for extended battery life.
PowerPath controller
USB PowerPath Controller
Battery charger
The input current limit and charger control circuits of the
LTC3554 are designed to limit input current as well as
control battery charge current as a function of IVOUT. VOUT
drives the combination of the external load, the two stepdown switching regulators and the battery charger.
Ideal diode
Pushbutton controller
Two step-down switching regulators
Designed speciﬁcally for USB applications, the PowerPath
controller incorporates a precision input current limit
which communicates with the battery charger to ensure
that input current never violates the USB speciﬁcations.
The ideal diode from BAT to VOUT guarantees that ample
power is always available to VOUT even if there is insufﬁcient
or absent power at VBUS. The LTC3554 also includes a
pushbutton input to control the two synchronous stepdown switching regulators and system reset. The two
constant-frequency current mode step-down switching
regulators provide 200mA each and support 100% duty
cycle operation as well as operating in Burst Mode operation
for high efﬁciency at light load. No external compensation
components are required for the switching regulators.
Either regulator can be programmed for a minimum output voltage of 0.8V and can be used to power a microcontroller core, microcontroller I/O, memory or other
logic circuitry. The buck regulators can be operated at
1.125MHz or 2.25MHz. They also include a low power
If the combined load does not exceed the programmed
input current limit, VOUT will be connected to VBUS through
an internal 350mΩ P-channel MOSFET. If the combined
load at VOUT exceeds the programmed input current limit,
the battery charger will reduce its charge current by the
amount necessary to enable the external load to be satisﬁed
while maintaining the programmed input current. Even if
the battery charge current is set to exceed the allowable
USB current, the average input current USB speciﬁcation
will not be violated. Furthermore, load current at VOUT will
always be prioritized and only excess available current will
be used to charge the battery.
The input current limit is programmed by the HPWR and
SUSP pins. If SUSP pin set high, the input current limit
is disabled. If SUSP pin is low, the input current limit is
enabled. HPWR pin selects between 100mA input current
limit when it is low and 500mA input current limit when
it is high.
Simpliﬁed PowerPath Block Diagram
VBUS 20
18 VOUT
CC/CV
CHARGER
+
–
100mA/500mA
INPUT CURRENT
LIMIT
IDEAL
15mV
17 BAT
3554 F01
3554f
14
LTC3554
OPERATION
Ideal Diode From BAT to VOUT
Battery Charger
The LTC3554 has an internal ideal diode from BAT to VOUT
designed to respond quickly whenever VOUT drops below
BAT. If the load increases beyond the input current limit,
additional current will be pulled from the battery via the ideal
diode. Furthermore, if power to VBUS (USB) is removed,
then all of the application power will be provided by the
battery via the ideal diode. The ideal diode is fast enough
to keep VOUT from dropping signiﬁcantly with just the
recommended output capacitor. The ideal diode consists
of a precision ampliﬁer that enables an on-chip P-channel
MOSFET whenever the voltage at VOUT is approximately
15mV (VFWD) below the voltage at BAT. The resistance of
the internal ideal diode is approximately 240mΩ.
The LTC3554 includes a constant-current/constant-voltage battery charger with automatic recharge, automatic
termination by safety timer, low voltage trickle charging,
bad cell detection and thermistor sensor input for out of
temperature charge pausing. When a battery charge cycle
begins, the battery charger ﬁrst determines if the battery
is deeply discharged. If the battery voltage is below V TRKL,
typically 2.9V, an automatic trickle charge feature sets the
battery charge current to 10% of the programmed value. If
the low voltage persists for more than 1/2 hour, the battery
charger automatically terminates. Once the battery voltage
is above 2.9V, the battery charger begins charging in full
power constant current mode. The current delivered to
the battery will try to reach 750V/RPROG. Depending on
available input power and external load conditions, the
battery charger may or may not be able to charge at the
full programmed current. The external load will always be
prioritized over the battery charge current. The USB current limit programming will always be observed and only
additional current will be available to charge the battery.
When system loads are light, battery charge current will
be maximized.
Suspend Mode
When the SUSP pin is pulled high the LTC3554 enters
suspend mode to comply with the USB speciﬁcation. In
this mode, the power path between VBUS and VOUT is put
in a high impedance state to reduce the VBUS input current
to 15μA. The system load connected to VOUT is supplied
through the ideal diode connected to BAT.
VBUS Undervoltage Lockout (UVLO) and Undervoltage
Current Limit (UVCL)
An internal undervoltage lockout circuit monitors VBUS
and keeps the input current limit circuitry off until VBUS
rises above the rising UVLO threshold (3.8V) and at least
200mV above VBAT. Hysteresis on the UVLO turns off the
input current limit circuitry if VBUS drops below 3.6V or
within 50mV of VBAT. When this happens, system power at
VOUT will be drawn from the battery via the ideal diode. To
minimize the possibility of oscillation in and out of UVLO
when using resistive input supplies, the input current limit
is reduced as VBUS falls below 4.45V typical.
Charge Termination
The battery charger has a built-in safety timer. When the
battery voltage approaches the ﬂoat voltage, the charge
current begins to decrease as the LTC3554 enters constant-voltage mode. Once the battery charger detects that
it has entered constant-voltage mode, the four hour safety
timer is started. After the safety timer expires, charging
of the battery will terminate and no more current will be
delivered to the battery.
3554f
15
LTC3554
OPERATION
Automatic Recharge
After the battery charger terminates, it will remain off
drawing only microamperes of current from the battery.
If the portable product remains in this state long enough,
the battery will eventually self discharge. To ensure that
the battery is always topped off, a charge cycle will automatically begin when the battery voltage falls below
VRECHRG (typically 4.1V). In the event that the safety timer
is running when the battery voltage falls below VRECHRG,
the timer will reset back to zero. To prevent brief excursions below VRECHRG from resetting the safety timer, the
battery voltage must be below VRECHRG for approximately
2ms. The charge cycle and safety timer will also restart
if the VBUS UVLO cycles low and then high (e.g., VBUS, is
removed and then replaced).
Charge Current
The charge current is programmed using a single resistor from PROG to ground. 1/750th of the battery charge
current is delivered to PROG which will attempt to servo
to 1.000V. Thus, the battery charge current will try to
reach 750 times the current in the PROG pin. The program
resistor and the charge current are calculated using the
following equations:
R PROG =
750V
750V
,I CHG =
I CHG
R PROG
In either the constant-current or constant-voltage charging modes, the PROG pin voltage will be proportional to
the actual charge current delivered to the battery. Therefore, the actual charge current can be determined at any
time by monitoring the PROG pin voltage and using the
following equation:
I BAT =
V PROG
• 750
R PROG
In many cases, the actual battery charge current, IBAT, will
be lower than ICHG due to limited input current available and
prioritization with the system load drawn from VOUT.
Thermal Regulation
To prevent thermal damage to the IC or surrounding
components, an internal thermal feedback loop will automatically decrease the programmed charge current if
the die temperature rises to approximately 110°C. Thermal regulation protects the LTC3554 from excessive
temperature due to high power operation or high ambient
thermal conditions and allows the user to push the limits
of the power handling capability with a given circuit board
design without risk of damaging the LTC3554 or external
components. The beneﬁt of the LTC3554 thermal regulation loop is that charge current can be set according to the
desired charge rate rather than worst-case conditions with
the assurance that the battery charger will automatically
reduce the current in worst-case conditions.
Charge Status Indication
The CHRG pin indicates the status of the battery charger. An
open-drain output, the CHRG pin can drive an indicator LED
through a current limiting resistor for human interfacing or
simply a pull-up resistor for microprocessor interfacing.
When charging begins, CHRG is pulled low and remains
low for the duration of a normal charge cycle. When charging is complete, i.e., the charger enters constant-voltage
mode and the charge current has dropped to one-tenth
of the programmed value, the CHRG pin is released (high
impedance). The CHRG pin does not respond to the C/10
threshold if the LTC3554 reduces the charge current due
to excess load on the VOUT pin. This prevents false end
of charge indications due to insufﬁcient power available
to the battery charger. Even though charging is stopped
during an NTC fault the CHRG pin will stay low indicating
that charging is not complete.
3554f
16
LTC3554
OPERATION
Battery Charger Stability Considerations
The LTC3554’s battery charger contains both a constantvoltage and a constant-current control loop. The constantvoltage loop is stable without any compensation when a
battery is connected with low impedance leads. Excessive
lead length, however, may add enough series inductance
to require a bypass capacitor of at least 1μF from BAT to
GND. Furthermore, a 100μF 1210 ceramic capacitor in
series with a 0.3Ω resistor from BAT to GND is required
to keep ripple voltage low if operation with the battery
disconnected is allowed.
High value, low ESR multilayer ceramic chip capacitors
reduce the constant-voltage loop phase margin, possibly
resulting in instability. Ceramic capacitors up to 22μF may
be used in parallel with a battery, but larger ceramics should
be decoupled with 0.2Ω to 1Ω of series resistance.
In constant-current mode, the PROG pin is in the feedback loop rather than the battery voltage. Because of the
additional pole created by any PROG pin capacitance,
capacitance on this pin must be kept to a minimum. With
no additional capacitance on the PROG pin, the battery
charger is stable with program resistor values as high
as 25k. However, additional capacitance on this node
reduces the maximum allowed program resistor. The pole
frequency at the PROG pin should be kept above 100kHz.
Therefore, if the PROG pin has a parasitic capacitance,
CPROG, the following equation should be used to calculate
the maximum resistance value for RPROG:
R PROG ≤
1
2π • 100kHz • C PROG
NTC Thermistor
The battery temperature is measured by placing a negative temperature coefﬁcient (NTC) thermistor close to the
battery pack. To use this feature connect the NTC thermistor, RNTC, between the NTC pin and ground and a bias
resistor, RNOM, from VBUS to NTC, as shown in Figure 1.
RNOM should be a 1% resistor with a value equal to the
value of the chosen NTC thermistor at 25°C (R25). The
LTC3554 will pause charging when the resistance of the
NTC thermistor drops to 0.54 times the value of R25
or approximately 54k (for a Vishay curve 1 thermistor,
this corresponds to approximately 40°C). If the battery
charger is in constant-voltage mode, the safety timer also
pauses until the thermistor indicates a return to a valid
temperature. As the temperature drops, the resistance of
the NTC thermistor rises. The LTC3554 is also designed
to pause charging when the value of the NTC thermistor
increases to 3.17 times the value of R25. For a Vishay
curve 1 thermistor this resistance, 317k, corresponds to
approximately 0°C. The hot and cold comparators each
have approximately 3°C of hysteresis to prevent oscillation
about the trip point.
Alternate NTC Thermistors and Biasing
The LTC3554 provides temperature qualiﬁed charging if
a grounded thermistor and a bias resistor are connected
to NTC. By using a bias resistor whose value is equal to
the room temperature resistance of the thermistor (R25)
the upper and lower temperatures are preprogrammed
to approximately 40°C and 0°C, respectively (assuming
a Vishay curve 1 thermistor).
The upper and lower temperature thresholds can be
adjusted by either a modiﬁcation of the bias resistor value
or by adding a second adjustment resistor to the circuit.
If only the bias resistor is adjusted, then either the upper
or the lower threshold can be modiﬁed but not both. The
other trip point will be determined by the characteristics
of the thermistor. Using the bias resistor in addition to an
adjustment resistor, both the upper and the lower temperature trip points can be independently programmed
with the constraint that the difference between the upper
and lower temperature thresholds cannot decrease.
Examples of each technique are given below.
3554f
17
LTC3554
OPERATION
NTC thermistors have temperature characteristics which
are indicated on resistance-temperature conversion tables. The Vishay-Dale thermistor NTHS0603N011-N1003F,
used in the following examples, has a nominal value of
100k and follows the Vishay curve 1 resistance-temperature characteristic.
In the explanation below, the following notation is used.
R25 = Value of the thermistor at 25°C
RNTC|COLD = Value of thermistor at the cold trip point
rCOLD = Ratio of RNTC|COLD to R25
rHOT = Ratio of RNTC|HOT to R25
RNOM = Primary thermistor bias resistor (see Figure 2)
R1 = Optional temperature range adjustment resistor (see
Figure 2)
The trip points for the LTC3554’s temperature qualiﬁcation are internally programmed at 0.35 • VBUS for the hot
threshold and 0.76 • VBUS for the cold threshold.
RNTC|HOT = Value of the thermistor at the hot trip point
20
20
–
TOO_COLD
0.76 • VBUS
(NTC RISING)
RNOM
100k
15
–
TOO_COLD
15
0.76 • VBUS
(NTC RISING)
RNOM
105k
NTC BLOCK
VBUS
VBUS
NTC
+
RNTC
100k
NTC
+
R1
12.7k
RNTC
100k
–
0.35 • VBUS
(NTC FALLING)
–
0.35 • VBUS
(NTC FALLING)
TOO_HOT
+
TOO_HOT
+
+
NTC_ENABLE
0.017 • VBUS
(NTC FALLING)
+
NTC_ENABLE
0.017 • VBUS
(NTC FALLING)
–
3554 F02
–
Figure 2. NTC Thermistor Circuit with Additional Bias Resistor
3554 F01
Figure 1. Typical NTC Thermistor Circuit
3554f
18
LTC3554
OPERATION
Therefore, the hot trip point is set when:
R NTC|HOT
R NOM +R NTC|HOT
• VBUS = 0.35 • VBUS
and the cold trip point is set when:
R NTC|COLD
R NOM +R NTC|COLD
• V BUS = 0.76 • V BUS
Solving these equations for RNTC|COLD and RNTC|HOT
results in the following:
RNTC|HOT = 0.538 • RNOM
and
RNTC|COLD = 3.17 • RNOM
By setting RNOM equal to R25, the above equations result
in rHOT = 0.538 and rCOLD = 3.17. Referencing these ratios
to the Vishay Resistance-Temperature Curve 1 chart gives
a hot trip point of about 40°C and a cold trip point of about
0°C. The difference between the hot and cold trip points
is approximately 40°C.
By using a bias resistor, RNOM, different in value from
R25, the hot and cold trip points can be moved in either
direction. The temperature span will change somewhat due
to the nonlinear behavior of the thermistor. The following
equations can be used to easily calculate a new value for
the bias resistor:
r
R NOM = HOT • R25
0.538
r
R NOM = COLD • R25
3.17
are linked. Therefore, only one of the two trip points can
be independently set, the other is determined by the default ratios designed in the IC.
Consider an example where a 60°C hot trip point is desired.
From the Vishay curve 1 R-T characteristics, rHOT is 0.2488
at 60°C. Using the above equation, RNOM should be set
to 46.4k. With this value of RNOM, the cold trip point is
about 16°C. Notice that the span is now 44°C rather than
the previous 40°C. This is due to the decrease in temperature gain of the thermistor as absolute temperature
increases.
The upper and lower temperature trip points can be independently programmed by using an additional bias
resistor as shown in Figure 2. The following formulas can
be used to compute the values of RNOM and R1:
r COLD – r HOT
R NOM =
• R25
2.714
R 1 = 0.536 • R NOM – r HOT • R25
For example, to set the trip points to 0°C and 45°C with
a Vishay curve 1 thermistor choose:
R NOM =
3.266 – 0.4368
• 100k =104.2k
2.714
the nearest 1% value is 105k
R1 = 0.536 • 105k – 0.4368 • 100k = 12.6k
The nearest 1% value is 12.7k. The ﬁnal solution is shown
in Figure 2 and results in an upper trip point of 45°C and
a lower trip point of 0°C.
where rHOT and rCOLD are the resistance ratios at the desired hot and cold trip points. Note that these equations
3554f
19
LTC3554
OPERATION
STEP-DOWN SWITCHING REGULATOR
below the VOUT UVLO threshold. If driving the step-down
switching regulator input supplies from a voltage other
than VOUT, the regulators should not be operated outside
their speciﬁed operating voltage range as operation is not
guaranteed beyond this range.
Introduction
The LTC3554 includes two constant-frequency current-mode 200mA step-down switching regulators, also
known as buck regulators. At light loads, each regulator
automatically enters Burst Mode operation to maintain
high efﬁciency.
Output Voltage Programming
Figure 3 shows the step-down switching regulator
application circuit. The output voltage for each step-down
switching regulator is programmed using a resistor divider
from the step-down switching regulator output connected
to the feedback pins (FB1 and FB2) such that:
Applications with a near-zero-current sleep or memory
keep-alive mode can command the LTC3554 switching
regulators into a standby mode that maintains output
regulation while drawing only 1.5μA quiescent current
per active regulator. Load capability drops to 5mA per
regulator in this mode.
R1 VOUTx = 0.8V • +1
R2 Switching frequency and switch slew rate are pin-selectable, allowing the application circuit to dynamically trade
off efﬁciency and EMI performance.
Typical values for R1 can be as high as 2.2MΩ.
(R1 + R2) can be as high as 3MΩ. The capacitor CFB
cancels the pole created by feedback resistors and
the input capacitance of the FB pin and also helps to
improve transient response for output voltages much
greater than 0.8V. A variety of capacitor sizes can be used
for CFB but a value of 10pF is recommended for most
applications. Experimentation with capacitor sizes between
2pF and 22pF may yield improved transient response.
The regulators are enabled, disabled and sequenced
through the pushbutton interface (see the Pushbutton
Interface section for more information). It is recommended
that the step-down switching regulator input supply
(BVIN) be connected to the system supply pin (VOUT).
This is recommended because the undervoltage lockout
circuit on the VOUT pin (VOUT UVLO) disables the stepdown switching regulators when the VOUT voltage drops
VIN
EN
FSEL
MP
SWx
PWM
CONTROL
L
VOUTx
MN
CFB
R1
COUT
FBx
GND
0.8V
R2
3554 F03
Figure 3. Step-down Switching Regulator
Application Circuit
3554f
20
LTC3554
OPERATION
PGOOD Operation
The PGOOD pin is an open-drain output which indicates
that all enabled step-down switching regulators have
reached their ﬁnal regulation voltage. It goes high-impedance 230ms after all enabled switching regulators reach
92% of their regulation value. The delay allows ample time
for an external processor to reset itself. PGOOD may be
used as a power-on reset to a microprocessor powered
by the step-down switching regulators. Since PGOOD is
an open-drain output, a pull-up resistor to an appropriate
power source is needed. A suggested approach is to connect the pull-up resistor to one of the step-down switching
regulator output voltages so that power is not dissipated
while the regulators are disabled.
In hard reset, the PGOOD pin is placed in high impedance
state to minimize current draw from the battery in this
ultralow power state. This will cause the PGOOD pin to
signal the wrong state (high level) if it is pulled up to a
supply that is not shut down in hard reset (e.g. BAT). If
PGOOD is pulled up to one of the step-down switching
regulator outputs then the PGOOD pin will indicate the
correct state (low level) in hard reset because the switching regulator output will be low.
Normal Operating Mode (STBY Pin Low)
In normal mode (STBY pin low), the regulators perform
as traditional constant-frequency current mode switching regulators. Switching frequency is determined by an
internal oscillator whose frequency is selectable via the
FSEL pin. An internal latch is set at the start of every
oscillator cycle, turning on the main P-channel MOSFET
switch. During each cycle, a current comparator compares
the inductor current to the output of an error ampliﬁer.
The output of the current comparator resets the internal
latch, which causes the main P-channel MOSFET switch
to turn off and the N-channel MOSFET synchronous
rectiﬁer to turn on. The N-channel MOSFET synchronous
rectiﬁer turns off at the end of the clock cycle, or when
the current through the N-channel MOSFET synchronous
rectiﬁer drops to zero, whichever happens ﬁrst. Via this
mechanism, the error ampliﬁer adjusts the peak inductor
current to deliver the required output power. All necessary compensation is internal to the step-down switching
regulator requiring only a single ceramic output capacitor
for stability.
At light load and no-load conditions, the buck automatically
switches to a power-saving hysteretic control algorithm
that operates the switches intermittently to minimize
switching losses. Known as Burst Mode operation, the
buck cycles the power switches enough times to charge
the output capacitor to a voltage slightly higher than
the regulation point. The buck then goes into a reduced
quiescent current sleep mode. In this state, power loss is
minimized while the load current is supplied by the output
capacitor. Whenever the output voltage drops below a
predetermined value, the buck wakes from sleep and cycles
the switches again until the output capacitor voltage is once
again slightly above the regulation point. Sleep time thus
depends on load current, since the load current determines
the discharge rate of the output capacitor.
Standby Mode (STBY Pin High)
There are situations where even the low quiescent current
of Burst Mode operation is not low enough. For instance,
in a static memory keep alive situation, load current may
fall well below 1μA. In this case, the 25μA typical BVIN
quiescent current per active regulator in Burst Mode
operation becomes the main factor determining battery
run time.
Standby mode cuts BVIN quiescent current down to just
1.5μA per active regulator, greatly extending battery run
time in this essentially no-load region of operation. The
application circuit commands the LTC3554 into and out
of standby mode via the STBY pin logic input. Bringing
the STBY pin high places both regulators into standby
mode, while bringing it low returns them to Burst Mode
operation. In standby mode, load capability drops to 5mA
per regulator.
3554f
21
LTC3554
OPERATION
In standby mode, each regulator operates hysteretically.
When the FB pin voltage falls below the internal 0.8V
reference, a current source from BVIN to SW turns on,
delivering current through the inductor to the switching
regulator output capacitor and load. When the FB pin
voltage rises above the reference plus a small hysteresis
voltage, that current is shut off. In this way, output regulation is maintained.
Since the power transfer from BVIN to SW is through a
high impedance current source rather than through a low
impedance MOSFET switch, power loss scales with load
current as in a linear low dropout (LDO) regulator, rather
than as in a switching regulator. For near-zero load conditions where regulator quiescent current is the dominant
power loss, standby mode is ideal. But at any appreciable
load current, Burst Mode operation yields the best overall
conversion efﬁciency.
Shutdown
Each step-down switching regulator is shut down and
enabled via the pushbutton interface. In shutdown, each
switching regulator draws only a few nanoamps of leakage current from the BVIN pin. Each disabled regulator
also pulls down on its output with a 10k resistor from its
switch pin to ground.
Dropout Operation
It is possible for a step-down switching regulator’s input
voltage to fall near or below its programmed output voltage (e.g., a battery voltage of 3.4V with a programmed
output voltage of 3.3V). When this happens, the PMOS
switch duty cycle increases to 100%, keeping the switch on
continuously. Known as dropout operation, the respective
output voltage equals the regulator’s input voltage minus
the voltage drops across the internal P-channel MOSFET
and the inductor.
Soft-Start Operation
In normal operating mode, soft-start works by gradually
increasing the peak inductor current for each step-down
switching regulator over a 500μs period. This allows each
output to rise slowly, helping minimize the inrush current
needed to charge up the output capacitor. A soft-start cycle
occurs whenever a given switching regulator is enabled.
Soft-start occurs only in normal operation, but not in
standby mode. Standby mode operation is already inherently current-limited, since the regulator works by
intermittently turning on a current source from BVIN to
SW. Changing the state of the STBY pin while the regulators are operating doesn’t trigger a new soft-start cycle,
to avoid glitching the outputs.
Frequency/Slew Rate Select
The FSEL pin allows an application to dynamically trade
off between highest efﬁciency and reduced electromagnetic interference (EMI) emission.
When FSEL is high, the switching regulator frequency is
set to 2.25MHz to stay out of the AM radio band. Also,
new patented circuitry is enabled which limits the slew rate
of the switch nodes (SW1 and SW2). This new circuitry
is designed to transition the switch node over a period of
a few nanoseconds, signiﬁcantly reducing radi-ated EMI
and conducted supply noise.
3554f
22
LTC3554
OPERATION
When FSEL is low, the frequency of the switching regulators
is reduced to 1.125Mhz. The slower switching frequency
reduces switching losses and raises efﬁciency as shown
in Figures 4 and 5. Switch node slew rate is also increased
to minimize transition losses. As the programmed output
voltage decreases, the difference in efﬁciency is more
appreciable.
ing regulators from operating at low supply voltages
where loss of regulation or other undesirable operation
may occur. If driving the step-down switching regulator
input supply from a voltage other than the VOUT pin, the
regulators should not be operated outside the speciﬁed
operating range as operation is not guaranteed beyond
this range.
Low Supply Operation
Inductor Selection
An undervoltage lockout circuit on the VOUT pin (VOUT
UVLO) shuts down the step-down switching regulators
when VOUT drops below about 2.6V. It is thus recommended that the step-down switching regulator input
supply (BVIN) be connected directly to the power path
output (VOUT). The UVLO prevents the step-down switch-
Many different sizes and shapes of inductors are available from numerous manufacturers. Choosing the right
inductor from such a large selection of devices can be
overwhelming, but following a few basic guidelines will
make the selection process much simpler.
1000
100
BAT = 3.8V
1000
100
90
BAT = 3.8V
50
POWER LOSS
40
1
30
20
0.1
FSEL = L
FSEL = H
10
0
0.01
0.1
1
10
100
LOAD CURRENT (mA)
0
1000
EFFICIENCY (%)
10
60
POWER LOSS (mW)
EFFICIENCY (%)
100
EFFICIENCY
70
EFFICIENCY
70
10
60
50
POWER LOSS
40
1
30
0.1
20
FSEL = L
FSEL = H
10
0
0.01
POWER LOSS (mW)
80
100
80
90
0.1
1
10
100
LOAD CURRENT (mA)
0
1000
LTXXXX GXX
LTXXXX GXX
Figure 4. 1.2V Output Efﬁciency and Power Loss
vs Load Current
Figure 5. 3.3V Output Efﬁciency and Power Loss
vs Load Current
3554f
23
LTC3554
OPERATION
Inductor value should be chosen based on the desired
output voltage. See Table 2. Table 3 shows several
inductors that work well with the step-down switching
regulators. These inductors offer a good compromise
in current rating, DCR and physical size. Consult each
manufacturer for detailed information on their entire
selection of inductors.
Choose an inductor with a DC current rating at least 1.5
times larger than the maximum load current to ensure that
the inductor does not saturate during normal operation.
If output short circuit is a possible condition, the inductor should be rated to handle the maximum peak current
speciﬁed for the step-down converters.
Larger value inductors reduce ripple current, which
improves output ripple voltage. Lower value inductors
result in higher ripple current and improved transient
response time, but will reduce the available output current. To maximize efﬁciency, choose an inductor with a
low DC resistance.
Different core materials and shapes will change the size/current and price/current relationship of an inductor. Toroid
or shielded pot cores in ferrite or permalloy materials
are small and do not radiate much energy, but generally
cost more than powdered iron core inductors with similar
electrical characteristics. Inductors that are very thin or
have a very small volume typically have much higher core
Table 1. Ceramic Capacitor Manufacturers
Table 2. Choosing the Inductor Value
AVX
www.avxcorp.com
DESIRED OUTPUT VOLTAGE
RECOMMENDED INDUCTOR VALUE
Murata
www.murata.com
1.8V or Less
10μH
Taiyo Yuden
www.t-yuden.com
1.8V to 2.5V
6.8μH
Vishay Siliconix
www.vishay.com
2.5V to 3.3V
4.7μH
TDK
www.tdk.com
Table 3. Recommended Inductors for Step-Down Switching Regulators
L (μH)
MAX IDC (A)
MAX DCR (Ω)
1117AS-4R7M
1117AS-6R8M
1117AS-100M
INDUCTOR PART NO.
4.7
6.8
10
0.64
0.54
0.45
0.18*
0.250*
0.380*
SIZE (L × W × H) (mm)
3.0 × 2.8 × 1.0
Toko
www.toko.com
MANUFACTURER
CDRH2D11BNP-4R7N
CDRH2D11BNP-6R8N
CDRH2D11BNP-100N
4.7
6.8
10
0.7
0.6
0.48
0.248
0.284
0.428
3.0 × 3.0 × 1.2
Sumida
www.sumida.com
SD3112-4R7-R
SD3112-6R8-R
SD3112-100-R
4.7
6.8
10
0.8
0.68
0.55
0.246*
0.291*
0.446*
3.1 × 3.1 × 1.2
Cooper
www.cooperet.com
EPL2014-472ML_
EPL2014-682ML_
EPL2014-103ML_
4.7
6.8
10
0.88
0.8
0.6
0.254
0.316
0.416
2.0 × 1.8 × 1.4
Coilcraft
www.coilcraft.com
* = Typical DCR
3554f
24
LTC3554
OPERATION
and DCR losses, and will not give the best efﬁciency. The
choice of which style inductor to use often depends more
on the price versus size, performance and any radiated
EMI requirements than on what the step-down switching
regulators requires to operate.
The inductor value also has an effect on Burst Mode
operation. Lower inductor values will cause Burst Mode
switching frequency to increase.
Input/Output Capacitor Selection
Low ESR (equivalent series resistance) ceramic capacitors
should be used at both step-down switching regulator
outputs as well as at the step-down switching regulator
input supply. Only X5R or X7R ceramic capacitors should
be used because they retain their capacitance over wider
voltage and temperature ranges than other ceramic types.
For good transient response and stability the output capacitor for each step-down switching regulator should retain at
least 4μF of capacitance over operating temperature and
bias voltage. Generally, a good starting point is to use a
10μF output capacitor.
The switching regulator input supply should be bypassed
with a 2.2μF capacitor. Consult with capacitor manufacturers for detailed information on their selection and
speciﬁcations of ceramic capacitors. Many manufacturers
now offer very thin (<1mm tall) ceramic capacitors ideal
for use in height-restricted designs. Table 1 shows a list
of several ceramic capacitor manufacturers.
PUSHBUTTON INTERFACE
State Diagram/Operation
Figure 6 shows the LTC3554 pushbutton state diagram.
HR
PUP2
EXTPWR OR
PB400MS
EXTPWR OR
PB400MS
5SEC
PWR_ONx
PUP1
1SEC
5SEC
POFF
PWR_ONx
AND UVLO
PON
HRST
1SEC
PWR_ONx
OR UVLO
PDN2
HRST
HRST
PDN1
POR
3554 F06
Figure 6. Pushbutton State Diagram
Upon ﬁrst application of power, VBUS or BAT, an internal power on reset (POR) signal places the pushbutton
circuitry into the power-down (PDN1) state. One second
after entering the PDN1 state the pushbutton circuitry will
transition into the hard reset (HR) state.
3554f
25
LTC3554
OPERATION
In the HR state, all supplies are disabled. The PowerPath
circuitry is placed in an ultralow quiescent state to minimize
battery drain. If no external charging supply is present
(VBUS) then the ideal diode is shut down, disconnecting
VOUT from BAT to further minimize battery drain. The ultralow power consumption in the HR state makes it ideal for
shipping or long term storage, minimizing battery drain.
state (PDN2), both switching regulators are kept disabled
regardless of the states of the PWR_ON pins. The state
machine remains in the power-down state for one second,
before automatically entering the power-off (POFF) state.
This one second delay allows all LTC3554 generated supplies time to power down completely before they can be
re-enabled.
The following events cause the state machine to transition
out of HR into the power-up (PUP1) state:
The same events used to exit the hard reset (HR) state
are also used to exit the POFF state and enter the PUP2
state. The PUP2 state operates in the same manner as
the PUP1 state previously described.
ON input low for 400ms (PB400MS)
Application of external power (EXTPWR)
Upon entering the PUP1 state, the pushbutton circuitry
will sequence up the two step-down switching regulators,
buck1 followed by buck2. The PWR_ON1 and PWR_ON2
inputs are ignored in the PUP1 state. The state machine
remains in the PUP1 state for ﬁve seconds. During the
ﬁve seconds, the application’s microprocessor, powered
by the switching regulators, has time to boot and assert
PWR_ON1 and/or PWR_ON2. Five seconds after entering
the PUP1 state, the pushbutton circuitry automatically
transitions into the power-on (PON) state.
In the PON state, the switching regulators can be enabled and shut down at any time by the PWR_ON1 and
PWR_ON2 pins. A high on PWR_ON1 is needed to keep
buck1 enabled, and a high on PWR_ON2 is needed to
keep buck2 enabled. To remain in the PON state, the application circuit must keep at least one of the PWR_ON
inputs high, else the state machine enters the power-down
(PDN2) state.
When PWR_ON1 and PWR_ON2 are both low, or when
VOUT drops to its undervoltage lockout (VOUT UVLO)
threshold, the state machine will leave the PON state and
enter the power-down (PDN2) state. In the power-down
Both bucks remain powered up during the ﬁve second
power-up (PUP1 or PUP2) period, regardless of the state
of the PWR_ON inputs.
In either the HR or POFF states, if any PWR_ON pin is
driven high, the pushbutton circuitry directly enters the
PON state, without passing through the power-up (PUP1
or PUP2) states. This is because by asserting logic high
on the PWR_ON1 or PWR_ON2 pins, the application has
already told the LTC3554 exactly which buck(s) to turn
on, so there is no need for an intermediate PUP state in
which both bucks are enabled for ﬁve seconds.
Starting from the HR state, bringing any PWR_ON pin
high enables the PowerPath, if it wasn’t already enabled
due to VBUS power being available. This powers up the
VOUT pin from VBUS or BAT. When the VOUT voltage rises
above the VOUT UVLO threshold, the state machine transitions from the HR state into the PON state, allowing the
selected buck(s) to turn on.
The hard reset (HRST) event is generated by pressing
and holding the pushbutton (ON input low) for 5 seconds.
For a valid HRST event to occur the button press must
start in the PUP1, PUP2 or PON state, but can end in any
3554f
26
LTC3554
OPERATION
state. If a valid HRST event is present in PON, PDN2 or
POFF, then the state machine will transition to the PDN1
state and subsequently transition to the HR state one
second later.
Power-Up Via Pushbutton Press
In the PON, PUP1, and PUP2 states, the PBSTAT opendrain output pin outputs a debounced version of the ON
pushbutton signal. ON must be held low for at least 50ms
for the pushbutton interface to recognize it and cause
PBSTAT to go low. PBSTAT goes high impedance when
ON goes high, except the logic enforces a minimum pulse
width on PBSTAT. Once it goes low, it stays low for at
least 50ms.
Figure 7 shows the LTC3554 powering up through application of the external pushbutton. For this example the
pushbutton circuitry starts in the POFF or HR state with a
battery connected and both bucks disabled. Pushbutton
application (ON low) for 400ms transitions the pushbutton
circuitry into the PUP state and powers up buck1 followed
by buck2. If either PWR_ON is low or goes low after the
5 second period the corresponding buck(s) will be shut
down. In the above example PWR_ON2 is low at the end
of the 5 second period and therefore buck2 is disabled
at the end of the 5 second period. PGOOD is asserted
once all enabled bucks are within 8% of their regulation
voltage for 230ms.
In the HR, POFF, PDN1, and PDN2 states, PBSTAT remains
high impedance regardless of the state of ON.
The PWR_ON inputs can be driven via a μP/μC or by one
of the buck outputs through a high impedance (100kΩ
Debounced Pushbutton Output (PBSTAT)
1
BAT
0
1
VBUS
0
1
ON (PB)
0
1
PBSTAT
0
400ms
1
BUCK1
0
1
BUCK2
0
230ms
1
PGOOD
0
5s
1
PWR_ON1
0
1
PWR_ON2
0
STATE
POFF/HR
PUP2/PUP1
PON
3554 TD01
Figure 7. Power-Up Via Pushbutton Press
3554f
27
LTC3554
OPERATION
typical) to keep the bucks enabled as described above.
PBSTAT does not go low on initial pushbutton application
for power-up, but will go low with subsequent ON pushbutton applications in the PUP1, PUP2 or PON states.
the end of the 5 second period and therefore both bucks
continue to stay on at the end of the 5 second period.
PGOOD is asserted once all enabled bucks are within 8%
of their regulation voltage for 230ms.
Power-Up Via Applying External Power
The PWR_ON inputs can be driven via a μP/μC or one of
the buck outputs through a high impedance (100kΩ typ)
to keep the bucks enabled as described above.
Figure 8 shows the LTC3554 powering up through application of external power (VBUS). For this example the
pushbutton circuitry starts in the POFF or HR state with a
battery connected and both bucks disabled. 100ms after
VBUS application the pushbutton circuitry transitions into
the PUP state and powers up buck1 followed by buck2.
The 100ms delay time allows the applied supply to settle.
The bucks will stay powered as long as their respective
PWR_ON inputs are driven high before the 5 second PUP
period is over. If either PWR_ON is low or goes low after
the 5 second period the corresponding buck(s) will be shut
down. In the above example both PWR_ONs are high at
Without a battery present, initial power application causes
a power-on reset which puts the pushbutton circuitry in
the PDN1 state and subsequently the HR state one second
later. At this time, if a valid supply voltage is detected
at the BUS pin (i.e., VBUS > VUVLO and VBUS – VBAT >
VDUVLO), the pushbutton circuity immediately enters the
PUP1 state. For this to work reliably, the BAT pin voltage
must be kept well-behaved when no battery is connected.
Ensure this by bypassing the BAT pin to GND with an RC
network consisting of a 100μF ceramic capacitor in series
with 0.3Ω.
1
BAT
0
1
VBUS
0
1
ON (PB)
0
1
PBSTAT
0
100ms
1
BUCK1
0
1
BUCK2
0
230ms
1
PGOOD
0
5s
1
PWR_ON1
0
5s
1
PWR_ON2
0
STATE
POFF/HR
PUP2/PUP1
PON
3554 TD02
Figure 8. Power-Up Via Applying External Power
3554f
28
LTC3554
OPERATION
Power-Up Via Asserting PWR_ON Pins
Power-Down Via PWR_ON De-Assertion
Figure 9 shows the LTC3554 powering up by driving
PWR_ON1 high. For this example the pushbutton circuitry
starts in the POFF or HR state with a battery connected
and all bucks disabled. Once PWR_ON1 goes high, the
pushbutton circuitry enters the PON state and buck1
powers up. Once buck1’s output is within 8% of its regulation voltage for 230ms, PGOOD is asserted. Similarly,
if PWR_ON2 is brought high at a later time, buck2 will
power up. The pushbutton circuitry remains in the PON
state. During the time that buck2 powers up, PGOOD will
be held low. PGOOD will be asserted again once buck2 is
within 8% of its regulation for 230ms.
Figure 10 shows the LTC3554 powering down by μC/μP
control. For this example the pushbutton circuitry starts
in the PON state with a battery connected and all bucks
enabled. The user presses the pushbutton (ON low) for at
least 50ms, which generates a debounced, low impedance
pulse on the PBSTAT output. After receiving the PBSTAT
signal, the μC/μP software decides to drive the PWR_ON
inputs low in order to power down. After the last PWR_ON
pin goes low, the pushbutton circuitry will enter the PDN2
state. In the PDN2 state a one second wait time is initiated after which the pushbutton circuitry enters the POFF
state. During this one second time, the ON and PWR_ON
inputs as well as external power application are ignored to
allow all LTC3554 generated supplies to go low. Though
the above assumes a battery present, the same operation
would take place with a valid external supply (VBUS) with
or without a battery present.
Powering up via PWR_ON is useful for applications
containing an always-on μC that’s not powered by the
LTC3554 regulators. That μC can power the application
up and down for housekeeping and other activities not
needing the user’s control.
1
1
BAT
BAT
0
0
1
1
VBUS
VBUS
0
0
1s
1
1
ON (PB)
ON (PB)
0
0
PBSTAT
PBSTAT
0
0
μC/μP CONTROL
1
1
PWR_ON1
PWR_ON1
0
0
μC/μP CONTROL
1
1
PWR_ON2
PWR_ON2
0
0
1
1
BUCK1
BUCK1
0
0
1
1
BUCK2
BUCK2
0
0
230ms
230ms
1
1
PGOOD
PGOOD
0
0
STATE
50ms
1
1
POFF/HR
STATE
PON
PON
PDN2
POFF
3554 TD04
3554 TD03
Figure 9. Power-Up Via Asserting PWR_ON Pins
Figure 10. Power-Down Via PWR_ON De-Assertion
3554f
29
LTC3554
OPERATION
Holding ON low through the one second power-down
period will not cause a power-up event at end of the one
second period. The ON pin must be brought high following
the power-down event and then go low again to establish
a valid power-up event.
UVLO Minimum Off-Time Timing (Low Battery)
Figure 11 assumes the battery is either missing or at a
voltage below the VOUT UVLO threshold, and the application is running via external power (VBUS). A glitch on the
external supply causes VOUT to drop below the VOUT UVLO
threshold temporarily. This VOUT UVLO condition causes
the pushbutton circuitry to transition from the PON state
to the PDN2 state. Upon entering the PDN2 state PGOOD
will go low and the bucks power down together.
1
BAT
0
1
VBUS
0
1
ON (PB)
0
1
PBSTAT
In the typical case where the PWR_ON1 and PWR_ON2 pins
are driven by logic powered by the bucks, the PWR_ON1
and PWR_ON2 pins would also go low, as depicted in
Figure 11. If the external supply recovers after entering
the PDN2 state such that VOUT is no longer in UVLO, then
the LTC3554 will transition back into the PUP2 state once
the PDN2 one second delay is complete. Following the
state diagram, the transition from PDN2 to PUP2 in this
case actually occurs via a brief visit to the POFF state,
during which the state machine immediately recognizes
that valid external power is available and transitions into
the PUP2 state. Entering the PUP2 state will cause the
bucks to sequence up as described previously in the
power-up sections.
Not depicted here, but in the case where the PWR_ON
pins are driven by a supply other than the bucks, and
are able to remain high while both bucks are off in the
PDN2 state, then as per the state diagram in Figure 6,
once the one second PDN2 delay is over, the pushbutton
circuitry enters the POFF state. Provided at least one
PWR_ON pin is high, and VOUT is no longer in UVLO, the
pushbutton circuitry will transition directly into the PON
state, enabling the buck(s) corresponding to the asserted
PWR_ON pin(s).
Note: If VOUT drops too low (below about 1.9V ) the LTC3554
will see this as a POR condition and will enter the PDN1
rather than the PDN2 state. One second later the part
will transition to the HR state. Under these conditions an
explicit power up event (such as a pushbutton press) may
be required to bring the LTC3554 out of hard reset.
0
5s
1
PWR_ON1
0
5s
1
PWR_ON2
0
1s, BUCK1 POWERS UP
1
BUCK1
Hard Reset Timing
0
BUCK2 POWERS UP
1
BUCK2
0
230ms
1
PGOOD
0
STATE
PON
PDN2
PUP2
PON
3554 TD05
Figure 11. UVLO Minimum Off-Time Timing
HARD RESET provides an ultralow power-down state for
shipping or long term storage as well as a way to power
down the application in case of a software lockup. In the
case of software lockup, the user can hold the pushbutton
(ON low) for 5 seconds and a hard reset event (HRST) will
occur, placing the pushbutton circuitry in the power-down
(PDN1) state. At this point the bucks will be shut down
and PGOOD will go low. Following a one second powerdown period the pushbutton circuitry will enter the hard
reset state (HR).
3554f
30
LTC3554
OPERATION
Holding ON low through the one second power-down
period will not cause a power-up event at end of the one
second period. ON must be brought high following the
power-down event and then go low again for 400ms to
establish a valid power-up event, as shown in Figure 12.
The regulators in Figure 13 are slewing up with nominal
output capacitors and no-load. Adding a load or increasing output capacitance on any of the outputs will reduce
the slew rate and lengthen the time it takes the regulator
to get into regulation.
1
BAT
0
VOUT1
1
1V/DIV
VBUS
0
0V
5s
1
VOUT2
0.5V/DIV
ON (PB)
0
50ms
0V
1
PBSTAT
100μs/DIV
0
400ms
3554 F13
Figure 13. Power-Up Sequencing
1
BUCK1
0
1
LAYOUT AND THERMAL CONSIDERATIONS
BUCK2
0
1s
Printed Circuit Board Power Dissipation
1
PWR_ON1
0
1
PWR_ON2
0
1
PGOOD
0
STATE
PON
PDN1
HR
PUP1
3554 TD06
Figure 12. Hard Reset Via Holding ON Low for 5s
Power-Up Sequencing
Figure 13 shows the actual power-up sequencing of the
LTC3554. Buck1 and buck2 are both initially disabled (0V).
Once the pushbutton has been applied (ON low) for 400ms
buck1 is enabled. Buck1 slews up and enters regulation.
The actual slew rate is controlled by the soft start function of buck1 in conjunction with output capacitance and
load (see the Step-Down Switching Regulator Operation
section for more information). When buck1 is within about
8% of ﬁnal regulation, buck2 is enabled and slews up
into regulation. 230ms after buck2 is within 8% of ﬁnal
regulation, the PGOOD output will go high impedance.
In order to be able to deliver maximum charge current
under all conditions, it is critical that the Exposed Pad
on the backside of the LTC3554 package is soldered
to a ground plane on the board. Correctly soldered to a
2500mm2 ground plane on a double-sided 1oz copper
board, the LTC3554 has a thermal resistance (θJA) of
approximately 70°C/W. Failure to make good thermal
contact between the Exposed Pad on the backside of the
package and an adequately sized ground plane will result
in thermal resistances far greater than 70°C/W.
The conditions that cause the LTC3554 to reduce charge
current due to the thermal protection feedback can be
approximated by considering the power dissipated in the
part. For high charge currents the LTC3554 power dissipation is approximately:
PD = (VBUS –BAT) • IBAT + PD(REGS)
where PD is the total power dissipated, VBUS is the supply
voltage, BAT is the battery voltage, and IBAT is the battery
charge current. PD(REGS) is the sum of power dissipated
on chip by the step-down switching regulators.
3554f
31
LTC3554
OPERATION
The power dissipated by a step-down switching regulator
can be estimated as follows:
PD(SWx) = (BOUTx • IOUT) • (100 - Eff)/100
Where BOUTx is the programmed output voltage, IOUT is
the load current and Eff is the % efﬁciency which can
be measured or looked up on an efﬁciency table for the
programmed output voltage.
Thus the power dissipated by all regulators is:
PD(REGS) = PD(SW1) + PD(SW2)
It is not necessary to perform any worst-case power dissipation scenarios because the LTC3554 will automatically
reduce the charge current to maintain the die temperature
at approximately 110°C. However, the approximate ambient temperature at which the thermal feedback begins to
protect the IC is:
TA = 110°C – PD • θJA
Example: Consider the LTC3554 operating from a wall
adapter with 5V (VBUS) providing 400mA (IBAT) to charge a
Li-Ion battery at 3.3V (BAT). Also assume PD(REGS) = 0.3W,
so the total power dissipation is:
PD = (5V – 3.3V) • 400mA + 0.3W = 0.98W
The ambient temperature above which the LTC3554 will
begin to reduce the 400mA charge current, is approximately:
TA = 110°C – 0.98W • 70°C/W = 41.4°C
The LTC3554 can be used above 41.4°C, but the charge
current will be reduced below 400mA. The charge current at
a given ambient temperature can be approximated by:
PD = (110°C – TA) / θJA = (VBUS – BAT) • IBAT + PD(REGS)
Thus:
IBAT = [(110°C – TA) / θJA - PD(REGS)]
(VBUS – BAT)
Consider the above example with an ambient temperature of 60°C. The charge current will be reduced to
approximately:
Printed Circuit Board Layout
When laying out the printed circuit board, the following
list should be followed to ensure proper operation of the
LTC3554:
1. The Exposed Pad of the package (Pin 21) should connect directly to a large ground plane to minimize thermal
and electrical impedance.
2. The trace to the step-down switching regulator input
supply pin (BVIN) and its decoupling capacitor should be
kept as short as possible. The GND side of this capacitor
should connect directly to the ground plane of the part.
This capacitor provides the AC current to the internal
power MOSFETs and their drivers. It is important to
minimize inductance from this capacitor to the pin of
the LTC3554. Connect BVIN to VOUT through a short
low impedance trace.
3. The switching power traces connecting SW1, and SW2
to their respective inductors should be minimized to
reduce radiated EMI and parasitic coupling. Due to the
large voltage swing of the switching nodes, sensitive
nodes such as the feedback nodes (FB1 and FB2) should
be kept far away or shielded from the switching nodes
or poor performance could result.
4. Connections between the step-down switching regulator inductors and their respective output capacitors
should be kept as short as possible. The GND side of
the output capacitors should connect directly to the
thermal ground plane of the part.
5. Keep the buck feedback pin traces (FB1, and FB2) as
short as possible. Minimize any parasitic capacitance
between the feedback traces and any switching node
(i.e., SW1, SW2 and logic signals). If necessary, shield
the feedback nodes with a GND trace.
6. Connections between the LTC3554 PowerPath pins
(VBUS and VOUT) and their respective decoupling capacitors should be kept as short as possible. The GND
side of these capacitors should connect directly to the
ground plane of the part.
IBAT = [(110°C - 60°C) / 70°C/W - 0.3W]/(5V – 3.3V)
IBAT = (0.71W - 0.3W) / 1.7V = 241mA
3554f
32
LTC3554
TYPICAL APPLICATION
4.35V TO 5.5V
USB INPUT
20
R1
100k
R2
100k
15
VBUS
VOUT
NTC
CHRG
16
PROG
1
R3
BAT
9
2
10
4
8
3
5
PB1
HPWR
BVIN
17
+
SW1
FSEL
FB1
C2
2.2μF
13
6
L1 4.7μH
C3
10pF
STBY
PGOOD
SW2
PWR_ON2
11
PBSTAT
ON
FB2
GND
Li-Ion
BATTERY
12
SUSP
PWR_ON1
EN
14
RPROG
1.87k
19
1.8V
C1
10μF
LTC3554
T
LDO
SYSTEM LOAD
18
7
L2
10μH
C5
10pF
3.3V
RUP1
2.05M
MEMORY
I/O
C4
10μF
RLO1
649k
1.2V
RUP2
332k
CORE
C6
10μF
μC
RLO2
649k
R2
100k
R3
100k
PBSTAT
PWR_ON2
PGOOD
STBY
FSEL
PWR_ON1
SUSP
HPWR
3554 F14
Figure 14. USB PowerPath with LI-Ion Battery (NTC Qualiﬁed Charging)
3554f
33
LTC3554
TYPICAL APPLICATION
U1
20
4.35V TO 5.5V
USB INPUT
15
VBUS
VOUT
NTC
CHRG
LTC3554
16
BAT
SYSTEM LOAD
18
C1
10μF
14
17
+
PROG
RPROG
1.87k
1
19
9
2
10
4
8
3
5
PB1
BVIN
HPWR
3 CELL
ALKALINE
OR LITHIUM
12
C2
2.2μF
SUSP
SW1
PWR_ON1
FB1
FSEL
13
6
L1 10μH
C3
10pF
STBY
PGOOD
SW2
PWR_ON2
11
PBSTAT
ON
FB2
7
U2
L2
10μH
C5
10pF
2.5V
RUP1
1M
I/O
C4
10μF
RLO1
464k
1.8V
RUP2
590k
CORE
C6
10μF
μC
GND
RLO2
464k
R4
100k
R2
100k
R3
100k
PBSTAT
PGOOD
STBY
FSEL
EN
SUSP
HPWR
3554 F15
Figure 15. 3-Cell Alkaline/Lithium with PowerPath (Charger Disabled)
3554f
34
LTC3554
PACKAGE DESCRIPTION
PD Package
20-Lead Plastic UTQFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1835 Rev Ø)
0.70 ±0.05
3.50 ± 0.05
1.60 ± 0.05
1.65 ±0.05
2.10 ± 0.05
1.65 ±0.05
PACKAGE
OUTLINE
0.20 ±0.05
0.40 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
BOTTOM VIEW—EXPOSED PAD
R = 0.10
TYP
0.55 ± 0.05
3.00 ± 0.10
PIN 1 NOTCH
0.35 s 45°
CHAMFER
R = 0.05
TYP
PIN 1
TOP MARK
(NOTE 6)
19 20
0.40 ± 0.10
1
2
3.00 ± 0.10
1.60 REF
1.65 ±0.10
1.65 ±0.10
(PD20) UTQFN 0409 REV Ø
0.150 REF
0.00 – 0.05
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.20 ± 0.05
0.40 BSC
3554f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LTC3554
RELATED PARTS
PART
NUMBER
DESCRIPTION
COMMENTS
LTC3455
Dual DC/DC Converter with USB Power
Manager and Li-Ion Battery Charger
Seamless Transition Between Input Power Sources: Li-Ion Battery, USB and 5V Wall
Adapter, Two High Efﬁciency DC/DC Converters: Up to 96%, Full Featured Li-Ion Battery
Charger with Accurate USB Current Limiting (500mA/100mA) Pin-Selectable Burst
Mode Operation, Hot Swap TM Output for SDIO and Memory Cards, 4mm × 4mm QFN-24
Package
LTC3456
2-Cell, Multioutput DC/DC Converter with Seamless Transition Between 2-Cell Battery, USB and AC Wall Adapter Input Power
USB Power Manager
Sources, Main Output: Fixed 3.3V Output, Core Output: Adjustable from 0.8V to
VBATT(MIN), Hot Swap Output for Memory Cards, Power Supply Sequencing: Main and
Hot Swap Accurate USB Current Limiting, High Frequency Operation = 1MHz, High
Efﬁciency: Up to 92%, 4mm × 4mm QFN-24 Package
LTC3550
Dual Input USB/AC Adapter Li-Ion Battery Synchronous Buck Converter, Efﬁciency = 93%, Adjustable Output at 600mA, Charge
Charger with Adjustable Output 600mA
Current: 950mA Programmable, USB-Compatible, Automatic Input Power Detection
Buck Converter
and Selection
LTC3552
Standalone Linear Li-Ion Battery Charger Synchronous Buck Converter, Efﬁciency > 90%, Adjustable Outputs at 800mA and
with Adjustable Output Dual Synchronous 400mA, Charge Current Programmable Up to 950mA, USB-Compatible, 5mm × 3mm
Buck Converter
DFN-16 Package
LTC3552-1
Standalone Linear Li-Ion Battery Charger Synchronous Buck Converter, Efﬁciency > 90%, Outputs 1.8V at 800mA and 1.575 at
with Dual Synchronous Buck Converter
400mA, Charge Current Programmable Up to 950mA, USB-Compatible
LTC3557
USB Power Manager with Li-Ion Charger, Triple Step-Down Switching Regulators (600mA, 400mA); Seamlessly Transition Input
Triple Step-Down DC/DC Regulators and Power between Li-Ion Battery, USB, 5V Wall Adapter, or External High Voltage Buck
External High Voltage Buck Control
Regulator with Bat-Track™; 4mm × 4mm QFN Package
LTC3559
USB Charger with Dual Buck Regulators
Adjustable, Synchronous Buck Converters, Efﬁciency > 90%, Outputs: Down to 0.8V at
400mA Each, Charge Current Programmable Up to 950mA, USB-Compatible, 3mm ×
3mm QFN-16 Package
LTC3577
I2C Controlled USB Power Manager with
Li-Ion Charger, Triple Step-Down DC/DC
Regulators, Dual LDOs and 40V LED
Backlight Driver
High Integration USB Power Management Solution for Portable Products
LTC4080
500mA Standalone Charger with 300mA
Synchronous Buck
Charges Single-Cell Li-Ion Batteries, Timer Termination + C/10, Thermal Regulation, Buck
Output: 0.8V to VBAT, Buck Input VIN: 2.7V to 5.5V, 3mm × 3mm DFN-10 Package
Hot Swap and Bat-Track are trademarks of Linear Technology Corporation.
3554f
36 Linear Technology Corporation
LT 0509 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2009

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