LTC3417A-1 Dual Synchronous 1.5A/1A 4MHz Step-Down DC/DC Regulator with POR DESCRIPTION FEATURES n n n n n n n n n n n n n n n n n High Efficiency: Up to 95% 1.5A/1A Guaranteed Minimum Output Current Synchronizable to External Clock Power-On-Reset Output No Schottky Diodes Required Programmable Frequency Operation: 1.5MHz or Adjustable From 0.6MHz to 4MHz Low Ripple (< 35mVP-P) BurstMode® Operation Low RDS(ON) Internal Switches Short-Circuit Protected VIN: 2.25V to 5.5V Current Mode Operation for Excellent Line and Load Transient Response 125μA Quiescent Current in Sleep Mode Ultralow Shutdown Current: IQ < 1μA Low Dropout Operation: 100% Duty Cycle Phase Pin Selects 2nd Channel Phase Relationship with Respect to 1st Channel Internal Soft-Start with Individual Run Pin Control Available in Small Thermally Enhanced (3mm × 5mm) DFN and 20-Lead TSSOP Packages APPLICATIONS n n n n n The LTC®3417A-1 is a dual constant frequency, synchronous step-down DC/DC converter. Intended for medium power applications, it operates from a 2.25V to 5.5V input voltage range and has a constant programmable switching frequency, allowing the use of tiny, low cost capacitors and inductors 2mm or less in height. Each output voltage is adjustable from 0.8V to 5V. Internal synchronous, low RDS(ON) power switches provide high efficiency without the need for external Schottky diodes. The open drain POR pin goes low when either output voltage falls 6% below regulation. The output will remain low 150ms longer than the duration of the out of regulation condition. A user selectable mode input allows the user to trade off ripple voltage for light load efficiency. Burst Mode operation provides high efficiency at light loads, while pulse skip mode provides low ripple noise at light loads. A phase mode pin allows the second channel to operate in-phase or 180° out-of-phase with respect to channel 1. Out-of-phase operation produces lower RMS current on VIN and thus lower stress on the input capacitor. To further maximize battery life, the P-channel MOSFETs are turned on continuously in dropout (100% duty cycle) and both channels draw a total quiescent current of only 100μA. In shutdown, the device draws <1μA. GPS/Navigation Systems Automotive Instrumentation PC Cards Industrial Power Supplies General Purpose Point of Load DC/DC L, LT, LTC and LTM and Burst Mode are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131, 6144194. OUT2 Efficiency (Burst Mode Operation) TYPICAL APPLICATION VIN 2.5V TO 5.5V 100 VIN 1.5μH 22pF VIN SW2 RUN1 RUN2 22pF VIN LTC3417A-1 511k 47μF 2.2μH SW1 VFB1 VFB2 ITH1 ITH2 412k 5.9k 2200pF VOUT2 2.5V 1A 866k 412k GND 95 RESET POR FREQ 0.1 85 0.01 80 POWER LOSS 22μF 75 3417A-1 TA01 1 EFFICIENCY 90 2.87k 6800pF 10 REFER TO FIGURE 4 70 0.001 0.001 VIN = 3.6V VOUT = 2.5V FREQ = 1MHz 0.01 0.1 LOAD CURRENT (A) POWER LOSS (W) VOUT1 1.8V 1.5A 100k EFFICIENCY (%) 10μF 0.0001 1 3417A-1 TA01a 3417a1fa 1 LTC3417A-1 ABSOLUTE MAXIMUM RATINGS (Note 1) VIN1, VIN2 Voltages ...................................... – 0.3V to 6V SYNC/MODE, SW1, SW2, RUN1, RUN2, VFB1, VFB2, PHASE, FREQ, ITH1, ITH2 Voltages........ –0.3V to ((VIN1 or VIN2) + 0.3V) VIN1 – VIN2, VIN2 – VIN1 .......................................... 0.3V POR Voltage ................................................ –0.3V to 6V Operating Temperature Range (Note 2) LTC3417AE-1 ...................................... –40°C to 85°C LTC3417AI-1 ..................................... –40°C to 125°C Junction Temperature (Notes 7, 8) ...................... 125°C Storage Temperature Range................... –65°C to 150°C PIN CONFIGURATION TOP VIEW TOP VIEW GNDD 1 20 GNDD RUN1 2 19 PGND1 15 SW1 VIN1 3 18 SW1 3 14 PHASE ITH1 4 17 PHASE 4 13 GNDA VFB1 5 12 FREQ VFB2 6 15 FREQ 11 POR ITH2 7 14 POR RUN2 8 13 SW2 VIN2 9 12 SYNC/MODE RUN1 1 16 PGND1 VIN1 2 ITH1 VFB1 VFB2 ITH2 5 6 17 RUN2 7 10 SW2 VIN2 8 9 SYNC/MODE PGND2 10 DHC PACKAGE 16-LEAD (5mm × 3mm) PLASTIC DFN 21 16 GNDA 11 PGND2 FE PACKAGE 20-LEAD PLASTIC TSSOP TJMAX = 125°C, θJA = 43°C/ W EXPOSED PAD (PIN 17) IS PGND2/GNDD MUST BE SOLDERED TO PCB TJMAX = 125°C, θJA = 38°C/ W EXPOSED PAD (PIN 21) IS PGND2/GNDD MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3417AEDHC-1#PBF LTC3417AEDHC-1#TRPBF 3417A1 16-Lead (3mm × 5mm) Plastic DFN –40°C to 85°C LTC3417AIDHC-1#PBF LTC3417AIDHC-1#TRPBF 3417A1 16-Lead (3mm × 5mm) Plastic DFN –40°C to 125°C LTC3417AEFE-1#PBF LTC3417AEFE-1#TRPBF LTC3417AFE-1 20-Lead Plastic TSSOP –40°C to 85°C LTC3417AIFE-1#PBF LTC3417AIFE-1#TRPBF LTC3417AFE-1 20-Lead Plastic TSSOP –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V unless otherwise specified (Note 2). SYMBOL PARAMETER CONDITIONS MIN VIN1, VIN2 Operating Voltage Range VIN1 = VIN2 2.25 IFB1, IFB2 Feedback Pin Input Current VIN = 6V Pin Under Test = 3V TYP MAX UNITS 5.5 V ± 0.1 μA 3417a1fa 2 LTC3417A-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V unless otherwise specified (Note 2). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VFB1, VFB2 Feedback Voltage (Note 3) 0.784 0.8 0.816 V ΔVLINEREG Reference Voltage Line Regulation. %/V is the Percentage Change in VOUT with a Change in VIN VIN = 2.25V to 5V (Note 3) 0.02 0.2 %/V ΔVLOADREG Output Voltage Load Regulation ITH1, ITH2 = 0.36V (Note 3) ITH1, ITH2 = 0.84V (Note 3) 0.02 –0.02 0.2 –0.2 % % gm(EA) Error Amplifier Transconductance ITH1, ITH2(PINLOAD) = ±5μA (Note 3) 1400 IS Input DC Supply Current (Note 4) Active Mode VFB1 = VFB2 = 0.75V, VSYNC/MODE = VIN, VRUN1 = VRUN2 = VIN 400 600 μA IS l μS Half Active Mode (VRUN2 = 0V, 1.5A Only) VFB1 = 0.75V, VSYNC/MODE = VIN, VRUN1 = VIN 260 400 μA Half Active Mode (VRUN1 = 0V, 1A Only) VFB2 = 0.75V, VSYNC/MODE = VIN, VRUN2 = VIN 260 400 μA Both Channels in Sleep Mode VFB1 = VFB2 = 1V, VSYNCMODE = VIN, VRUN1 = VRUN2 = VIN 125 250 μA Shutdown VRUN1 = VRUN2 = 0V 0.01 1 μA fOSC Oscillator Frequency VFREQ = VIN VFREQ: RT = 143k VFREQ: Resistor (Note 6) 1.2 0.85 1.5 1 1.8 1.25 4 ILIM1 Peak Switch Current Limit on SW1 (1.5A) 2.1 2.5 A ILIM2 Peak Switch Current Limit on SW2 (1A) 1.4 1.7 A RDS(ON)1 SW1 Top Switch On-Resistance (1.5A) SW1 Bottom Switch On-Resistance VIN1 = 3.6V (Note 5) VIN1 = 3.6V (Note 5) 0.088 0.084 Ω Ω RDS(ON)2 SW2 Top Switch On-Resistance (1A) SW2 Bottom Switch On-Resistance VIN2 = 3.6V (Note 5) VIN2 = 3.6V (Note 5) 0.16 0.15 Ω Ω ISW1(LKG) Switch Leakage Current SW1 (1.5A) VIN1 = 6V, VRUN1 = 0V 0.01 1 μA ISW2(LKG) Switch Leakage Current SW2 (1A) VIN2 = 6V, VRUN2 = 0V 0.01 1 μA VUVLO Undervoltage Lockout Threshold VIN1, VIN2 Ramping Down VIN1, VIN2 Ramping Up 2.07 2.12 2.2 2.25 V V VTH(POR) Power-On-Reset Threshold VFB1 or VFB2 Ramping Up Percentage Deviation of VFB Voltage from VFB1 or VFB2 Ramping Down Steady State Value (Typically 0.8V) –6 % –8 % RPOR Power-On-Reset Pull Down On-Resistance 120 tPOR Power-On-Reset De-Assertion Delay from FREQ = VIN Fault Removal 1.9 1.95 FREQ Tied to GND Through 143k Resistor VRUN1, VRUN2 RUN1, RUN2 Threshold VPHASE PHASE Threshold High-CMOS Levels 0.3 Clock Cycles 294,912 Clock Cycles 0.85 1.5 VIN –0.5 VIN = 6V, Pin Under Test = 3V Ω 212,992 V V PHASE Threshold Low-CMOS Levels IRUN1, IRUN2, IPHASE, RUN1, RUN2, PHASE and SYNC/MODE Leakage Current ISYNC/MODE 300 MHz MHz MHz ±0.01 0.5 V ±1 μA 0.5 V VTLSYNC/MODE SYNC/MODE Threshold Voltage Low VTHSYNC/MODE SYNC/MODE Threshold Voltage High VIN –0.5 V VTHFREQ FREQ Threshold Voltage High VIN –0.5 V 3417a1fa 3 LTC3417A-1 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3417AE-1 is guaranteed to meet specified performance from 0°C to 85°C. Specifications over the –40°C to 85°C operating ambient temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3417AI-1 is guaranteed to meet performance specifications over the –40°C to 125°C operating temperature range. Note 3: The LTC3417A-1 is tested in feedback loop which servos VFB1 to the midpoint for the error amplifier (VITH1 = 0.6V) and VFB2 to the midpoint for the error amplifier (VITH2 = 0.6V). Note 4: Total supply current is higher due to the internal gate charge being delivered at the switching frequency. Note 5: Switch on-resistance is guaranteed by design and test correlation on the DHC package and by final test correlation on the FE package. Note 6: Variable frequency operation with resistor is guaranteed by design but not production tested and is subject to duty cycle limitations. Note 7: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 8: TJ is calculated from the ambient temperature, TA, and power dissipation, PD, according to the following formula: LTC3417AEDHC-1: TJ = TA + (PD • 43°C/W) LTC3417AEFE-1: TJ = TA + (PD • 38°C/W) TYPICAL PERFORMANCE CHARACTERISTICS OUT1 Pulse Skipping Mode Operation OUT1 Burst Mode Operation OUT1 Forced Continuous Mode Operation VOUT 20mV/DIV VOUT 20mV/DIV VOUT 20mV/DIV IL 250mA/DIV IL 250mA/DIV IL 250mA/DIV 2μs/DIV VIN = 3.6V VOUT = 1.8V ILOAD = 100mA REFER TO FIGURE 4 3417A-1 G01 VIN = 3.6V 2μs/DIV VOUT = 1.8V ILOAD = 100mA REFER TO FIGURE 4 VIN = 3.6V 2μs/DIV VOUT = 1.8V ILOAD = 100mA REFER TO FIGURE 4 3417A-1 G02 OUT2 Pulse Skipping Mode Operation OUT2 Burst Mode Operation OUT2 Forced Continuous Mode Operation VOUT 20mV/DIV VOUT 20mV/DIV VOUT 20mV/DIV IL 250mA/DIV IL 250mA/DIV IL 250mA/DIV VIN = 3.6V 2μs/DIV VOUT = 2.5V ILOAD = 60mA REFER TO FIGURE 4 3417A-1 G04 VIN = 3.6V 2μs/DIV VOUT = 2.5V ILOAD = 60mA REFER TO FIGURE 4 3417A-1 G03 3417A-1 G05 VIN = 3.6V 2μs/DIV VOUT = 2.5V ILOAD = 60mA REFER TO FIGURE 4 3417A-1 G06 3417a1fa 4 LTC3417A-1 TYPICAL PERFORMANCE CHARACTERISTICS OUT1 Efficiency vs Load Current 100 100 90 90 100 VIN = 3.6V 95 VOUT = 2.5V 85 80 75 Burst Mode OPERATION PULSE SKIP FORCED CONTINUOUS REFER TO FIGURE 4 70 65 0.01 0.1 1 85 80 75 Burst Mode OPERATION PULSE SKIP FORCED CONTINUOUS REFER TO FIGURE 4 70 65 60 0.001 10 0.01 LOAD CURRENT (A) VOUT = 1.8V 95 EFFICIENCY (%) EFFICIENCY (%) EFFICIENCY (%) VIN = 2.5V 95 VOUT = 1.8V 60 0.001 OUT1 Efficiency vs VIN (Burst Mode Operation) OUT2 Efficiency vs Load Current 0.1 1 ILOAD = 460mA 90 ILOAD = 1.4A 85 80 75 REFER TO FIGURE 4 70 2 10 2.5 3 3.5 4 4.5 LOAD CURRENT (A) 3417A-1 G07 5.5 3417A-1 G09 3417A-1 G08 OUT2 Efficiency vs VIN (Pulse Skipping Mode) 5 VIN (V) Load Step OUT1 Load Step OUT2 100 ILOAD = 250mA EFFICIENCY (%) 95 VOUT1 100mV/DIV VOUT2 100mV/DIV IOUT1 500mA/DIV IOUT2 500mA/DIV ILOAD = 800mA 90 85 80 75 70 2 2.5 3 3.5 4 4.5 3417A-1 G11 VIN = 3.6V 100μs/DIV VOUT = 1.8V ILOAD = 0.25A to 1.4A REFER TO FIGURE 4 VOUT = 2.5V REFER TO FIGURE 4 5 3417A-1 G12 VIN = 3.6V 100μs/DIV VOUT = 2.5V ILOAD = 0.25A to 0.8A REFER TO FIGURE 4 VIN (V) 3417A-1 G10 Efficiency vs Frequency OUT1 TA = 27°C VIN = 3.6V VOUT = 1.8V IOUT = 300mA 92 88 86 75 82 60 3 4 5 FREQUENCY (MHz) TA = 27°C VIN = 3.6V VOUT = 2.5V IOUT = 100mA 0 1 2 0.090 0.085 N-CHANNEL SWITCH 0.080 2 3 2.5 3 3.5 4 4.5 5 5.5 VIN (V) FREQUENCY (MHz) 3417A-1 G13 0.095 70 65 2 0.100 80 84 1 TA = 27°C P-CHANNEL SWITCH 90 0 RDS(ON) vs VIN OUT1 0.105 85 EFFICIENCY (%) EFFICIENCY (%) Efficiency vs Frequency OUT2 90 RDS(ON) (Ω) 94 3417A-1 G14 3417A-1 G15 3417a1fa 5 LTC3417A-1 TYPICAL PERFORMANCE CHARACTERISTICS RDS(ON) vs VIN OUT2 Frequency vs VIN 0.20 TA = 27°C FREQUENCY VARIATION (%) P-CHANNEL SWITCH 0.18 0.17 0.16 2 FREQUENCY VARIATION (%) 4 0.19 RDS(ON) (Ω) Frequency vs Temperature 15 6 FREQ = 143k TO GROUND 0 –2 –4 FREQ = VIN –6 0.15 10 FREQ = VIN 5 0 FREQ = 143k TO GROUND –5 –10 –8 N-CHANNEL SWITCH 0.14 2 2.5 3 3.5 4 4.5 5 5.5 –10 2 2.5 3 VIN (V) 3.5 4 4.5 5 5.5 0 25 50 75 100 125 TEMPERATURE (°C) VIN (V) 3417A-1 G16 –15 –50 –25 3417A-1 G17 3417A-1 G18 PIN FUNCTIONS (DFN/TSSOP) RUN1 (Pin 1/Pin 2): Enable for 1.5A Regulator. When at Logic 1, 1.5A regulator is running. When at 0V, 1.5A regulator is off. When both RUN1 and RUN2 are at 0V, the part is in shutdown. VIN1 (Pin 2/Pin 3): Supply Pin for P-Channel Switch of 1.5A Regulator. ITH1 (Pin 3/Pin 4): Error Amplifier Compensation Point for 1.5A Regulator. The current comparator threshold increases with this control voltage. Nominal voltage range for this pin is 0V to 1.5V. VFB1 (Pin 4/Pin 5): Receives the feedback voltage from external resistive divider across the 1.5A regulator output. Nominal voltage for this pin is 0.8V. SYNC/MODE (Pin 9/Pin 12): Combination Mode Selection and Oscillator Synchronization Pin. This pin controls the operation of the device. When the voltage on the SYNC/MODE pin is >(VIN – 0.5V), Burst Mode operation is selected. When the voltage on the SYNC/MODE pin is <0.5V, pulse skipping mode is selected. When the SYNC/MODE pin is held at VIN/2, forced continuous mode is selected. The oscillation frequency can be synchronized to an external oscillator applied to this pin. When synchronized to an external clock, pulse skip mode is selected. SW2 (Pin 10/Pin 13): Switch Node Connection to the Inductor for the 1A Regulator. This pin swings from VIN2 to PGND2. ITH2 (Pin 6/Pin 7): Error Amplifier Compensation Point for 1A regulator. The current comparator threshold increases with this control voltage. Nominal voltage range for this pin is 0V to 1.5V. POR (Pin 11/Pin 14): The Power-On-Reset Pin. This open drain-logic output is pulled to GND when the output voltage of either regulator falls 8% below regulation and goes high approximately 150ms after both regulators are above –6% of regulation. If either RUN1 or RUN2 is low (the respective regulator is in sleep mode and therefore the output voltage is low), then POR reflects the regulation of the running regulator. RUN2 (Pin 7/Pin 8): Enable for 1A Regulator. When at Logic 1, 1A regulator is running. When at 0V, 1A regulator is off. When both RUN1 and RUN2 are at 0V, the part is in shutdown. FREQ (Pin 12/Pin 15): Frequency Set Pin. When FREQ is at VIN, internal oscillator runs at 1.5MHz. When a resistor is connected from this pin to ground, the internal oscillator frequency can be varied from 0.6MHz to 4MHz. VIN2 (Pin 8/Pin 9): Supply Pin for P-Channel Switch of 1A Regulator and Supply for Analog Circuitry. GNDA (Pin 13/Pin 16): Analog Ground Pin for Internal Analog Circuitry. VFB2 (Pin 5/Pin 6): Receives the feedback voltage from external resistive divider across the 1A regulator output. Nominal voltage for this pin is 0.8V. 3417a1fa 6 LTC3417A-1 PIN FUNCTIONS PHASE (Pin 14/Pin 17): Selects 1A regulator switching phase with respect to 1.5A regulator switching. Set to VIN, the 1.5A regulator and the 1A regulator are in phase. When PHASE is at 0V, the 1.5A regulator and the 1A regulator are switching 180 degrees out-of-phase. Do not float this pin. SW1 (Pin 15/Pin 18): Switch Node Connection to the Inductor for the 1.5A Regulator. This pin swings from VIN1 to PGND1. PGND1 (Pin 16/Pin 19): Ground for SW1 N-Channel Driver. PGND2, GNDD (Pins 1,10,11,20): TSSOP Package Only. Ground for SW2 N-channel driver and digital ground for circuit. Exposed Pad (Pin 17/Pin 21): PGND2, GNDD. Ground for SW2 N-channel driver and digital ground for circuit. The Exposed Pad must be soldered to PCB ground. FUNCTIONAL DIAGRAM 1.5A REGULATOR VFB1 ITH1 + – – VIN1 ITH LIMIT + + – VB 0.752V SLOPE COMPENSATION + ANTI-SHOOTTHROUGH – SW1 + + LOGIC 0.848V – – – PGND1 + RUN1 POR VOLTAGE REFERENCE VIN2 DELAY RUN2 PHASE SYNC/MODE OSCILLATOR FREQ PGND2 + – – LOGIC + – 0.848V + – SW2 ANTI-SHOOTTHROUGH SLOPE COMPENSATION – + VB – + 1A REGULATOR + VFB2 + – 0.752V ITH2 ITH LIMIT VIN2 3417A-1 BD 3417a1fa 7 LTC3417A-1 OPERATION The LTC3417A-1 uses a constant frequency, current mode architecture. Both channels share the same clock frequency. The PHASE pin sets whether the channels are running in-phase or out of phase. The operating frequency is determined by connecting the FREQ pin to VIN for 1.5MHz operation or by connecting a resistor from FREQ to ground for a frequency from 0.6MHz to 4MHz. To suit a variety of applications, the SYNC/MODE pin allows the user to trade off noise for efficiency. The output voltages are set by external dividers returned to the VFB1 and VFB2 pins. An error amplifier compares the divided output voltage with a reference voltage of 0.8V and adjusts the peak inductor current accordingly. Undervoltage comparators will pull the POR output low when either output voltage is 8% below its targeted value. The POR output will go high after 212,992 cycles (when FREQ is high) or 294,912 cycles (when FREQ is tied to ground through an external resistor), or about 150ms, after both regulators are above -6% of the target output voltage. Main Control Loop For each regulator, during normal operation, the P-channel MOSFET power switch is turned on at the beginning of a clock cycle when the VFB voltage is below the reference voltage. The current into the inductor and the load increases until the current limit is reached. The switch turns off and energy stored in the inductor flows through the bottom N-channel MOSFET switch into the load until the next clock cycle. The peak inductor current is controlled by the voltage on the ITH pin, which is the output of the error amplifier. This amplifier compares the VFB pin to the 0.8V reference. When the load current increases the VFB voltage decreases slightly below the reference. This decrease causes the error amplifier to increase the ITH voltage until the average inductor current matches the new load current. Low Current Operation Three modes are available to control the operation of the LTC3417A-1 at low currents. Each of the three modes automatically switch from continuous operation to the selected mode when the load current is low. To optimize efficiency, Burst Mode operation can be selected. When the load is relatively light, the LTC3417A-1 automatically switches into Burst Mode operation in which the PMOS switches operate intermittently based on load demand. By running cycles periodically, the switching losses, which are dominated by the gate charge losses of the power MOSFETs, are minimized. The main control loop is interrupted when the output voltage reaches the desired regulated value. The hysteresis voltage comparator trips when ITH is below 0.24V, shutting off the switch and reducing the power. The output capacitor and the inductor supply the power to the load until ITH exceeds 0.31V, turning on the switch and the main control loop which starts another cycle. For lower output voltage ripple at low currents, pulse skipping mode can be used. In this mode, the LTC3417A-1 continues to switch at constant frequency down to very low currents, where it will begin skipping pulses used to control the power MOSFETs. Finally, in forced continuous mode, the inductor current is constantly cycled creating a fixed output voltage ripple at all output current levels. This feature is desirable in telecommunications since the noise is a constant frequency and is thus easy to filter out. Another advantage of this mode is that the regulator is capable of both sourcing current into a load and sinking some current from the output. The mode selection for the LTC3417A-1 is set using the SYNC/MODE pin. The SYNC/MODE pin sets the mode for both the1A and the 1.5A step-down DC/DC converters. The main control loop is shut down by pulling the RUN pin to ground. A digital soft-start is enabled after shutdown, which will slowly ramp the peak inductor current up over 1024 clock cycles. 3417a1fa 8 LTC3417A-1 OPERATION Dropout Operation Low Supply Operation When the input supply voltage decreases toward the output voltage, the duty cycle increases to 100%. In this dropout condition, the PMOS switch is turned on continuously with the output voltage being equal to the input voltage minus the voltage drops across the internal P-channel MOSFET and inductor. The LTC3417A-1 incorporates an undervoltage lockout circuit which shuts down the part when the input voltage drops below about 2.07V to prevent unstable operation. APPLICATIONS INFORMATION 140 120 100 RT (kΩ) A general LTC3417A-1 application circuit is shown in Figure 4. External component selection is driven by the load requirement, and begins with the selection of the inductors L1 and L2. Once L1 and L2 are chosen, CIN, COUT1 and COUT2 can be selected. 160 80 60 Operating Frequency 40 Selection of the operating frequency is a tradeoff between efficiency and component size. High frequency operation allows the use of smaller inductor and capacitor values. Operation at lower frequencies improves efficiency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. 20 The operating frequency, fO, of the LTC3417A-1 is determined by pulling the FREQ pin to VIN for 1.5MHz operation or by connecting an external resistor from FREQ to ground. The value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator and can be calculated by using the following equation: RT ≈ 1.61• 10 fO 11 (Ω) – 16.586kΩ for 0.6MHz ≤ fO ≤ 4MHz. Alternatively, use Figure 1 to select the value for RT. The maximum operating frequency is also constrained by the minimum on-time and duty cycle. This can be calculated as: 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 FREQUENCY (MHz) 3417A-1 F01 Figure 1. Frequency vs RT V fO(MAX) 6.67 OUT (MHz ) VIN(MAX) The minimum frequency is limited by leakage and noise coupling due to the large resistance of RT. Inductor Selection Although the inductor does not influence the operating frequency, the inductor value has a direct effect on ripple current. The inductor ripple current, ΔIL, decreases with higher inductance and increases with higher VIN or VOUT. IL = VOUT VOUT 1– fO • L VIN Accepting larger values of ΔIL allows the use of low inductances, but results in higher output voltage ripple, greater core losses and lower output current capability. 3417a1fa 9 LTC3417A-1 APPLICATIONS INFORMATION A reasonable starting point for setting ripple current is ΔIL = 0.35ILOAD(MAX), where ILOAD(MAX) is the maximum current output. The largest ripple, ΔIL, occurs at the maximum input voltage. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation: L= VOUT VOUT 1– fO • IL VIN(MAX) The inductor value will also have an effect on Burst Mode operation. The transition from low current operation begins when the peak inductor current falls below a level set by the burst clamp. Lower inductor values result in higher ripple current which causes this to occur at lower load currents. This causes a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductor values will cause the burst frequency to increase. Inductor Core Selection typical surface mount inductors that work well in LTC3417A-1 applications. Input Capacitor (CIN) Selection In continuous mode, the input current of the converter can be approximated by the sum of two square waves with duty cycles of approximately VOUT1/VIN and VOUT2/VIN. To prevent large voltage transients, a low equivalent series resistance (ESR) input capacitor sized for the maximum RMS current must be used. Some capacitors have a de-rating spec for maximum RMS current. If the capacitor being used has this requirement, it is necessary to calculate the maximum RMS current. The RMS current calculation is different if the part is used in “in phase” or “out of phase”. For “in phase”, there are two different equations: VOUT1 > VOUT2: IRMS = 2 •I1 •I2 • D2(1– D1) +I2 2 (D2 – D22 ) +I12 (D1– D12 ) Different core materials and shapes will change the size/ current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don’t radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. The choice of which style inductor to use often depends more on the price vs size requirements of any radiated field/EMI requirements than on what the LTC3417A-1 requires to operate. Table 1 shows some VOUT2 > VOUT1: IRMS = 2 •I1 •I2 • D1(1– D2) +I2 2 (D2 – D22 ) +I12 (D1– D12 ) where: D1= VOUT1 V and D2 = OUT2 VIN VIN Table 1 MANUFACTURER PART NUMBER VALUE (μH) MAX DC CURRENT (A) DCR DIMENSIONS L × W × H (mm) 1.5 1.5 2.8 2.9 0.014 0.018 6 × 6 × 2.5 6×6×2 L1 on OT1 Toko A920CY-1R5M-D62CB A918CY-1R5M-D62LCB Coilcraft D01608C-152ML 1.5 2.6 0.06 6.6 × 4.5 × 2.9 Sumida CDRH4D22/HP 1R5 1.5 3.9 0.031 5 × 5 × 2.4 Midcom DUP-1813-1R4R 1.4 5.5 0.033 4.3 × 4.8 × 3.5 A915AY-2ROM-D53LC 2.0 3.9 0.027 5×5×3 L2 on OUT2 Toko Coilcraft D01608C-222ML 2.2 2.3 0.07 6.6 × 4.5 × 2.9 Sumida CDRH3D16/HP 2R2 2.2 2.2 1.75 1.6 0.047 0.035 4 × 4 × 1.8 3.2 × 3.2 × 2 Midcom DUP-1813-2R2R 2.2 3.9 0.047 4.3 × 4.8 × 3.5 3417a1fa 10 LTC3417A-1 APPLICATIONS INFORMATION When D1 = D2 then the equation simplifies to: IRMS = (I1 +I2 ) D (1– D) or IRMS = (I1 +I2 ) VOUT ( VIN – VOUT ) VIN where the maximum average output currents I1 and I2 equal the respective peak currents minus half the peakto-peak ripple currents: ΔIL1 2 ΔI I2 =ILIM2 – L2 2 I1 =ILIM1 – These formula have a maximum at VIN = 2VOUT, where IRMS = (I1 + I2)/2. This simple worst case is commonly used to determine the highest IRMS. For “out of phase” operation, the ripple current can be lower than the “in phase” current. In the “out of phase” case, the maximum IRMS does not occur when VOUT1 = VOUT2. The maximum typically occurs when VOUT1 – VIN/2 = VOUT2 or when VOUT2 – VIN/2 = VOUT1. As a good rule of thumb, the amount of worst case ripple is about 75% of the worst case ripple in the “in phase” mode. Also note that when VOUT1 = VOUT2 = VIN/2 and I1 = I2, the ripple is zero. Note that capacitor manufacturer’s ripple current ratings are often based on only 2000 hours lifetime. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet the size or height requirements of the design. An additional 0.1μF to 1μF ceramic capacitor is also recommended on VIN for high frequency decoupling, when not using an all ceramic capacitor solution. Output Capacitor (COUT1 and COUT2) Selection The selection of COUT1 and COUT2 is driven by the required ESR to minimize voltage ripple and load step transients. Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple (ΔVOUT) is determined by: 1 VOUT IL ESRCOUT + 8 • fO • COUT where fO = operating frequency, COUT = output capacitance and ΔIL = ripple current in the inductor. The output ripple is highest at maximum input voltage, since ΔIL increases with input voltage. With ΔIL = 0.35ILOAD(MAX), the output ripple will be less than 100mV at maximum VIN and fO = 1MHz with: ESRCOUT < 150mΩ Once the ESR requirements for COUT have been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement, except for an all ceramic solution. In surface mount applications, multiple capacitors may have to be paralleled to meet the capacitance, ESR or RMS current handling requirement of the application. Aluminum electrolytic, special polymer, ceramic and dry tantalum capacitors are all available in surface mount packages. The OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest ESR(size) product of any aluminum electrolytic at a somewhat higher price. Special polymer capacitors, such as Sanyo POSCAP, offer very low ESR, but have a lower capacitance density than other types. Tantalum capacitors have the highest capacitance density, but it has a larger ESR and it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface tantalums, available in case heights ranging from 2mm to 4mm. Aluminum electrolytic capacitors have a significantly larger ESR, and are often used in extremely cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have the lowest ESR and cost but also have the lowest capacitance density, high voltage and temperature coefficient and exhibit audible piezoelectric effects. In addition, the high Q of ceramic capacitors along with trace inductance can lead to significant ringing. Other capacitor types include the Panasonic specialty polymer (SP) capacitors. 3417a1fa 11 LTC3417A-1 APPLICATIONS INFORMATION In most cases, 0.1μF to 1μF of ceramic capacitors should also be placed close to the LTC3417A-1 in parallel with the main capacitors for high frequency decoupling. Ceramic Input and Output Capacitors Higher value, lower cost ceramic capacitors are now becoming available in smaller case sizes. Because the LTC3417 control loop does not depend on the output capacitor’s ESR for stable operation, ceramic capacitors can be used freely to achieve very low output ripple and small circuit size. When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. Great care must be taken when using only ceramic input and output capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the VIN pin. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, the ringing at the input can be large enough to damage the part. Since the ESR of a ceramic capacitor is so low, the input and output capacitor must fulfill a charge storage requirement. During a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. The time required for the feedback loop to respond is dependent on the compensation components and the output capacitor size. Typically, 3 to 4 cycles are required to respond to a load step, but only in the first cycle does the output drop linearly. The output droop, VDROOP , is usually about 2 to 3 times the linear droop of the first cycle. Thus, a good place to start is with the output capacitor size of approximately: COUT ≈ 2.5 ΔIOUT fO • VDROOP More capacitance may be required depending on the duty cycle and load step requirements. In most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is very low. A 10μF ceramic capacitor is usually enough for these conditions. Setting the Output Voltage The LTC3417A-1 develops a 0.8V reference voltage between the feedback pins, VFB1 and VFB2, and the signal ground as shown in Figure 4. The output voltages are set by two resistive dividers according to the following formulas: R1 VOUT1 0.8V 1+ R2 R3 VOUT2 0.8V 1+ R4 Keeping the current small (<5μA) in these resistors maximizes efficiency, but making the current too small may allow stray capacitance to cause noise problems and reduce the phase margin of the error amp loop. To improve the frequency response, a feed-forward capacitor, CF, may also be used. Great care should be taken to route the VFB node away from noise sources, such as the inductor or the SW line. Power-On Reset The POR pin is an open-drain output which pulls low when either regulator is out of regulation. When both output voltages are above –6% of regulation, a timer is started which allows the POR output to go high after 212,992 clock cycles (when FREQ is tied to VIN) or 294,912 clock cycles (when FREQ is tied to ground through an external resistor). This results in a delay of approximately 150ms when the oscillator is set to 2MHz. When either channel is shut down, the POR output reflects the condition of the running regulator. 3417a1fa 12 LTC3417A-1 APPLICATIONS INFORMATION The LTC3417A-1 can be synchronized to an external clock signal by the SYNC/MODE pin. The internal oscillator frequency should be set to 20% lower than the external clock frequency to ensure adequate slope compensation, since slope compensation is derived from the internal oscillator. During synchronization, the mode is set to pulse skipping and the top switch turn-on is synchronized to the rising edge of the external clock. VRUN 2V/DIV VOUT 1V/DIV IL 1A/DIV VIN = 3.6V VOUT = 1.8V RL = 0.9Ω 200μs/DIV 3417A-1 F02 Figure 2. Digital Soft-Start OUT1 Soft-Start Soft-start reduces surge currents from VIN by gradually increasing the peak inductor current. Power supply sequencing can also be accomplished by controlling the ITH pin. The LTC3417A-1 has an internal digital soft-start for each regulator output, which steps up a clamp on ITH over 1024 clock cycles, as can be seen in Figures 2 and 3. As the voltage on ITH ramps through its operating range, the internal peak current limit is also ramped at a proportional linear rate. Mode Selection The SYNC/MODE pin is a multipurpose pin which provides mode selection and frequency synchronization. Connecting this pin to VIN enables Burst Mode operation for both regulators, which provides the best low current efficiency at the cost of a higher output voltage ripple. When SYNC/ MODE is connected to ground, pulse skipping operation is selected for both regulators, which provides the lowest output voltage and current ripple at the cost of low current efficiency. Applying a voltage that is more than 1V from either supply results in forced continuous mode for both regulators, which creates a fixed output ripple and allows the sinking of some current (about 1/2ΔIL). Since the switching noise is constant in this mode, it is also the easiest to filter out. In many cases, the output voltage can be simply connected to the SYNC/MODE pin, selecting the forced continuous mode except at start-up. When using an external clock, with the PHASE pin low, the switching of the two channels occur at the edges of the external clock. A 50% duty cycle will therefore produce 180° out-of-phase operation. Checking Transient Response The ITH pin compensation allows the transient response to be optimized for a wide range of loads and output capacitors. The availability of the ITH pin not only allows optimization of the control loop behavior, but also provides a DC coupled and AC filited closed-loop response test point. The DC step, rise time, and settling at this test point truly reflects the closed-loop response. Assuming a predominantly second order system, phase margin and/or or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated using the percentage of overshoot seen at this pin or by examining the rise time at this pin. VRUN 2V/DIV VOUT 1V/DIV IL 0.5A/DIV VIN = 3.6V VOUT = 2.5V RL = 2Ω 200μs/DIV 3417A-1 F03 Figure 3. Digital Soft-Start OUT2 3417a1fa 13 LTC3417A-1 APPLICATIONS INFORMATION The ITH external components shown in the Figure 4 circuit will provide an adequate starting point for most applications. The series RC filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be selected because of various types and values determine the loop feedback factor gain and phase. An output current pulse of 20% to 100% of full load current having a rise time of 1μs to 10μs will produce output voltage and ITH pin waveforms that will give a sense of overall loop stability without breaking the feedback loop. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ΔILOAD • ESRCOUT, where ESRCOUT is the effective series resistance of COUT. ΔILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. The initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order overshoot/DC ratio cannot be used to determine phase margin. The gain of the loop increases with RITH and the bandwidth of the loop increases with decreasing CITH. If RITH is increased by the same factor that CITH is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. In addition, feedforward capacitors, C1 and C2, can be added to improve the high frequency response, as shown in Figure 4. Capacitor C1 provides phase lead by creating a high frequency zero with R1 which improves the phase margin for the 1.5A SW1 channel. Capacitor C2 provides phase lead by creating a high frequency zero with R3 which improves the phase margin for the 1A SW2 channel. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. For a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to Linear Technology Application Note 76. Although a buck regulator is capable of providing the full output current in dropout, it should be noted that as the input voltage VIN drops toward VOUT, the load step capability does decrease due to the decreasing voltage across the inductor. Applications that require large load step capability near dropout should use a different topology such as SEPIC, Zeta, or single inductor, positive buck boost. In some applications, a more severe transient can be caused by switching in loads with large (>1μF) input capacitors. The discharged input capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem, if the switch connecting the load has low resistance and is driven quickly. The solution is to limit the turn-on speed of the load switch driver. A Hot Swap™ controller is designed specifically for this purpose and usually incorporates current limiting, short-circuit protection, and soft- starting. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: % Efficiency = 100% – (P1+ P2 + P3 +…) where P1, P2, etc. are the individual losses as a percentage of input power. Hot Swap is a trademark of Linear Technology Corporation. 3417a1fa 14 LTC3417A-1 APPLICATIONS INFORMATION Although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in LTC3417A-1 circuits: 1) LTC3417A-1 IS current, 2) switching losses, 3) I2R losses, 4) other losses. 1) The IS current is the DC supply current given in the electrical characteristics which excludes MOSFET driver and control currents. IS current results in a small (< 0.1%) loss that increases with VIN, even at no load. 2) The switching current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge moves from VIN to ground. The resulting charge over the switching period is a current out of VIN that is typically much larger than the DC bias current. The gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages. 3) I2R losses are calculated from the DC resistances of the internal switches, RSW, and the external inductor, RL. In continuous mode, the average output current flowing through inductor L is “chopped” between the internal top and bottom switches. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses: I2R losses = IOUT2(RSW + RL) where RL is the resistance of the inductor. 4) Other “hidden” losses such as copper trace and internal battery resistances can account for additional efficiency degradations in portable systems. It is very important to include these “system” level losses in the design of a system. The internal battery and fuse resistance losses can be minimized by making sure that CIN has adequate charge storage and very low ESRCOUT at the switching frequency. Other losses including diode conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. Thermal Considerations The LTC3417A-1 requires the package Exposed Pad (PGND2/GNDD pin) to be well soldered to the PC board. This gives the DFN and TSSOP packages exceptional thermal properties, compared to similar packages of this size, making it difficult in normal operation to exceed the maximum junction temperature of the part. In a majority of applications, the LTC3417A-1 does not dissipate much heat due to its high efficiency. However, in applications where the LTC3417A-1 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150°C, both switches in both regulators will be turned off and the SW nodes will become high impedance. To prevent the LTC3417A-1 from exceeding its maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: TRISE = PD • θJA where PD is the power dissipated by the regulator and θJA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: TJ = TRISE + TAMBIENT As an example, consider the case when the LTC3417A-1 is in dropout in both regulators at an input voltage of 3.3V with load currents of 1.5A and 1A. From the Typical Performance Characteristics graph of Switch Resistance, the RDS(ON) resistance of the 1.5A P-channel switch is 0.09Ω and the RDS(ON) of the 1A P-channel switch is 0.163Ω. 3417a1fa 15 LTC3417A-1 APPLICATIONS INFORMATION The power dissipated by the part is: Using the 1.5MHz frequency setting (FREQ = VIN), we get the following equations for L1 and L2: PD = I12 • RDS(ON)1 + I22 • RDS(ON)2 PD = 1.52 • 0.09 + 12 • 0.163 1.8V 1.8V 1– = 1.3μH 1.5MHz • 525mA 4.2V Use 1.5μH. L1= PD = 366mW The DFN package junction-to-ambient thermal resistance, θJA, is about 43°C/W. Therefore, the junction temperature of the regulator operating in a 70°C ambient temperature is approximately: 2.5V 2.5V 1– = 1.9μH 1.5MHz • 350mA 4.2V Use 2.2μH. L2 = TJ = 0.366 • 43 + 70 TJ = 85.7°C Remembering that the above junction temperature is obtained from an RDS(ON) at 25°C, we might recalculate the junction temperature based on a higher RDS(ON) since it increases with temperature. However, we can safely assume that the actual junction temperature will not exceed the absolute maximum junction temperature of 125°C. Design Example As a design example, consider using the LTC3417A-1 in a portable application with a Li-Ion battery. The battery provides a VIN from 2.8V to 4.2V. One load requires 1.8V at 1.5A in active mode, and 1mA in standby mode. The other load requires 2.5V at 1A in active mode, and 500μA in standby mode. Since both loads still need power in standby, Burst Mode operation is selected for good low load efficiency (SYNC/MODE = VIN). First, determine what frequency should be used. Higher frequency results in a lower inductor value for a given ΔIL (ΔIL is estimated as 0.35ILOAD(MAX)). Reasonable values for wire wound surface mount inductors are usually in the range of 1μH to 10μH. CONVERTER OUTPUT ILOAD(MAX) ΔIL SW1 1.5A 525mA SW2 1A 350mA COUT selection is based on load step droop instead of ESR requirements. For a 2.5% output droop: COUT1 = 2.5 • 1.5A = 28μF 1.5MHz ( 5% • 1.8V ) COUT2 = 2.5 • 1A = 13μF 1.5MHz ( 5% • 2.5V ) The closest standard values are 47μF and 22μF. The output voltages can now be programmed by choosing the values of R1, R2, R3, and R4. To maintain high efficiency, the current in these resistors should be kept small. Choosing 2μA with the 0.8V feedback voltages makes R2 and R4 equal to 400k. A close standard 1% resistor is 412k. This then makes R1 = 515k. A close standard 1% is 511k. Similarily, with R4 at 412k, R3 is equal to 875k. A close 1% resistor is 866k. The compensation should be optimized for these components by examining the load step response, but a good place to start for the LTC3417A-1 is with a 5.9kΩ and 2200pF filter on ITH1 and 2.87k and 6800pF on ITH2. The output capacitor may need to be increased depending on the actual undershoot during a load step. The POR pin is an open drain output and requires a pullup resistor. A 100k resistor is used for adequate speed. Figure 4 shows a complete schematic for this design. 3417a1fa 16 LTC3417A-1 APPLICATIONS INFORMATION VIN 2.25V TO 5.5V CIN 10μF CIN2 0.1μF CIN1 0.1μF R7 100k VIN1 VIN2 VOUT1 1.8V 1.5A C1 22pF L1 1.5μH VIN SYNC/MODE POR SW1 SW2 RUN1 RUN2 RESET L2 2.2μH VIN C2 22pF LTC3417A-1 R1 511k VFB1 COUT1 47μF R2 412k R3 866k VFB2 PHASE FREQ COUT2 22μF R4 412k VIN ITH1 R5 5.9k ITH2 EXPOSED GNDA PAD GNDD VOUT2 2.5V 1A R6 2.87k C3 2200pF C4 6800pF 3417A-1 F04 L2: MIDCOM DUS-5121-2R2R COUT2, CIN: KEMET C1206C106K4PAC L1: MIDCOM DUS-5121-1R5R COUT1: KEMET C1210C226K8PAC OUT1 Efficiency vs Load Current 10 100 90 1 EFFICIENCY 0.1 85 POWER LOSS 80 POWER LOSS (W) EFFICIENCY (%) VIN = 3.6V VOUT = 1.8V 95 FREQ = 1MHz REFER TO FIGURE 4 0.01 75 70 0.001 0.01 0.1 1 LOAD CURRENT (A) 0.001 10 3417A-1 F04a Figure 4. 1.8V at 1.5A/2.5V at 1A Step-Down Regulators 3417a1fa 17 LTC3417A-1 APPLICATIONS INFORMATION Board Layout Considerations When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3417A-1. These items are also illustrated graphically in the layout diagram of Figure 5. Check the following in your layout. 1. Does the capacitor CIN connect to the power VIN1 (Pin 2), VIN2 (Pin 8), and PGND2/GNDD (Pin 17) as close as possible (DFN package)? It may be necessary to split CIN into two capacitors. This capacitor provides the AC current to the internal power MOSFETs and their drivers. 2. Are the COUT1, L1 and COUT2, L2 closely connected? The (–) plate of COUT1 returns current to PGND1, and the (–) plate of COUT2 returns current to the PGND2/GNDD and the (–) plate of CIN. 3. The resistor divider, R1 and R2, must be connected between the (+) plate of COUT1 and a ground line terminated near GNDA. The resistor divider, R3 and R4, must be connected between the (+) plate of COUT2 and a ground line terminated near GNDA. The feedback signals VFB1 and VFB2 should be routed away from noise components and traces, such as the SW lines, and its trace should be minimized. 4. Keep sensitive components away from the SW pins. The input capacitor CIN, the compensation capacitors CC1, CC2, CITH1 and CITH2 and all resistors R1, R2, R3, R4, RITH1 and RITH2 should be routed away from the SW traces and the inductors L1 and L2. 5. A ground plane is preferred, but if not available, keep the signal and power grounds segregated with small signal components returning to the GNDA pin at one point which is then connected to the PGND2/GNDD pin. 6. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. These copper areas should be connected to one of the input supplies. VIN CIN2 0.1μF CIN 10μF VIN2 VIN1 PGND2/ EXPOSED PAD PGND1 GNDA COUT2 COUT1 L2 VOUT2 L1 SW1 SW2 CC2 R3 VFB2 LTC3417A-1 RITH2 CITH2 R8 VOUT1 CC1 R1 VFB1 R4 STAR TO GNDA VIN CIN1 0.1μF R2 ITH2 ITH1 POR FREQ RUN2 PHASE RITH1 R7 STAR TO GNDA CITH1 VIN RUN1 SYNC/MODE GNDD 3417A-1 F05 Figure 5. Layout Guideline 3417a1fa 18 LTC3417A-1 PACKAGE DESCRIPTION DHC Package 16-Lead Plastic DFN (5mm × 3mm) (Reference LTC DWG # 05-08-1706) R = 0.115 TYP 5.00 ± 0.10 (2 SIDES) R = 0.20 TYP 0.65 ± 0.05 3.50 ± 0.05 1.65 ± 0.05 2.20 ± 0.05 (2 SIDES) 9 3.00 ± 0.10 (2 SIDES) PACKAGE OUTLINE 1.65 ± 0.10 (2 SIDES) PIN 1 NOTCH PIN 1 TOP MARK (SEE NOTE 6) (DHC16) DFN 1103 8 1 0.25 ± 0.05 0.50 BSC 0.75 ± 0.05 0.200 REF 0.25 ± 0.05 0.50 BSC 0.40 ± 0.10 16 4.40 ± 0.05 (2 SIDES) 4.40 ± 0.10 (2 SIDES) 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE FE Package 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663) Exposed Pad Variation CA 6.40 – 6.60* (.252 – .260) 4.95 (.195) 4.95 (.195) 20 1918 17 16 15 14 13 12 11 6.60 ± 0.10 2.74 (.108) 4.50 ± 0.10 6.40 2.74 (.252) (.108) BSC SEE NOTE 4 0.45 ± 0.05 1.05 ± 0.10 0.65 BSC 1 2 3 4 5 6 7 8 9 10 RECOMMENDED SOLDER PAD LAYOUT 4.30 – 4.50* (.169 – .177) 0.09 – 0.20 (.0035 – .0079) 0.25 REF 0.50 – 0.75 (.020 – .030) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE 1.20 (.047) MAX 0° – 8° 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) TYP 0.05 – 0.15 (.002 – .006) FE20 (CA) TSSOP 0204 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 3417a1fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC3417A-1 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3406A/B 600mA, 1.5MHz, Synchronous Step-Down DC/DC Converter 96% Efficiency, VIN(MIN): 2.5V, VIN(MAX): 5.5V, VOUT(MIN) = 0.6V, IQ = 20μA, ISD < 1μA, ThinSOT™ Package LTC3407A Dual 600mA/600mA 1.5MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN(MIN): 2.5V, VIN(MAX): 5.5V, VOUT(MIN) = 0.6V, IQ = 40μA, ISD < 1μA, MS10E, 3mm × 3mm DFN-10 Package LTC3409 600mA, 1.7/2.6MHz, Synchronous Step-Down DC/DC Converter 96% Efficiency, VIN(MIN): 1.6V, VIN(MAX): 5.5V, VOUT(MIN) = 0.6V, IQ = 65μA, ISD < 1μA, 3mm × 3mm DFN-8 Package LTC3410/B 300mA, 2.25MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN(MIN): 2.5V, VIN(MAX): 5.5V, VOUT(MIN) = 0.8V, IQ = 26μA, ISD < 1μA, SC70 Package LTC3411A 1.25A, 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN(MIN): 2.5V, VIN(MAX): 5.5V, VOUT(MIN) = 0.8V, IQ = 60μA, ISD < 1μA, MS10, 3mm × 3mm DFN-10 Package LTC3412A 2.5A, 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN(MIN): 2.5V, VIN(MAX): 5.5V, VOUT(MIN) = 0.8V, IQ = 60μA, ISD < 1μA, 4mm × 4mm QFN-16, TSSOP-16E Package LTC3414 4A, 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN(MIN): 2.25V, VIN(MAX): 5.5V, VOUT(MIN) = 0.8V, IQ = 64μA, ISD < 1μA, TSSOP-20E Package LTC3416 4A, 4MHz, Synchronous Step-Down DC/DC Converter with Tracking 95% Efficiency, VIN(MIN): 2.25V, VIN(MAX): 5.5V, VOUT(MIN) = 0.8V, IQ = 64μA, ISD < 1μA, TSSOP-20E Package LTC3417 Dual 1.4A/800mA, 4MHz Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 125μA, ISD < 1μA, 3mm × 5mm DFN-16, TSSOP-20E Packages LTC3417A Dual 1.5A/1A, 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN(MIN): 2.3V, VIN(MAX): 5.5V, VOUT(MIN) = 0.8V, IQ = 125μA, ISD < 1μA, TSSOP-16E, 3mm × 3mm DFN-16 Package LTC3417A-2 Dual 1.5A/1A (IOUT) 4MHz Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.25V to 5V, VOUT(MIN) = 0.8V, IQ = 125μA, ISD < 1μA, 3mm × 5mm DFN-16, TSSOP-20E Packages LTC3418 8A, 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN(MIN): 2.25V, VIN(MAX): 5.5V, VOUT(MIN) = 0.8V, IQ = 380μA, ISD < 1μA, 5mm × 7mm QFN-38 Package LTC3419/-1 Dual 600mA/600mA 2.25MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN(MIN): 2.5V, VIN(MAX): 5.5V, VOUT(MIN) = 0.6V, IQ = 35μA, ISD < 1μA, MS10, 3mm × 3mm DFN-10 Package LTC3438 800mA, 1MHz, Synchronous Buck-Boost DC/DC Converter 95% Efficiency, VIN(MIN): 2.4V, VIN(MAX): 5.5V, VOUT(MIN) = 1.5V to 5.25V, IQ = 35μA, ISD < 1μA, 2mm × 3mm DFN-8 Package LTC3440 600mA, 2MHz, Synchronous Buck-Boost DC/DC Converter 95% Efficiency, VIN(MIN): 2.5V, VIN(MAX): 5.5V, VOUT(MIN) = 2.5V to 5.5V, IQ = 25μA, ISD < 1μA, MS10, 3mm × 3mm DFN-10 Package LTC3441/2/3 1.2A, 2MHz, Synchronous Buck-Boost DC/DC Converter 95% Efficiency, VIN(MIN): 2.4V, VIN(MAX): 5.5V, VOUT(MIN) = 2.4V to 5.25V, IQ = 50μA, ISD < 1μA, 3mm × 4mm DFN-12 Package LTC3530 600mA, 2MHz, Synchronous Buck-Boost DC/DC Converter 95% Efficiency, VIN(MIN): 1.8V, VIN(MAX): 5.5V, VOUT(MIN) = 1.8V to 5.5V, IQ = 40μA, ISD < 1μA, MS10, 3mm × 3mm DFN-10 Package LTC3531/-3/3.3 200mA, 1.5MHz, Synchronous Buck-Boost DC/DC Converter 95% Efficiency, VIN(MIN): 1.8V, VIN(MAX): 5.5V, VOUT(MIN) = 2V to 5V, IQ = 16μA, ISD < 1μA, ThinSOT, 3mm × 3mm DFN-6 Package LTC3542 500mA, 2.25MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN(MIN): 2.5V, VIN(MAX): 5.5V, VOUT(MIN) = 0.6V, IQ = 26μA, ISD < 1μA, 2mm × 2mm DFN-6, ThinSOT Package LTC3544/B Quad 100/200/200/300mA, 2.25MHz Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN(MIN): 2.3V, VIN(MAX): 5.5V, VOUT(MIN) = 0.8V, IQ = 70μA, ISD < 1μA, 3mm × 3mm QFN-16 Package LTC3545/-1 Triple, 800mA x 3, 2.25MHz Synchronous Step-Down DC/DC 95% Efficiency, VIN(MIN): 2.3V, VIN(MAX): 5.5V, VOUT(MIN) = 0.6V, IQ = 58μA, ISD < 1μA, 3mm × 3mm QFN-16 Package Converter LTC3547/B Dual 300mA, 2.25MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN(MIN): 2.5V, VIN(MAX): 5.5V, VOUT(MIN) = 0.6V, IQ = 40μA, ISD < 1μA, DFN-8 Package LTC3548/-1/-2 Dual 400mA & 800mA IOUT, 2.25MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN(MIN): 2.5V, VIN(MAX): 5.5V, VOUT(MIN) = 0.6V, IQ = 40μA, ISD < 1μA, MS10E, 3mm × 3mm DFN-10 Package LTC3560 800mA 2.25MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN(MIN): 2.5V, VIN(MAX): 5.5V, VOUT(MIN) = 0.6V, IQ = 16μA, ISD < 1μA, ThinSOT Package LTC3561 1.25A, 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN(MIN): 2.5V, VIN(MAX): 5.5V, VOUT(MIN) = 0.8V, IQ = 240μA, ISD < 1μA, 3mm × 3mm DFN-8 Package LTC3562 Quad, I2C Interface, 600/600/400/400mA , 2.25MHz Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN(MIN): 2.9V, VIN(MAX): 5.5V, VOUT(MIN) = 0.425V, IQ = 100μA, ISD < 1μA, 3mm × 3mm QFN-20 Package ThinSOT is a trademark of Linear Technology Corporation. 20 Linear Technology Corporation 3417a1fa LT 0808 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008