LINER LTC3548-2

LTC3548-2
Dual Synchronous,
Fixed/Adjustable Output, 2.25MHz
Step-Down DC/DC Regulator
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FEATURES
DESCRIPTIO
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The LTC®3548-2 is a dual, constant frequency, synchronous step down DC/DC converter. Intended for low power
applications, it operates from 2.5V to 5.5V input voltage
range and has a constant 2.25MHz switching frequency,
allowing the use of tiny, low cost capacitors and inductors
with a profile ≤1.2mm. For channel 1, the output voltage
is fixed at 1.8V/800mA; for channel 2, the output voltage
is adjustable from 0.6V to VIN. Internal synchronous
0.35Ω, 1.2A/0.7A power switches provide high efficiency
without the need for external Schottky diodes.
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High Efficiency: Up to 95%
1.8V/800mA Fixed Output and 400mA Adjustable
Output Voltage
Only 40µA Quiescent Current (Both Channels)
2.25MHz Constant Frequency Operation
High Switch Current Limits: 1.2A and 0.7A
No Schottky Diodes Required
Low RDS(ON) Internal Switches: 0.35Ω
Current Mode Operation for Excellent Line
and Load Transient Response
Short-Circuit Protected
Low Dropout Operation: 100% Duty Cycle
Ultralow Shutdown Current: IQ < 1µA
Power-On Reset Output
Externally Synchronizable Oscillator
Small Thermally Enhanced 3mm × 3mm DFN Package
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APPLICATIO S
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PDAs/Palmtop PCs
Digital Cameras
Cellular Phones
Portable Media Players
PC Cards
Wireless and DSL Modems
A user selectable mode input is provided to allow the user
to trade-off noise ripple for low power efficiency. Burst
Mode® operation provides high efficiency at light loads,
while Pulse Skip Mode provides low noise ripple at light
loads.
To further maximize battery run time, the P-channel
MOSFETs are turned on continuously in dropout (100%
duty cycle), and both channels draw a total quiescent
current of only 40µA. In shutdown, the device draws <1µA.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Burst Mode is a registered
trademark of Linear Technology Corporation. Protected by U.S. Patents including 5481178,
6580258, 6304066, 6127815, 6498466, 6611131.
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TYPICAL APPLICATIO
Efficiency and Power Loss
vs Load Current
VIN
2.8V TO 5.5V
100
RUN2
VIN
MODE/SYNC
RUN1
95
100k
POR
RESET
887k
SW1
SW2
68pF
4.7µF
2.2µH
GND
85
POWER LOSS
10
80
75
70
VOUT1
VFB2
280k
VOUT1
1.8V
800mA
10µF
35482 F01
Figure 1. 2.5V/1.8V at 400mA/800mA Step-Down Regulators
100
65
60
1
VIN = 3.6V
1
VOUT = 1.8V
Burst Mode OPERATION
CHANNEL 1
NO LOAD ON CHANNEL 2
0.1
10
100
1000
LOAD CURRENT (mA)
POWER LOSS (mW)
LTC3548-2
4.7µH
VOUT2
2.5V
400mA
EFFICIENCY
90
EFFICIENCY (%)
10µF
1000
35482 F01b
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LTC3548-2
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ABSOLUTE
AXI U RATI GS
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PACKAGE/ORDER I FOR ATIO
(Note 1)
VIN Voltages.................................................– 0.3V to 6V
VOUT1, VFB2 Voltages ...................... – 0.3V to VIN + 0.3V
RUN1, RUN2 Voltages ................................ – 0.3V to VIN
MODE/SYNC Voltage ...................... – 0.3V to VIN + 0.3V
SW1, SW2 Voltage ......................... – 0.3V to VIN + 0.3V
POR Voltage ................................................– 0.3V to 6V
Ambient Operating Temperature Range
(Note 2) .................................................. – 40°C to 85°C
Junction Temperature (Note 5) ............................. 125°C
Storage Temperature Range ................. – 65°C to 125°C
TOP VIEW
10 VFB2
VOUT1
1
RUN1
2
VIN
3
SW1
4
7 SW2
GND
5
6 MODE/
SYNC
9 RUN2
11
8 POR
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 40°C/W, θJC = 3°C/W (4-LAYER BOARD)
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB GND
ORDER PART NUMBER
DD PART MARKING
LTC3548EDD-2
LCDK
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, unless otherwise specified. (Note 2)
SYMBOL
PARAMETER
VIN
Operating Voltage Range
IFB2
Feedback Pin Input Current
VFB2
Feedback Voltage of Channel 2 (Note 3)
VOUT1
Output Voltage of Channel 1 (Note 3)
CONDITIONS
MIN
●
TYP
2.5
●
0°C ≤ TA ≤ 85°C
–40°C ≤ TA ≤ 85°C
0°C ≤ TA ≤ 85°C
–40°C ≤ TA ≤ 85°C
MAX
UNITS
5.5
V
30
nA
●
0.588
0.585
0.6
0.6
0.612
0.612
V
V
●
1.764
1.755
1.8
1.8
1.836
1.836
V
V
0.5
∆VLINE REG
Reference Voltage Line Regulation
VIN = 2.5V to 5.5V (Note 3)
0.3
∆VLOAD REG
Output Voltage Load Regulation
(Note 3)
0.5
IS
Input DC Supply Current (Note 4)
Active Mode
Sleep Mode
Shutdown
VOUT1 = 1.5V, VFB2 = 0.5V
VOUT1 = 1.9V, VFB2 = 0.63V, MODE/SYNC = 3.6V
RUN = 0V, VIN = 5.5V, MODE/SYNC = 0V
700
40
0.1
950
60
1
fOSC
Oscillator Frequency
VOUT1 = 1.8V, VFB2 = 0.6V
2.25
2.7
fSYNC
Synchronization Frequency
ILIM
Peak Switch Current Limit Channel 1
Peak Switch Current Limit Channel 2
VIN = 3V, Duty Cycle <35%
VIN = 3V, VFB2 = 0.5V, Duty Cycle <35%
RDS(ON)
Top Switch On-Resistance
Bottom Switch On-Resistance
ISW(LKG)
Switch Leakage Current
●
1.8
%
2.25
0.95
0.6
%/V
µA
µA
µA
MHz
MHz
1.2
0.7
1.6
0.9
A
A
(Note 6)
(Note 6)
0.35
0.30
0.45
0.45
Ω
Ω
VIN = 5V, VRUN = 0V, VFB2 = 0V, VOUT1 = 0V
0.01
1
µA
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LTC3548-2
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, unless otherwise specified. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
POR
Power-On Reset Threshold
VOUT1, VFB2 Ramping Down, MODE/SYNC = 0V
MIN
TYP
Power-On Reset On-Resistance
RUN Threshold
●
IRUN
RUN Leakage Current
●
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3548-2 is guaranteed to meet specified performance from
0°C to 85°C. Specifications over the – 40°C and 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
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Burst Mode Operation
VOUT
20mV/DIV
IL
500mA/DIV
VOUT
10mV/DIV
ILOAD
500mA/DIV
35482 G02
1µs/DIV
VIN = 3.6V
VOUT = 1.8V
ILOAD = 30mA
CHANNEL 1; CIRCUIT OF FIGURE 3
100
2.5
10
VIN = 3.6V
8
FREQUENCY DEVIATION (%)
2.4
FREQUENCY (MHz)
EFFICIENCY (%)
90
10mA
1mA
800mA
75
70
60
2
3
4
2.3
2.2
2.1
VOUT = 1.8V, CHANNEL 1
Burst Mode OPERATION
CIRCUIT OF FIGURE 3
35482 G03
Oscillator Frequency
vs Input Voltage
95
100mA
µA
VIN = 3.6V
20µs/DIV
VOUT = 1.8V
ILOAD = 80mA TO 800mA
CHANNEL 1; CIRCUIT OF FIGURE 3
Oscillator Frequency
vs Temperature
Efficiency vs Input Voltage
V
1
VOUT
200mV/DIV
IL
200mA/DIV
35482 G01
1.5
Load Step
SW
5V/DIV
IL
200mA/DIV
1
0.01
TA = 25°C unless otherwise specified.
Pulse Skipping Mode
SW
5V/DIV
65
0.3
Cycles
Note 3: The LTC3548-2 is tested in a proprietary test mode that connects
the output of the error amplifier with an outside servo loop.
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 5: TJ is calculated from the ambient TA and power dissipation PD
according to the following formula: TJ = TA + (PD • θJA).
Note 6: The DFN switch on-resistance is guaranteed by correlation to
wafer level measurements.
TYPICAL PERFOR A CE CHARACTERISTICS
80
Ω
200
262,144
VRUN
85
UNITS
%
100
Power-On Reset Delay
2µs/DIV
VIN = 3.6V
VOUT = 1.8V
ILOAD = 60mA
CHANNEL 1; CIRCUIT OF FIGURE 3
MAX
–8.5
6
4
2
0
–2
–4
–6
–8
5
6
INPUT VOLTAGE (V)
35482 G04
2.0
–50 –25
–10
50
25
75
0
TEMPERATURE (°C)
100
125
2
3
4
5
6
VIN (V)
35482 G05
35482 G06
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LTC3548-2
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TYPICAL PERFOR A CE CHARACTERISTICS
Reference Voltage
vs Temperature
TA = 25°C unless otherwise specified.
RDS(ON) vs Input Voltage
0.615
RDS(ON) vs Junction Temperature
500
VIN = 3.6V
550
VIN = 2.7V
500
450
VIN = 4.2V
450
0.600
0.595
400
MAIN
SWITCH
RDS(ON) (mΩ)
0.605
RDS(ON) (mΩ)
350
300
0.590
250
0.585
–50 –25
200
SYNCHRONOUS
SWITCH
100
1
125
3
2
4
VIN (V)
5
350
300
250
100
–50 –25
7
6
Line Regulation
Load Regulation
Efficiency vs Load Current
2.0
0.5
95
1.5
0.4
VOUT ERROR (%)
80
PULSE SKIP MODE
75
0.5
0
PULSE SKIP MODE
–0.5
–1.0
70
VIN = 3.6V, VOUT = 1.8V
NO LOAD ON OTHER CHANNEL
CHANNEL 1; CIRCUIT OF FIGURE 3
65
60
1
10
100
LOAD CURRENT (mA)
–2.0
1
1000
10
100
LOAD CURRENT (mA)
0.2
0.1
0
–0.1
–0.2
–0.3
VIN = 3.6V, VOUT = 1.8V
NO LOAD ON OTHER CHANNEL
CHANNEL 1; CIRCUIT OF FIGURE 3
–1.5
–0.4
–0.5
1000
2
Efficiency vs Load Current
95
95
95
90
90
VIN = 3.6V
EFFICIENCY (%)
EFFICIENCY (%)
VIN = 2.7V
VIN = 4.2V
80
75
70
VOUT2 = 1.5V
Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
CIRCUIT OF FIGURE 3
65
60
1
10
100
LOAD CURRENT (mA)
1000
35482 G13
100
VIN = 2.7V
VIN = 4.2V
85
80
75
70
VOUT2 = 2.5V
Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
CIRCUIT OF FIGURE 3
65
60
1
10
100
LOAD CURRENT (mA)
6
5
Efficiency vs Load Current
Efficiency vs Load Current
100
85
4
VIN (V)
35482 G12
100
90
3
35482 G11
35482 G10
VIN = 3.6V
VOUT = 1.8V
IOUT = 200mA
0.3
Burst Mode OPERATION
VOUT ERROR (%)
1.0
Burst Mode OPERATION
85
25 50 75 100 125 150
0
JUNCTION TEMPERATURE (°C)
3548 G09
100
90
MAIN SWITCH
SYNCHRONOUS SWITCH
35482 G08
35482 G07
EFFICIENCY (%)
400
150
50
25
75
0
TEMPERATURE (°C)
VIN = 3.6V
200
EFFICIENCY (%)
REFERENCE VOLTAGE (V)
0.610
1000
35482 G14
VIN = 5V
85
80
75
70
VOUT2 = 3.3 V
Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
CIRCUIT OF FIGURE 3
65
60
1
10
100
LOAD CURRENT (mA)
1000
35482 G15
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LTC3548-2
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PI FU CTIO S
VOUT1 (Pin 1): Output Voltage Feedback for Channel 1. An
internal resistive divider divides the output voltage down
for comparison to the internal reference voltage.
RUN1 (Pin 2): Regulator 1 Enable. Forcing this pin to VIN
enables regulator 1, while forcing it to GND causes regulator 1 to shut down. This pin must be driven; do not float.
VIN (Pin 3): Input Power Supply. Must be closely decoupled
to GND.
SW1 (Pin 4): Regulator 1 Switch Node Connection to the
Inductor. This pin swings from VIN to GND.
GND (Pin 5): Ground. Connect to the (–) terminal of COUT,
and (–) terminal of CIN.
MODE/SYNC (Pin 6): Combination Mode Selection and
Oscillator Synchronization. This pin controls the operation
of the device. When tied to VIN or GND, Burst Mode
operation or pulse skipping mode is selected, respectively. Do not float this pin. The oscillation frequency can
be synchronized to an external oscillator applied to this pin
and pulse skipping mode is automatically selected.
SW2 (Pin 7): Regulator 2 Switch Node Connection to the
Inductor. This pin swings from VIN to GND.
POR (Pin 8): Power-On Reset . This common-drain logic
output is pulled to GND when the output voltage falls
below –8.5% of regulation and goes high after 117ms
when both channels are within regulation.
RUN2 (Pin 9): Regulator 2 Enable. Forcing this pin to VIN
enables regulator 2, while forcing it to GND causes regulator 2 to shut down. This pin must be driven; do not float.
VFB2 (Pin 10): Output Feedback. Receives the feedback
voltage from the external resistive divider across the
output. Nominal voltage for this pin is 0.6V.
Exposed Pad (GND) (Pin 11): Ground. Connect to the
(–) terminal of COUT, and (–) terminal of CIN. Must be
connected to PCB ground for electrical contact and rated
thermal performance.
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LTC3548-2
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BLOCK DIAGRA
REGULATOR 1
MODE/SYNC
6
BURST
CLAMP
VIN
SLOPE
COMP
EA
VOUT1
ITH1
BURST
SLEEP
–
+
5Ω
ICOMP
+
0.35V
–
1
EN
–
+
0.6V
R1
VFB1
S
Q
RS
LATCH
R
Q
R2
0.55V
–
UVDET
SWITCHING
LOGIC
AND
BLANKING
CIRCUIT
UV
+
ANTI
SHOOTTHRU
4 SW1
+
OVDET
–
+
0.65V
OV
IRCMP
SHUTDOWN
–
11 GND
VIN
3 VIN
PGOOD1
RUN1
8 POR
2
0.6V REF
RUN2
POR
COUNTER
OSC
9
OSC
5 GND
PGOOD2
REGULATOR 2 (IDENTICAL TO REGULATOR 1)
0.6V
7 SW2
+
EA
ITH2
–
VFB2 10
0.55V
–
UVDET
UV
+
+
OVDET
0.65V
OV
–
35482 BD
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LTC3548-2
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OPERATIO
The LTC3548-2 uses a constant frequency, current mode
architecture. The operating frequency is set at 2.25MHz
and can be synchronized to an external oscillator. Both
channels share the same clock and run in-phase. To suit
a variety of applications, the selectable Mode pin allows
the user to choose between low noise and high efficiency.
The output voltage for channel 1 is set by an internal
divider returned to the VOUT1 pin. The output voltage for
channel 2 is set by an external divider returned to the VFB2
pin. An error amplfier compares the feedback output
voltage with a reference voltage of 0.6V and adjusts the
peak inductor current accordingly. An undervoltage comparator will pull the POR output low if the output voltage
is not above –8.5% of the reference voltage. The POR
output will go high after 262,144 clock cycles (about
117ms in pulse skip mode) of achieving regulation.
Main Control Loop
During normal operation, the top power switch (P-channel
MOSFET) is turned on at the beginning of a clock cycle
when the VFB voltage (see Block Diagram) is below the the
reference voltage. The current into the inductor and the
load increases until the current limit is reached. The switch
turns off and energy stored in the inductor flows through
the bottom switch (N-channel MOSFET) into the load until
the next clock cycle.
The peak inductor current is controlled by the internally
compensated ITH voltage, which is the output of the error
amplifier.This amplifier compares the VFB to the 0.6V
reference. When the load current increases, the VFB voltage decreases slightly below the reference. This
decrease causes the error amplifier to increase the ITH
voltage until the average inductor current matches the new
load current.
To optimize efficiency, the Burst Mode operation can be
selected. When the load is relatively light, the LTC3548-2
automatically switches into Burst Mode operation in which
the PMOS switch operates intermittently based on load
demand with a fixed peak inductor current. By running
cycles periodically, the switching losses which are dominated by the gate charge losses of the power MOSFETs are
minimized. The main control loop is interrupted when the
output voltage reaches the desired regulated value. A
voltage comparator trips when ITH is below 0.35V, shutting off the switch and reducing the power. The output
capacitor and the inductor supply the power to the load
until ITH exceeds 0.65V, turning on the switch and the main
control loop which starts another cycle.
For lower ripple noise at low currents, the pulse skipping
mode can be used. In this mode, the LTC3548-2 continues
to switch at a constant frequency down to very low
currents, where it will begin skipping pulses. The efficiency in pulse skip mode can be improved slightly by
connecting the SW node to the MODE/SYNC input which
reduces the clock frequency by approximately 30%.
Dropout Operation
When the input supply voltage decreases toward the
output voltage, the duty cycle increases to 100% which is
the dropout condition. In dropout, the PMOS switch is
turned on continuously with the output voltage being
equal to the input voltage minus the voltage drops across
the internal P-channel MOSFET and the inductor.
The main control loop is shut down by pulling the RUN pin
to ground.
An important design consideration is that the RDS(ON) of
the P-channel switch increases with decreasing input
supply voltage (see Typical Performance Characteristics).
Therefore, the user should calculate the power dissipation
when the LTC3548-2 is used at 100% duty cycle with low
input voltage (see Thermal Considerations in the Applications Information section).
Low Current Operation
Low Supply Operation
By selecting MODE/SYNC (pin 6), two modes are available
to control the operation of the LTC3548-2 at low currents.
Both modes automatically switch from continuous operation to the selected mode when the load current is low.
To prevent unstable operation, the LTC3548-2 incorporates an Undervoltage Lockout circuit that shuts down the
part when the input voltage drops below about 1.65V.
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LTC3548-2
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APPLICATIO S I FOR ATIO
A general LTC3548-2 application circuit is shown in
Figure 2. External component selection is driven by the
load requirement, and begins with the selection of the
inductor L. Once the inductor is chosen, CIN and COUT can
be selected.
Inductor Selection
Although the inductor does not influence the operating
frequency, the inductor value has a direct effect on ripple
current. The inductor ripple current ∆IL decreases with
higher inductance and increases with higher VIN or VOUT:
⎛ V ⎞
V
∆IL = OUT • ⎜ 1 – OUT ⎟
fO • L ⎝
VIN ⎠
Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple,
greater core losses and lower output current capability. A
reasonable starting point for setting ripple current is
∆IL = 0.3 • IOUT(MAX), where IOUT(MAX) is 800mA for
channel 1 and 400mA for channel 2. The largest ripple
current ∆IL occurs at the maximum input voltage. To
guarantee that the ripple current stays below a specified
maximum, the inductor value should be chosen according
to the following equation:
L=
VOUT
fO • ∆IL
⎛
⎞
V
• ⎜ 1 – OUT ⎟
⎝ VIN(MAX) ⎠
VIN
2.5V TO 5.5V
CIN
RUN2
BM*
PS*
VIN
MODE/SYNC
RUN1
R5
POWER-ON
RESET
POR
LTC3548-2
L1
L2
VOUT2
SW1
SW2
C5
R1
Inductor Core Selection
Different core materials and shapes will change the size/
current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy materials are small and don’t radiate much energy, but generally cost more than powdered iron core inductors with
similar electrical characterisitics. The choice of which
style inductor to use often depends more on the price vs
size requirements and any radiated field/EMI requirements than on what the LTC3548-2 requires to operate.
Table 1 shows some typical surface mount inductors that
work well in LTC3548-2 applications.
Table 1. Representative Surface Mount Inductors
PART
NUMBER
VALUE
(µH)
DCR
(Ω MAX)
MAX DC
CURRENT (A)
SIZE
W × L × H (mm3)
Sumida
CDRH3D16
2.2
3.3
4.7
0.075
0.110
0.162
1.20
1.10
0.90
3.8 × 3.8 × 1.8
Sumida
CDRH2D11
1.5
2.2
0.068
0.170
0.900
0.780
3.2 × 3.2 × 1.2
Sumida
CMD4D11
2.2
3.3
0.116
0.174
0.950
0.770
4.4 × 5.8 × 1.2
Murata
LQH32CN
1.0
2.2
0.060
0.097
1.00
0.79
2.5 × 3.2 × 2.0
Toko
D312F
2.2
3.3
0.060
0.260
1.08
0.92
2.5 × 3.2 × 2.0
Panasonic
ELT5KT
3.3
4.7
0.17
0.20
1.00
0.95
4.5 × 5.4 × 1.2
VOUT1
VFB2
R2
COUT2
VOUT1
The inductor value will also have an effect on Burst Mode
operation. The transition from low current operation
begins when the peak inductor current falls below a level
set by the burst clamp. Lower inductor values result in
higher ripple current which causes this to occur at lower
load currents. This causes a dip in efficiency in the upper
range of low current operation. In Burst Mode operation,
lower inductance values will cause the burst frequency to
increase.
GND
COUT1
35482 F02
*MODE/SYNC = 0V: PULSE SKIP
MODE/SYNC = VIN: Burst Mode
Figure 2. LTC3548-2 General Schematic
Input Capacitor (CIN) Selection
In continuous mode, the input current of the converter is
a square wave with a duty cycle of approximately VOUT/
VIN. To prevent large voltage transients, a low equivalent
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LTC3548-2
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APPLICATIO S I FOR ATIO
series resistance (ESR) input capacitor sized for the maximum RMS current must be used. The maximum RMS
capacitor current is given by:
IRMS ≈ IMAX
VOUT ( VIN – VOUT
VIN
where the maximum average output current IMAX equals
the peak current minus half the peak-to-peak ripple current, IMAX = ILIM – ∆IL/2.
This formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT/2. This simple worst-case is commonly used to
design because even significant deviations do not offer
much relief. Note that capacitor manufacturer’s ripple
current ratings are often based on only 2000 hours lifetime. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature
than required. Several capacitors may also be paralleled to
meet the size or height requirements of the design. An
additional 0.1µF to 1µF ceramic capacitor is also recommended on VIN for high frequency decoupling, when not
using an all ceramic capacitor solution.
Output Capacitor (COUT) Selection
The selection of COUT is driven by the required ESR to
minimize voltage ripple and load step transients. Typically,
once the ESR requirement is satisfied, the capacitance is
adequate for filtering. The output ripple (∆VOUT) is determined by:
⎛
⎞
1
∆VOUT ≈ ∆IL ⎜ ESR +
8 • fO • COUT ⎟⎠
⎝
where f = operating frequency, COUT = output capacitance
and ∆IL = ripple current in the inductor. The output ripple
is highest at maximum input voltage since ∆IL increases
with input voltage. With ∆IL = 0.3 • IOUT(MAX) the output
ripple will be less than 100mV at maximum VIN and
fO = 2.25MHz with:
ESRCOUT < 150mΩ
Once the ESR requirements for COUT have been met, the
RMS current rating generally far exceeds the IRIPPLE(P-P)
requirement, except for an all ceramic solution.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the capacitance, ESR or RMS
current handling requirement of the application. Aluminum electrolytic, special polymer, ceramic and dry tantulum
capacitors are all available in surface mount packages. The
OS-CON semiconductor dielectric capacitor available from
Sanyo has the lowest ESR(size) product of any aluminum
electrolytic at a somewhat higher price. Special polymer
capacitors, such as Sanyo POSCAP, Panasonic Special
Polymer (SP), and Kemet A700, offer very low ESR, but
have a lower capacitance density than other types. Tantalum capacitors have the highest capacitance density, but
they have a larger ESR and it is critical that the capacitors
are surge tested for use in switching power supplies. An
excellent choice is the AVX TPS series of surface mount
tantalums, available in case heights ranging from 2mm to
4mm. Aluminum electrolytic capacitors have a significantly larger ESR, and are often used in extremely costsensitive applications provided that consideration is given
to ripple current ratings and long term reliability. Ceramic
capacitors have the lowest ESR and cost, but also have the
lowest capacitance density, a high voltage and temperature coefficient, and exhibit audible piezoelectric effects.
In addition, the high Q of ceramic capacitors along with
trace inductance can lead to significant ringing.
In most cases, 0.1µF to 1µF of ceramic capacitors should
also be placed close to the LTC3548-2 in parallel with the
main capacitors for high frequency decoupling.
Ceramic Input and Output Capacitors
Higher value, lower cost ceramic capacitors are now
becoming available in smaller case sizes. These are tempting for switching regulator use because of their very low
ESR. Unfortunately, the ESR is so low that it can cause
loop stability problems. Solid tantalum capacitor ESR
generates a loop “zero” at 5kHz to 50kHz that is instrumental in giving acceptable loop phase margin. Ceramic capacitors remain capacitive to beyond 300kHz and usually
resonate with their ESL before ESR becomes effective.
Also, ceramic caps are prone to temperature effects which
requires the designer to check loop stability over the
operating temperature range. To minimize their large
temperature and voltage coefficients, only X5R or X7R
35482fa
9
LTC3548-2
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APPLICATIO S I FOR ATIO
ceramic capacitors should be used. A good selection of
ceramic capacitors is available from Taiyo Yuden, AVX,
Kemet, TDK, and Murata.
Great care must be taken when using only ceramic input
and output capacitors. When a ceramic capacitor is used
at the input and the power is being supplied through long
wires, such as from a wall adapter, a load step at the output
can induce ringing at the VIN pin. At best, this ringing can
couple to the output and be mistaken as loop instability. At
worst, the ringing at the input can be large enough to
damage the part.
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement. During a load step, the output capacitor must
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough to
support the load. The time required for the feedback loop
to respond is dependent on the compensation and the
output capacitor size. Typically, 3-4 cycles are required to
respond to a load step, but only in the first cycle does the
output drop linearly. The output droop, VDROOP, is usually
about 2-3 times the linear drop of the first cycle. Thus, a
good place to start is with the output capacitor size of
approximately:
COUT ≈ 2.5
∆IOUT
fO • VDROOP
More capacitance may be required depending on the duty
cycle and load step requirements.
In most applications, the input capacitor is merely required to supply high frequency bypassing, since the
impedance to the supply is very low. A 10µF ceramic
capacitor is usually enough for these conditions.
Setting the Output Voltage for Channel 2
The LTC3548-2 develops a 0.6V reference voltage between the feedback pin, VFB2, and the ground as shown in
Figure 2. The output voltage, VOUT2, is set by a resistive
divider according to the following formula:
Keeping the current small (<5µA) in these resistors maximizes efficiency, but making them too small may allow
stray capacitance to cause noise problems and reduce the
phase margin of the error amp loop.
To improve the frequency response, a feed-forward capacitor CF may also be used. Great care should be taken to
route the VOUT1, VFB2 line away from noise sources, such
as the inductor or the SW line.
Power-On Reset
The POR pin is an open-drain output which pulls low when
either regulator is out of regulation. When both output
voltages are above –8.5% of regulation, a timer is started
which releases POR after 218 clock cycles (about 117ms
in pulse skip mode). This delay can be significantly longer
in Burst Mode operation with low load currents, since the
clock cycles only occur during a burst and there could be
milliseconds of time between bursts. This can be bypassed by tying the POR output to the MODE/SYNC input,
to force pulse skipping mode during a reset. In addition, if
the output voltage faults during Burst Mode sleep, POR
could have a slight delay for an undervoltage output
condition. This can be avoided by using pulse skipping
mode instead. When either channel is shut down, the POR
output is pulled low, since one or both of the channels are
not in regulation.
Mode Selection and Frequency Synchronization
The MODE/SYNC pin is a multipurpose pin which provides
mode selection and frequency synchronization. Connecting this pin to VIN enables Burst Mode operation, which
provides the best low current efficiency at the cost of a
higher output voltage ripple. Connecting this pin to ground
selects pulse skipping mode, which provides the lowest
output ripple, at the cost of low current efficiency.
The LTC3548-2 can also be synchronized to an external
2.25MHz clock signal by the MODE/SYNC pin. During
synchronization, the mode is set to pulse skipping and the
top switch turn-on is synchronized to the rising edge of the
external clock.
⎛ R2 ⎞
VOUT2 = 0.6 V ⎜ 1+ ⎟
⎝ R1⎠
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LTC3548-2
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Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to ∆ILOAD • ESR, where ESR is the effective series
resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT, generating a feedback error signal used
by the regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability
problem.
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard secondorder overshoot/DC ratio cannot be used to determine
phase margin. In addition, a feed-forward capacitor, CF,
can be added to improve the high frequency response, as
shown in Figure 2. Capacitor CF provides phase lead by
creating a high frequency zero with R2, which improves
the phase margin.
The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance. For a detailed
explanation of optimizing the compensation components,
including a review of control loop theory, refer to Application Note 76.
In some applications, a more severe transient can be
caused by switching loads with large (>1µF) load input
capacitors. The discharged load input capacitors are effectively put in parallel with COUT, causing a rapid drop in
VOUT. No regulator can deliver enough current to prevent
this problem, if the switch connecting the load has low
resistance and is driven quickly. The solution is to limit the
turn-on speed of the load switch driver. A Hot SwapTM
controller is designed specifically for this purpose and
usually incorporates current limiting, short-circuit protection and soft-starting.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
% Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, 4 main sources usually account for most of the
losses in LTC3548-2 circuits: 1)VIN quiescent current,
2) switching losses, 3) I2R losses, 4) other losses.
1) The VIN current is the DC supply current given in the
Electrical Characteristics which excludes MOSFET driver
and control currents. VIN current results in a small (<0.1%)
loss that increases with VIN, even at no load.
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current results
from switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from VIN to
ground. The resulting dQ/dt is a current out of VIN that is
typically much larger than the DC bias current. In continuous mode, IGATECHG = fO(QT + QB), where QT and QB are the
gate charges of the internal top and bottom MOSFET
switches. The gate charge losses are proportional to VIN
and thus their effects will be more pronounced at higher
supply voltages.
3) I2R losses are calculated from the DC resistances of the
internal switches, RSW, and external inductor, RL. In
continuous mode, the average output current flows through
inductor L, but is “chopped” between the internal top and
bottom switches. Thus, the series resistance looking into
the SW pin is a function of both top and bottom MOSFET
RDS(ON) and the duty cycle (D) as follows:
RSW = (RDS(ON)TOP)(D) + (RDS(ON)BOT)(1 – D)
The RDS(ON) for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I2R losses:
I2R losses = IOUT2(RSW + RL)
Hot Swap is a trademark of Linear Technology Corporation.
35482fa
11
LTC3548-2
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APPLICATIO S I FOR ATIO
4) Other “hidden” losses such as copper trace and internal
battery resistances can account for additional efficiency
degradations in portable systems. It is very important to
include these “system” level losses in the design of a
system. The internal battery and fuse resistance losses
can be minimized by making sure that CIN has adequate
charge storage and very low ESR at the switching frequency. Other losses including diode conduction losses
during dead-time and inductor core losses generally account for less than 2% total additional loss.
Thermal Considerations
In a majority of applications, the LTC3548-2 does not
dissipate much heat due to its high efficiency. However, in
applications where the LTC3548-2 is running at high
ambient temperature with low supply voltage and high
duty cycles, such as in dropout, the heat dissipated may
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 150°C,
both power switches will turn off and the SW node will
become high impedance.
To prevent the LTC3548-2 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The temperature rise is given by:
TRISE = PD • θJA
where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to the
ambient temperature.
The junction temperature, TJ, is given by:
TJ = TRISE + TAMBIENT
As an example, consider the case when the LTC3548-2 is
at an input voltage of 2.7V with a load current of 400mA
and 800mA and an ambient temperature of 70°C. From
the Typical Performance Characteristics graph of Switch
Resistance, the RDS(ON) resistance of the main switch is
0.425Ω. Therefore, power dissipated by each channel is:
PD = I2 • RDS(ON) = 272mW and 68mW
The DFN package junction-to-ambient thermal resistance,
θJA, is 40°C/W. Therefore, the junction temperature of the
regulator operating in a 70°C ambient temperature is
approximately:
TJ = (0.272 + 0.068) • 40 + 70 = 83.6°C
which is below the absolute maximum junction temperature of 125°C.
Design Example
As a design example, consider using the LTC3548-2 in an
portable application with a Li-Ion battery. The battery
provides a VIN = 2.8V to 4.2V. The load requires a maximum of 800mA in active mode and 2mA in standby mode.
The output voltage is VOUT1 = 1.8V. Since the load still
needs power in standby, Burst Mode operation is selected
for good low load efficiency.
First, calculate the inductor value for about 30% ripple
current at maximum VIN:
L=
1.8 V
⎛ 1.8 V ⎞
• ⎜ 1–
= 1.9µH
2.25MHz • 240mA ⎝ 4.2V ⎟⎠
Choosing a vendor’s closest inductor value of 2.2µH,
results in a maximum ripple current of:
∆IL =
1.8 V
⎛ 1.8 V ⎞
= 208mA
• ⎜ 1−
2.25MHz • 2.2µ ⎝ 4.2V ⎟⎠
For cost reasons, a ceramic capacitor will be used. COUT
selection is then based on load step droop instead of ESR
requirements. For a 5% output droop:
COUT ≈ 2.5
800mA
= 9.9µF
2.25MHz •(5% • 1.8 V)
A good standard value is 10µF. Since the output impedance of a Li-Ion battery is very low, CIN is typically 10µF.
Following the same procedure for VOUT2 = 2.5V, the
inductor value is derived as 4.7µH and the output capacitor
value is 4.7µF.
The output voltage, VOUT2, can now be programmed by
choosing the values of R1 and R2. To maintain high
efficiency, the current in these resistors should be kept
small. Choosing 2µA with the 0.6V feedback voltage
35482fa
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LTC3548-2
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APPLICATIO S I FOR ATIO
makes R1 approximately 280k. A close standard 1%
resistor is 280k, and R2 is then 887k.
The PGOOD pin is a common drain output and requires a
pull-up resistor. A 100k resistor is used for adequate speed.
Figure 3 shows the complete schematic for this design
example.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3548-2. These items are also illustrated graphically in
the layout diagram of Figure 4. Check the following in your
layout:
1. Does the capacitor CIN connect to the power VIN (Pin 3)
and GND (exposed pad) as close as possible? This capacitor provides the AC current to the internal power MOSFETs
and their drivers.
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of COUT and a ground sense line
terminated near GND (exposed pad). The feedback signals
VOUT1, VFB2 should be routed away from noisy components and traces, such as the SW line (Pins 4 and 7), and
its trace should be minimized.
4. Keep sensitive components away from the SW pins. The
input capacitor CIN and the resistors R1 to R2 should be
routed away from the SW traces and the inductors.
5. A ground plane is preferred, but if not available, keep the
signal and power grounds segregated with small signal
components returning to the GND pin at one point and
should not share the high current path of CIN or COUT.
6. Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise of
power components. These copper areas should be connected to VIN or GND.
2. Are the COUT and L1 closely connected? The (–) plate of
COUT returns current to GND and the (–) plate of CIN.
VIN
VIN
2.5V* TO 5.5V
C1
10µF
RUN2 VIN
RUN1
POR
MODE/SYNC
VOUT2
2.5V*
400mA
L2
4.7µH
R5
100k
RUN2
POWER-ON
RESET
L1
2.2µH
LTC3548-2
SW2
SW1
VFB2
VOUT1
C5 68pF
C3
4.7µF
R2
887k
R1
280k
GND
VOUT1
1.8V
800mA
CIN
RUN1
POR
LTC3548-2
L1
L2
VOUT2
SW1
SW2
VOUT1
C5
COUT2
VOUT1
VFB2
R2
C2
10µF
VIN
MODE/SYNC
GND
COUT1
R1
35482 F03
C1, C2, C3: TAIYO YUDEN JMK212BJ106MG
C3: TAIYO YUDEN JMK212BJ475MG
L1: MURATA LQH32CN2R2M11
L2: MURATA LQH32CN4R7M23
35482 F04
BOLD LINES INDICATE
HIGH CURRENT PATHS
*VOUT CONNECTED TO VIN FOR VIN ≤ 2.8V (DROPOUT)
Figure 3. LTC3548-2 Typical Application
Figure 4. LTC3548-2 Layout Diagram
(See Board Layout Checklist)
35482fa
13
LTC3548-2
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TYPICAL APPLICATIO S
Low Ripple Buck Regulators Using Ceramic Capacitors
100
C1
10µF
RUN2
VIN
RUN1
POWER-ON
RESET
POR
LTC3548-2
L2
10µH
SW2
L1
4.7µH
SW1
C5 68pF
VOUT2 = 2.5V
95
R5
100k
VOUT1
1.8V
800mA
90
EFFICIENCY (%)
VIN
2.5V TO 5.5V
VOUT2
2.5V
400mA
Efficiency vs Load Current
85
VOUT1 = 1.8V
80
75
70
VOUT1
VFB2
R2
C3
10µF 887k
R1
280k
MODE/SYNC
65
C2
10µF
GND
VIN = 3.3V
PULSE SKIP MODE
60
10
35482 TA01
C1, C2, C3: TDK C2012X5R0J106M
L1: SUMIDA CDRH2D18/HP-4R7NC
L2: SUMIDA CDRH2D18/HP-100NC
1000
35482 TA01b
1mm Profile Core and I/O Supplies
Efficiency vs Load Current
100
C1*
10µF
RUN2
VIN
MODE/SYNC
RUN1
SW2
POWER-ON
RESET
POR
LTC3548-2
L2
4.7µH
L1
2.2µH
SW1
C5 68pF
95
R5
100k
VOUT1
1.8V
800mA
VOUT2 = 3.3V
90
EFFICIENCY (%)
VIN
3.6V TO 5.5V
VOUT2
3.3V
400mA
100
LOAD CURRENT (mA)
VOUT1 = 1.8V
85
80
75
70
R2
C3
4.7µF 887k
VOUT1
VFB2
R1
196k
GND
65
C2
10µF
35482 TA02a
C1, C2: MURATA GRM219R60J106KE19
C3: MURATA GRM219R60J475KE19
L1: COILTRONICS LPO3310-222MX
L2: COILTRONICS LPO3310-472MX
*IF C1 IS GREATER THAN 3" FROM POWER SOURCE,
ADDITIONAL CAPACITANCE MAY BE REQUIRED.
VIN = 5V
Burst Mode OPERATION
60
1
10
100
LOAD CURRENT (mA)
1000
35482 TA02b
35482fa
14
LTC3548-2
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PACKAGE DESCRIPTIO
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
0.675 ±0.05
3.50 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
PACKAGE
OUTLINE
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
3.00 ±0.10
(4 SIDES)
R = 0.115
TYP
6
0.38 ± 0.10
10
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
(DD10) DFN 1103
5
0.200 REF
1
0.75 ±0.05
0.00 – 0.05
0.25 ± 0.05
0.50 BSC
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
35482fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC3548-2
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TYPICAL APPLICATIO
2mm Height Lithium-Ion Single Inductor Buck-Boost Regulator and a Buck Regulator
VIN
2.8V TO 4.2V
C1
10µF
RUN2
VIN
MODE/SYNC
L2
15µH
D1
VOUT2
3.3V
100mA
M1
POWER-ON
RESET
POR
L1
2.2µH
LTC3548-2
SW1
SW2
+
R5
100k
RUN1
C5 22pF
C6
22µF
C3
4.7µF
R4
887k
VOUT1
VFB2
R3
196k
VOUT1
1.8V
800mA
GND
C2
10µF
35482 TA03a
C1, C2: TAIYO YUDEN JMK316BJ106ML
C3: MURATA GRM21BR60J475KA11B
C6: KEMET C1206C226K9PAC
D1: PHILIPS PMEG2010
L1: MURATA LQH32CN2R2M33
L2: TOKO A914BYW-150M (D52LC SERIES)
M1: SILICONIX Si2302DS
Efficiency vs Load Current
Efficiency vs Load Current
100
90
95
80
2.8V
60
50
EFFICIENCY (%)
EFFICIENCY (%)
90
4.2V
3.6V
2.8V
70
85
4.2V
3.6V
80
75
70
40 VOUT = 3.3V
Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
30
1
10
100
LOAD CURRENT (mA)
VOUT = 1.8V
Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
65
60
1000
1
10
100
LOAD CURRENT (mA)
1000
3548 TA03c
35482 TA03b
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800mA/400mA (IOUT), Dual 2.25MHz,
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35482fa
16
Linear Technology Corporation
LT 0406 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
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