CYPRESS CY7C1021DV33

CY7C1021DV33
1-Mbit (64 K x 16) Static RAM
Features
Functional Description[1]
■
Temperature ranges
❐ Industrial: –40 °C to 85 °C
❐ Automotive-A: –40 °C to 85 °C
■
Pin-and function-compatible with CY7C1021CV33
The CY7C1021DV33 is a high-performance CMOS static
RAM organized as 65,536 words by 16 bits. This device has
an automatic power-down feature that significantly reduces
power consumption when deselected.
■
High speed
❐ tAA = 10 ns
■
Low active power
❐ ICC = 60 mA @ 10 ns
■
Low CMOS standby power
❐ ISB2 = 3 mA
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A15).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the end of this data sheet for a complete
description of Read and Write modes.
■
2.0 V data retention
■
Automatic power-down when deselected
■
CMOS for optimum speed/power
■
Independent control of upper and lower bits
■
Available in Pb-free 44-pin 400-Mil wide molded SOJ,
44-pin TSOP II and 48-ball VFBGA packages
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation
(CE LOW, and WE LOW).
The CY7C1021DV33 is available in Pb-free 44-pin 400-Mil
wide Molded SOJ, 44-pin TSOP II and 48-ball VFBGA
packages.
Logic Block Diagram
64K x 16
RAM Array
SENSE AMPS
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
A8
A9
A10
A11
A12
A13
A14
A15
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation
Document #: 38-05460 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 25, 2011
CY7C1021DV33
Selection Guide
–10 (Industrial/Automotive-A)
Unit
Maximum access time
10
ns
Maximum operating current
60
mA
Maximum CMOS standby current
3
mA
Pin Configuration[1]
SOJ/TSOP II
Top View
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
48-ball VFBGA
Top View
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
I/O8
BHE
A3
A4
CE
I/O0
B
I/O9
I/O10
A5
A6
I/O2
I/O1
C
VSS
I/O11
NC
A7
I/O3
VCC
D
VCC
I/O12
NC
NC
I/O4
VSS
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
H
Notes
1. NC pins are not connected on the die.
Document #: 38-05460 Rev. *G
Page 2 of 13
CY7C1021DV33
Maximum Ratings
Current into outputs (LOW) ......................................... 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static discharge voltage........................................... > 2001 V
(per MIL-STD-883, method 3015)
Storage temperature ................................ –65 C to +150 C
Latch-up current ...................................................... >200 mA
Ambient temperature with
power applied ........................................... –55 C to +125 C
Operating Range
Range
Ambient
Temperature
VCC
Industrial
–40 °C to +85°C
3.3 V  0.3 V
Automotive-A
–40 °C to +85°C
Supply voltage on VCC to Relative GND[2] ...–0.3 V to +4.6 V
DC Voltage applied to outputs
in high-Z State[2] .................................... –0.3 V to VCC+0.3 V
DC input voltage[2] ................................. –0.3 V to VCC+0.3 V
Speed
10 ns
10 ns
DC Electrical Characteristics Over the Operating Range
Parameter
Description
–10 (Ind’l/Auto-A)
Test Conditions
Min.
Unit
Max.
VOH
Output HIGH voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW voltage
VCC = Min., IOL = 8.0 mA
0.4
V
VIH
Input HIGH voltage
2.0
VCC + 0.3
V
VIL
Input LOW voltage[2]
0.3
0.8
V
IIX
Input leakage current
GND < VI < VCC
1
+1
A
IOZ
Output leakage current
GND < VI < VCC, Output Disabled
1
+1
A
ICC
VCC operating
supply current
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
100 MHz
60
mA
83 MHz
55
mA
66 MHz
45
mA
40 MHz
30
mA
10
mA
3
mA
ISB1
ISB2
2.4
V
Automatic CE Power-Down Max. VCC, CE > VIH
Current —TTL Inputs
VIN > VIH or VIN < VIL, f = fMAX
Automatic CE Power-Down Max. VCC, CE > VCC – 0.3 V,
Current —CMOS Inputs
VIN > VCC – 0.3 V or VIN < 0.3 V, f = 0
Capacitance[3]
Parameter
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25C, f = 1 MHz, VCC = 3.3 V
Max.
Unit
8
pF
8
pF
Thermal Resistance[3]
Parameter
Description
JA
Thermal resistance
(Junction to Ambient)
JC
Thermal resistance
(Junction to Case)
Test Conditions
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
SOJ
TSOP II VFBGA
Unit
59.52
53.91
36
C/W
36.75
21.24
9
C/W
Notes
2. VIL (min.) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 5 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05460 Rev. *G
Page 3 of 13
CY7C1021DV33
AC Test Loads and Waveforms[4]
90%
OUTPUT
50 
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
ALL INPUT PULSES
3.0 V
Z = 50
30 pF*
GND
90%
10%
10%
1.5 V
Rise Time: 1 V/ns
(a)
(b)
Fall Time: 1 V/ns
High-Z characteristics: R 317
3.3 V
OUTPUT
R2
351
5 pF
(c)
Note
4. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure (c).
Document #: 38-05460 Rev. *G
Page 4 of 13
CY7C1021DV33
Switching Characteristics Over the Operating Range[5]
-10 (Ind’l/Auto-A)
Parameter
Description
Min.
Max.
Unit
Read Cycle
tpower[6]
VCC(typical) to the first access
100
s
tRC
Read cycle time
10
ns
tAA
Address to data valid
tOHA
Data hold from address change
tACE
CE LOW to data valid
10
ns
tDOE
OE LOW to data valid
5
ns
[8]
OE LOW to low-Z
tLZOE
tHZOE
OE HIGH to
CE LOW to
tHZCE
CE HIGH to
high-Z[7, 8]
tPU[9]
tPD[9]
CE LOW to power-up
tDBE
Byte Enable to data valid
tLZBE
Byte Enable to low-Z
ns
5
3
ns
ns
5
0
ns
ns
10
ns
5
ns
0
Byte Disable to high-Z
ns
ns
0
CE HIGH to power-down
tHZBE
Write Cycle
3
high-Z[7, 8]
low-Z[8]
tLZCE
10
ns
6
ns
[10]
tWC
Write cycle time
10
ns
tSCE
CE LOW to write end
8
ns
tAW
Address set-up to write end
8
ns
tHA
Address hold from write end
0
ns
tSA
Address set-up to write start
0
ns
tPWE
WE pulse width
7
ns
tSD
Data set-up to write end
5
ns
tHD
Data hold from write end
0
ns
3
ns
tLZWE
[8]
WE HIGH to low-Z
high-Z[7, 8]
tHZWE
WE LOW to
tBW
Byte enable to end of write
5
7
ns
ns
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V.
6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
7. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. This parameter is guaranteed by design and is not tested.
10. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write
and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that
terminates the Write.
Document #: 38-05460 Rev. *G
Page 5 of 13
CY7C1021DV33
Data Retention Characteristics Over the Operating Range
Parameter
Description
Conditions
VDR
VCC for data retention
ICCDR
Data retention current
tCDR[3]
Chip deselect to data retention time
tR[11]
Operation recovery time
Min.
Max.
Unit
3
mA
2
V
VCC = VDR = 2.0 V, CE > VCC – 0.3 V,
Industrial
VIN > VCC – 0.3 V or VIN < 0.3 V
0
ns
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
3.0 V
VCC
VDR > 2 V
tCDR
3.0 V
tR
CE
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[12, 13]
tRC
RC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[13, 14]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
tLZOE
BHE, BLE
tHZCE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
tHZBE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
50%
ICC
50%
ISB
Notes
11. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s.
12. Device is continuously selected. OE, CE, BHE and/or BLE = VIL.
13. WE is HIGH for Read cycle.
14. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05460 Rev. *G
Page 6 of 13
CY7C1021DV33
Switching Waveforms
(continued)
Write Cycle No. 1 (CE Controlled)[15, 16]
tWC
ADDRESS
tSA
tSCE
CE
tAW
tHA
tPWE
WE
tBW
BHE, BLE
tSD
tHD
DATA IN VALID
DATA I/O
Write Cycle No. 2 (BLE or BHE Controlled)
tWC
ADDRESS
tSA
tBW
BHE, BLE
tAW
tHA
tPWE
WE
tSCE
CE
tSD
DATA I/O
tHD
DATA IN VALID
Notes
15. Data I/O is high impedance if OE or BHE and/or BLE = VIH.
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05460 Rev. *G
Page 7 of 13
CY7C1021DV33
Switching Waveforms
(continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
OE
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
DATA I/O
tSD
tHD
DATA IN VALID
tLZWE
Truth Table
CE
OE
WE
H
X
X
X
X
High-Z
High-Z
Power-down
Standby (ISB)
L
L
H
L
L
Data Out
Data Out
Read – All bits
Active (ICC)
L
H
Data Out
High-Z
Read – Lower bits only
Active (ICC)
H
L
High-Z
Data Out
Read – Upper bits only
Active (ICC)
L
L
Data In
Data In
Write – All bits
Active (ICC)
L
H
Data In
High-Z
Write – Lower bits only
Active (ICC)
H
L
High-Z
Data In
Write – Upper bits only
Active (ICC)
L
X
L
BLE
BHE
I/O0–I/O7
I/O8–I/O15
Mode
Power
L
H
H
X
X
High-Z
High-Z
Selected, outputs disabled
Active (ICC)
L
X
X
H
H
High-Z
High-Z
Selected, outputs disabled
Active (ICC)
Document #: 38-05460 Rev. *G
Page 8 of 13
CY7C1021DV33
Ordering Information
Speed
(ns)
10
10
Ordering Code
Package
Name
Package Type
CY7C1021DV33-10VXI
51-85082
44-pin (400-Mil) Molded SOJ (Pb-free)
CY7C1021DV33-10ZSXI
51-85087
44-pin TSOP Type II (Pb-free)
CY7C1021DV33-10BVXI
51-85150
48-ball VFBGA (Pb-free)
CY7C1021DV33-10ZSXA
51-85087
44-pin TSOP Type II (Pb-free)
Operating
Range
Industrial
Automotive-A
Ordering Code Definitions
CY 7 C 1 02 1
D V33 - XX XXX X
Temperature Range: X = I or A or E
I = Industrial; A = Automotive-A; E = Automotive-E
Package Type: XXX = VX or ZSX or BVX
VX = 44-pin Molded SOJ (Pb-free)
ZSX = 44-pin TSOP Type II (Pb-free)
BVX = 48-ball VFBGA (Pb-free)
Speed: XX = 10 ns or 12 ns
V33 = Voltage range (3 V to 3.6 V)
D = C9, 90 nm Technology
1 = Data width × 16-bits
02 = 1-Mbit density
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
7 = SRAM
CY = Cypress
Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05460 Rev. *G
Page 9 of 13
CY7C1021DV33
Package Diagrams
Figure 1. 44-pin (400-Mil) Molded SOJ (51-85082)
51-85082 *D
Figure 2. 44-pin Thin Small Outline Package Type II (51-85087)
51-85087 *D
Document #: 38-05460 Rev. *G
Page 10 of 13
CY7C1021DV33
Package Diagrams (continued)
Figure 3. 48-ball VFBGA (6 x 8 x 1 mm) (51-85150)
51-85150 *G
Document #: 38-05460 Rev. *G
Page 11 of 13
CY7C1021DV33
Document History Page
Document Title: CY7C1021DV33, 1-Mbit (64K x 16) Static RAM
Document Number: 38-05460
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
201560
See ECN
SWI
Advance Information data sheet for C9 IPP
*A
233693
See ECN
RKF
DC parameters are modified as per Eros (Spec # 01-02165).
Pb-free Offering In Ordering Information
*B
263769
See ECN
RKF
Changed I/O1 – I/O16 to I/O0 – I/O15
Added Data Retention Characteristics table
Added Tpower Spec in Switching Characteristics table
Shaded Ordering Information
*C
307601
See ECN
RKF
Reduced Speed bins to –8 and –10 ns
*D
520652
See ECN
VKN
Converted from Preliminary to Final
Removed Commercial Operating range
Removed 8 ns speed bin
Added ICC values for the frequencies 83MHz, 66MHz and 40MHz
Added Automotive Information
Updated Thermal Resistance table
Updated Ordering Information Table
Changed Overshoot spec from VCC+2 V to VCC+1 V in footnote #4
*E
2898399
03/24/2010
AJU
Updated Package Diagrams
*F
3109897
12/14/2010
AJU
Added Ordering Code Definitions.
Updated Package Diagrams.
*G
3421856
10/25/2011
TAVA
Template Update
Updated Features, Selection Guide, Operating Range, DC Electrical Characteristics Over the Operating Range, Switching Characteristics Over the
Operating Range[5], Data Retention Characteristics Over the Operating Range,
Switching Waveforms, and Ordering Information
Updated Package Diagrams
Document #: 38-05460 Rev. *G
Page 12 of 13
CY7C1021DV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
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cypress.com/go/automotive
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PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
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PSoC
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cypress.com/go/memory
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cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
All products and company names mentioned in this document are the trademarks of their respective holders.
© Cypress Semiconductor Corporation, 2008-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05460 Rev. *G
<
Revised October 25, 2011
Page 13 of 13