LTM2220-AA 12-Bit, 170Msps ADC FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTION Pin Compatible with the AD9430 Sample Rate: 170Msps 66.2dB SNR, 84dB SFDR No Missing Codes Single 3.3V supply Power Dissipation: 1050mW LVDS Digital Outputs 1.536VPP Input Range Clock Duty Cycle Stabilizer Out-of-Range Indicator Data Ready Output Clock Integrated Bypass Capacitors 100-Pin SiPLGA Package The LTM®2220-AA is a 170Msps sampling 12-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTM2220-AA is perfect for demanding communications applications with AC performance that includes 66.2dB SNR and 84dB spurious free dynamic range. DC specs include ±0.5LSB INL (typ), ±0.3LSB DNL (typ) and no missing codes over temperature. The CLK+ and CLK- inputs may be driven differentially or single ended with a sine wave, PECL, TTL or CMOS inputs. A clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. APPLICATIONS ■ ■ Wireless and Wired Broadband Communication Spectral Analysis The LTM2220-AA is pin compatible with the AD9430 when used with LVDS outputs, 2’s complement output format and the 1.536VPP input range. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION 3.3V AVDD 3.3V REFERENCE DRVDD + ANALOG INPUT INPUT S/H – 12-BIT PIPELINED ADC CORE CORRECTION LOGIC D11 • • • D0 OUTPUT DRIVERS LVDS OUTPUTS DRGND CLOCK/DUTY CYCLE CONTROL AGND 2220 TA01 CLOCK INPUT 2220aaf 1 LTM2220-AA ABSOLUTE MAXIMUM RATINGS AVDD = DRVDD (Notes 1, 2) Supply Voltage (AVDD, DRVDD) .................................4V Analog Input Voltage (Note 3) .... -0.3V to (AVDD + 0.3V) Digital Input Voltage................... -0.3V to (AVDD + 0.3V) Digital Output Voltage ............. -0.3V to (DRVDD + 0.3V) Power Dissipation ............................................ 1500mW Operating Temperature Range ..................-40°C to 85°C Storage Temperature Range....................-65°C to 125°C PACKAGE/ORDER INFORMATION D9– D9+ D10– D10+ D11– D11+ DRGND DRVDD OR– OR+ AGND AGND AVDD AVDD AVDD AGND AGND AGND AVDD AVDD AGND AGND AVDD AVDD AGND TOP VIEW 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC 1 75 DRVDD NC 2 74 DRGND NC 3 73 D8+ AGND 4 72 D8– NC 5 71 D7+ NC 6 70 D7– NC 7 69 D6+ AVDD 8 68 D6– AGND 9 AGND NC 10 67 DRGND AGND 66 D5+ 65 D5– NC 11 AGND 12 64 DCO+ AGND 13 63 DCO– AVDD 14 62 DRVDD AVDD 15 61 DRGND AGND 16 60 D4+ AGND AGND AGND 17 59 D4– AVDD 18 58 D3+ AVDD 19 57 D3– AGND 20 56 D2+ VIN+ 21 55 D2– VIN– 22 54 DRVDD AGND 23 53 DRGND AVDD 24 52 D1+ AGND 25 51 D1– D0+ D0– DRGND DRVDD NC NC NC NC NC AGND AVDD AVDD AGND CLK– CLK+ AGND AVDD NC AGND AGND AGND AVDD AVDD AVDD AGND 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SiPLGA PACKAGE 100-LEAD (16mm × 16mm) TJMAX = 125°C, θJA = 20°C/W EXPOSED PADS ARE AGND ORDER PART NUMBER LTM2220IV-AA#PBF LGA PART MARKING LTM2220V-AA Consult LTC Marketing for parts specified with wider operating temperature ranges. 2220aaf 2 LTM2220-AA CONVERTER CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER CONDITIONS Resolution (No Missing Codes) Integral Linearity Error (Note 5) Differential Linearity Error Offset Error MIN TYP MAX UNITS ● 12 ● –1.5 ±0.5 1.5 LSB ● –1 ±0.3 1 LSB –35 ±3 35 mV (Note 6) Gain Error Bits ±0.5 %FS ANALOG INPUTS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS VIN Differential Input Range VIN, CM Common Mode Input Range VIN+ – VIN– (VIN+ + VIN–)/2 fL Lower –3dB Frequency fH Upper –3dB Frequency tJITTER Sample and Hold Jitter MIN ● ● TYP MAX 1.536 0 RS = 75Ω UNITS V 3.6 V 1.6 kHz 195 MHz 0.2 psRMS DYNAMIC ACCURACY The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4) SYMBOL PARAMETER CONDITIONS SNR Signal-to-Noise Ratio 10MHz Input SINAD Signal to Noise Plus Distortion Ratio 70MHz Input SFDR IMD ● 63.5 10MHz Input 70MHz Input SFDR MIN Spurious Free Dynamic Range: 2nd or 3rd Harmonic 10MHz Input Spurious Free Dynamic Range: 4th Harmonic or Higher 10MHz Input Intermodulation Distortion fIN1 = 138MHz, fIN2 = 140MHz 70MHz Input 70MHz Input ● 63.2 TYP MAX UNITS 66.2 dB 66.1 dB 66.1 dB 65.9 dB 84 dB dB ● 70 84 90 dB ● 78 90 dB 81 dB 2220aaf 3 LTM2220-AA DIGITAL INPUTS AND OUTPUTS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CLOCK INPUTS (CLK+, CLK–) VID Differential Input Voltage VICM Common Mode Input Voltage RIN Input Resistance CIN Input Capacitance Internally Set Externally Set ● 0.2 ● 1.1 (Note 7) V 1.6 1.6 V V 2.5 6 kΩ 3 pF DIGITAL LOGIC OUTPUTS VOD Differential Output Voltage VOS Output Common Mode Voltage 100Ω Load ● 247 350 454 ● 1.125 1.250 1.375 mV V POWER REQUIREMENTS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX AVDD Analog Supply Voltage (Note 8) ● 3.1 3.3 3.5 UNITS V DRVDD Digital Supply Voltage (Note 8) ● 3.0 3.3 3.6 V IAVDD Analog Supply Current ● 264 288 mA IDVDD Digital Supply Current ● 55 70 mA PDISS Power Dissipation ● 1050 1182 mW TIMING CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fS Sampling Frequency 170 MHz tL CLK Low Time tH CLK High Time tAP Sample-and-Hold Aperture Delay tD CLK to DATA Delay (Note 7) ● 1.5 3 4.3 ns tC CLK to DCO Delay (Note 7) ● 1.5 3 4.3 ns DATA to DCO Skew (tC – tD), (Note 7) ● –0.6 0 0.6 ns ● 1 (Note 7) ● 2 2.94 500 ns (Note 7) ● 2 2.94 500 ns 0 ns Rise Time 0.5 ns Fall Time 0.5 ns Pipeline Latency Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with AGND and DRGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. 5 Cycles Note 4: AVDD = DRVDD = 3.3V, fSAMPLE =170MHz, differential CLK+/CLK= 2Vpp sine wave, differential analog inputs, unless otherwise noted. Note 5: Integral nonlinearity is defined as the deviation of a code from a “best fit straight line” fit to the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from -0.5 LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111. Note 7: Guaranteed by design, not subject to test. Note 8: Recommended operating conditions. 2220aaf 4 LTM2220-AA TYPICAL PERFORMANCE CHARACTERISTICS 8192 Point FFT, fIN = 30MHz, –1dB, 170Msps 8192 Point FFT, fIN = 70MHz, –1dB, 170Msps 0 0 –10 –10 –20 –20 –20 –30 –30 –30 –40 –50 –60 –70 AMPLITUDE (dB) 0 –10 AMPLITUDE (dB) AMPLITUDE (dB) 8192 Point FFT, fIN = 5MHz, –1dB, 170Msps –40 –50 –60 –70 –40 –50 –60 –70 –80 –80 –90 –90 –90 –100 –100 –100 –110 –80 –110 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 –110 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 2220 G01 0 INL Error –10 0.8 0.8 –20 0.6 0.6 0.4 0.4 –30 ERROR (LSB) –70 ERROR (LSB) 1.0 –60 0.2 0 – 0.2 0 – 0.4 – 0.4 – 0.6 – 0.6 –100 – 0.8 – 0.8 – 1.0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 2220 G04 80 – 0.2 –90 0 70 0.2 –80 –110 30 40 50 60 FREQUENCY (MHz) DNL Error 1.0 –50 20 2220 G03 0 –40 10 2220 G02 8192 Point FFT, fIN = 140MHz, –1dB, 170Msps AMPLITUDE (dB) 80 – 1.0 0 1024 3072 2048 OUTPUT CODE 4096 2220 G05 0 1024 3072 2048 OUTPUT CODE 4096 2220 G06 2220aaf 5 LTM2220-AA PIN FUNCTIONS NC (Pins 1, 2, 3, 5, 6, 7, 10, 11, 33, 42, 43, 44, 45, 46): Pin is not connected internally. AGND (Pins 4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31, 32, 35, 38, 41, 86, 87, 91, 92, 93, 96, 97, 100): Analog Ground. AVDD (Pins 8, 14, 15, 18, 19, 24, 27, 28, 29, 34, 39, 40, 88, 89, 90, 94, 95, 98, 99): 3.3V Analog Supply. D3+ (Pin 58): D3 True Output Bit. D4- (Pin 59): D4 Complement Output Bit. D4+ (Pin 60): D4 True Output Bit. DCO- (Pin 63): Data Clock Output Complement. DCO+ (Pin 64): Data Clock Output True. D5- (Pin 65): D5 Complement Output Bit. VIN + (Pin 21): Positive Analog Input. D5+ (Pin 66): D5 True Output Bit. VIN - (Pin 22): Negative Analog Input. D6- (Pin 68): D6 Complement Output Bit. CLK+ (Pin 36): Clock Input. The input sample starts on the positive edge. D6+ (Pin 69): D6 True Output Bit. CLK- (Pin 37): Clock Complement Input. Conversion starts on the negative edge. Bypass to ground with a 0.1µF ceramic for a single-ended clock. D7+ (Pin 71): D7 True Output Bit. D7- (Pin 70): D7 Complement Output Bit. D8- (Pin 72): D8 Complement Output Bit. DRVDD (Pins 47, 54, 62, 75, 83): 3.3V Digital Output Driver Supply. D8+ (Pin 73): D8 True Output Bit. DRGND (Pins 48, 53, 61, 67, 74, 82): Digital Output Driver Ground. D9+ (Pin 77): D9 True Output Bit. D0- (Pin 49): D0 Complement Output Bit (LSB). D10- (Pin 78): D10 Complement Output Bit. D0+ (Pin 50): D0 True Output Bit (LSB). D10+ (Pin 79): D10 True Output Bit. D1- (Pin 51): D1 Complement Output Bit. D11- (Pin 80): D11 Complement Output Bit (MSB). D1+ (Pin 52): D1 True Output Bit. D11+ (Pin 81): D11 True Output Bit (MSB). D2- (Pin 55): D2 Complement Output Bit. OR- (Pin 84): Overrange Output Complement. D2+ (Pin 56): D2 True Output Bit. OR+ (Pin 85): Overrange Output True. D3- (Pin 57): D3 Complement Output Bit. GND (Exposed Pads): The exposed pads on the bottom of the package need to be soldered to Analog Ground. D9- (Pin 76): D9 Complement Output Bit. TIMING DIAGRAM tAP ANALOG INPUT N+4 N+2 N N+3 tH N+1 tL CLK– CLK+ tD N–5 D0-D11, OR DCO– DCO+ N–4 N–3 N–2 N–1 tC 2220 TD01 2220aaf 6 LTM2220-AA APPLICATIONS INFORMATION DYNAMIC PERFORMANCE Lower and Upper –3dB Frequencies Signal-to-Noise Plus Distortion Ratio The input frequencies at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. Note that the analog input has a bandpass response. The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Signal-to-Noise Ratio The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to Total Harmonic Distortion (THD). IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodulation distortion is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product. Spurious Free Dynamic Range (SFDR) Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal. Aperture Delay Time The time from when a rising CLK+ equals the CLK– voltage to the instant that the input signal is held by the sample and hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = –20log (2π • fIN • tJITTER) CONVERTER OPERATION The LTM2220-AA is a CMOS pipelined multistep converter. The converter has five pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially. For cost sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. The clock input is differential for improved common mode noise immunity. The LTM2220-AA is pin compatible with the AD9430 when used with LVDS outputs, 2’s complement output format and the 1.536VPP input range. The LTM2220-AA package contains power supply bypass capacitors, which makes the part easy to use since it is insensitive to the PC board layout. 2220aaf 7 LTM2220-AA APPLICATIONS INFORMATION SAMPLE/HOLD OPERATION AND INPUT DRIVE Input Drive Impedance Sample/Hold Operation As with all high performance, high speed ADCs, the dynamic performance of the LTM2220-AA can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and input reactance can influence SFDR. Figure 1 shows an equivalent circuit for the LTM2220-AA CMOS differential sample-and-hold. The analog inputs are AC coupled to the sample and hold circuit through 0.1µF capacitors and 1k bias resistors. The 25Ω resistor and 0.5pF capacitor serve two purposes: isolating the drive circuitry from the sample and hold charging glitches and limiting the wideband noise at the converter input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. Single-Ended Input Input Drive Circuits For cost sensitive applications, the analog inputs can be driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and DNL will remain unchanged. Figure 2 shows the LTM2220-AA being driven by an RF transformer with a center tapped secondary. The secondary center tap is grounded as shown, but it can also be connected to any DC bias voltage from 0V to 3.6V. Terminating on the transformer secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. Common Mode Bias For optimal performance the analog inputs should be driven differentially. Each input should swing ±0.384V around a common mode voltage of between 0V and 3.6V. LTM2220-AA VDD 0.1µF 25Ω VIN+ 15Ω VDD 0.5pF 0.1µF 25Ω VIN– 1k 15Ω CSAMPLE 1.6pF CSAMPLE 1.6pF Driving the Clock Inputs The noise performance of the LTM2220-AA can depend on the encode signal quality as much as on the analog input. The CLK+/CLK– inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. Each input is biased through a 6k resistor to a 1.6V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. 1k 0.1µF ANALOG INPUT VDD T1 1:1 VIN+ 25Ω VREF LTM2220-AA 1.6V 25Ω VIN– 6k T1 = M/A-COM ETC1-1T OR EQUIVALENT CLK+ 2220 F02 Figure 2. Single-Ended to Differential Conversion Using a Transformer CLK– 6k 1.6V 2220 F01 Figure 1. Equivalent Input Circuit 2220aaf 8 LTM2220-AA APPLICATIONS INFORMATION Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. Maximum and Minimum Encode Rates 1. Differential drive should be used. The maximum encode rate for the LTM2220-AA is 170Msps. For the ADC to operate properly, the encode signal should have a 50% (±20%) duty cycle. Each half cycle must have at least 2ns for the ADC internal circuitry to have enough settling time for proper operation. 2. Use as large an amplitude as possible; if transformer coupled use a higher turns ratio to increase the amplitude. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the PLL to lock onto the input clock. 3. If the ADC is clocked with a sinusoidal signal, filter the encode signal to reduce wideband noise. The lower limit of the LTM2220-AA sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTM2220-AA is 1Msps. In applications where jitter is critical (high input frequencies) take the following into consideration: 4. Balance the capacitance and series resistance at both encode inputs so that any coupled noise will appear at both inputs as common mode noise. The clock inputs have a common mode range of 1.1V to 2.5V. Each input may be driven from ground to VDD for single-ended drive. CLK+ VTHRESHOLD = 1.6V 1.6V CLK– LTM2220-AA VDD LTM2220-AA 0.1µF TO INTERNAL ADC CIRCUITS VDD 2220 F04 Figure 4. Single-Ended CLK Drive, Not Recommended for Low Jitter 1.6V BIAS 6k 3.3V CLK+ 0.1µF MC100LVELT22 1:4 CLOCK INPUT VDD 50Ω 1.6V BIAS 3.3V 130Ω Q0 130Ω CLK+ D0 6k CLK– LTM2220-AA Q0 CLK– 83Ω 83Ω 2220 F05 2220 F03 Figure 3. Transformer Driven CLK+/CLK– Figure 5. CLK Drive Using a CMOS to PECL Translator 2220aaf 9 LTM2220-AA APPLICATIONS INFORMATION DIGITAL OUTPUTS Output Clock Table 1. Output Codes vs Input Voltage The ADC has a delayed version of the CLK+ input available as a digital output, DCO. The DCO pin can be used to synchronize the converter data to the digital system. This is necessary when using a sinusoidal clock. Data will be updated as DCO+/DCO– rises and can be latched on the falling edge of DCO+/DCO–. VIN+ – VIN– OR D11 – D0 >+0.768000V +0.768000V +0.767625V 1 0 0 0111 1111 1111 0111 1111 1111 0111 1111 1110 +0.000375V 0.000000V –0.000375V –0.000750V 0 0 0 0 0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110 –0.767625V –0.768000V <–0.768000V 0 0 1 1000 0000 0001 1000 0000 0000 1000 0000 0000 Digital Output Buffers Figure 6 shows an equivalent circuit for a differential output pair in the LVDS output mode. A 3.5mA current is steered from OUT+ to OUT– or vice versa which creates a ±350mV differential voltage across the 100Ω termination resistor at the LVDS receiver. A feedback loop regulates the common mode output voltage to 1.25V. For proper operation each LVDS output pair needs an external 100Ω termination resistor, even if the signal is not used (such as OR+/OR– or DCO+/DCO–). To minimize noise the PC board traces for each LVDS output pair should be routed close together. To minimize clock skew all LVDS PC board traces should have about the same length. Data Format The LTM2220-AA parallel digital output has 2’s complement format. Table 1 shows the relationship between the analog input voltage, the digital data bits and the overrange bit. LTM2220-AA DRVDD Output Driver Power Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. DRVDD should be connected to a 3.3V supply and DRGND should be connected to GND. GROUNDING AND BYPASSING The LTM2220-AA requires a printed circuit board with a clean unbroken ground plane. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital signal alongside an analog signal or underneath the ADC. The LTM2220-AA differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. The LTM2220-AA package contains power supply bypass capacitors on AVDD and DRVDD. External bypass capacitors can be added for additional low-frequency noise rejection, but they are not required if the power supplies come from quiet linear voltage regulators. HEAT TRANSFER D + D OUT+ – 10k 10k 100Ω 1.25V OUT– D D 3.5mA DRGND LVDS RECEIVER Most of the heat generated by the LTM2220-AA is transferred from the die through the bottom-side exposed pads and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pads should be soldered to a large grounded pad on the PC board. It is critical that all ground pins are connected to a ground plane of sufficient area. 2220 F06 Figure 6. Digital Output 2220aaf 10 LTM2220-AA PACKAGE DESCRIPTION SiPLGA Package 100-Lead (16mm × 16mm) 6.000 5.500 5.000 4.500 4.000 3.500 3.000 2.500 2.000 1.500 1.000 0.500 0.000 0.500 1.000 1.500 2.000 2.500 3.000 3.500 4.000 4.500 5.000 5.500 6.000 (Reference LTC DWG # 05-08-1802 Rev Ø) 26 aaa Z 25 4 X Y PAD 1 CORNER 3.1245 1.045 3.1245 1.045 51 6.000 5.500 5.000 4.500 4.000 3.500 3.000 2.500 2.000 1.500 1.000 0.500 0.000 0.500 1.000 1.500 2.000 2.500 3.000 3.500 4.000 4.500 5.000 5.500 6.000 15.90 – 16.10 (2X) 50 3.1245 3.1245 1.045 1.045 1.045 1.045 3.1245 3.1245 3.1245 1.045 1.045 3.1245 15.9 – 16.1 75 1 aaa Z 100 DETAILED PAD LAYOUT 1.93 – 2.13 0.315 – 0.385 0.218 – 0.278 (b) (2X) 76 TOP VIEW 11.90 – 12.10 eee M X Y 26 50 ROWS AF 0.05 – 0.15 25 51 1.120 – 1.180 1.313 – 1.383 PAD AE AD AC AB AA Y W V 0.5 BASIC DETAIL B U T S R 11.90 – 12.10 P N M L K J MOLD CAP SUBSTRATE H G F E D 0.33 – 0.43 C 1.60 – 1.70 Z bbb Z 1 5 75 DETAIL B B A 100 DETAIL A DETAIL A COLUMNS 1 76 3 2 5 4 7 6 9 8 11 10 13 12 15 14 17 16 19 18 21 20 23 22 3 25 24 26 BOTTOM VIEW NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3 LAND DESIGNATION PER JESD MO-222, SPP-010 4 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE 5 PRIMARY DATUM -Z- IS SEATING PLANE SYMBOL TOLERANCE 0.10 aaa 0.10 bbb 0.03 eee 10_10_06 6. DIMENSION (b) IS MEASURED AT THE MAXIMUM LAND WIDTH, PARALLEL TO PRIMARY DATUM -Z7. TOTAL NUMBER OF PADS: 104 TOTAL (100 PERIPHERAL + 4 COMMON CENTER) 2220aaf Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 11 LTM2220-AA RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC2220 12-Bit, 170Msps, 3.3V ADC, LVDS Outputs 890mW, 67.7dB SNR, 84dB SFDR, 64-Pin QFN Package LTC2242-12 12-Bit, 250Msps, 2.5V ADC, LVDS Outputs 740mW, 65.4dB SNR, 84dB SFDR, 64-Pin QFN Package LT1993-2 High Speed Differential Op Amp 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain 2220aaf 12 Linear Technology Corporation LT 0107 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2007