M62370GP 3 V Type 8-bit 36ch Selector SW Built-in D/A Converter with Buffer Amplifiers REJ03D0879-0300 Rev.3.00 Mar 25, 2008 Description The M62370GP is a CMOS semiconductor IC, containing 36 channels of 8-bit D/A converters. It is operable with a low supply voltage between 2.7 to 3.6 V, and is easy to use due to serial data input, and 3-pin (DI, CLK, LD) connection with microcomputer. The IC also contains DO pin terminal, enabling cascade connection, and therefore is suitable for automatic control in combination with a microcomputer. Features • • • • Operable with a low voltage between 2.7 to 3.6 V 16-bit serial data input (connected via 3 pins: DI, CLK, LD) 36 channels built-in of 8-bit D/A converter 6 channels of D/A converters capable of selecting and outputting 4 data stored in each converter, through 2 control terminals Application Digital/analog conversion in industrial or home-use electronic equipment. Automatic control in combination with EEPROM and microcomputer (Substitute for conventional semi-fixed resistor). Block Diagram CLK 2 DI 1 VCC GND 29 5 16-bit shift register D15 D14 D13 D12 D11 D10 D9 D8 VSS1 7 ............. D/A ............. 38 AO1 8-bit latch × 4 8-bit latch × 4 ............. D/A D/A ............. 21 ............. AO24 REJ03D0879-0300 Rev.3.00 Mar 25, 2008 Page 1 of 8 ............. + − ............. + − D/A 8-bit latch × 4 + − 8 + − VDD1 Decoder ............. DO 3 LD 6 C0 D5 D4 D3 D2 D1 D0 8 8-bit latch 4 36 37 AO35 AO36 Data control 30 C1 31 32 VDD2 VSS2 M62370GP Pin Arrangement AO11 AO10 AO9 AO8 AO7 AO6 AO5 AO4 AO3 AO2 AO1 AO36 48 47 46 45 44 43 42 41 40 39 38 37 M62370GP AO31 AO13 10 27 AO30 AO14 11 26 AO29 AO15 12 25 AO28 24 28 AO27 AO12 9 23 VCC AO26 29 22 VDD1 8 21 C1 AO25 30 20 VSS1 7 AO24 VDD2 AO23 31 19 C0 6 AO22 VSS2 18 32 AO21 GND 5 17 AO32 AO20 AO33 33 16 34 Do 4 AO19 LD 3 15 AO34 AO18 35 14 CLK 2 AO17 AO35 13 36 AO16 DI 1 (Top view) Outline: 48P6D-A Pin Description Pin No. 1 4 2 3 38 to 48 9 to 28 33 to 37 29 5 6 30 8 Pin Name DI DO CLK Function Serial data input terminal to input serial data of 16-bit length Terminal to output MSB data of 16-bit shift register LD When H-level signal is input to this terminal, the value stored in 16-bit shift register is loaded in decoder and D/A converter output register. 8-bit D/A converter output terminal AO1 to AO11 AO12 to AO31 AO32 to AO36 VCC GND C0 C1 VDD1 7 31 VSS1 VDD2 32 VSS2 Shift clock input terminal. Input signal at DI pin is input to 16-bit shift register at rise of shift clock pulse Power supply terminal GND terminal Data select signal input terminal 1 for channel No.31 through 36 Data select signal input terminal 2 for channel No.31 through 36 Upper reference voltage input terminal and power supply to operational amplifier for channel No.1 through 24 Lower reference voltage input terminal for channel No.1 through 24 Upper reference voltage input terminal and power supply to operational amplifier for channel No.25 through 36 Lower reference voltage input terminal for channel No.25 through 36 REJ03D0879-0300 Rev.3.00 Mar 25, 2008 Page 2 of 8 M62370GP Block Diagram for Explanation of Terminals VCC GND 5 29 CLK 2 16-bit shift register DI 1 D15 D14 D13 D12 D11 D10 D9 D8 D7 4 Do D6 D5 D4 D3 D2 D1 D0 3 LD Address decoder (8) ....................................... 1 2 3 4 (4) 6 C0 ............. 1 VDD1 8 VSS1 7 ............. 8-bit latch .......... 30 8-bit latch 8-bit D/A converter .......... 8-bit D/A converter ............. ........ 31 8-bit latch × 4 selector .......... 8-bit D/A converter ........ 36 8-bit latch × 4 selector .......... 8-bit D/A converter 28 AO31 30 C1 + − 27 AO30 Data control ............. (4) + − + − + − 38 AO1 (4) 37 AO36 31 VDD2 32 VSS2 Absolute Maximum Ratings (Ta = 25°C, unless otherwise noted.) Item Supply voltage Upper reference voltage of D/A converter Input voltage Output voltage Power dissipation Terminal derating Operating temperature Storage temperature REJ03D0879-0300 Rev.3.00 Mar 25, 2008 Page 3 of 8 Symbol VCC VDD VIN VO Pd Kθ Topr Tstg Ratings –0.3 to +7.0 –0.3 to +7.0 –0.3 to VCC + 0.3 –0.3 to VCC + 0.3 400 4 –20 to +85 –40 to +125 Unit V V V V mW mW/°C °C °C Conditions Ta ≥ 25°C M62370GP Electrical Characteristics <Digital Part> (VCC = +3 V ± 10%, VCC = VDD, Ta = –20 to +85°C, unless otherwise noted.) Min Limits Typ Max Unit Supply voltage Circuit current VCC ICC 2.7 — 3.0 1.0 5.5 — V mA Input leak current Input low voltage Input high voltage Output low voltage Output high voltage IILK VIL VIH VOL VOH –10 — 2.4 — VCC – 0.4 — — — — — 10 0.6 — 0.4 — µA V V V V Item Note: Symbol Conditions CLK = 1 MHz operation, VCC = 3 V, IAO = 0 µA IOL = 2.5 mA IOH = –400 µA Standard value is at Ta = 25°C <Analog Part> (VCC = +3 V ± 10%, VCC = VDD, Ta = –20 to +85°C, unless otherwise noted.) Item Symbol Min Limits Typ Max Unit Current dissipation IDD D/A converter upper reference voltage range VDD — 2.7 5.0 3.0 — 5.5 mA V D/A converter lower reference voltage range VSS GND — VDD – 2 V Buffer amplifier output voltage range VAO 0.1 0.2 — — VDD – 0.1 VDD – 0.2 V V Buffer amplifier output driving range IAO –300 — 500 µA Differential nonlinearity error Nonlinearity error Zero code error Full scale error Output capacitive load SDL –1.0 — 1.0 LSB SL SZERO SFULL CO –1.5 –2 –2 — — — — — — 50 1.5 2 2 0.1 — LSB LSB LSB µF Ω Buffer amplifier output impedance RO REJ03D0879-0300 Rev.3.00 Mar 25, 2008 Page 4 of 8 Conditions IAO = ±100 µA IAO = +300 µA –200 µA Upper saturation voltage = 0.4 V Lower saturation voltage = 0.3 V VCC = 2.700 V VDD = 2.700 V VSS = 0.050 V No load (IAO = ±0) M62370GP AC Characteristics (VCC = VDD, Ta = –20 to +85°C, unless otherwise noted.) Item Symbol Clock "L" pulse width Clock "H" pulse width Clock rise time Clock fall time Data setup time Data hold time LD setup time LD hold time LD "H" pulse duration time Data output delay time tCKL tCKH tCR tCF tDCH tCHD tCHL tLDC tLDH tDO D/A converter output setting time tLDD Min Limits Typ Max Unit 200 200 — — 30 60 200 100 100 70 — — — — — — — — — — — — — — 200 200 — — — — — 350 100 ns ns ns ns ns ns ns ns ns ns µs Conditions CL = 100 pF CL ≤ 100 pF, VAO: 0.3 ↔ 2.7 V This time until the output becomes the final value of ±2 LSB Timing Chart tCR tCKH tCF CLK tCKL DI tDCH tLDC tCHD tLDH tCHL LD tLDD D/A output tDO DO output REJ03D0879-0300 Rev.3.00 Mar 25, 2008 Page 5 of 8 M62370GP Digital Data Format First LSB D0 D1 D2 D3 D4 D5 D6 D7 D8 DAC select data D9 D10 D11 D12 D13 D14 DAC data DAC Data D8 0 1 0 1 : 0 1 D9 0 0 1 1 : 1 1 Note: D10 0 0 0 0 : 1 1 D11 0 0 0 0 : 1 1 D12 0 0 0 0 : 1 1 D13 0 0 0 0 : 1 1 D14 0 0 0 0 : 1 1 D15 0 0 0 0 : 1 1 D/A Output (VrefU – VrefL) / 256 × 1 + VrefL (VrefU – VrefL) / 256 × 2 + VrefL (VrefU – VrefL) / 256 × 3 + VrefL (VrefU – VrefL) / 256 × 4 + VrefL : (VrefU – VrefL) / 256 × 255 + VrefL VrefU VrefU = VDD1, VDD2, VrefL = VSS1, VSS2 DAC Select Data D5 0 0 0 : 0 0 1 : 1 1 : 1 1 : 1 1 : 1 1 D4 0 0 0 : 1 1 0 : 0 0 : 0 0 : 1 1 : 1 1 D3 0 0 0 : 1 1 0 : 0 0 : 1 1 : 0 0 : 0 0 D2 0 0 0 : 1 1 0 : 1 1 : 0 0 : 0 0 : 1 1 D1 0 0 1 : 1 1 0 : 0 0 : 1 1 : 0 0 : 1 1 D0 0 1 0 : 0 1 0 : 0 1 : 0 1 : 0 1 : 0 1 : 1 : 1 : 1 : 1 : 1 : 1 C0 0 0 1 1 C1 0 1 0 1 REJ03D0879-0300 Rev.3.00 Mar 25, 2008 Page 6 of 8 DAC Selection Don't care AO1 selection AO2 selection : AO30 selection AO31 (0) selection AO32 (0) selection : AO36 (0) selection AO31 (1) selection : AO36 (1) selection AO31 (2) selection : AO36 (2) selection AO31 (3) selection : AO36 (3) selection Don't care : Don't care AO31 Through AO36 Data Selected Address 0 selected Address 1 selected Address 2 selected Address 3 selected Last MSB D15 M62370GP Timing Chart (Model) LSB DI D0 MSB D1 CLK LD D/A output REJ03D0879-0300 Rev.3.00 Mar 25, 2008 Page 7 of 8 D2 D3 ............. .................. D13 D14 D15 M62370GP Package Dimensions 48P6D-A Plastic 48pin 7 × 7mm body LQFP EIAJ Package Code LQFP48-P-77-0.50 Weight(g) 0.18 Lead Material Alloy 42 MD ME e JEDEC Code — b2 HD D 48 37 1 I2 Recommended Mount Pad 36 E HE Symbol 25 12 13 24 A F L1 A3 A2 e A A1 A2 b c D E e HD HE L L1 Lp b x M REJ03D0879-0300 Rev.3.00 Mar 25, 2008 Page 8 of 8 L Detail F Lp c y A1 A3 x y b2 I2 MD ME Dimension in Millimeters Min Nom Max — — 1.7 0.1 0.2 0 1.4 — — 0.13 0.18 0.28 0.105 0.125 0.175 6.9 7.0 7.1 6.9 7.0 7.1 — 0.5 — 8.8 9.0 9.2 8.8 9.0 9.2 0.3 0.5 0.7 — — 1.0 0.45 0.6 0.75 0.25 — — 0.08 — — 0.1 — — 0° 10° — — — 0.225 — — 1.0 — — 7.4 7.4 — — Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. 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