June 15, 2009 DS92LV010AEP Bus LVDS 3.3/5.0V Single Transceiver General Description Features The DS92LV010AEP is one in a series of transceivers designed specifically for the high speed, low power proprietary bus backplane interfaces. The device operates from a single 3.3V or 5.0V power supply and includes one differential line driver and one receiver. To minimize bus loading the driver outputs and receiver inputs are internally connected. The logic interface provides maximum flexibility as 4 separate lines are provided (DIN, DE, RE, and ROUT). The device also features flow through which allows easy PCB routing for short stubs between the bus pins and the connector. The driver has 10 mA drive capability, allowing it to drive heavily loaded backplanes, with impedance as low as 27 Ohms. The driver translates between TTL levels (single-ended) to Low Voltage Differential Signaling levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition the differential signaling provides common mode noise rejection of ±1V. The receiver threshold is ±100mV over a ±1V common mode range and translates the low voltage differential levels to standard (CMOS/TTL) levels. ENHANCED PLASTIC ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ • • • • • • Bus LVDS Signaling (BLVDS) Designed for Double Termination Applications Balanced Output Impedance Lite Bus Loading 5pF typical Glitch free power up/down (Driver disabled) 3.3V or 5.0V Operation ±1V Common Mode Range ±100mV Receiver Sensitivity High Signaling Rate Capability (above 100 Mbps) Low Power CMOS design Product offered in 8 lead SOIC package Applications Selected Military Applications Selected Avionics Applications Extended Temperature Performance of -40°C to +85°C Baseline Control - Single Fab & Assembly Site Process Change Notification (PCN) Qualification & Reliability Data Solder (PbSn) Lead Finish is standard Enhanced Diminishing Manufacturing Sources (DMS) Support Ordering Information PART NUMBER VID PART NUMBER NS PACKAGE NUMBER (Note 3) DS92LV010ATMEP V62/04740-01 M08A (Notes 1, 2) TBD TBD Note 1: For the following (Enhanced Plastic) version, check for availability: - DS92LV010ATMXEP Parts listed with an "X" are provided in Tape & Reel and parts without an "X" are in Rails. Note 2: FOR ADDITIONAL ORDERING AND PRODUCT INFORMATION, PLEASE VISIT THE ENHANCED PLASTIC WEB SITE AT: www.national.com/ mil Note 3: Refer to package details under Physical Dimensions Connection Diagram 20119301 See NS Package Number M08A TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2009 National Semiconductor Corporation 201193 201193 Version 3 Revision 1 www.national.com Print Date/Time: 2009/06/15 11:42:19 DS92LV010AEP Bus LVDS 3.3/5.0V Single Transceiver OBSOLETE DS92LV010AEP Block Diagram 20119302 www.national.com 2 201193 Version 3 Revision 1 Print Date/Time: 2009/06/15 11:42:19 If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) Enable Input Voltage (DE, RE) Driver Input Voltage (DIN) Receiver Output Voltage (ROUT) Bus Pin Voltage (DO/RI±) Driver Short Circuit Current 6.0V DS92LV010AEP Derate SOIC Package Storage Temperature Range Lead Temperature (Soldering, 4 sec.) Absolute Maximum Ratings (Notes 4, 5) 8.2 mW/°C −65°C to +150°C 260°C Recommended Operating Conditions −0.3V to (VCC + 0.3V) −0.3V to (VCC + 0.3V) −0.3V to (VCC + 0.3V) −0.3V to + 3.9V Continuous >2.0 kV ESD (HBM 1.5 kΩ, 100 pF) Maximum Package Power Dissipation at 25°C SOIC 1025 mW Supply Voltage (VCC), or Supply Voltage (VCC) Receiver Input Voltage Operating Free Air Temperature Min 3.0 4.5 0.0 −40 Max 3.6 5.5 2.9 +85 Units V V V °C DC Electrical Characteristics (Notes 5, 6, 12) TA = −40°C to +85°C unless otherwise noted, VCC = 3.3V ± 0.3V Symbol Parameter Conditions RL = 27Ω, Figure 1 VOD Output Differential Voltage ΔVOD VOD Magnitude Change VOS Offset Voltage ΔVOS Offset Magnitude Change IOSD Output Short Circuit Current VO = 0V, DE = VCC VOH Voltage Output High VID = +100 mV Pin Min Typ Max Units DO+/RI+, DO−/RI− 140 250 360 mV 3 30 mV 1.25 1.65 V 5 50 mV −12 −20 mA 1 2.8 3 V Inputs Open I OH = −400 µA 2.8 3 V Inputs Shorted 2.8 3 V Inputs Terminated, RL = 27Ω 2.8 3 V 0.1 0.4 V −5 −35 −85 mA +100 mV VOL Voltage Output Low IOL = 2.0 mA, VID = −100 mV IOS Output Short Circuit Current VOUT = 0V, VID = +100 mV VTH Input Threshold High DE = 0V VTL Input Threshold Low IIN Input Current R OUT DO+/RI+, DO−/RI− −100 mV DE = 0V, VIN = +2.4V, or 0V −20 ±1 +20 µA VCC = 0V, VIN = +2.4V, or 0V −20 ±1 +20 µA 2.0 VCC V GND 0.8 V ±1 ±10 µA ±1 ±10 µA VIH Minimum Input High Voltage VIL Maximum Input Low Voltage DIN, DE, RE IIH Input High Current VIN = VCC or 2.4V IIL Input Low Current VIN = GND or 0.4V VCL Input Diode Clamp Voltage ICLAMP = −18 mA ICCD Power Supply Current DE = RE = VCC , RL = 27Ω −1.5 V CC −0.8 13 V 20 mA ICCR DE = RE = 0V 5 8 mA ICCZ DE = 0V, RE = VCC 3 7.5 mA 16 22 mA DE = VCC, RE = 0V, RL = 27Ω ICC Coutput Capacitance @ BUS Pins DO+/RI+, DO−/RI− 3 201193 Version 3 Revision 1 Print Date/Time: 2009/06/15 11:42:19 5 pF www.national.com DS92LV010AEP DC Electrical Characteristics (Notes 5, 6, 12) TA = −40°C to +85°C unless otherwise noted, VCC = 5.0V ± 0.5V Symbol Parameter Conditions RL = 27Ω, Figure 1 VOD Output Differential Voltage ΔVOD VOD Magnitude Change VOS Offset Voltage ΔVOS Offset Magnitude Change IOSD Output Short Circuit Current VO = 0V, DE = VCC VOH Voltage Output High VID = +100 mV Pin Min Typ Max Units DO+/RI+, DO−/RI− 145 270 390 mV 3 30 mV 1.35 1.65 V 5 50 mV −12 −20 mA 1 4.3 5.0 V Inputs Open IOH = −400 µA 4.3 5.0 V Inputs Shorted 4.3 5.0 V Inputs Terminated, RL = 27Ω 4.3 5.0 VOL Voltage Output Low IOL = 2.0 mA, VID = −100 mV IOS Output Short Circuit Current VOUT = 0V, VID = +100 mV VTH Input Threshold High DE = 0V VTL Input Threshold Low IIN Input Current VIH Minimum Input High Voltage VIL Maximum Input Low Voltage IIH Input High Current VIN = VCC or 2.4V IIL ROUT −35 DO+/RI+, DO−/RI− VCC = 0V, VIN = +2.4V, or 0V Input Low Current VIN = GND or 0.4V VCL Input Diode Clamp Voltage ICLAMP = −18 mA ICCD Power Supply Current DE = RE = VCC, RL = 27Ω 0.4 V −90 −130 mA +100 mV −100 DE = 0V, VIN = +2.4V, or 0V DIN, DE, RE V 0.1 mV −20 ±1 −20 ±1 2.0 GND −1.5 V CC +20 µA +20 µA VCC V 0.8 V ±1 ±10 µA ±1 ±10 µA −0.8 V 17 25 mA ICCR DE = RE = 0V 6 10 mA ICCZ DE = 0V, RE = VCC 3 8 mA 20 25 mA DE = VCC, RE = 0V, RL = 27Ω ICC Coutput Capacitance @ BUS Pins DO+/RI+, DO−/RI− AC Electrical Characteristics 5 pF (Notes 9, 12) TA = −40°C to +85°C, VCC = 3.3V ± 0.3V Symbol Parameter Conditions Min Typ Max Units 1.0 3.0 5.0 ns 1.0 DIFFERENTIAL DRIVER TIMING REQUIREMENTS RL = 27Ω, Figures 2, 3 CL = 10 pF tPHLD Differential Prop. Delay High to Low tPLHD Differential Prop. Delay Low to High 2.8 5.0 ns tSKD Differential SKEW |t PHLD - tPLHD| 0.2 1.0 ns tTLH Transition Time Low to High 0.3 2.0 ns tTHL Transition Time High to Low 0.3 2.0 ns tPHZ Disable Time High to Z tPLZ Disable Time Low to Z tPZH tPZL RL = 27Ω, Figures 4, 5 CL = 10 pF 0.5 4.5 9.0 ns 0.5 5.0 10.0 ns Enable Time Z to High 2.0 5.0 7.0 ns Enable Time Z to Low 1.0 4.5 9.0 ns DIFFERENTIAL RECEIVER TIMING REQUIREMENTS www.national.com 4 201193 Version 3 Revision 1 Print Date/Time: 2009/06/15 11:42:19 Parameter Conditions Figures 6, 7 CL = 10 pF Min Typ Max Units 2.5 5.0 12.0 ns 2.5 5.5 10.0 ns tPHLD Differential Prop. Delay High to Low tPLHD Differential Prop. Delay Low to High tSKD Differential SKEW |t PHLD - tPLHD| 0.5 2.0 ns tr Rise Time 1.5 4.0 ns tf Fall Time tPHZ Disable Time High to Z tPLZ Disable Time Low to Z tPZH Enable Time Z to High tPZL Enable Time Z to Low RL = 500Ω, Figures 8, 9 CL = 10 pF (Note 11) AC Electrical Characteristics 1.5 4.0 ns 2.0 4.0 6.0 ns 2.0 5.0 7.0 ns 2.0 7.0 13.0 ns 2.0 6.0 10.0 ns Min Typ Max Units 0.5 2.7 4.5 ns 0.5 (Notes 9, 12) TA = −40°C to +85°C, VCC = 5.0V ± 0.5V Symbol Parameter Conditions DIFFERENTIAL DRIVER TIMING REQUIREMENTS RL = 27Ω, Figures 2, 3 CL = 10 pF tPHLD Differential Prop. Delay High to Low tPLHD Differential Prop. Delay Low to High 2.5 4.5 ns tSKD Differential SKEW |t PHLD - tPLHD| 0.2 1.0 ns tTLH Transition Time Low to High 0.3 2.0 ns tTHL Transition Time High to Low 0.3 2.0 ns tPHZ Disable Time High to Z 0.5 3.0 7.0 ns tPLZ Disable Time Low to Z 0.5 5.0 10.0 ns tPZH Enable Time Z to High 2.0 4.0 7.0 ns tPZL Enable Time Z to Low 1.0 4.0 9.0 ns 2.5 5.0 12.0 ns 2.5 4.6 10.0 ns RL = 27Ω, Figures 4, 5 CL = 10 pF DIFFERENTIAL RECEIVER TIMING REQUIREMENTS tPHLD Differential Prop. Delay High to Low tPLHD Differential Prop. Delay Low to High Figures 6, 7 CL = 10 pF tSKD Differential SKEW |t PHLD - tPLHD| 0.4 2.0 ns tr Rise Time 1.2 2.5 ns tf Fall Time tPHZ Disable Time High to Z tPLZ Disable Time Low to Z tPZH Enable Time Z to High tPZL Enable Time Z to Low RL = 500Ω, Figures 8, 9 CL = 10 pF (Note 11) 1.2 2.5 ns 2.0 4.0 6.0 ns 2.0 4.0 6.0 ns 2.0 5.0 9.0 ns 2.0 5.0 7.0 ns 5 201193 Version 3 Revision 1 Print Date/Time: 2009/06/15 11:42:19 www.national.com DS92LV010AEP Symbol DS92LV010AEP Electrical Characteristics Note 4: “Absolute Maximum Ratings” are these beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Note 5: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground except VOD, VID, VTH and VTL unless otherwise specified. Note 6: All typicals are given for VCC = +3.3V or 5.0 V and TA = +25°C, unless otherwise stated. Note 7: ESD Rating: HBM (1.5 kΩ, 100 pF) > 2.0 kV EAT (0Ω, 200 pF) > 300V. Note 8: CL includes probe and fixture capacitance. Note 9: Generator waveforms for all tests unless otherwise specified: f = 1MHz, ZO = 50Ω, tr, tf ≤ 6.0ns (0%–100%) on control pins and ≤ 1.0ns for RI inputs. Note 10: The DS92LV010AEP is a current mode device and only function with datasheet specification when a resistive load is applied between the driver outputs. Note 11: For receiver TRI-STATE® delays, the switch is set to VCC for tPZL, and tPLZ and to GND for tPZH, and tPHZ. Note 12: "Testing and other quality control techniques are used to the extent deemed necessary to ensure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific PARAMETRIC testing, product performance is assured by characterization and/or design." Test Circuits and Timing Waveforms 20119303 FIGURE 1. Differential Driver DC Test Circuit 20119304 FIGURE 2. Differential Driver Propagation Delay and Transition Time Test Circuit 20119305 FIGURE 3. Differential Driver Propagation Delay and Transition Time Waveforms www.national.com 6 201193 Version 3 Revision 1 Print Date/Time: 2009/06/15 11:42:19 DS92LV010AEP 20119306 FIGURE 4. Driver TRI-STATE Delay Test Circuit 20119307 FIGURE 5. Driver TRI-STATE Delay Waveforms 20119308 FIGURE 6. Receiver Propagation Delay and Transition Time Test Circuit 20119309 FIGURE 7. Receiver Propagation Delay and Transition Time Waveforms 7 201193 Version 3 Revision 1 Print Date/Time: 2009/06/15 11:42:19 www.national.com DS92LV010AEP 20119310 FIGURE 8. Receiver TRI-STATE Delay Test Circuit 20119311 FIGURE 9. Receiver TRI-STATE Delay Waveforms TRI-STATE Delay Waveforms Typical Bus Application Configurations 20119312 Bi-Directional Half-Duplex Point-to-Point Applications 20119313 Multi-Point Bus Applications www.national.com 8 201193 Version 3 Revision 1 Print Date/Time: 2009/06/15 11:42:19 There are a few common practices which should be implied when designing PCB for BLVDS signaling. Recommended practices are: • Use at least 4 layer PCB board (BLVDS signals, ground, power and TTL signals). • Keep drivers and receivers as close to the (BLVDS port side) connector as possible. • Bypass each BLVDS device and also use distributed bulk capacitance. Surface mount capacitors placed close to • • TABLE 1. Functional Table MODE SELECTED DE RE DRIVER MODE H H RECEIVER MODE L L TRI-STATE MODE L H LOOP BACK MODE H L TABLE 2. Transmitter Mode INPUTS OUTPUTS DE DI DO+ DO− H L L H H H H L H 2 > & > 0.8 X X L X Z Z L = Low state H = High state TABLE 3. Receiver Mode INPUTS OUTPUT RE (RI+)-(RI−) L L (< −100 mV) L L H (> +100 mV) H L 100 mV > & > −100 mV X H X Z X = High or Low logic state Z = High impedance state L = Low state H = High state TABLE 4. Device Pin Description Pin Name Pin # Input/Output DIN 2 I Description DO±/RI± 6, 7 I/O LVDS Driver Outputs/LVDS Receiver Inputs ROUT 3 O TTL Receiver Output RE 5 I Receiver Enable TTL Input (Active Low) DE 1 I Driver Enable TTL Input (Active High) GND 4 NA Ground VCC 8 NA Power Supply TTL Driver Input 9 201193 Version 3 Revision 1 Print Date/Time: 2009/06/15 11:42:19 www.national.com DS92LV010AEP power and ground pins work best. Two or three multi-layer ceramic (MLC) surface mount capacitors (0.1 µF, and 0.01 µF in parallel should be used between each VCC and ground. The capacitors should be as close as possible to the VCC pin. Use the termination resistor which best matches the differential impedance of your transmission line. Leave unused LVDS receiver inputs open (floating) Application Information DS92LV010AEP Physical Dimensions inches (millimeters) unless otherwise noted See NS Package Number M08A www.national.com 10 201193 Version 3 Revision 1 Print Date/Time: 2009/06/15 11:42:19 DS92LV010AEP Notes 11 201193 Version 3 Revision 1 Print Date/Time: 2009/06/15 11:42:19 www.national.com DS92LV010AEP Bus LVDS 3.3/5.0V Single Transceiver Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Design Support Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage Reference www.national.com/vref Design Made Easy www.national.com/easy www.national.com/powerwise Solutions www.national.com/solutions Mil/Aero www.national.com/milaero PowerWise® Solutions Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic Wireless (PLL/VCO) www.national.com/wireless www.national.com/training PowerWise® Design University THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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