DS92LV222A Two Channel Bus LVDS MUXed Repeater General Description Features The DS92LV222A is a repeater designed specifically for the bridging of multiple backplanes in a rack. The DS92LV222A utilizes low voltage differential signaling to deliver high speed while consuming minimal power with reduced EMI. The RSEL pin and DE pins allow maximum flexibility as to which receiver/driver are used. The DS92LV222A repeats signals between backplanes and accepts or drives signals onto the local bus. It also features a flow through pin out which allows easy PCB routing for short stubs between its pins and the connector. The driver is selectable between 3.5 mA (100Ω load) and 8.5 mA (27Ω load) output loop currents depending upon the level applied to the ISEL pin. This allows for single termination (point-to-point) and also double termination (multipoint) applications while maintain similar differential levels. The receiver threshold is ± 100 mV, while providing ± 1V common mode range. n n n n n n n n n n n n Bus LVDS Signaling (BLVDS) Designed for Double Termination Applications Low power CMOS design High Signaling Rate Capability (above 100 Mbps) Ultra Low Power Dissipation (13.2 mW quiescent) Balanced Output Impedance Lite Bus Loading 5 pF typical Selectable Drive Capability (3.5 mA or 8.5 mA) 3.3V operation ± 1V Common Mode Range ± 100 mV Receiver Sensitivity Available in 16 pin SOIC package. Connection Diagram DS100055-1 Order Number DS92LV222ATM See NS Package Number M16A Block Diagram DS100055-2 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100055 www.national.com DS92LV222A Two Channel Bus LVDS MUXed Repeater May 1998 Absolute Maximum Ratings (Notes 1, 2) Derate SOIC Package above 25˚C If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) −0.3V to (VCC + 0.3V) Current Select Voltage (ISEL) −0.3V to (VCC + 0.3V) Receiver Select Voltage (RSEL) −0.3V to (VCC + 0.3V) Bus Pin Voltage (DO/RI ± ) (Soldering, 4 sec.) Continuous ESD (HBM 1.5 kΩ, 100 pF) > 2 kV 260˚C Recommended Operating Conditions Min −0.3V to +3.9V Driver Short Circuit Current −65˚C to +150˚C Lead Temperature 6.0V Enable Input Voltage (DE) 8mW/˚C Storage Temperature Range Max Units Supply Voltage (VCC) 3.0 3.6 V Receiver Input Voltage 0.0 2.9 V Operating Free Air Temperature −40 +85 ˚C Maximum Package Power Dissipation at 25˚C SOIC 970 mW DC Electrical Characteristics TA = −40˚C to +85˚C unless otherwise noted, VCC = 3.3V ± 0.3V (Notes 2, 3) Symbol Parameter Conditions Pin Min Typ Max Units 170 220 280 mV 2 10 mV 1.25 1.6 V 10 20 mV 360 480 mV 2 10 mV 1.25 1.6 V 10 20 mV VO = VCC or GND, DE = 0 ±1 ± 10 µA DIFFERENTIAL DRIVER CHARACTERISTICS RL = 27Ω Figure 1 Isel = 0V DO+, DO− VOD Output Differential Voltage ∆VOD VOD Magnitude Change VOS Offset Voltage ∆VOS Offset Magnitude Change VOD Output Differential Voltage ∆VOD VOD Magnitude Change VOS Offset Voltage ∆VOS Offset Magnitude Change IOZD TRI-STATE IOXD Power-Off Leakage VO = 2.9V or GND, VCC = 0V ±1 ± 10 µA IOSD Output Short Circuit Current ISEL = VCC VO = 0V −11 −13 mA +100 mV ® 1.0 RL = 100Ω Figure 1 Isel = 3.3V 250 0.9 Leakage DIFFERENTIAL RECEIVER CHARACTERISTICS VTH Input Threshold High VTL Input Threshold Low IIN Input Current RI+, RI− −100 −10 VIN = +2.9V, or 0V, VCC = 3.6 V or 0 V mV ±1 +10 µA 2.0 VCC V GND 0.8 V ± 10 ± 10 µA DEVICE CHARACTERISTICS VIH Minimum Input High Voltage VIL Maximum Input Low Voltage IIH Input High Current VIN = VCC or 2.4V IIL Input Low Current VIN = GND or 0.4V VCL Input Diode Clamp Voltage ICLAMP = −18 mA www.national.com DE0, DE1, RSEL, ISEL0, ISEL1 ±1 ±1 −1.5 2 −0.8 µA V DC Electrical Characteristics (Continued) TA = −40˚C to +85˚C unless otherwise noted, VCC = 3.3V ± 0.3V (Notes 2, 3) Symbol Parameter Conditions Pin Min Typ Max Units 25 45 mA 24 40 mA 4 8 mA DEVICE CHARACTERISTICS ICCD Power Supply Current No Load; DE = RSEL = VCC Isel = 0 V VCC RL = 27Ω; DE = RSEL = VCC Isel = 0 V ICCZ DE = 0V; RSEL = VCC Cinput Capacitance at RO+/RO- 5 pF Coutput Capacitance at DO+/DO- 5 pF Note 1: “Absolute Maximum Ratings” are these beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. Note 3: All typicals are given for VCC = +3.3V and T A = +25˚C, unless otherwise stated. Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF) > 2 kV EIAJ (0Ω, 200 pF) > 200V Note 5: CL includes probe and fixture capacitance. Note 6: Generator waveforms for all tests unless otherwise specified: f = 1MHz, ZO = 50Ω, tf = < 6.0 ns (0%–100%). Note 7: The DS92LV222A is a current mode device and only functions datasheet specifications when a resistive load is applied to the drivers outputs. Note 8: During receiver select transition(s), data must be held in a steady state 15 ns before and 15 ns after the RSEL pin changes state. Note 9: Channel-to-channel skew is the measurement between outputs of D0 and D1. AC Electrical Characteristics TA = −40˚C to +85˚C, VCC = 3.3V ± 0.3V (Note 6) Symbol Parameter tTLH Transition Time Low to High tTHL Transition Time High to Low tPHZ Disable Time High to Z tPLZ Disable Time Low to Z tPZH Enable Time Z to High tPZL Enable Time Z to Low Min Typ Max Units RL = 27Ω Figures 2, 3 CL = 10 pF Figures 2, 3 Conditions 0.15 0.4 2.0 ns 0.15 0.4 2.0 ns RL = 27Ω Figures 4, 5 CL = 10 pF Figures 4, 5 2.0 6.0 9.0 ns 2.0 6.0 9.0 ns 2.0 6.0 9.0 ns 2.0 6.0 9.0 ns 3.0 7.7 13 ns 3.0 8.0 13 ns 0 0.3 2.0 ns 2.0 7.5 13 ns 2.0 8.0 13 ns DIFFERENTIAL RECEIVER TO DRIVER TIMING REQUIREMENTS tPHL_RD Differential Prop. Delay High to Low tPLH_RD Differential Prop. Delay Low to High tSK_RD Pulse SKEW |t PHL –tPLH| tPHL_RS0 Prop. Delay High to Low tPLH_RS1 Prop. Delay Low to High RL = 27Ω Figures 2, 3 CL = 10 pF Figures 2, 3 RSEL to Driver Outputs RL = 27Ω Figures 6, 7 CL = 10 pF (Note 8) tPHL_R0 Dx Channel-to-Channel Skew R 0 to Dx tPLH_R0 Dx Channel-to-Channel Skew R 0 to Dx tPHL_R1 Dx Channel-to-Channel Skew R 1 to Dx tPLH_R1 Dx Channel-to-Channel Skew R 1 to Dx RL = 27Ω CL = 10 pF (Note 9) 3 0.3 0.8 ns 0.3 0.8 ns 0.3 0.8 ns 0.3 0.8 ns www.national.com Test Circuits and Timing Waveforms DS100055-3 FIGURE 1. Differential Driver DC Test Circuit DS100055-4 FIGURE 2. Differential Receiver to Driver Propagation Delay and Driver Transition Time Test Circuit DS100055-5 FIGURE 3. Differential Receiver to Driver Propagation Delay and Driver Transition Time Waveforms DS100055-6 FIGURE 4. Driver TRI-STATE Delay Test Circuit www.national.com 4 Test Circuits and Timing Waveforms (Continued) DS100055-7 FIGURE 5. Driver TRI-STATE Delay Waveforms DS100055-8 FIGURE 6. Receiver Select to Driver Propagation Delay Test Circuit DS100055-9 FIGURE 7. Receiver Select to Driver Propagation Delay Waveforms Pin Description Pin Name Number of Pins Input/ Output Description RI ± 4 I Bus LVDS Receiver Inputs DO ± 4 O Bus LVDS Driver Outputs RSEL 1 I Receiver Select TTL Input, (see Truth Tables) DE 2 I Driver Enable TTL Input, Active High ISEL 2 I IOL Control Pin (Select High = 3.5 mA (100Ω Load), Select Low = 8.5mA (27Ω Load)) GND 1 NA Ground Reference VCC 1 NA Power Supply Reserved 1 NA Reserved Pin 5 www.national.com Function Select Table DE0 DE1 Receiver Zero ON, Driver Zero ON, Driver One OFF MODE SELECTED H L L Receiver Zero ON, Driver Zero OFF, Driver One ON L H L Receiver One ON, Driver Zero ON, Driver One OFF H L H Receiver One ON, Driver Zero OFF, Driver One ON L H H Receiver Zero ON, Driver Zero ON, Driver One ON H H L Receiver One ON, Driver Zero ON, Driver One ON H H H Driver Zero and Driver One TRI-STATE L L X Truth Table for Receiver Zero INPUTS RSEL Truth Table for Receiver One OUTPUTS INPUTS OUTPUTS DE0 RSEL (RI0+)–(RI0−) DO+ DO− DE1 RSEL (RI1+)–(RI1−) DO+ DO− H L L L H H H L L H H L H H L H H H H L H L 100 mV > & > −100 mV X X H H 100 mV > & > −100 mV X X L X X Z Z L X X Z Z X = High or low logic state Z = High impedance state L = Low state X = High or low logic state Z = High impedance state L = Low state Truth Table for Current Drive Driver Current Drive ISEL0 ISEL1 Driver 0 3.5 mA H X Driver 0 8.5 mA L X Driver 1 3.5 mA X H Driver 1 8.5 mA X L • Applications Information There are few common practices which should be employed when designing PCB for Bus LVDS signaling. Recommended practices are: • Use at least 4 PCB board layer (Bus LVDS signals, ground, power and TTL signals). • Keep drivers and receivers as close to the (Bus LVDS port side) connector as possible. • Bypass each Bus LVDS device and also use distributed bulk capacitance. Surface mount capacitors placed close to power and ground pins work best. Two or three multilayer ceramic (MLC) surface mount capacitors (0.1µ and 0.01 µF in parallel should be used between each VCC and ground. The capacitors should be as close as possible to the VCC pin. Use controlled impedance traces which match the differential impedance of your transmission medium (i.e., Cable) and termination resistor. • • Use the termination resistor which best matches the differential impedance of your transmission line. • • Leave unused Bus LVDS receiver inputs open (floating). Isolate TTL signals from Bus LVDS signals. • • MEDIA (CABLE, CONNECTOR OR BACKPLANE) SELECTION: • Use controlled impedance media. The cables and connectors should have a matched differential impedance. www.national.com 6 Balanced cables (e.g., twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax) for noise reduction and signal quality. There are different types of failsafe situations to consider, these are Open Input, Terminated Input, and other special cases. The first, Open input failsafe occurs when only one receiver is being used (R0 for example). The unused receiver (R1) inputs should be left open for noise minimization. The second case is for terminated inputs. This occurs when the inputs have a low impedance (typically 100 Ohm) termination (R T) across them, and the cable is unplugged. For this case, and if the output state needs to maintain a known state, two external bias resistors may be used to provide a strong common mode bias point. For this a 10K Ohm pull up and pull down resistor may be used to set the output high. Note that R1 and R2 should be much larger ( 2 orders of magnitude) compared to R T to minimize loading effects to the Bus LVDS driver when it is active. Applications Information (Continued) DS100055-10 FIGURE 8. Terminated Input Failsafe Circuit 7 www.national.com DS92LV222A Two Channel Bus LVDS MUXed Repeater Physical Dimensions inches (millimeters) unless otherwise noted Order Number DS92LV222ATM NS Package Number M16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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