NCV7424 Four Channel LIN Transceiver NCV7424 is a four channel physical layer device using the Local Interconnect Network (LIN) protocol. It allows interfacing of four independent LIN physical buses and the LIN protocol controllers. The device is compliant to LIN 2.x Protocol Specification package and the SAE J2602 standard. The NCV7424 LIN device is a member of the in-vehicle networking (IVN) transceiver family. The device is a monolithic solution incorporating 4 times the NCV7321-1 transceiver. It is designed to work in a harsh automotive environment and is qualified following the TS16949 flow. http://onsemi.com 16 1 TSSOP−16 CASE 948F Features • TSSOP16 Package. Pin-out Compatible with One Single LIN • • • • • • • • • • • • NCV7321 Transceiver (Pin Numbers 4 to 7, and 10 to 13) Compliant with LIN2.x, Backwards Compatible to Version 1.3 and J2602 Transmission Rate 1 kbps to 20 kbps Indefinite Short-Circuit Protection on LIN towards Supply and Ground Bus Pins Protected Against Transients in an Automotive Environment Thermal Shutdown System ESD on LIN Pin Exceeding 10 kV, No Need for External ESD Protections Load Dump Protection (45 V) Integrated Slope Control Resulting into Excellent EME Performance also without any Capacitor on LIN Pin Excellent EMI Performance Remote Wake-up via LIN Bus on all Four Channels 3.3 V and 5 V Compatible Digital Inputs These are Pb-Free Devices PACKAGE PICTURE NCV7424 TxD4 RxD3 TxD3 RxD1 EN TxD2 TxD1 RxD2 16 1 TSSOP−16 8 9 RxD4 LIN4 GND LIN3 VBB LIN1 GND LIN2 MARKING DIAGRAM 16 NV74 24−0 ALYWG G 1 NV7424−0 = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (*Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 11 of this data sheet. © Semiconductor Components Industries, LLC, 2013 August, 2013 − Rev. 0 1 Publication Order Number: NCV7424/D NCV7424 BLOCK DIAGRAM NCV7424 VBB Undervoltage POR State & Wake−up Control EN VINT Osc GND Thermal Shutdown Timeouts GND RxD1 COMP Vint Filter Driver Control TxD1 LIN1 Slope Control Channel1 RxD2 TxD2 RxD3 TxD3 RxD4 TxD4 Channel2 LIN2 Channel3 LIN3 Channel4 LIN4 RB20111020.1 Figure 1. Block Diagram http://onsemi.com 2 NCV7424 Table 1. KEY TECHNICAL CHARACTERISTICS AND OPERATING RANGES Symbol VBB Parameter Nominal Battery Operating Voltage (Note 1) Min Typ Max Unit 5 12 27 V Load Dump Protection 45 IBB_SLP Supply Current in Sleep Mode, VBB = 12 V, TJ < 85°C VLINx = VBB 10 30 mA VLIN LIN Bus Voltage −45 45 V V_Dig_IO Operating DC Voltage on Digital IO Pins (EN, RxD1-4, TxD1-4) 0 5.5 V TJ Junction Thermal Shutdown Temperature 150 Tamb Operating Ambient Temperature −40 185 °C 125 °C VESD Electrostatic Discharge Voltage (all pins) Human Body Model (Note 2) Conform to EIA−JESD22−A114−B −4 4 kV Electrostatic Discharge Voltage (LIN) System Human Body Model (Note 3) Conform to EIC 61000−4−2 −10 10 kV 165 1. Below 5 V on VBB in normal mode, the bus will either stay recessive or comply with the voltage level specifications and transition time specifications as required by SAE J2602. It is ensured by the battery monitoring circuit. Above 27 V on VBB, LIN communication is operational (LIN pin toggling) but parameters cannot be guaranteed. For higher battery voltage operation above 27 V, LIN pull-up resistor must be selected large enough to avoid clamping of LIN pin by voltage drop over external pull-up resistor and LIN pin min current limitation. 2. Equivalent to discharging a 100 pF capacitor through a 1.5 kW resistor. 3. Equivalent to discharging a 150 pF capacitor through a 330 W resistor. System HBM levels are verified by an external test−house. Table 2. PIN FUNCTION DESCRIPTION Pin Name 1 TxD4 Transmit Data Input, Low for Dominant State; Pull-up to internal supply guaranteed above pin input threshold Description 2 RxD3 Receive Data Output; Low in Dominant State 3 TxD3 Transmit Data Input, Low for Dominant State; Pull-up to internal supply guaranteed above pin input threshold 4 RxD1 Receive Data Output; Low in Dominant State 5 EN 6 TxD2 Transmit Data Input, Low for Dominant State; Pull-up to internal supply guaranteed above pin input threshold 7 TxD1 Transmit Data Input, Low for Dominant State; Pull-up to internal supply guaranteed above pin input threshold 8 RxD2 Receive Data Output; Low in Dominant State 9 LIN2 LIN Bus Output/Input 10 GND Ground 11 LIN1 LIN Bus Output/Input 12 VBB Battery Supply Input 13 LIN3 LIN Bus Output/Input 14 GND Ground 15 LIN4 LIN Bus Output/Input 16 RxD4 Receive Data Output; Low in Dominant State Enable Input, Transceiver in Normal Operation Mode when High, Pull-down Resistor to GND http://onsemi.com 3 NCV7424 TYPICAL APPLICATION VBAT VBB VCC 2.7 V to 5V 4 5.1k 1k VBB 4 LINx 4 RxDx 4 LINx 4 TxDx Micro 4 controller NCV7424 EN 1nF GND GND GND GND RB 20111103 4 KL30 LIN BUS 1,2,3,4 KL31 Figure 2. Application Diagram, Four LIN Master Nodes Table 3. ABSOLUTE MAXIMUM RATINGS Max Unit VBB Symbol Voltage on Pin VBB Parameter −0.3 Min Typ 45 V VLINx LINx Bus Voltage (LIN1-4) −45 45 V V_Dig_IO DC Input Voltage on Pins (EN, RxD1-4, TxD1-4) −0.3 6 V TJ Maximum Junction Temperature −40 150 °C VESD HBM (All Pins) (Note 4) Conform to EIA−JESD22−A114−B −4 4 kV CDM (All Pins) According to ESD STM 5.3.1−1999 −750 750 V HBM (LINx and VBB) (Note 4) −8 8 kV System HBM (LINx and VBB) (Note 5) Conform to EIC 61000−4−2 −10 10 kV Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. Equivalent to discharging a 100 pF capacitor through a 1.5 kW resistor. 5. Equivalent to discharging a 150 pF capacitor through a 330 W resistor. System HBM levels are verified by an external test−house. http://onsemi.com 4 NCV7424 Table 4. THERMAL CHARACTERISTICS Symbol Parameter Conditions Value Unit RqJA_1 Thermal Resistance Junction−to−Air, JESD51-3 1S0P PCB Free air 128 K/W RqJA_2 Thermal Resistance Junction−to−Air, JESD51-7 2S2P PCB Free air 72 K/W FUNCTIONAL DESCRIPTION Overall Functional Description excellent EMC performance due to reduced slew rate of the LIN outputs. The junction temperature is monitored via a thermal shutdown circuit that switches the LIN transmitters off when temperature exceeds the TSD trigger level. The NCV7424 has four operating states (unpowered mode, standby mode, normal mode and sleep mode) that are determined by the supply voltage VBB, input signals EN and activity on the LIN bus. The operating states and principal transitions between them are depicted in Figure 3. LIN is a serial communication protocol that efficiently supports the control of mechatronic nodes in distributed automotive applications. The domain is class-A multiplex buses with a single master node and a set of slave nodes. The NCV7424 contains four independent LIN transmitters, LIN receivers plus common battery monitoring, power-on-reset (POR) circuits and thermal shutdown (TSD). The used LIN transmitter is optimized for the maximum specified transmission speed of 20 kbps with OPERATING STATES Standby mode Normal mode − LIN Transceivers: OFF − LIN Term: 30 kW − RxD1, 2, 3, 4: Low to indicate wake−up on bus / floating otherwise EN = High for t > tenable − LIN Transceivers: ON − LIN Term: 30 kW − RxD1, 2, 3, 4: Received LIN Data LIN1, 2, 3 or 4 wakeup EN = Low for t > tdisable Unpowered (VBB Below Reset Level) − LIN Transceivers: OFF − LIN Term: Floating − RxD1, 2, 3, 4: Floating EN = High for t > tenable Sleep Mode − LIN Transceivers: OFF − LIN Term: Current Source − RxD1, 2, 3, 4: Floating VBB Above Reset Level Figure 3. State Diagram Unpowered Mode As long as VBB remains below its power-on-reset level, the chip is kept in a safe unpowered state. LIN transmitters are inactive, LINx pins are left floating. Pins RxDx remain floating. The unpowered state will be entered from any other state when VBB falls below its power-on-reset level. sleep mode, the RxD1,2,3 or 4 pin is pulled low depending on which of the respective pins LIN1,2,3 or 4 the valid LIN wake-up occurred. While staying in standby mode, wake-up signaling by RxDx pins on each LIN channel is fully functional. This is also in case if wake event(s) started in sleep mode but actual transition from sleep to standby was caused by preceding wake-up event on other LIN channel. Standby Mode Normal Mode Standby mode is a low-power mode, where the LIN transceivers remain inactive. A 30 kW resistor in series with a reverse-protection diode is internally connected between individual LIN pins and pin VBB. Standby mode is entered after a wake-up event is recognized while the chip was in the In normal mode, the full functionality of the LIN transceivers is available. Data are sent to the LINx bus according to the state of TxDx inputs and RxDx pins reflect the logical symbol received on the LINx bus – high-impedant for recessive and Low level for dominant. http://onsemi.com 5 NCV7424 Normal mode can be entered from either standby or sleep mode when EN Pin is High for longer than tenable. When the transition is made from standby mode, RxDx is put high-impedant immediately after EN becomes High (before the expiration of tenable filtering time). Transmission on each LINx channel is only possible for particular TxDx pin starting from High to Low level (if TxDx pin is Low when entering Normal mode, transmission is not enabled). A 30 kW resistor in series with a reverse-protection diode is internally connected between LIN and VBB pins. To avoid that, due to a failure of the application (e.g. software error, a short to ground, ), the LIN bus is permanently driven dominant and thus blocking all subsequent communication, the signal on each TxDx pin passes through an independent timer per LIN channel, which releases the bus in case TxDx remains Low for longer than tTxD_timeout. The transmission can continue once the TxDx returns to High logical level. This is independent on each channel, means permanent dominant on one channel is not blocking the other channels from communication. In case the junction temperature increases above the thermal shutdown threshold, e.g. due to a short of the LIN wiring to the battery and high ambient temperature, all four transmitters are disabled and LIN buses are kept in recessive state independently of TxDx inputs. RxDx pins are kept Low during thermal shutdown. Once the junction temperature decreases below the thermal shutdown release level, the transmission is enabled again. RxD pins are released from asserted thermal shutdown low level immediately when chip is below thermal shutdown threshold. As required by SAE J2602, the transceiver behaves safely below its operating range – it either continues to transmit correctly (according to its specification) or remains silent (transmits a recessive state regardless of the TxDx signal). A battery monitoring circuit in NCV7424 deactivates the transmitter in normal mode if the VBB level drops below MONL_VBB. Transmission is enabled again when VBB reaches MONH_VBB. The internal logic remains in normal mode and the reception from the LIN line is still possible even if the battery monitor disables the transmission. Although the specifications of the monitoring and power-on-reset levels are overlapping, it is ensured by the implementation that the monitoring level never falls below the power-on-reset level. Sleep Mode Sleep mode provides extremely low current consumption. The LIN transceiver is inactive and the battery consumption is minimized. Only a weak pull-up current source is internally connected between LIN and VBB pins, in order to minimize current consumption even in case of LIN short to GND. Sleep mode can be entered: • After the voltage level at VBB pin rises above its power-on-reset level. RxDx pins are set high-impedant after start-up • From normal mode by assigning a Low logical level to pin EN for longer than tdisable. The sleep mode can be entered even if a permanent short occurs on the LINx Pin. If a wake-up event occurs during the transition between normal and sleep mode (during the tdisable filtering time), it will be regarded as a valid wake-up and the chip will enter standby mode with the appropriate setting of pins RxDx. LIN Wake−up Remote (or LIN) wake-up can be recognized on all LINx pins on NCV7424 when LINx bus is externally driven dominant for longer than tLIN_wake and a rising edge on LIN occurs afterwards – see Figure 4. Wake-up events can be exclusively detected in sleep mode or during the transition from normal mode to sleep mode. Due to timing tolerances, valid wake-up events beginning shortly before normal-to-sleep mode transition can be also sometimes regarded as valid wake−ups. LINx Detection of Remote Wake−Up VBB LIN recessive level tLIN_wake 60% VBB tto_stb 40% VBB Sleep Mode LIN dominant level Standby Mode Figure 4. LIN Bus Wake−up Detection http://onsemi.com 6 t NCV7424 ELECTRICAL CHARACTERISTICS Definitions All voltages are referenced to GND (Pins 10, 14. These pins are electrically connected inside of the package). Positive currents flow into the IC. Table 5. DC CHARACTERISTICS (VBB = 5 V to 27 V; TJ = −40°C to +150°C; RL(LIN−VBB) = 500 W, unless otherwise specified. Typical values are given at V(VBB) = 12 V and TJ = 25°C, unless otherwise specified.) Parameter Symbol Conditions Min Typ Max Unit CURRENT CONSUMPTION IBB_ON_rec VBB Consumption Normal Mode; LIN Recessive VLINx = VBB 2.3 4.7 mA IBB_ON_dom VBB Consumption Normal Mode; LIN Dominant TxDx = Low 16.5 28 mA IBB_STB VBB Consumption Standby Mode VLINx = VBB 0.22 0.45 mA IBB_SLP VBB Consumption Sleep Mode VLINx = VBB 11 35 mA IBB_SLP_18V VBB Consumption Sleep Mode, VBB < 18 V VLINx = VBB 10 33 mA IBB_SLP_12V VBB Consumption Sleep Mode, VBB = 12 V, TJ < 85°C VLINx = VBB 9 30 mA POR AND VBB MONITOR PORH_VBB Power−on Reset High Level on VBB VBB Rising 2 3.3 4.5 V PORL_VBB Power−on Reset Low Level on VBB VBB Falling 1.7 2.9 4 V MONH_VBB Battery Monitoring High Level VBB Rising 4.1 4.5 V MONL_VBB Battery Monitoring Low Level VBB Falling VLINx_dom_LoSup LINx Dominant Output Voltage TxDx = Low; VBB = 7.3 V 1 1.2 V VLINx_dom_HiSup LINx Dominant Output Voltage TxDx = Low; VBB = 18 V 1.4 2.0 V VLINx_REC LIN Recessive Output Voltage TxDx = High; ILIN = 10 mA (Note 6) VBB V ILINx_lim Short Circuit Current Limitation VLINx = VBB = 18 V; TxDx = Low RLINxslave Internal Pull−up Resistance 3 4 V LIN TRANSMITTERs VBB − 1.5 70 140 200 mA 20 33 47 kW 0.4 VBB LIN RECEIVERs VLINx_bus_dom Bus Voltage for Dominant State VLINx_bus_rec Bus Voltage for Recessive State VLINx_rec_dom Receiver Threshold LIN Bus Recessive − Dominant 0.4 0.45 0.6 VBB VLINx_rec_rec Receiver Threshold LIN Bus Dominant − Recessive 0.4 0.55 0.6 VBB 0.6 VBB 6. The voltage drop in Normal mode between LIN and VBB pin is the sum of the diode drop and the drop at serial pull−up resistor. The drop at the switch is negligible. See Figure 1. http://onsemi.com 7 NCV7424 Table 5. DC CHARACTERISTICS (VBB = 5 V to 27 V; TJ = −40°C to +150°C; RL(LIN−VBB) = 500 W, unless otherwise specified. Typical values are given at V(VBB) = 12 V and TJ = 25°C, unless otherwise specified.) Symbol Parameter Conditions Min Typ Max Unit LIN RECEIVERs VLINx_rec_cnt Receiver Centre Voltage (VLINx_rec_dom + VLINx_rec_rec) / 2 0.475 0.5 0.525 VBB VLINx_rec_hys Receiver Hysteresis (VLINx_rec_rec − VLINx_rec_dom) 0.05 0.1 0.175 VBB ILINx_off_dom LIN Output Current, Bus externally driven to dominant state Normal Mode, Driver Off; VBB = 12 V; TxDx = High; VLINx = 0 V −1 −0.37 −0.2 mA ILINx_off_dom_slp LIN Output Current, Bus externally driven to dominant state Sleep Mode, Driver Off; VBB = 12 V; TxDx = High; VLINx = 0 V −20 −8 −2 mA ILINx_off_rec LIN Output Current, Bus in Recessive State Driver Off; VBB < 18 V; VBB < VLINx < 18 V 2 mA ILINx_no_GND Communication not Affected VBB = GND = 12 V; 0 < VLINx < 18 V 1 mA ILINx_no_VBB LIN Bus Remains Operational VBB = GND = 0 V; 0 < VLINx < 18 V 0 5 mA CLINx Capacitance on LINx pin Not tested in production, guaranteed by design 20 30 pF −1 PIN EN Vil_EN Low Level Input Voltage −0.3 0.8 V Vih_EN High Level Input Voltage 2.0 5.5 V Rpd_EN Pull−down Resistance to Ground 150 350 650 kW PIN RxDx Iol_RxDx Low Level Output Current VRxD = 0.4 V, Normal Mode, VLINx = 0 V 1.5 4.3 Ioh_RxDx High Level Output Current VRxD = 5 V, Normal Mode, VLINx = VBB −5 0 mA 5 mA PIN TxDx Vil_TxDx Low Level Input Voltage −0.3 0.8 V Vih_TxDx High Level Input Voltage 2.0 5.5 V Rpd_TxDx Pull−up on TxDx Pins 60 100 150 kW 150 165 185 °C THERMAL SHUTDOWN TJSD Thermal Shutdown Junction Temperature TJSD_HYST Thermal Shutdown Hysteresis Temperature Rising 5 °C 6. The voltage drop in Normal mode between LIN and VBB pin is the sum of the diode drop and the drop at serial pull−up resistor. The drop at the switch is negligible. See Figure 1. http://onsemi.com 8 NCV7424 Table 6. AC CHARACTERISTICS (VBB = 5 V to 27 V; TJ = −40°C to +150°C; RL(LIN−VBB) = 500 W, unless otherwise specified. For the transmitter parameters, the following bus loads are considered: L1 = 1 kW / 1 nF; L2 = 660 W / 6.8 nF; L3 = 500 W / 10 nF Symbol Parameter Conditions Min Typ Max Unit LIN TRANSMITTER D1 Duty Cycle 1 = tBUS_REC(min) / (2 x tBIT) THREC(max) = 0.744 x VBB THDOM(max) = 0.581 x VBB tBIT = 50 ms V(VBB) = 7 V to 18 V 0.396 0.5 D2 Duty Cycle 2 = tBUS_REC(max) / (2 x tBIT) THREC(min) = 0.422 x VBB THDOM(min) = 0.284 x VBB tBIT = 50 ms V(VBB) = 7.6 V to 18 V 0.5 0.581 D3 Duty Cycle 3 = tBUS_REC(min) / (2 x tBIT) THREC(max) = 0.778 x VBB THDOM(max) = 0.616 x VBB tBIT = 96 ms V(VBB) = 7 V to 18 V 0.417 0.5 D4 Duty Cycle 4 = tBUS_REC(max) / (2 x tBIT) THREC(min) = 0.389 x VBB THDOM(min) = 0.251 x VBB tBIT = 96 ms V(VBB) = 7.6 V to 18 V 0.5 0.590 D1e Duty Cycle 1 = tBUS_REC(min) / (2 x tBIT) THREC(max) = 0.744 x VBB THDOM(max) = 0.581 x VBB tBIT = 50 ms V(VBB) = 5 V to 40 V, (Notes 7 and 8) 0.39 0.5 D2e Duty Cycle 2 = tBUS_REC(max) / (2 x tBIT) THREC(min) = 0.422 x VBB THDOM(min) = 0.284 x VBB tBIT = 50 ms V(VBB) = 5 V to 40 V, (Notes 7 and 8) 0.5 0.59 D3e Duty Cycle 3 = tBUS_REC(min) / (2 x tBIT) THREC(max) = 0.778 x VBB THDOM(max) = 0.616 x VBB tBIT = 96 ms V(VBB) = 5 V to 40 V, (Notes 7 and 8) 0.41 0.5 D4e Duty Cycle 4 = tBUS_REC(max) / (2 x tBIT) THREC(min) = 0.389 x VBB THDOM(min) = 0.251 x VBB tBIT = 96 ms V(VBB) = 5 V to 40 V, (Notes 7 and 8) 0.5 0.6 ttx_prop_down_x Propagation Delay of TxDx to LINx. TxD High to Low 1.3 4.2 10 ms ttx_prop_up_x Propagation Delay of TxDx to LINx. TxD Low to High 1.3 4.6 10 ms ttx_sym_x Propagation Delay Symmetry ttrx_prop_down_x − ttrx_prop_up_x −2.5 −0.4 2.5 ms tfall LINx Falling Edge Normal Mode; VBB = 12 V 9 22.5 ms trise LINx Rising Edge Normal Mode; VBB = 12 V 10 22.5 ms tsym LINx Slope Symmetry Normal Mode; VBB = 12 V −4 0 4 ms LIN RECEIVERs trec_prop_down_x Propagation Delay of LINx to RxDx Receiver Falling Edge 0.1 1.6 6 ms trec_prop_up_x Propagation Delay of LINx to RxDx Receiver Rising Edge 0.1 1.35 6 ms trec_sym_x Propagation Delay Symmetry −2 0.25 2 ms trec_prop_down_x − trec_prop_up_x 7. The external pull-up resistor for duty cycles on V(VBB) = 40 V is 1 kW 8. Not tested in production Extended battery range (5 V; 40 V) is tested on limited sample base only http://onsemi.com 9 NCV7424 Table 6. AC CHARACTERISTICS (VBB = 5 V to 27 V; TJ = −40°C to +150°C; RL(LIN−VBB) = 500 W, unless otherwise specified. For the transmitter parameters, the following bus loads are considered: L1 = 1 kW / 1 nF; L2 = 660 W / 6.8 nF; L3 = 500 W / 10 nF Symbol Parameter Conditions Min Typ Max Unit MODE TRANSITIONS AND TIMEOUTS tLINx_wake Duration of LINx Dominant for Detection of Wake−up via LINx bus Sleep Mode 30 90 150 ms tto_stb Delay from LIN Bus Dominant to Recessive Edge to Entering of Standby Mode after Valid LIN Wake−up See Figure 4 2 2.8 18.5 ms tenable Duration of High Level on EN Pin for Tran− sition to Normal Mode 2 18 47 ms tdisable Duration of Low Level on EN Pin for Tran− sition to Sleep Mode 2 7.5 18.5 ms tTxD_timeout TxD Dominant Timeout 15 28 50 ms Normal Mode, TxD = Low, Guaran− tees Baudrate as Low as 1 kbps 7. The external pull-up resistor for duty cycles on V(VBB) = 40 V is 1 kW 8. Not tested in production Extended battery range (5 V; 40 V) is tested on limited sample base only TxDx t BIT t BIT 50% t LINx tBUS_dom(max) tBUS_rec(min) THREC(max) THDOM(max) Thresholds of receiving node 1 THREC(min) THDOM(min) Thresholds of receiving node 2 t tBUS_dom(min) tBUS_rec(max) Figure 5. LINx Bus Transmitter Duty Cycle http://onsemi.com 10 NCV7424 LINx 100% 60% 60% 40% 40% 0% tfall t trise Figure 6. LINx Bus Transmitter Rising and Falling Times LINx VBB 60% VBB 40% VBB t RxDx trec_prop_down trec_prop_up 50% t Figure 7. LINx Bus Receiver Timing TxDx tBIT tBIT 50% t LINx VBB 60% VBB 40% VBB ttx_prop_down t ttx_prop_up Figure 8. LINx Transmitter Timing ORDERING INFORMATION Part Number NCV7424DB0R2G Description Temperature Range Package Shipping† Quad LIN Transceiver −40°C to +125°C TSSOP16 GREEN (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 11 NCV7424 PACKAGE DIMENSIONS TSSOP−16 CASE 948F ISSUE B 16X K REF 0.10 (0.004) 0.15 (0.006) T U T U M S V S K S ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ ÇÇÇ K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. N 8 1 0.25 (0.010) M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE D H G DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ SOLDERING FOOTPRINT 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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