CY7C197D PRELIMINARY 256K (256K x 1) Static RAM Functional Description[1] Features • Pin- and function-compatible with CY7C197B The CY7C197D is a high-performance CMOS static RAM organized as 256K words by 1 bit. Easy memory expansion is provided by an active LOW Chip Enable (CE) and three-state drivers. The CY7C197D has an automatic power-down feature, reducing the power consumption when deselected. • High speed — tAA = 10 ns • CMOS for optimum speed/power Writing to the device is accomplished when the Chip Enable (CE) and Write Enable (WE) inputs are both LOW. Data on the input pin (DIN) is written into the memory location specified on the address pins (A0 through A17). • Low active power — ICC = 60 mA @ 10 ns • Low CMOS standby power — ISB2 = 3 mA Reading the device is accomplished by taking chip enable (CE) LOW while Write Enable (WE) remains HIGH. Under these conditions the contents of the memory location specified on the address pins will appear on the data output (DOUT) pin. • TTL-compatible inputs and outputs • Data retention at 2.0V • Automatic power-down when deselected The output pin stays in a high-impedance state when Chip Enable (CE) is HIGH or Write Enable (WE) is LOW. • Available in Pb-Free Packages The CY7C197D is available in standard 24-Lead DIP and SOJ Pb-Free Packages. Logic Block Diagram Pin Configurations DI DIP/SOJ Top View A0 A1 A2 A3 A4 A5 A6 A7 A8 SENSE AMPS A13 A14 A15 A16 A17 A0 A1 A2 A3 A4 ROW DECODER INPUT BUFFER 1024 x 256 ARRAY COLUMN DECODER DO POWER DOWN DOUT WE GND CE A5 A6 A7 A8 A9 A10 A11 A12 1 24 2 23 22 3 4 21 5 20 6 7C197D 19 18 7 8 17 9 16 10 15 14 11 12 13 VCC A17 A16 A15 A14 A13 A12 A11 A10 A9 DIN CE WE Selection Guide CY7C197D-10 CY7C197D-12 CY7C197D-15 Maximum Access Time (ns) 10 12 15 Maximum Operating Current (mA) 60 50 40 Maximum Standby Current (mA) 3 3 3 Note: 1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05458 Rev. *C • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised January 11, 2005 PRELIMINARY CY7C197D DC Input Voltage[2].................................... −0.5V to VCC + 0.5V Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .....................................−65°C to +150°C Ambient Temperature with Power Applied..................................................−55°C to +125°C Supply Voltage to Ground Potential (Pin 24 to Pin 12).................................................−0.5V to +7.0V DC Voltage Applied to Outputs in High-Z State[2] ....................................... −0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... >200 mA Operating Range Range Ambient Temperature VCC 0°C to +70°C 5V ± 10% −40°C to +85°C 5V ± 10% Commercial Industrial Electrical Characteristics Over the Operating Range 7C197D-10 Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = −4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage Voltage[2] Min. 7C197D-12 Max. Min. 2.4 Max. Unit 2.4 0.4 V 0.4 V 2.0 VCC + 0.3V 2.0 VCC +0.3V V −0.5 0.8 −0.5 0.8 V +1 −1 +1 µA +1 −1 VIL Input LOW IIX Input Load Current GND < VI < VCC −1 GND < VO < VCC, Output Disabled −1 IOZ Output Leakage Current +1 µA IOS Output Short Circuit Current[3] VCC = Max., VOUT = GND −300 −300 mA ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 60 50 mA ISB1 Automatic CE Power-down Current—TTL Inputs Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX 10 10 mA ISB2 Automatic CE Power-down Current—CMOS Inputs Max. VCC, CE > VCC − 0.3V, VIN > VCC − 0.3V or VIN < 0.3V 3 3 mA 7C197D-15 Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = −4.0 mA VCC = Min., IOL = 8.0 mA Min. Max. Unit 2.4 V VOL Output LOW Voltage 0.4 V VIH Input HIGH Voltage 2.0 VCC + 0.3V V VIL Input LOW Voltage[2] −0.5 0.8 V IIX Input Load Current GND < VI < VCC −1 +1 µA IOZ Output Leakage Current GND < VO < VCC, Output Disabled −1 +1 µA −300 mA [3] IOS Output Short Circuit Current VCC = Max., VOUT = GND ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 40 mA ISB1 Automatic CE Power Down Current—TTL Inputs Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX 10 mA ISB2 Automatic CE Power-Down Current—CMOS Inputs Max. VCC, CE > VCC − 0.3V, VIN > VCC − 0.3V or VIN < 0.3V 3 mA Capacitance[4] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. Unit 8 pF 10 pF Notes: 2. VIL (min.) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. 3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 4. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05458 Rev. *C Page 2 of 8 PRELIMINARY CY7C197D Thermal Resistance[4] Parameter Description ΘJA Thermal Resistance (Junction to Ambient)[4] ΘJC Thermal Resistance (Junction to Case)[4] Test Conditions All-Packages Unit TBD °C/W TBD °C/W Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board AC Test Loads and Waveforms[5] 10-ns Device ALL INPUT PULSES Z = 50Ω 3.0V OUTPUT 50 Ω * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 10% GND 30 pF* 90% 10% 90% < tr < tr 1.5V 12, 15 -ns Devices (a) 5V R1 480 Ω High-Z characteristics: R1 480 Ω 5V OUTPUT OUTPUT Equivalent to: THÉVENIN EQUIVALENT 167Ω OUTPUT 1.73V R2 255Ω 30 pF INCLUDING JIG AND SCOPE R2 255Ω 5 pF INCLUDING JIG AND SCOPE (b) (c) Switching Characteristics Over the Operating Range[6] 7C197D-10 Parameter Description Min. Max. 7C197D-12 Min. Max. 7C197D-15 Min. Max. Unit Read Cycle tpower[7] VCC(typical) to the first access 100 100 100 µs tRC Read Cycle Time 10 12 15 ns tAA Address to Data Valid tOHA Output Hold from Address Change tACE CE LOW to Data Valid tLZCE CE LOW to Low Z[8] 10 3 12 3 10 3 Z[8, 9] ns 15 ns 3 12 3 5 15 ns 3 tHZCE CE HIGH to High tPU CE LOW to Power-Up tPD CE HIGH to Power-Down tSCE CE LOW to Write End 8 9 10 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 ns 0 5 ns 0 10 7 0 12 ns ns 15 ns [10] Write Cycle tWC Write Cycle Time 10 12 15 ns tAW Address Set-Up to Write End 7 9 10 ns Notes: 5. tr = < 3 ns for all speeds. 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device. 9. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) in AC Test Loads and Waveforms. Transition is measured ±200 mV from steady-state voltage. 10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. Document #: 38-05458 Rev. *C Page 3 of 8 PRELIMINARY CY7C197D Switching Characteristics Over the Operating Range[6] 7C197D-10 Parameter Description Min. 7C197D-12 Max. Min. Max. 7C197D-15 Min. Max. Unit tPWE WE Pulse Width 7 8 9 ns tSD Data Set-Up to Write End 6 8 9 ns tHD Data Hold from Write End 0 0 0 ns Z[8] tLZWE WE HIGH to Low tHZWE WE LOW to High Z[8,9] 3 3 6 3 ns 7 7 ns Max. Unit 3 mA 1.2 mA Data Retention Characteristics Over the Operating Range Parameter Description Conditions VDR VCC for Data Retention ICCDR Data Retention Current tCDR[4] Chip Deselect to Data Retention Time tR[11] Operation Recovery Time Min. 2.0 Non-L, Com’l / Ind’l L-Version Only VCC = VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V V 0 ns tRC ns Data Retention Waveform VCC DATA RETENTION MODE 4.5V 4.5V VDR > 2V tCDR tR CE Switching Waveforms Read Cycle No. 1[12, 13] tRC Address tAA t OHA Data Out Previous Data Valid Data Valid Notes: 11. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs. 12. WE is HIGH for read cycle. 13. Device is continuously selected, CE = VIL. Document #: 38-05458 Rev. *C Page 4 of 8 PRELIMINARY CY7C197D Switching Waveforms (continued) Read Cycle No. 2[12] t RC Address CE t ACE t HZCE t LZ CE High Z Data O ut tP U I CC Vcc Supply Current High Z Data Valid tPD 50% 50% I SB Write Cycle No. 1 (WE Controlled)[10] tW C Address t SC E CE t AW tH A t PW E tSA WE t SD Data Valid Data In t H ZW E Data O ut tH D Data Undefined Document #: 38-05458 Rev. *C tLZW E High Im pedance Page 5 of 8 PRELIMINARY CY7C197D Switching Waveforms (continued) Write Cycle No. 2 (CE Controlled)[10,14] tW C A ddress tS C E tS A CE tH A tA W tP W E WE tS D D ata In tH D D ata V alid H igh Z D ata O ut Truth Table CE WE Input/Output Mode H X High Z Deselect/Power-Down L H Data Out Read L L Data In Write Ordering Information Speed (ns) 10 12 15 Ordering Code Package Name Package Type CY7C197D-10PXC P13 24-Lead (300-Mil) Molded DIP (Pb-Free) CY7C197D-10VXC V13 24-Lead Molded SOJ (Pb-Free) CY7C197D-10PXI P13 24-Lead (300-Mil) Molded DIP (Pb-Free) CY7C197D-10VXI V13 24-Lead Molded SOJ (Pb-Free) CY7C197D-12PXC P13 24-Lead (300-Mil) Molded DIP (Pb-Free) CY7C197D-12VXC V13 24-Lead Molded SOJ (Pb-Free) CY7C197D-12PXI P13 24-Lead (300-Mil) Molded DIP (Pb-Free) CY7C197D-12VXI V13 24-Lead Molded SOJ (Pb-Free) CY7C197D-15PXC P13 24-Lead (300-Mil) Molded DIP (Pb-Free) CY7C197D-15VXC V13 24-Lead Molded SOJ (Pb-Free) CY7C197D-15PXI P13 24-Lead (300-Mil) Molded DIP (Pb-Free) CY7C197D-15VXI V13 24-Lead Molded SOJ (Pb-Free) Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Note: 14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Document #: 38-05458 Rev. *C Page 6 of 8 PRELIMINARY CY7C197D Package Diagram 24-Lead (300-Mil) PDIP P13 51-85013-*B 24-lead (300-mil) SOJ V13 PIN 1 ID 12 1 MIN. DIMENSIONS IN INCHES[MM] MAX. 0.291[7.39] 0.300[7.62] REFERENCE JEDEC MO-088 0.330[8.38] 0.350[8.89] PACKAGE WEIGHT 0.75gms PART # 13 24 0.597[15.16] 0.613[15.57] V24.3 STANDARD PKG. VZ24.3 LEAD FREE PKG. SEATING PLANE 0.120[3.05] 0.140[3.55] 0.007[0.17] 0.013[0.33] 0.004[0.10] 0.050[1.27] TYP. 0.025[0.63] MIN. 0.262[6.65] 51-85030-*B 0.272[6.91] 0.013[0.33] 0.019[0.48] All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05458 Rev. *C Page 7 of 8 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY CY7C197D Document History Page Document Title: CY7C197D 256K (256K x 1) Static RAM (Preliminary) Document Number: 38-05458 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 201560 See ECN SWI Advance Datasheet for C9 IPP *A 233693 See ECN RKF DC parameters modified as per EROS (Spec # 01-02165) Pb-free Offering in Ordering Information *B 263769 See ECN RKF Removed 28-LCC Pinout and Package Diagrams Added Data Retention Characteristics table Added Tpower Spec in Switching Characteristics table Shaded Ordering Information *C 307593 See ECN RKF 1) Reduced Speed bins to -10, -12 and -15 ns 2) Added ‘Industrial’ grade parts to the Ordering Info on Page #6 Document #: 38-05458 Rev. *C Page 8 of 8