PANJIT PJLC1V5D

PJLC1V5, 1V5D
SINGLE AND DUAL LOW CAPACITANCE ESD / TRANSIENT PROTECTOR
FOR 1.5 V SYSTEMS
This patented Single and Dual Zener like ESD/Transient Protector has been designed
to protect Sensitive Equipment against ESD and prevent Latch-Up events, offering a
minimum insertion loss in High speed Data Lines in Communications ports used in
Portable Consumer, Computing and Networking Applications operating at 1.5V and
below.
3
1
SPECIFICATION FEATURES
2
Maximum Capacitance of 10pF @ 0Vdc, 1 MHz
Maximum Leakage Current of 2µA @ 1.5V
Breakdown Voltage of 1.9V @ 1mA
IEC61000-4-2 Compliance 15kV Air, 8kV Contact Discharge
Industry Standard SOT23 Package
APPLICATIONS
2
1
High Speed Data Transmission Lines
Microcontroller and Microprocessor I/O Interfaces
Portable Consumer Electronics
Instrumentation Equipment
LAN/WAN Equipment
3 (GND)
SOT23
MAXIMUM RATINGS
Symbol
Value
Units
Peak Pulse Power (8/20µs Waveform)
P pp
50
W
ESD Voltage (HBM)
V ESD
>25
kV
Operating Temperature Range
TJ
-55 to +125
°C
Storage Temperature Range
Tstg
-55 to +150
°C
Lead Soldering Temperature (max 10 s)
TL
260
°C
Rating
ELECTRICAL CHARACTERISTICS Tj = 25°C
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Conditions
Symbol
Min
Typical
VWRM
VBR
Reverse Leakage Current
IR
Clamping Voltage (8/20µs)
Vc
Clamping Voltage (8/20µs)
Max
Units
1.5
V
I BR = 100µA
1.75
1.8
V
I BR = 1mA
1.9
2.2
V
2.0
µA
I pp = 1 A
4
V
Vc
I pp = 3 A
7
V
Maximum Peak Pulse Current
I pp
8/20 µs Waveform
5
A
Off State Junction Capacitance
Cj
10
pF
7/21/2006
VR = 1.5V
0 Vdc Bias f = 1MHz
Between I/O pins and pin 3
Page
1
6
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PJLC1V5, 1V5D
TYPICAL CHARACTERISTICS Tj = 25°C
Voltage vs Current Characterisitc
100
Current, mA
10
1
0.1
0.01
1
1.5
2
2.5
3
Voltage, Volts
Leakage Current
100
TA = 25°C
Leakage Current, µA
10
1
0.1
0.01
0.001
0.8
1
1.2
1.4
1.6
1.8
2
Voltage, Volts
Pulse Waveform
110
100
90
Percent of Ipp
80
50% of Ipp @ 20µs
70
60
50
40
30
Rise time 10-90% - 8µs
20
10
0
0
7/21/2006
5
10
15
time, µsec
Page 2
20
25
30
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PJLC1V5, 1V5D
TYPICAL APPLICATION INFORMATION
ESD Protection for two Data Lines
1.2-1.5V
DATA LINE 1
0
DATA LINE 2
1
2
PJLC1V5D
3 (GND)
ESD Protection for Four Data Lines
0
1.2-1.5V
DATA LINE 1
0
DATA LINE 2
DATA LINE 3
DATA LINE 4
1
2
PJLC1V5D
1
2
PJLC1V5D
3 (GND)
7/21/2006
Page 3
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PJLC1V5, 1V5D
PACKAGE AND PAD LAYOUT DIMENSIONS
De vice
PJLC1V5
PJLC1V5D
Ma rking Code
T1L
T2L
© Copyright PanJit International, Inc 2006
The information presented in this document is believed to be accurate and reliable. The specifications and information herein are
subject to change without notice. Pan Jit makes no warranty, representation or guarantee regarding the suitability of its products for
any particular purpose. Pan Jit products are not authorized for use in life support devices or systems. Pan Jit does not convey any
license under its patent rights or rights of others.
7/21/2006
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