PJESD5V6LCQ5G Series 5-TVS/ZENER ARRAY FOR ESD AND LATCH-UP PROTECTION This 5-TVS array has been designed to Protect Sensitive Equipment against ESD and to prevent Latch-Up events in CMOS circuitry, operating at 3.3V and 5V Systems. This TVS array offers an integrated solution to protect up to 5 data lines where the board space is a premium. 6 5 4 1 2 3 SPECIFICATION FEATURES 15W Power Dissipation (8/20µs Waveform) Low Leakage Current, Maximum of 0.5µA @ VWRM Very low Off-State Capacitance, Maximum of 10pF at 1MHz 0Vdc 6 IEC61000-4-2 ESD 20kV air, 15kV Contact Compliance 5 4 100% Tin plated finish (LEAD FREE) RoHS Compliant New SMT package QFN 1.6mm x 1.6mm; Max Height of 0.75mm Same Footprint compared to the SOT563 1 2 3 APPLICATIONS Personal Digital Assistant (PDA) MP3 Players 1 Portable Global positioning Systems Port Mobile Phones and Accessories 3 2 QFN 2X2 6 Memory Card Port Protection 5 4 QFN 1.6x1.6 sq mm Package MAXIMUM RATINGS (Per Device) Symbol Value Units Peak Pulse Power (8/20µs Waveform) P pp 15 W ESD Voltage (HBM) V ESD >25 kV Operating Temperature Range TJ -55 to +150 °C Storage Temperature Range Tstg -55 to +150 °V Typical Max Units 3.3 V 5.88 V 0.5 µA Rating ELECTRICAL CHARACTERISTICS (Per Device) Tj = 25°C PJESD5V6LCQ5G Parameter Reverse Stand-Off Voltage Conditions Symbol Min VWRM Reverse Breakdown Voltage VBR I BR = 1mA Reverse Leakage Current IR VR = 3.3V Clamping Voltage (8/20µs) Vc I pp = 1 A 7.0 V Clamping Voltage (8/20µs) Vc I pp = 2 A 8.0 V Off State Junction Capacitance Cj 0 Vdc Bias f = 1MHz Between I/O pins and pin 2 9.6 10 pF Off State Junction Capacitance Cj 3.3 Vdc Bias f = 1MHz Between I/O pins and pin 2 6.2 8 pF 10/5/2006 Page 1 5.3 5.6 www.panjit.com PJESD5V6LCQ5G Series ELECTRICAL CHARACTERISTICS (Per Device) Tj = 25°C PJESD6V8LCQ5G Parameter Reverse Stand-Off Voltage Min Conditions Symbol Typical VWRM Max Units 5.0 V 7.2 V 0.5 µA Reverse Breakdown Voltage VBR I BR = 1mA Reverse Leakage Current IR VR = 5.0V Clamping Voltage (8/20µs) Vc I pp = 1 A 9 V Clamping Voltage (8/20µs) Vc I pp = 2 A 10 V Off State Junction Capacitance Cj 0 Vdc Bias f = 1MHz Between I/O pins and pin 2 9.1 10 pF Off State Junction Capacitance Cj 5 Vdc Bias f = 1MHz Between I/O pins and pin 2 5.0 6 pF TYPICAL CHARACTERISTICS 6.2 6.8 25°C unless otherwise noted Clamping Voltage vs. Peak current Surge Pulse Waveform Definition 110 100 90 80 70 60 50 40 30 20 10 0 10 Clamping voltage, V Percent of Ipp Pulse Waveform 50% of Ipp @ 20µs Rise time 10-90% - 8µs 9 6V8 8 5V6 7 6 0 5 10 15 20 25 1 30 1.2 1.4 1.6 1.8 2 Ipp, A (8/20µsec) time, µsec Off-State junction Capacitance Typical Leakage Current vs Temperature 0.1000 12 5V6 8 0.0100 6 6V8 4 5V Current, µA Capacitance, pF 10 0.0010 3V 2 0 0.0001 0 1 2 3 4 5 50 75 100 125 150 Temp,°C Bias Voltage, Vdc 10/5/2006 25 Page 2 www.panjit.com PJESD5V6LCQ5G Series TYPICAL APPLICATION EXAMPLE I/O Data lines Ground (Pin 2) Marking Code Information Device Marking Code PJESD5V6LCQ5G QE PJESD6V8LCQ5G QG 10/5/2006 Page 3 www.panjit.com PJESD5V6LCQ5G Series PACKAGE DIMENSIONS AND SUGGESTED BOND PAD LAYOUT TOP VIEW BOTTOM VIEW 0.50 ± 0.05 mm 1.60 ± 0.05 mm 1.60 ± 0.05 mm QE 0.20 ± 0.05 mm 0.20 ± 0.05 mm 1.1 ± 0.05 mm 0.6 ± 0.05 mm SIDE VIEW 0.203 ± 0.05 mm 0.75 ± 0.05 mm PREFERRED ALTERNATE 0.25 ± 0.05 mm 0.25 ± 0.05 mm 0.40 ± 0.05 mm 0.40 ± 0.05 mm 0.90 ± 0.05 mm 0.55 mm 1.0 ± 0.05 mm 1.00 ± 0.05 mm 0.50 ± 0.05 mm 0.50 ± 0.05 mm © Copyright PanJit International, Inc 2006 The information presented in this document is believed to be accurate and reliable. The specifications and information herein are subject to change without notice. Pan Jit makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose. Pan Jit products are not authorized for use in life support devices or systems. Pan Jit does not convey any license under its patent rights or rights of others. 10/5/2006 Page 4 www.panjit.com