CY2303 Phase-Aligned Clock Multiplier Phase-Aligned Clock Multiplier Features Functional Description ■ 3-Multiplier configuration (1x, 2x, 4x ref) ■ 10 MHz to 166.67 MHz operating range (reference input from 10 MHz to 41.67 MHz) ■ Phase alignment ■ 80 ps typical period jitter ■ Output enable pin ■ 3.3 V operation ■ 5 V tolerant input ■ 8-pin 150-mil small-outline integrated circuit (SOIC) package ■ Commercial temperature range The CY2303 is a 3 output 3.3 V phase-aligned system clock designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications. The part allows user to obtain 1x, 2x, and 4x REFIN output frequencies on respective output pins. The CY2303 has an on-chip PLL, which locks to an input clock presented on the REFIN pin. The PLL feedback is internally connected to the REF output. The input-to-output is guaranteed to be less than 200 ps, and output-to-output skew is guaranteed to be less than 200 ps. Multiple CY2303 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 400 ps. Logic Block Diagram FBK x1 REF PLL REFIN x2 x4 REFx2 REFx4 OE Cypress Semiconductor Corporation Document #: 38-07249 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 01, 2010 [+] Feedback CY2303 Pinouts Figure 1. CY2303 - 8-pin SOIC Top View REF GND REFIN N/C 1 2 3 4 8 7 6 5 OE VDD REFx4 REFx2 Pin Description Signal[1] Pin Description 1 REF REF output (1x reference input) 2 GND Ground 3 REFIN Input reference frequency, 5 V tolerant input 4 N/C No connect 5 REFx2 2x reference input 6 REFx4 4x reference input 7 VDD 3.3 V supply 8 OE Output enable (weak pull-up) Maximum Ratings Supply voltage to ground potential ...............–0.5 V to +7.0 V Storage temperature ................................ –65 °C to +150 °C DC input voltage (except ref) ............... –0.5 V to VDD + 0.5 V Junction temperature................................................. 150 °C DC input voltage REFIN ....................................–0.5 V to 7 V Static discharge voltage (per MIL-STD-883, method 3015) ........................... > 2000 V Operating Conditions Parameter Description Min Max Unit VDD Supply voltage 3.0 3.6 V TA Operating temperature (ambient temperature) 0 70 °C CL Load capacitance, 10 MHz < FOUT < 133.33 MHz – 18 pF Load capacitance, 133.33 MHz < FOUT < 166.67 MHz – 12 pF CIN Input capacitance tPU Power-up time for all VDD’s to reach minimum specified voltage (power ramps must be monotonic) – 7 pF 0.05 50 ms Notes 1. Weak pull-down on all outputs. Document #: 38-07249 Rev. *E Page 2 of 9 [+] Feedback CY2303 Electrical Characteristics Parameter Description Test Conditions Min Max Unit – 0.8 V VIL Input LOW voltage VIH Input HIGH voltage 2.0 – V IIL Input LOW current VIN = 0 V – 100 A IIH Input HIGH current VIN = VDD – 50 A VOL Output LOW voltage[2] IOL = 8 mA – 0.4 V VOH Output HIGH voltage [2] 2.4 – V IDD Supply current Unloaded outputs, REFIN = 41.67 MHz – 45 mA Unloaded outputs, REFIN = 25 MHz – 32 mA Unloaded outputs, REFIN = 10 MHz – 18 mA IOH = –8 mA Switching Characteristics Parameter 1/t1 Name Output frequency Test Conditions Min Typ Max Unit 18-pF load 10 – 133.33 MHz 12-pF load – – 166.67 MHz Measured at VDD/2 40 50 60 % Measured between 0.8 V and 2.0 V – – 1.20 ns Duty cycle[3] t3 Rise time[3] t4 Fall time[3] Measured between 0.8 V and 2.0 V – – 1.20 ns t5 Output to output skew on rising edges[3] All outputs equally loaded Measured at VDD/2 – – 200 ps t6 Delay, REFIN rising edge to Measured at VDD/2 from REFIN to any output REF rising edge[3] – – 200 ps t7 Device to device skew[3] Measured at VDD/2 on the REF pin of the device (pin 1) – – 400 ps tJ Period jitter[3] Measured at FOUT < 133.33 MHz, loaded outputs, 18-pF load – 80 175 ps tLOCK PLL lock time[3] Stable power supply, valid clocks presented on REFIN – – 1.0 ms = t2 t1 Switching Waveforms Figure 2. Duty Cycle Timing t1 t2 VDD/2 Notes 2. Parameter is guaranteed by design and characterization. It is not 100% tested in production. 3. All parameters are specified with loaded outputs. Document #: 38-07249 Rev. *E Page 3 of 9 [+] Feedback CY2303 Switching Waveforms (continued) Figure 3. All Outputs Rise/Fall Time OUTPUT 2.0V 0.8V 2.0V 0.8V 3.3V 0V t4 t3 Figure 4. Output to Output Skew OUTPUT VDD/2 VDD/2 OUTPUT t5 Figure 5. Input to Output Propagation Delay INPUT VDD/2 VDD/2 FBK t6 Figure 6. Device to Device Skew FBK, Device 1 VDD/2 VDD/2 FBK, Device 2 t7 Document #: 38-07249 Rev. *E Page 4 of 9 [+] Feedback CY2303 Test Circuits Figure 7. Test Circuit #1 VDD 0.1 F OUTPUTS CLK OUT C LOAD GND Document #: 38-07249 Rev. *E Page 5 of 9 [+] Feedback CY2303 Ordering Information Ordering Code Package Type Operating Range Pb-free CY2303SXC 8-pin 150-mil SOIC Commercial (0 to 70 °C) CY2303SXCT 8-pin 150-mil SOIC - Tape and Reel Commercial (0 to 70 °C) Ordering Code Definitions CY 2303 S X C (T) T = Tape and Reel, Blank = Tube Temperature Grade: C = Commercial Fixed for Pb-free Package Type: S = SOIC Part Identifier Company ID: CY = Cypress Package Diagram Figure 8. 8-pin (150-Mil) SOIC S8 51-85066 *D Document #: 38-07249 Rev. *E Page 6 of 9 [+] Feedback CY2303 Acronyms Acronym Description FBK Feedback OE Output enable PLL Phase locked loop REFIN Reference input Reference Documents Reference documents are available through your local Cypress sales representative. You can also direct your requests to [email protected]. Document Number NA Document Title NA Description NA Document Conventions Units of Measure Symbol °C Unit of Measure degrees Celsius Hz Hertz kHz kilo Hertz MHz Mega Hertz µA micro Amperes µF micro Farads µs micro seconds µV micro Volts mA milli Amperes mm milli meters ms milli seconds mV milli Volts ns nano seconds pA pico Amperes pF pico Farads ps pico seconds V Volts Document #: 38-07249 Rev. *E Page 7 of 9 [+] Feedback CY2303 Document History Page Document Title: CY2303 Phase-Aligned Clock Multiplier Document Number: 38-07249 REV. ECN Orig. of Change Submission Date Description of Change ** 110514 SZV 01/07/02 Change from Spec number: 38-01036 to 38-07249 *A 121852 RBI 12/14/02 Power up requirements added to Operating Conditions Information *B 390413 RGL 08/10/05 Added Lead-free devices Added typical values for jitter *C 2568533 AESA 09/23/08 Updated template. Removed part number CY2303SC and CY2303SI from Selector Guide table. Removed part number CY2303SC, CY2303SCT, CY2303SI, and CY2303SIT. *D 2897294 KVM 03/22/10 Removed part numbers CY2303SXI and CY2303SXIT from ordering information table and related industrial temperature references. Updated package diagram. Updated copyright section. *E 3026183 BASH Document #: 38-07249 Rev. *E 09/01/2010 Updated tJ from 80 ps to 80 ps in Switching Characteristics on page 3. Ordering Code Definitions added on page 6. Acronyms, Reference Documents and Document Conventions added on page 7. Page 8 of 9 [+] Feedback CY2303 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2002-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07249 Rev. *E Revised September 01, 2010 Page 9 of 9 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback