CYPRESS CY23EP05

CY23EP05
2.5 V or 3.3 V,10-220-MHz, Low Jitter,
5 Output Zero Delay Buffer
Features
Functional Description
■
10 MHz to 220 MHz maximum operating range
■
Zero input-output propagation delay, adjustable by loading on
CLKOUT pin
■
Multiple low-skew outputs
❐ 30 ps typical output-output skew
❐ One input drives five outputs
The CY23EP05 is a 2.5 V or 3.3 V zero delay buffer designed to
distribute low-jitter high-speed clocks and is available in a 8-pin
SOIC package. It accepts one reference input, and drives out five
low-skew clocks. The –1H version operates up to 220 (200) MHz
frequencies at 3.3 V (2.5 V), and has a higher drive strength than
the –1 devices. All parts have on-chip PLLs which lock to an input
clock on the REF pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad.
■
22 ps typical cycle-to-cycle jitter
■
13 ps typical period jitter
■
Standard and high drive strength options
■
Available in space-saving 150-mil SOIC package
■
3.3 V or 2.5 V operation
■
Industrial temperature available
The CY23EP05 PLL enters a power-down mode when there are
no rising edges on the REF input (< ~2 MHz). In this state, the
outputs are three-stated and the PLL is turned off, resulting in
less than 25 μA of current draw.
The CY23EP05 is available in different configurations, as shown
in the Ordering Information table. The CY23EP05-1 is the base
part. The CY23EP05-1H is the high-drive version of the –1, and
its rise and fall times are much faster than the –1.
These parts are not intended for 5 V input-tolerant applications.
Logic Block Diagram
CLKOUT
PLL
REF
CLK1
CLK2
CLK3
CLK4
Cypress Semiconductor Corporation
Document #: 38-07759 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 7, 2011
[+] Feedback
CY23EP05
Contents
Pin Configuration ............................................................. 3
Pin Description ................................................................. 3
Zero Delay and Skew Control .......................................... 3
Absolute Maximum Conditions ....................................... 4
Operating Conditions ....................................................... 4
3.3-V DC Electrical Specifications .................................. 4
2.5-V DC Electrical Specifications .................................. 5
3.3-V and 2.5-V AC Electrical Specifications ................. 5
Switching Waveforms ...................................................... 6
Test Circuits ...................................................................... 7
Document #: 38-07759 Rev. *C
Supplemental Parametric Information ............................ 8
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Acronyms ........................................................................ 13
Document Conventions ................................................. 13
Units of Measure ....................................................... 13
Sales, Solutions, and Legal Information ...................... 15
Worldwide Sales and Design Support ....................... 15
Products .................................................................... 15
PSoC Solutions ......................................................... 15
Page 2 of 15
[+] Feedback
CY23EP05
Pin Configuration
Top View
REF
CLK2
CLK1
GND
1
8
2
7
3
6
4
5
CLKOUT
CLK4
VDD
CLK3
Pin Description
Pin
Signal
Description
1
REF[1]
Input reference frequency
2
CLK2[2]
Buffered clock output
3
CLK1[2]
Buffered clock output
4
GND
Ground
5
CLK3[2]
Buffered clock output
6
VDD
3.3 V or 2.5 V supply
7
CLK4[2]
Buffered clock output
8
CLKOUT[2,3]
Buffered clock output, internal feedback on this pin
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve zero delay
between the input and output. Since the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust the
input-output delay.
each output pin (including CLKOUT) must be the same. If
input-output delay adjustments are required, the CLKOUT load
may be changed to vary the delay between the REF input and
remaining outputs.
The output driving the CLKOUT pin will be driving a total load of
5 pF plus any additional load externally connected to this pin. For
applications requiring zero input-output delay, the total load on
For zero output-output skew, be sure to load all outputs equally.
For further information refer to the application note titled
“CY2305 and CY2309 as PCI and SDRAM Buffers”.
Notes
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
Document #: 38-07759 Rev. *C
Page 3 of 15
[+] Feedback
CY23EP05
Absolute Maximum Conditions
Storage temperature................................... –65 °C to 150 °C
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Supply voltage to ground potential .................–0.5 V to 4.6 V
Junction temperature.................................................. 150 °C
Static discharge voltage
(per MIL-STD-883, Method 3015............................. > 2000 V
DC Input Voltage ......................................VSS – 0.5 V to 4.6 V
Operating Conditions
Min
Typ
Max
Unit
VDD3.3
Parameter
3.3 V supply voltage
Description
3.0
3.3
3.6
V
VDD2.5
2.5 V supply voltage
2.3
2.5
2.7
V
TA
Operating temperature (ambient temperature) – commercial
Operating temperature (ambient temperature) – industrial
CL[4]
0
–
70
°C
–40
–
85
°C
Load capacitance, < 100 MHz, 3.3 V
–
–
30
pF
Load capacitance, < 100 MHz, 2.5 V with high drive
–
–
30
pF
Load capacitance, < 133.3 MHz, 3.3 V
–
–
22
pF
Load capacitance, < 133.3 MHz, 2.5 V with high drive
–
–
22
pF
Load capacitance, < 133.3 MHz, 2.5 V with standard drive
–
–
15
pF
Load capacitance, > 133.3 MHz, 3.3 V
–
–
15
pF
Load capacitance, > 133.3 MHz, 2.5 V with high drive
–
–
15
pF
CIN
Input capacitance[5]
–
–
5
pF
BW
Closed-loop bandwidth, 3.3 V
–
1–1.5
–
MHz
Closed-loop bandwidth, 2.5 V
–
0.8
–
MHz
ROUT
Output impedance, 3.3 V high drive
–
29
–
Ω
Output impedance, 3.3 V standard drive
–
41
–
Ω
Output impedance, 2.5 V high drive
–
37
–
Ω
Output Impedance, 2.5 V standard drive
–
41
–
Ω
0.01
–
50
ms
Dissipation, junction to ambient, 8-pin SOIC
–
131
–
°C/W
Dissipation, junction to case, 8-pin SOIC
–
81
–
°C/W
Min
Typ
Max
Unit
V
Power-up time for all VDDs to reach minimum specified voltage
(power ramps must be monotonic)
tPU
Theta JA[6]
Theta JC
[6]
3.3-V DC Electrical Specifications
Parameter
Description
Test Conditions
VDD
Supply voltage
3.0
3.3
3.6
VIL
Input LOW voltage
–
–
0.8
V
VIH
Input HIGH voltage
2.0
–
VDD + 0.3
V
IIL
Input leakage current
0 < VIN < VIL
–10
–
10
μA
IIH
Input HIGH current
VIN = VDD
–
–
100
μA
VOL
Output LOW voltage
IOL = 8 mA (standard drive)
IOL = 12 mA (High drive)
–
–
–
0.4
0.4
V
V
VOH
Output HIGH voltage
IOH = –8 mA (standard drive)
IOH = –12 mA (high drive)
2.4
2.4
–
–
–
V
V
IDD (PD mode)
Power down supply current
REF = 0 MHz (commercial)
–
–
12
μA
REF = 0 MHz (industrial)
–
–
25
μA
Unloaded outputs, 66-MHz REF
–
–
30
mA
IDD
Supply current
Notes
4. Applies to Test Circuit #1.
5. Applies to both REF Clock and internal feedback path on CLKOUT.
6. Theta Ja, EIA JEDEC 51 test board conditions, 2S2P; Theta Jc Mil-Spec 883E Method 1012.1.
Document #: 38-07759 Rev. *C
Page 4 of 15
[+] Feedback
CY23EP05
2.5-V DC Electrical Specifications
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
2.3
2.5
2.7
V
–
0.7
V
–
VDD + 0.3
V
VDD
Supply voltage
VIL
Input LOW voltage
–
VIH
Input HIGH voltage
1.7
IIL
Input leakage current
0 < VIN < VDD
–10
–
10
μA
IIH
Input HIGH current
VIN = VDD
–
–
100
μA
VOL
Output LOW voltage
IOL = 8 mA (standard drive)
IOL = 12 mA (high drive)
–
–
–
0.5
0.5
V
V
VOH
Output HIGH voltage
IOH = –8 mA (standard drive)
IOH = –12 mA (high drive)
VDD – 0.6
VDD – 0.6
–
–
–
V
V
IDD (PD mode)
Power Down supply current
IDD
Supply current
REF = 0 MHz (commercial)
–
–
12
μA
REF = 0 MHz (industrial)
–
–
25
μA
Unloaded outputs, 66-MHz REF
–
–
45
mA
3.3-V and 2.5-V AC Electrical Specifications
Parameter
1/t1
TIDC
t2 ÷ t1
t3,t4
t3, t4
Description
Test Conditions
frequency[7]
Maximum
(input/output)
Input duty cycle
Output duty cycle[8]
Rise, fall time (3.3
Rise, fall time (2.5
V)[8]
V)[8]
[8]
Min
Typ
Max
Unit
3.3 V high drive
10
–
220
MHz
3.3 V standard drive
10
–
167
MHz
2.5 V high drive
10
–
200
MHz
2.5 V standard drive
10
–
133
MHz
< 133.3 MHz
25
–
75
%
> 133.3 MHz
40
–
60
%
< 133.3 MHz
47
–
53
%
> 133.3 MHz
45
–
55
%
Std drive, CL = 30 pF, < 100 MHz
–
–
1.6
ns
Std drive, CL = 22 pF, < 133.3 MHz
–
–
1.6
ns
Std drive, CL = 15 pF, < 167 MHz
–
–
0.6
ns
High drive, CL = 30 pF, < 100 MHz
–
–
1.2
ns
High drive, CL = 22 pF, < 133.3 MHz
–
–
1.2
ns
High drive, CL = 15 pF, > 133.3 MHz
–
–
0.5
ns
Std drive, CL = 15 pF, < 133.33 MHz
–
–
1.5
ns
High drive, CL = 30 pF, < 100 MHz
–
–
2.1
ns
High drive, CL = 22 pF, < 133.3 MHz
–
–
1.3
ns
High drive, CL = 15 pF, > 133.3 MHz
–
–
1.2
ns
t5
Output to output skew
–
30
100
ps
t6
Delay, REF rising edge to PLL enabled at 3.3 V
CLKOUT rising edge[8]
PLL enabled at 2.5 V
–100
–
100
ps
–200
–
200
ps
t7
Part to part skew[8]
Measured at VDD/2.
Any output to any output, 3.3 V supply
–150
–
150
ps
Measured at VDD/2.
Any output to any output, 2.5 V supply
–300
–
300
ps
All outputs equally loaded
Notes
7. For the given maximum loading conditions. See CL in Operating Conditions Table.
8. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document #: 38-07759 Rev. *C
Page 5 of 15
[+] Feedback
CY23EP05
3.3-V and 2.5-V AC Electrical Specifications (continued)
Parameter
Description
[8]
tLOCK
PLL lock time
TJCC[8,9]
Cycle-to-cycle jitter, peak
TPER[8,9]
Period jitter, peak
Test Conditions
Min
Typ
Max
Unit
Stable power supply, valid clocks presented on REF
and CLKOUT pins
–
–
1.0
ms
3.3 V supply, > 66 MHz, < 15 pF
–
22
55
ps
3.3 V supply, > 66 MHz, < 30 pF, standard drive
–
45
125
ps
3.3 V supply, > 66 MHz, < 30 pF, high drive
–
45
100
ps
2.5 V supply, > 66 MHz, < 15 pF, standard drive
–
40
100
ps
2.5 V supply, > 66 MHz, < 15 pF, high drive
–
35
80
ps
2.5 V supply, > 66 MHz, < 30 pF, high drive
–
52
125
ps
3.3 V supply, 66–100 MHz, < 15 pF
–
18
60
ps
3.3 V supply, > 100 MHz, < 15 pF
–
13
35
ps
3.3 V supply, > 66 MHz, < 30 pF, standard drive
–
28
75
ps
3.3 V supply, > 66 MHz, < 30 pF, high drive
–
26
70
ps
2.5 V supply, > 66 MHz, < 15 pF, standard drive
–
25
60
ps
2.5 V supply, 66–100 MHz, < 15 pF, high drive
–
22
60
ps
2.5 V supply, > 100 MHz, < 15 pF, high drive
–
19
45
ps
Switching Waveforms
Figure 1. Duty Cycle Timing
t1
t2
VDD/2
VDD/2
VDD/2
Figure 2. All Outputs Rise/Fall Time
2.0 V(1.8 V)
0.8 V(0.6 V)
OUTPUT 2.0 V(1.8 V)
0.8 V(0.6 V)
3.3 V(2.5 V)
0V
t4
t3
Figure 3. Output-Output Skew
OUTPUT
VDD/2
VDD/2
OUTPUT
t5
Note
9. Typical jitter is measured at 3.3 V or 2.5 V, 29°C, with all outputs driven into the maximum specified load. Further information regarding jitter specifications may be
found in the application notes, “Understanding Data Sheet Jitter Specifications for Cypress Products.”
Document #: 38-07759 Rev. *C
Page 6 of 15
[+] Feedback
CY23EP05
Switching Waveforms (continued)
Figure 4. Input-Output Propagation Delay
INPUT
VDD/2
VDD/2
CLKOUT
t6
Figure 5. Part-Part Skew
VDD/2
Any output, Part 1 or 2
VDD/2
Any output, Part 1 or 2
t7
Test Circuits
Test Circuit # 1
V DD
CLK
0.1 μ F
OUTPUTS
C LOAD
V DD
0.1 μ F
Document #: 38-07759 Rev. *C
GND
GND
Page 7 of 15
[+] Feedback
CY23EP05
Supplemental Parametric Information
Delay REF Input to CLKn (ps)
Figure 6. 2.5 V Typical Room Temperature Graph for REF Input to CLKn Delay versus Loading
Difference between CLKOUT and CLKn. Data is shown for 66 MHz. Delay is a weak function of frequency
1500
1250
1000
750
500
250
0
-250
-500
-750
-1000
-1250
-1500
2.5V Standard Drive
2.5V High Drive
-20
-10
0
10
20
Load CLKOUT- Load CLKn (pF)
Figure 7. 3.3 V Typical Room Temperature Graph for REF Input to CLKn Delay versus Loading
Difference between CLKOUT and CLKn. Data is shown for 66 MHz. Delay is a weak function of frequency
Delay REF Input to CLKn (ps)
1000
3.3V Standard Drive
3.3V High Drive
800
600
400
200
0
-200
-400
-600
-800
-1000
-20
-10
0
10
20
Load CLKOUT- Load CLKn (pF)
Document #: 38-07759 Rev. *C
Page 8 of 15
[+] Feedback
CY23EP05
Figure 8. 2.7 V Measured Supply Current versus Frequency, Drive Strength, Loading, and Temperature.
Note that the 30-pF data above 100 MHz is beyond the data sheet specification of 22 pF
70
60
50
40
30
15pF, -45C, Standard Drive
15pF, 90C, Standard Drive
20
15pF, -45C, High Drive
15pF, 90C, High Drive
10
30pF, -45C, High Drive
30pF, 90C, High Drive
0
33
66
100
133
166
200
Frequency (MHz)
Figure 9. 3.6 V Measured Supply Current versus Frequency, Drive Strength, Loading, and Temperature.
Note that the 30-pF high-drive data above 100 MHz is beyond the data sheet specification of 22 pF
100
80
60
15pF, -45C, Standard Drive
15pF, 90C, Standard Drive
30pF, -45C, Standard Drive
30pF, 90C, Standard Drive
15pF, -45C, High Drive
15pF, 90C, High Drive
30pF, -45C, High Drive
30pF, 90C, High Drive
40
20
0
33
66
100
133
166
200
233
Frequency (MHz)
Document #: 38-07759 Rev. *C
Page 9 of 15
[+] Feedback
CY23EP05
Figure 10. Typical 3.3 V Measured Cycle-to-cycle Jitter at 29 °C, versus Frequency, Drive Strength, and Loading
350
15
15
30
30
300
250
pF, Standard Drive
pF, High Drive
pF, Standard Drive
pF, High Drive
200
150
100
50
0
0
50
100
150
200
250
Frequency (MHz)
Figure 11. Typical 2.5 V Measured Cycle-to-cycle Jitter at 29 °C, versus Frequency, Drive Strength, and Loading
400
15 pF, Standard Drive
15 pF, High Drive
30 pF, High Drive
350
300
250
200
150
100
50
0
0
20
40
60
80
100
120
140
160
180
200
Frequency (MHz)
Figure 12. Typical 3.3 V Measured Period Jitter at 29 °C, versus Frequency, Drive Strength, and Loading
250
15 pF, Standard Drive
15 pF, High Drive
30 pF, Standard Drive
30 pF, High Drive
200
150
100
50
0
0
50
100
150
250
200
Frequency (MHz)
Figure 13. Typical 2.5 V Measured Period Jitter at 29 °C, versus Frequency, Drive Strength, and Loading
250
15 pF, Standard Drive
15 pF, High Drive
30 pF, High Drive
200
150
100
50
0
0
20
40
60
80
100
120
140
160
180
200
Frequency (MHz)
Document #: 38-07759 Rev. *C
Page 10 of 15
[+] Feedback
CY23EP05
Figure 14. 100 MHz (top) and 156.25 MHz (bottom) Typical Phase-noise Data versus VDD and Drive Strength[10]
-90
SSB Phase Noise (dBc/Hz)
-100
3.3V High Drive
3.3V Standard Drive
-110
-120
2.5V High Drive
2.5V Standard Drive
-130
100 MHz
-140
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
Offset Frequency (Hz)
-90
SSB Phase Noise (dBc/Hz)
-100
3.3V High Drive
3.3V Standard Drive
-110
-120
2.5V High Drive
-130
2.5V Standard Drive
156.25 MHz
-140
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
Offset Frequency (Hz)
Note
10. Typical jitter is measured at 3.3 V or 2.5 V, 29°C, with all outputs driven into the maximum specified load. Further information regarding jitter specifications may be
found in the application notes, “Understanding Data Sheet Jitter Specifications for Cypress Products.”
Document #: 38-07759 Rev. *C
Page 11 of 15
[+] Feedback
CY23EP05
Ordering Information
Ordering Code
Package Type
Operating Range
Pb-free
CY23EP05SXC-1
8-pin 150-mil SOIC
Commercial
CY23EP05SXC-1T
8-pin 150-mil SOIC – tape and reel
Commercial
CY23EP05SXI-1
8-pin 150-mil SOIC
Industrial
CY23EP05SXI-1T
8-pin 150-mil SOIC – tape and reel
Industrial
CY23EP05SXC-1H
8-pin 150-mil SOIC
Commercial
CY23EP05SXC-1HT
8-pin 150-mil SOIC – tape and reel
Commercial
CY23EP05SXI-1H
8-pin 150-mil SOIC
Industrial
CY23EP05SXI-1HT
8-pin 150-mil SOIC – tape and reel
Industrial
Ordering Code Definitions
CY 23EP05
SX
(C, I)
- 1H
T
Tape and reel
High output drive strength option
Temperature range:
C = Commercial, I = Industrial
8-pin SOIC package Pb-free
Base part number (Enhanced
performance 5 output zero delay buffer)
Company Code: CY = Cypress
Document #: 38-07759 Rev. *C
Page 12 of 15
[+] Feedback
CY23EP05
Package Drawing and Dimensions
Figure 15. 8-Pin (150-mil) SOIC S8
51-85066 *D
Acronyms
Document Conventions
Table 1. Acronyms Used in this Document
Units of Measure
Acronym
Description
Table 2. Units of Measure
AC
alternating current
DC
direct current
dBc
decibels relative to carrier
PCI
peripheral component interconnect
°C
degree Celsius
PLL
phase-locked loop
Hz
hertz
SDRAM
synchronous dynamic random access memory
MHz
megahertz
SOIC
small-outline integrated circuit
Document #: 38-07759 Rev. *C
Symbol
Unit of Measure
μA
microampere
mA
milliampere
W
ohm
pF
picofarad
ps
picosecond
V
volt
W
watt
Page 13 of 15
[+] Feedback
CY23EP05
Document History Page
Document Title: CY23EP05 2.5 V or 3.3 V, 10-220-MHz, Low Jitter, 5 Output Zero Delay Buffer
Document Number: 38-07759
Revision
ECN
Orig. of
Change
Submission
Date
**
349620
RGL
See ECN
New datasheet
*A
401073
RGL
See ECN
Updated Delay vs. Load graph with standard drive data
Added Phase-noise graph
Description of Change
*B
413826
RGL
See ECN
Minor Change: typo – changed from CY23EP05SXC-T to CY23EP05SXC-1T
*C
3273677
CXQ
06/07/2011
1) Added typical column to the Operating Conditions table.
Included 3.3 V and 2.5 V typical specs for the two VDD rows.
2) All BW, ROUT, and Theta JA specs are moved to typical column with only
dashes left in the Min and Max columns. Removed the “(typical)” note from the
description cells for these specs.
3) All other specs just have a dash for the new typical column cells.
4) Changed Iil spec in 3.3-V DC Electrical Specifications and 2.5-V DC
Electrical Specifications tables from +/– 10 µA max to –10 µA min and 10 µA
max.
5) Added typical column to the DC Electrical Specifications tables. Typical
column is all kept dashes except for the first row VDD (3.3 V or 2.5 V respectively).
6) Changed t7 spec from +/– 150 ps max to –150 ps min and 150 ps max (same
for the 300 ps spec).
7) Updated package drawing to latest revision.
8) Added Ordering Code Definitions, Acronyms, Units sections.
Document #: 38-07759 Rev. *C
Page 14 of 15
[+] Feedback
CY23EP05
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2005-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07759 Rev. *C
Revised June 7, 2011
Page 15 of 15
All products and company names mentioned in this document may be the trademarks of their respective holders.
[+] Feedback