STK11C88 256 Kbit (32K x 8) SoftStore nvSRAM Features Functional Description ■ 25 ns and 45 ns access times ■ Pin compatible with industry standard SRAMs ■ Software initiated STORE and RECALL ■ Automatic RECALL to SRAM on power up ■ Unlimited Read and Write endurance ■ Unlimited RECALL cycles ■ 1,000,000 STORE cycles The Cypress STK11C88 is a 256 Kb fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap™ technology producing the world’s most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent, nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers under Software control from SRAM to the nonvolatile elements (the STORE operation). On power up, data is automatically restored to the SRAM (the RECALL operation) from the nonvolatile memory. RECALL operations are also available under software control. ■ 100 year data retention ■ Single 5V+10% power supply ■ Commercial and Industrial Temperatures ■ 28-pin (300 mil and 330 mil) SOIC packages ■ RoHS compliance Logic Block Diagram Cypress Semiconductor Corporation Document Number: 001-50591 Rev. ** • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 29, 2009 [+] Feedback STK11C88 Pin Configurations Figure 1. Pin Diagram - 28-Pin SOIC $ 9&& $ $ :( $ $ $ $ $ $ 2( $ $ &( 723 $ $ $ $ '4 '4 '4 '4 '4 '4 '4 966 '4 Table 1. Pin Definitions - 28-Pin SOIC Pin Name Alt IO Type A0–A14 Input DQ0-DQ7 Input or Output Description Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM. Bidirectional Data IO lines. Used as input or output lines depending on operation. WE W Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO pins is written to the specific address location. CE E Input Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. OE G Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE HIGH causes the IO pins to tri-state. VSS VCC Ground Ground for the Device. The device is connected to the ground of the system. Power Supply Power Supply Inputs to the Device. Document Number: 001-50591 Rev. ** Page 2 of 15 [+] Feedback STK11C88 Device Operation The STK11C88 is a versatile memory chip that provides several modes of operation. The STK11C88 can operate as a standard 32K x 8 SRAM. A 32K x 8 array of nonvolatile storage elements shadow the SRAM. SRAM data can be copied from nonvolatile memory or nonvolatile data can be recalled to the SRAM. SRAM Read The STK11C88 performs a READ cycle whenever CE and OE are LOW, while WE is HIGH. The address specified on pins A0–14 determines the 32,768 data bytes accessed. When the READ is initiated by an address transition, the outputs are valid after a delay of tAA (READ cycle 1). If the READ is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (READ cycle 2). The data outputs repeatedly respond to address changes within the tAA access time without the need for transitions on any control input pins, and remain valid until another address change or until CE or OE is brought HIGH. SRAM Write A WRITE cycle is performed whenever CE and WE are LOW. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either CE or WE goes HIGH at the end of the cycle. The data on the common IO pins DQ0–7 are written into the memory if it has valid tSD, before the end of a WE controlled WRITE or before the end of an CE controlled WRITE. Keep OE HIGH during the entire WRITE cycle to avoid data bus contention on common IO lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW. Software STORE Data is transferred from the SRAM to the nonvolatile memory by a software address sequence. The STK11C88 software STORE cycle is initiated by executing sequential CE controlled READ cycles from six specific address locations in exact order. During the STORE cycle, an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. When a STORE cycle is initiated, input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence. If they intervene, the sequence is aborted and no STORE or RECALL takes place. To initiate the software STORE cycle, the following READ sequence is performed: Document Number: 001-50591 Rev. ** 1. Read address 0x0E38, Valid READ 2. Read address 0x31C7, Valid READ 3. Read address 0x03E0, Valid READ 4. Read address 0x3C1F, Valid READ 5. Read address 0x303F, Valid READ 6. Read address 0x0FC0, Initiate STORE cycle The software sequence is clocked with CE controlled READs. When the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. It is important that READ cycles and not WRITE cycles are used in the sequence. It is not necessary that OE is LOW for a valid sequence. After the tSTORE cycle time is fulfilled, the SRAM is again activated for READ and WRITE operation. Software RECALL Data is transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE controlled READ operations is performed: 1. Read address 0x0E38, Valid READ 2. Read address 0x31C7, Valid READ 3. Read address 0x03E0, Valid READ 4. Read address 0x3C1F, Valid READ 5. Read address 0x303F, Valid READ 6. Read address 0x0C63, Initiate RECALL cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared, and then the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is once again ready for READ and WRITE operations. The RECALL operation does not alter the data in the nonvolatile elements. The nonvolatile data can be recalled an unlimited number of times. Hardware RECALL (Power Up) During power up or after any low power condition (VCC<VRESET), an internal RECALL request is latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete. If the STK11C88 is in a WRITE state at the end of power up RECALL, the SRAM data is corrupted. To help avoid this situation, a 10 Kohm resistor is connected either between WE and system VCC or between CE and system VCC. Page 3 of 15 [+] Feedback STK11C88 Hardware Protect Figure 3. Icc (max) Writes The STK11C88 offers hardware protection against inadvertent STORE operation and SRAM WRITEs during low voltage conditions. When VCC<VSWITCH, all externally initiated STORE operations and SRAM WRITEs are inhibited. Noise Considerations The STK11C88 is a high speed memory. It must have a high frequency bypass capacitor of approximately 0.1 µF connected between VCC and VSS, using leads and traces that are as short as possible. As with all high speed CMOS ICs, careful routing of power, ground, and signals help prevent noise problems. Low Average Active Power CMOS technology provides the STK11C88 the benefit of drawing significantly less current when it is cycled at times longer than 50 ns. Figure 2 and Figure 3 show the relationship between ICC and READ or WRITE cycle time. Worst case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100 percent duty cycle on chip enable). Only standby current is drawn when the chip is disabled. The overall average current drawn by the STK11C88 depends on the following items: 1. The duty cycle of chip enable 2. The overall cycle rate for accesses 3. The ratio of READs to WRITEs 4. CMOS versus TTL input levels 5. The operating temperature 6. The VCC level 7. IO loading Best Practices nvSRAM products have been used effectively for over 15 years. While ease-of-use is one of the product’s main system values, the experience gained working with hundreds of applications has resulted in the following suggestions as best practices: ■ The nonvolatile cells in a nvSRAM are programmed on the test floor during final test and quality assurance. Incoming inspection routines at customer or contract manufacturer’s sites, sometimes, reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. The end product’s firmware should not assume that a NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration and cold or warm boot status, should always program a unique NV pattern (for example, a complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. ■ Power up boot firmware routines should rewrite the nvSRAM into the desired state. While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently (program bugs or incoming inspection routines). Figure 2. Icc (max) Reads Document Number: 001-50591 Rev. ** Page 4 of 15 [+] Feedback STK11C88 Table 2. Software STORE/RECALL Mode Selection CE L WE H L H A13 – A0 0x0E38 0x31C7 0x03E0 0x3C1F 0x303F 0x0FC0 0x0E38 0x31C7 0x03E0 0x3C1F 0x303F 0x0C63 Mode Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL IO Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Notes [1, 2] [1, 2] Notes 1. The six consecutive addresses must be in the order listed. WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle. 2. While there are 15 addresses on the STK11C88, only the lower 14 are used to control software modes. Document Number: 001-50591 Rev. ** Page 5 of 15 [+] Feedback STK11C88 Maximum Ratings Voltage on DQ0-7 ...................................–0.5V to Vcc + 0.5V Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Power Dissipation ......................................................... 1.0W DC Output Current (1 output at a time, 1s duration).... 15 mA Operating Range Temperature under bias .............................. –55°C to +125°C Supply Voltage on VCC Relative to GND.......... –0.5V to 7.0V Voltage on Input Relative to Vss ............–0.6V to VCC + 0.5V Range Ambient Temperature VCC 0°C to +70°C 4.5V to 5.5V -40°C to +85°C 4.5V to 5.5V Commercial Industrial DC Electrical Characteristics Over the operating range (VCC = 4.5V to 5.5V) Parameter ICC1 Description Test Conditions Average VCC Current tRC = 25 ns tRC = 45 ns Dependent on output loading and cycle rate. Values obtained without output loads. IOUT = 0 mA. Min Max Unit Commercial 97 70 mA mA Industrial 100 70 mA mA ICC2 Average VCC Current All Inputs Do Not Care, VCC = Max during STORE Average current for duration tSTORE 3 mA ICC3 Average VCC Current WE > (VCC – 0.2V). All other inputs cycling. at tRC= 200 ns, 5V, Dependent on output loading and cycle rate. Values obtained 25°C Typical without output loads. 10 mA ISB1[3] Average VCC Current tRC=25ns, CE > VIH (Standby, Cycling tRC=45ns, CE > VIH TTL Input Levels) Commercial 30 22 mA Industrial 31 23 mA 750 μA ISB2[3] VCC Standby Current CE > (VCC – 0.2V). All others VIN < 0.2V or > (VCC – 0.2V). (Standby, Stable CMOS Input Levels) IIX Input Leakage Current VCC = Max, VSS < VIN < VCC -1 +1 μA IOZ Off State Output Leakage Current VCC = Max, VSS < VIN < VCC, CE or OE > VIH or WE < VIL -5 +5 μA VIH Input HIGH Voltage 2.2 VCC + 0.5 V VIL Input LOW Voltage VSS – 0.5 0.8 V VOH Output HIGH Voltage IOUT = –4 mA VOL Output LOW Voltage IOUT = 8 mA 0.4 V 2.4 V Data Retention and Endurance Parameter Description DATAR Data Retention NVC Nonvolatile STORE Operations Min Unit 100 Years 1,000 K Note 3. CE > VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. Document Number: 001-50591 Rev. ** Page 6 of 15 [+] Feedback STK11C88 Capacitance In the following table, the capacitance parameters are listed.[4] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 0 to 3.0 V Max Unit 5 pF 7 pF Thermal Resistance In the following table, the thermal resistance parameters are listed.[4] Parameter ΘJA ΘJC Test Conditions 28-SOIC (300 mil) 28-SOIC (330 mil) Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. TBD TBD °C/W TBD TBD °C/W Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Figure 4. AC Test Loads R1 480Ω 5.0V Output 30 pF R2 255Ω AC Test Conditions Input Pulse Levels .................................................. 0 V to 3 V Input Rise and Fall Times (10% - 90%)........................ <5 ns Input and Output Timing Reference Levels ................... 1.5 V Note 4. These parameters are guaranteed by design and are not tested. Document Number: 001-50591 Rev. ** Page 7 of 15 [+] Feedback STK11C88 AC Switching Characteristics SRAM Read Cycle Parameter Cypress Alt Parameter tACE tELQV [5] tAVAV, tELEH tRC tAA [6] tAVQV tDOE tGLQV tAXQX tOHA [6] tLZCE [7] tELQX tHZCE [7] tEHQZ [7] tGLQX tLZOE tHZOE [7] tGHQZ tPU [4] tELICCH tEHICCL tPD [4] 25 ns Description Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold After Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby Min 45 ns Max Min 25 Max 45 25 45 25 10 45 20 5 5 5 5 10 15 0 0 10 15 0 0 25 45 Unit ns ns ns ns ns ns ns ns ns ns ns Switching Waveforms Figure 5. SRAM Read Cycle 1: Address Controlled [5, 6] W5& $''5(66 W $$ W2+$ '4'$7$287 '$7$9$/,' Figure 6. SRAM Read Cycle 2: CE and OE Controlled [5] W5& $''5(66 W$&( W3' W/=&( &( W+=&( 2( W+=2( W'2( W/=2( '4'$7$287 '$7$9$/,' W 38 ,&& $&7,9( 67$1'%< Notes 5. WE must be HIGH during SRAM Read Cycles and LOW during SRAM WRITE cycles. 6. I/O state assumes CE and OE < VIL and WE > VIH; device is continuously selected. 7. Measured ±200 mV from steady state output voltage. Document Number: 001-50591 Rev. ** Page 8 of 15 [+] Feedback STK11C88 SRAM Write Cycle Parameter Cypress Parameter 25 ns Description Alt tAVAV tWLWH, tWLEH tELWH, tELEH tDVWH, tDVEH tWHDX, tEHDX tAVWH, tAVEH tAVWL, tAVEL tWHAX, tEHAX tWLQZ tWHQX tWC tPWE tSCE tSD tHD tAW tSA tHA tHZWE [7,8] tLZWE [7] Min Write Cycle Time Write Pulse Width Chip Enable To End of Write Data Setup to End of Write Data Hold After End of Write Address Setup to End of Write Address Setup to Start of Write Address Hold After End of Write Write Enable to Output Disable Output Active After End of Write 45 ns Max 25 20 20 10 0 20 0 0 Min Max 45 30 30 15 0 30 0 0 10 5 15 5 Unit ns ns ns ns ns ns ns ns ns ns Switching Waveforms Figure 7. SRAM Write Cycle 1: WE Controlled [9] tWC ADDRESS tHA tSCE CE tAW tSA tPWE WE tSD tHD DATA VALID DATA IN tHZWE DATA OUT tLZWE HIGH IMPEDANCE PREVIOUS DATA Figure 8. SRAM Write Cycle 2: CE Controlled [9] tWC ADDRESS CE WE tHA tSCE tSA tAW tPWE tSD DATA IN DATA OUT tHD DATA VALID HIGH IMPEDANCE Notes 8. If WE is Low when CE goes Low, the outputs remain in the high impedance state. 9. CE or WE must be greater than VIH during address transitions. Document Number: 001-50591 Rev. ** Page 9 of 15 [+] Feedback STK11C88 STORE INHIBIT or Power Up RECALL Parameter tHRECALL [10] tSTORE [6] VRESET VSWITCH Alt tRESTORE tHLHZ Description Power up RECALL Duration STORE Cycle Duration Low Voltage Reset Level Low Voltage Trigger Level STK11C88 Min Max 550 10 3.6 4.0 4.5 Unit μs ms V V Switching Waveforms Figure 9. STORE INHIBIT/Power Up RECALL VCC 5V VSWITCH VRESET STORE INHIBIT POWER-UP RECALL tHRECALL DQ (DATA OUT) POWER-UP RECALL BROWN OUT STORE INHIBIT BROWN OUT STORE INHIBIT BROWN OUT STORE INHIBIT NO RECALL (VCC DID NOT GO BELOW VRESET) NO RECALL (VCC DID NOT GO BELOW VRESET) RECALL WHEN VCC RETURNS ABOVE VSWITCH Notes 10. tHRECALL starts from the time VCC rises above VSWITCH. Document Number: 001-50591 Rev. ** Page 10 of 15 [+] Feedback STK11C88 Software Controlled STORE/RECALL Cycle The software controlled STORE/RECALL cycle follows. [11, 12] Parameter tRC tSA [11] tCW[11] tHACE[11] tRECALL[11] Alt 25 ns Description Min 45 ns Max Min Max Unit tAVAV STORE/RECALL Initiation Cycle Time 25 45 ns tAVEL Address Setup Time 0 0 ns tELEH Clock Pulse Width 20 30 ns tELAX Address Hold Time 20 20 ns RECALL Duration 20 20 μs Switching Waveforms Figure 10. CE Controlled Software STORE/RECALL Cycle [12] tRC ADDRESS # 1 ADDRESS tSA tRC ADDRESS # 6 tSCE CE tHACE OE t STORE / t RECALL DQ (DATA) DATA VALID DATA VALID HIGH IMPEDANCE Notes 11. The software sequence is clocked on the falling edge of CE without involving OE (double clocking abort the sequence). 12. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles. Document Number: 001-50591 Rev. ** Page 11 of 15 [+] Feedback STK11C88 Part Numbering Nomenclature STK11C88 - N F 25 I TR Packaging Option: TR = Tape and Reel Blank = Tube Temperature Range: Blank - Commercial (0 to 70°C) I - Industrial (-40 to 85°C) Speed: 25 - 25 ns 45 - 45 ns Lead Finish F = 100% Sn (Matte Tin) Package: N = Plastic 28-pin 300 mil SOIC S = Plastic 28-pin 330 mil SOIC Ordering Information Speed (ns) 25 45 Ordering Code Package Diagram Operating Range Package Type STK11C88-NF25TR 51-85026 28-Pin SOIC (300 mil) STK11C88-NF25 51-85026 28-Pin SOIC (300 mil) STK11C88-SF25TR 51-85058 28-Pin SOIC (330 mil) STK11C88-SF25 51-85058 28-Pin SOIC (330 mil) STK11C88-NF25ITR 51-85026 28-Pin SOIC (300 mil) STK11C88-NF25I 51-85026 28-Pin SOIC (300 mil) STK11C88-SF25ITR 51-85058 28-Pin SOIC (330 mil) STK11C88-SF25I 51-85058 28-Pin SOIC (330 mil) STK11C88-NF45TR 51-85026 28-Pin SOIC (300 mil) STK11C88-NF45 51-85026 28-Pin SOIC (300 mil) STK11C88-SF45TR 51-85058 28-Pin SOIC (330 mil) STK11C88-SF45 51-85058 28-Pin SOIC (330 mil) STK11C88-NF45ITR 51-85026 28-Pin SOIC (300 mil) STK11C88-NF45I 51-85026 28-Pin SOIC (300 mil) STK11C88-SF45ITR 51-85058 28-Pin SOIC (330 mil) STK11C88-SF45I 51-85058 28-Pin SOIC (330 mil) Commercial Industrial Commercial Industrial All parts are Pb-free. The above table contains Final information. Contact your local Cypress sales representative for availability of these parts Document Number: 001-50591 Rev. ** Page 12 of 15 [+] Feedback STK11C88 Package Diagrams Figure 11. 28-Pin (300 mil) SOIC (51-85026) NOTE : PIN 1 ID 1. JEDEC STD REF MO-119 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT 14 DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE. 1 MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE 3. DIMENSIONS IN INCHES 0.291[7.39] MIN. MAX. 4. PACKAGE WEIGHT 0.85gms 0.300[7.62] 0.394[10.01] * 0.419[10.64] 15 28 PART # S28.3 STANDARD PKG. SZ28.3 LEAD FREE PKG. 0.026[0.66] 0.032[0.81] SEATING PLANE 0.697[17.70] 0.713[18.11] 0.092[2.33] 0.105[2.67] 0.004[0.10] 0.050[1.27] 0.013[0.33] 0.004[0.10] 0.019[0.48] 0.0118[0.30] * 0.0091[0.23] 0.0125[3.17] 0.015[0.38] 0.050[1.27] * TYP. 51-85026-*D 51 85127 *A Document Number: 001-50591 Rev. ** Page 13 of 15 [+] Feedback STK11C88 Package Diagrams (continued) Figure 12. 28-Pin (330 mil) SOIC (51-85058) 51-85058-*A Document Number: 001-50591 Rev. ** Page 14 of 15 [+] Feedback STK11C88 Document History Page Document Title: STK11C88 256 Kbit (32K x 8) SoftStore nvSRAM Document Number: 001-50591 Rev. ECN No. Orig. of Change Submission Date ** 2625096 GVCH/PYRS 12/19/08 Description of Change New data sheet Sales, Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers PSoC Solutions psoc.cypress.com clocks.cypress.com General Low Power/Low Voltage psoc.cypress.com/solutions psoc.cypress.com/low-power Wireless wireless.cypress.com Precision Analog Memories memory.cypress.com LCD Drive psoc.cypress.com/lcd-drive image.cypress.com CAN 2.0b psoc.cypress.com/can USB psoc.cypress.com/usb Image Sensors psoc.cypress.com/precision-analog © Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-50591 Rev. ** Revised January 29, 2009 Page 15 of 15 AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback