STK14C88 32 K x 8 AutoStore nvSRAM Features Description ■ 25 ns, 35 ns, and 45 ns read access and R/W cycle time The Cypress STK14C88 is a 256 Kb fast static RAM with a nonvolatile Quantum Trap storage element included with each memory cell. ■ Unlimited read/write endurance ■ Automatic nonvolatile STORE on power loss ■ Nonvolatile STORE under hardware or software control ■ Automatic RECALL to SRAM on power up ■ Unlimited RECALL cycles ■ 1-Million STORE cycles ■ 100-year nonvolatile data retention ■ Single 5 V + 10% power supply The Cypress nvSRAM is the first monolithic nonvolatile memory to offer unlimited writes and reads. It is the highest performance, most reliable nonvolatile memory available. ■ Commercial, industrial, military temperatures For a complete list of related documentation, click here. ■ 32-Pin 300 mil SOIC (RoHS-compliant) ■ 32-Pin CDIP and LCC packages The SRAM provides the fast access and cycle times, ease of use, and unlimited read and write endurance of a normal SRAM. Data automatically transfers to the nonvolatile storage cells when power loss is detected (the STORE operation). On power up, data is automatically restored to the SRAM (the RECALL operation). Both STORE and RECALL operations are also available under software control. Logic Block Diagram VCCX DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 POWER CONTROL STORE STATIC RAM ARRAY 512 x 512 STORE/ RECALL CONTROL RECALL SOFTWARE DETECT COLUMN I/O INPUT BUFFERS A5 A6 A7 A8 A9 A11 A12 A13 A14 ROW DECODER Quantum Trap 512 x 512 VCAP HSB A0 - A13 COLUMN DEC A0 A1 A2 A3 A4 A10 G E W Cypress Semiconductor Corporation Document Number: 001-52038 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 31, 2015 STK14C88 Contents Pin Configurations ........................................................... 3 Pin Descriptions ............................................................... 3 Absolute Maximum Ratings ............................................ 4 DC Characteristics ........................................................... 4 AC Test Conditions .......................................................... 5 Capacitance ...................................................................... 5 SRAM Read Cycles #1 and #2 ......................................... 6 SRAM Write Cycle #1 and #2 ........................................... 7 Hardware Mode Selection................................................ 8 Hardware STORE Cycle ................................................... 8 AutoStore/Power up RECALL ......................................... 9 Software STORE/RECALL Mode Selection .................. 10 Software-Controlled STORE/RECALL Cycle................ 10 nvSRAM Operation......................................................... 11 Noise Considerations..................................................... 11 SRAM Read ..................................................................... 11 SRAM Write ..................................................................... 11 Power Up RECALL ......................................................... 11 Software Nonvolatile STORE......................................... 11 Software Nonvolatile RECALL ...................................... 11 Document Number: 001-52038 Rev. *F AutoStore Mode.............................................................. AutoStore INHIBIT Mode................................................ HSB Operation ................................................................ Best Practices................................................................. Preventing STORES ....................................................... Hardware Protect............................................................ Low Average Active Power............................................ Ordering Information...................................................... Commercial and Industrial Ordering Information....... Military Ordering Information ..................................... Package Diagrams.......................................................... Acronyms ........................................................................ Document Conventions ................................................. Units of Measure ....................................................... Document History Page ................................................ Sales, Solutions, and Legal Information ...................... Worldwide Sales and Design Support....................... Products .................................................................... PSoC Solutions ......................................................... 11 12 12 13 13 13 13 14 14 15 16 19 19 19 20 21 21 21 21 Page 2 of 21 STK14C88 Pin Configurations 27 A9 7 26 A11 8 25 NC A2 9 24 G NC 10 23 A10 A1 A0 11 22 12 21 E DQ7 DQ0 13 20 DQ1 DQ2 14 19 DQ6 DQ5 15 18 DQ4 VSS 16 17 DQ3 (TOP) W 6 HSB A5 A4 A3 A6 A13 A5 A8 A4 A3 A11 A9 NC G (TOP) A2 NC A1 A10 A0 E DQ0 DQ7 DQ6 5 W A13 A8 DQ5 A6 29 28 VCap 4 VCCx HSB 30 DQ4 31 3 DQ3 2 A12 A7 A14 A14 VSS VCC A7 32 DQ2 1 DQ1 VCAP Figure 2. Pin Diagram - 32-Pin 450 Mil LCC A12 Figure 1. Pin Diagram - 32-Pin 300 Mil SOIC/CDIP Pin Descriptions Pin Name I/O A14-A0 Input DQ7-DQ0 I/O E Input Chip Enable: The active low E input selects the device. W Input Write Enable: The active low W enables data on the DQ pins to be written to the address location latched by the falling edge of E. G Input Output Enable: The active low G input enables the data output buffers during read cycles. Deasserting G high caused the DQ pins to tristate. VCC HSB Description Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array. Data: Bidirectional 8-bit data bus for accessing the nvSRAM. Power Supply Power: 5.0 V +10%. I/O Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak pull-up resistor keeps this pin high if not connected (optional connection). VCAP Power Supply AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile storage elements. VSS Power Supply Ground. NC No Connect Unlabeled pins have no internal connections. Document Number: 001-52038 Rev. *F Page 3 of 21 STK14C88 Absolute Maximum Ratings Note Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on Input Relative to Ground...............–0.5 V to 7.0 V Voltage on Input Relative to VSS .........–0.6 V to (VCC + 0.5 V) Voltage on DQ0-7 or HSB ....................–0.5 V to (VCC + 0.5 V) Temperature under Bias ............................. –55 C to 125 C Storage Temperature .................................. –65 C to 150 C Power Dissipation............................................................ 1 W DC Output Current (1 output at a time, 1s duration).... 15 mA DC Characteristics Over the operating range (VCC = 5.0 V ± 10%)[4] Symbol Parameter Commercial Industrial/ Military Unit Notes Min Max Min Max Average VCC current – 97 80 70 – 100 85 70 mA mA mA tAVAV = 25 ns tAVAV = 35 ns tAVAV = 45 ns ICC2[2] Average VCC current during STORE – 3 – 3 mA All Inputs Don’t Care, VCC = max ICC3[1] Average VCC Current at tAVAV = 200 ns 5V, 25°C, Typical – 10 – 10 mA W (V CC – 0.2 V) All others cycling, CMOS levels ICC4[2] Average VCAP current during AutoStore Cycle – 2 – 2 mA All Inputs Don’t Care ISB1[3] Average VCC current (Standby, Cycling TTL Input Levels) – 30 25 22 – 31 26 23 mA mA mA tAVAV = 25 ns, E VIH tAVAV = 35 ns, E VIH tAVAV = 45 ns, E VIH ISB2[3] VCC Standby current (Standby, Stable CMOS Input Levels) – 1.5 – 1.5 mA E (V CC – 0.2 V) All Others VIN 0.2 V or (VCC – 0.2 V) IILK Input Leakage current – 1 – 1 A VCC = max VIN = VSS to VCC IOLK Off-State output leakage current – 5 – 5 A VCC = max VIN = VSS to VCC, E or G VIH VIH Input Logic “1” voltage 2.2 VCC + 0.5 2.2 VCC +0.5 V All inputs VIL Input Logic “0” voltage VSS – .5 0.8 VSS – .5 0.8 V All inputs VOH Output Logic “1” voltage 2.4 – 2.4 – V IOUT = – 4 mA except HSB VOL Output Logic “0” voltage – 0.4 – 0.4 V IOUT = 8 mA except HSB VBL Logic “0” voltage on HSB output – 0.4 – 0.4 V IOUT = 3 mA TA Operating temperature 0 70 –40/–55 85/125 C ICC1 [1] Notes 1. ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. 2. ICC2 and ICC4 are the average currents required for the duration of the respective STORE cycles (tSTORE). 3. E VIH does not produce standby current levels until any nonvolatile cycle in progress has timed out. 4. VCC reference levels throughout this datasheet refer to VCC if that is where the power supply connection is made, or VCAP if VCC is connected to ground. Document Number: 001-52038 Rev. *F Page 4 of 21 STK14C88 AC Test Conditions Input pulse levels.................................................... 0 V to 3 V Input rise and fall times ............................................... <5 ns Input and output timing reference levels ....................... 1.5 V Output load........................................................ See Figure 3 Figure 3. AC Output Loading 5.0 V 480 Ohms OUTPUT 255 Ohms 30 pF INCLUDING SCOPE AND FIXTURE Capacitance Parameter[5] Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25 C, f = 1 MHz, Max Unit Conditions 5 pF V = 0 to 3 V 7 pF V = 0 to 3 V Note 5. These parameters are guaranteed but not tested. Document Number: 001-52038 Rev. *F Page 5 of 21 STK14C88 SRAM Read Cycles #1 and #2 (VCC = 5.0 V ± 10%)[9] NO. Symbols #1, #2 Alt. 1 tELQV tACS 2 3 tAVAV[6], tELEH[6] tAVQV7 4 STK14C88-25 STK14C88-35 STK14C88-45 Parameter Unit Min Max Min Max Min Max Chip enable access time – 25 – 35 – 45 tRC Read cycle time 25 35 – 45 – ns tAA Address access time – 25 – 35 – 45 ns tGLQV tOE Output enable to data valid – 10 – 15 – 20 ns 5 tAXQX[7] tOH Output hold after address change 5 – 5 – 5 – ns 6 tELQX tLZ Address change or chip enable to output active 5 – 5 – 5 – ns 7 tEHQZ[8] tHZ Address change or chip disable to output inactive – 10 – 13 – 15 ns 8 tGLQX tOLZ Output enable to output active 0 – 0 – 0 – ns 9 tGHQZ[8] tELICCH[10] tEHICCL[10] tOHZ Output disable to output inactive – 10 – 13 15 ns 0 10 11 tPA Chip enable to power active 0 – tPS Chip disable to power standby – 25 35 ns 0 – ns – 45 ns Figure 4. SRAM Read Cycle 1: Address Controlled [6, 7] 2 tAVAV ADDRESS 3 tAVQV 5 tAXQX DQ (DATA OUT) DATA VALID Figure 5. SRAM Read Cycle 2: E and G Controlled [6] 2 29 1 11 6 7 3 4 9 8 10 Notes 6. W and HSB must be high during SRAM read cycles. 7. I/O state assumes E and G < VIL and W VIH; device is continuously selected. 8. Measured ± 200 mV from steady state output voltage. 9. VCC reference levels throughout this datasheet refer to VCC if that is where the power supply connection is made, or VCAP if VCC is connected to ground. 10. These parameters are guaranteed but not tested. Document Number: 001-52038 Rev. *F Page 6 of 21 STK14C88 SRAM Write Cycle #1 and #2 (VCC = 5.0 V ± 10%)[15] Symbols NO. #1 #2 12 tAVAV tAVAV 13 tWLWH tWLEH 14 tELWH tELEH 15 tDVWH tDVEH 16 tWHDX tEHDX 17 tAVWH tAVEH 18 tAVWL tAVEL 19 tWHAX tEHAX 20 tWLQZ[11, 12] 21 tWHQX Alt. tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW STK14C88-25 STK14C88-35 STK14C88-45 Parameter Write cycle time Write pulse width Chip enable to end of write Data setup to end of write Data hold after end of write Address setup to end of write Address setup to start of write Address hold after end of write Write enable to output disable Min 25 20 20 10 0 20 0 0 – Max – – – – – – – – 10 Min 35 25 25 12 0 25 0 0 – Max – – – – – – – – 13 Min 45 30 30 15 0 30 0 0 – Max – – – – – – – – 15 Output active after end of write 5 – 5 – 5 – Unit ns ns ns ns ns ns ns ns ns ns Figure 6. SRAM Write Cycle 1: W Controlled [13, 14] 12 tAVAV ADDRESS 19 tWHAX 14 tELWH E 17 tAVWH 18 tAVWL 13 tWLWH W 15 tDVWH DATA IN DATA VALID 20 tWLQZ DATA OUT 13 tWHDX 21 tWHQX HIGH IMPEDANCE PREVIOUS DATA Figure 7. SRAM Write Cycle 2: E Controlled [13, 14] 12 tAVAV ADDRESS 18 tAVEL 14 tELEH 19 tEHAX E 17 tAVEH W 13 tWLEH 15 tDVEH DATA IN DATA OUT 16 tEHDX DATA VALID HIGH IMPEDANCE Notes 11. Measured ± 200 mV from steady state output voltage. 12. If W is low when E goes low, the outputs remain in the high impedance state. 13. E or W must be VIH during address transitions. 14. HSB must be high during SRAM write cycles. 15. VCC reference levels throughout this datasheet refer to VCC if that is where the power supply connection is made, or VCAP if VCC is connected to ground. Document Number: 001-52038 Rev. *F Page 7 of 21 STK14C88 Hardware Mode Selection E W HSB A13 - A0 (hex) Mode I/O Power Notes H X H X Not Selected Output High Z Standby – L H H X Read SRAM Output Data Active 23 L L H X Write SRAM Input Data Active – X X L X Nonvolatile STORE Output High Z lCC2 16 Hardware STORE Cycle No. 22 Symbols Standard Alternate tSTORE tHLHZ STK14C88 Parameter Units Notes Min Max STORE cycle duration – 10 ms 17 23 tDELAY tHLQZ Time allowed to complete SRAM cycle 1 – s 17 24 tRECOVER tHHQX Hardware STORE High to inhibit Off – 700 ns 17, 18 25 tHLHX Hardware STORE pulse width 15 – ns – 26 tHLBL Hardware STORE Low to STORE busy – 300 ns – Figure 8. Hardware STORE Cycle 25 tHLHX HSB (IN) 24 tRECOVER 22 tSTORE HSB (OUT) 27 tHLBL HIGH IMPEDANCE HIGH IMPEDANCE 23 tDELAY DQ (DATA OUT) DATA VALID DATA VALID Notes 16. HSB STORE operation occurs only if an SRAM write is done since the last nonvolatile cycle. After the STORE (if any) completes, the part goes into standby mode, inhibiting all operations until HSB rises 17. E and G low, W high for output behavior. 18. tRECOVER is only applicable after tSTORE is complete. Document Number: 001-52038 Rev. *F Page 8 of 21 STK14C88 AutoStore/Power up RECALL NO. Symbols Standard 27 tRESTORE STK14C88 Parameter Alt. 28 tSTORE tVSBL tHLHZ 30 tDELAY 31 VSWITCH Low voltage trigger level 32 VRESET Low voltage reset level tBLQZ Notes 550 s 19 Max – Power up RECALL duration 29 Unit Min STORE cycle duration – 10 ms 17, 20 Low voltage trigger (VSWITCH) to HSB Low – 300 ns 13 Time allowed to complete SRAM cycle 1 – s 17 4.0 4.5 V – – 3.6 V – Figure 9. AutoStore/POWER UP RECALL VCC 31 VSWITCH 27 VRESET AutoStore POWER UP RECALL 30 tVSBL 28 tRESTORE 29 tSTORE HSB 31 tDELAY W DQ (DATA OUT) POWER UP RECALL BROWN OUT NO STORE (NO SRAM Writes) BROWN OUT AutoStore BROWN OUT AutoStore NO RECALL (VCC DID NOT GO BELOW VRESET) NO RECALL (VCC DID NOT GO BELOW VRESET) RECALL WHEN VCC RETURNS ABOVE VSWITCH Notes 19. tRESTORE starts from the time VCC rises above VSWITCH. 20. HSB is asserted low for 1s when VCAP drops through VSWITCH. If an SRAM write has not taken place since the last nonvolatile cycle, HSB is released and no STORE takes place. Document Number: 001-52038 Rev. *F Page 9 of 21 STK14C88 Software STORE/RECALL Mode Selection E W A13 - A0 (hex) Mode I/O L H 0E38 31C7 03E0 3C1F 303F Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Output Data Output Data Output Data Output Data Output Data Active 0FC0 Nonvolatile STORE Output High Z ICC2 0E38 31C7 03E0 3C1F 303F 0C63 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL Output Data Output Data Output Data Output Data Output Data Output High Z Active L H POWER Notes 17, 21, 22, 23 17, 21, 22, 23 Software-Controlled STORE/RECALL Cycle NO. Symbols Parameter Standard Alt. 33 tAVAV tRC STORE/RECALL initiation cycle time 34 tAVEL tAS Address setup time 35 tELEH tCW 36 tELAX 37 tRECALL STK14C88-25 STK14C88-35 STK14C88-45 Min Max Min 35 – 0 – Clock pulse width 25 Address hold time 20 RECALL duration – Max Unit Notes Max Min 45 – 55 – ns 17 0 – 0 – ns 24, 25 – 30 – 35 – ns 24, 25 – 20 – 20 – ns 24, 25 20 – 20 – 20 s – Figure 10. E Controlled Software STORE/RECALL Cycle [25] 33 33 tAVAV ADDRESS tAVAV ADDRESS #1 34 tAVEL ADDRESS #6 35 tELEH E 36 tELAX 29 tSTORE DQ (DATA DATA VALID DATA VALID 37 / tRECALL HIGH IMPEDANCE Notes 21. The six consecutive addresses must be in the order listed. W must be high during all six consecutive E controlled cycles to enable a nonvolatile cycle. 22. While there are 15 addresses on the STK14C88, only the lower 14 are used to control software modes. 23. I/O state assumes G < VIL. Activation of nonvolatile cycles does not depend on state of G. 24. The software sequence is clocked on the falling edge of E controlled reads without involving G (double clocking aborts the sequence). 25. The six consecutive addresses must be in the order listed in the Software STORE/RECALL Mode Selection Table: (0E38, 31C7, 03E0, 3C1F, 303F, 0FC0) for a STORE cycle or (0E38, 31C7, 03E0, 3C1F, 303F, 0C63) for a RECALL cycle. W must be high during all six consecutive cycles. Document Number: 001-52038 Rev. *F Page 10 of 21 STK14C88 nvSRAM Operation Software Nonvolatile STORE The STK14C88 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as a standard-fast SRAM. In nonvolatile mode, data is transferred from SRAM to nonvolatile elements (the STORE operation) or from nonvolatile elements to SRAM (the RECALL operation). In this mode, SRAM functions are disabled. The STK14C88 software STORE cycle is initiated by executing sequential E controlled read cycles from six specific address locations. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. The program operation copies the SRAM data into nonvolatile memory. When a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Noise Considerations The STK14C88 is a high-speed memory and so must have a high frequency bypass capacitor of approximately 0.1 F connected between VCAP and VSS, using leads and traces that are as short as possible. As with all high-speed CMOS ICs, careful routing of power, ground, and signals helps to prevent noise problems. SRAM Read Because a sequence of reads from specific addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence, or the sequence will be aborted and no STORE or RECALL takes place. To initiate the software STORE cycle, the following read sequence must be performed: 1. Read address 0E38 (hex) Valid READ 2. Read address 31C7 (hex) Valid READ 3. Read address 03E0 (hex) Valid READ 4. Read address 3C1F (hex) Valid READ 5. Read address 303F (hex) Valid READ 6. Read address 0FC0 (hex) Initiate STORE cycle The STK14C88 performs a read cycle whenever E and G are low, and W and HSB are high. The address specified on pins A0-14 determines which of the 32,768 data bytes are accessed. When the read is initiated by an address transition, the outputs are valid after a delay of tAVQV (Read cycle #1). If the read is initiated by E or G, the outputs are valid at tELQV or at tGLQV, whichever is later (Read cycle #2). The data outputs repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and remain valid until another address change or until E or G is brought high, or W or HSB is brought low. After the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. Use only read cycles in the sequence, although it is not necessary that G be low for the sequence to be valid. After the tSTORE cycle time is fulfilled, the SRAM is again activated for read and write operation. SRAM Write Software Nonvolatile RECALL A write cycle is performed whenever E and W are low, and HSB is high. The address inputs must be stable prior to entering the write cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 are written into the memory if it is valid tDVWH before the end of a W controlled write or tDVEH before the end of an E controlled write. A software RECALL cycle is initiated with a sequence of read operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of E controlled read operations must be performed: 1. Read address 0E38 (hex) Valid READ 2. Read address 31C7 (hex) Valid READ 3. Read address 03E0 (hex) Valid READ 4. Read address 3C1F (hex) Valid READ 5. Read address 303F (hex) Valid READ 6. Read address 0C63 (hex) Initiate RECALL cycle Keep G high during the entire write cycle to avoid data bus contention on common I/O lines. If G is left low, internal circuitry turns off the output buffers tWLQZ after W goes low. Power Up RECALL During power up, or after any low-power condition (VCAP < VRESET), an internal RECALL request is latched. When VCAP again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tRESTORE to complete. If the STK14C88 is in a write state at the end of power-up RECALL, the SRAM data will be corrupted. To avoid this, a 10 k resistor should be connected either between W and system VCC or between E and system VCC. The software sequence must be clocked with E controlled reads. Internally, RECALL is a two step procedure. First, the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for read and write operations. The RECALL operation in no way alters the data in the nonvolatile elements. The nonvolatile data can be recalled an unlimited number of times. AutoStore Mode The STK14C88 can be powered in one of three modes. During normal AutoStore operation, the STK14C88 draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. After power up, when the voltage on the VCAP pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC and initiate a STORE operation. Document Number: 001-52038 Rev. *F Page 11 of 21 STK14C88 To prevent unneeded STORE operations, automatic STOREs and those initiated by externally driving HSB low are ignored unless at least one write operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a write operation has taken place. If the power supply drops faster than 20 ms/volt before VCC reaches VSWITCH, then a 2.2 resistor should be inserted between VCC and the system supply to avoid momentary excess of current between Vcc and VCAP. Figure 11. AutoStore Mode 1 32 10k 10k 31 + 0.1F Bypass 68F 6v, ±20% 30 16 17 AutoStore INHIBIT Mode If an automatic STORE on power loss is not required, then VCC can be tied to ground and system power applied to VCAP (Figure 12). This is the AutoStore Inhibit mode, in which the AutoStore function is disabled. If the STK14C88 is operated in this configuration, references to VCC should be changed to VCAP throughout this data sheet. In this mode, STORE operations may be triggered through software control. It is not permissible to change between these three options “on the fly.” Document Number: 001-52038 Rev. *F 10K? 1 10K? Figure 12. AutoStore Inhibit Mode 0.1µF Bypass Figure 11 shows the proper connection of capacitors for automatic store operation. A charge storage capacitor having a capacity of between 68 µF and 220 µF (±20%) rated at 6 V should be provided. In system power mode, both VCC and VCAP are connected to the + 5 V power supply without the 68 µF capacitor. In this mode, the AutoStore function of the STK14C88 operates on the stored system charge as power goes down. The user must, however, guarantee that VCC does not drop below 3.6 V during the 10 ms STORE cycle. If an automatic STORE on power loss is not required, then VCC can be tied to ground and + 5 V applied to VCAP (Figure 12). This is the AutoStore Inhibit mode, in which the AutoStore function is disabled. If the STK14C88 is operated in this configuration, references to VCC should be changed to VCAP throughout this datasheet. In this mode, STORE operations may be triggered through software control or the HSB pin. To enable or disable AutoStore using an I/O port pin, see Preventing STORES on page 13. 32 31 30 16 17 HSB Operation The STK14C88 provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin can be used to request a hardware STORE cycle. When the HSB pin is driven low, the STK14C88 conditionally initiates a STORE operation after tDELAY; an actual STORE cycle only begins if a write to the SRAM took place since the last STORE or RECALL cycle. The HSB pin has a very resistive pull-up and is internally driven low to indicate a busy condition when the STORE (initiated by any means) is in progress. Pull up this pin with an external 10 k resistor to VCAP if HSB is used as a driver. SRAM read and write operations that are in progress when HSB is driven low by any means are given time to complete before the STORE operation is initiated. After HSB goes low, the STK14C88 continues SRAM operations for tDELAY. During tDELAY, multiple SRAM read operations may take place. If a write is in progress when HSB is pulled low it is allowed a time, tDELAY, to complete. However, any SRAM write cycles requested after HSB goes low are inhibited until HSB returns high. The HSB pin can be used to synchronize multiple STK14C88s while using a single larger capacitor. To operate in this mode, the HSB pin should be connected together to the HSB pins from the other STK14C88s. An external pull-up resistor to + 5 V is required because HSB acts as an open drain pull-down. The VCAP pins from the other STK14C88 parts can be tied together and share a single capacitor. The capacitor size must be scaled by the number of devices connected to it. When any one of the STK14C88s detects a power loss and asserts HSB, the common HSB pin causes all parts to request a STORE cycle (a STORE takes place in those STK14C88s that are written since the last nonvolatile cycle). During any STORE operation, regardless of how it was initiated, the STK14C88 continues to drive the HSB pin low, releasing it only when the STORE is complete. Upon completion of the STORE operation the STK14C88 remains disabled until the HSB pin returns high. If HSB is not used, leave it unconnected. Page 12 of 21 STK14C88 Best Practices Low Average Active Power nvSRAM products have been used effectively for over 15 years. While ease-of-use is one of the product’s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: The STK14C88 draws significantly less current when it is cycled at times longer than 50 ns. Figure 13 shows the relationship between ICC and read cycle time. Worst case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5 V, 100% duty cycle on chip enable). Figure 14 shows the same relationship for write cycles. If the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. The overall average current drawn by the STK14C88 depends on the following items: ■ ■ The nonvolatile cells in an nvSRAM are programmed on the test floor during final test and quality assurance. Incoming inspection routines at customer or contract manufacturer’s sites sometimes reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. The end product’s firmware should not assume an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, and so on, should always program a unique NV pattern (for example, complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. Power-up boot firmware routines should rewrite the nvSRAM into the desired state (such as autostore enabled). While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently (program bugs, incoming inspection routines, and so on). The VCAP value specified in this datasheet includes a minimum and a maximum value size. Best practice is to meet this requirement and not exceed the max VCAP value because the nvSRAM internal algorithm calculates VCAP charge time based on this max VCAP value. Customers who want to use a larger VCAP value to make sure there is extra store charge and store time should discuss their VCAP size selection with Cypress to understand any impact on the VCAP voltage level at the end of a tRECALL period. ■ CMOS versus TTL input levels ■ The duty cycle of chip enable ■ The overall cycle rate for accesses ■ The ratio of reads to writes ■ The operating temperature ■ The VCC level ■ I/O loading. Figure 13. Icc (max) Reads 100 Average Active Current (mA) ■ 80 60 40 TTL 20 Preventing STORES Hardware Protect The STK14C88 offers hardware protection against inadvertent STORE operation and SRAM writes during low-voltage conditions. When VCAP < VSWITCH, all externally initiated STORE operations and SRAM writes are inhibited. AutoStore can be completely disabled by tying VCC to ground and applying + 5 V to VCAP. This is the AutoStore Inhibit mode; in this mode STOREs are only initiated by explicit request using either the software sequence or the HSB pin. Document Number: 001-52038 Rev. *F CMOS 0 50 100 150 Cycle Time (ns) 200 Figure 14. Icc (max) Writes 100 Average Active Current (mA) The STORE function can be disabled on the fly by holding HSB high with a driver capable of sourcing 30 mA at a VOH of at least 2.2 V, because it must overpower the internal pull down device that drives HSB low for 20 ms at the onset of a STORE. When the STK14C88 is connected for AutoStore operation (system VCC connected to VCC and a 68 uF capacitor on VCAP) and VCC crosses VSWITCH on the way down, the STK14C88 attempts to pull HSB low; if HSB does not actually get below VIL, the part stops trying to pull HSB low and abort the STORE attempt. 80 60 TTL 40 CMOS 20 0 50 100 150 Cycle Time (ns) 200 Page 13 of 21 STK14C88 Ordering Information These parts are not recommended for new designs. Part Number Description Access Times Temperature STK14C88-C45I 5-V 32 K x 8 AutoStore nvSRAM CDIP32-300 45 ns Industrial STK14C88-5L35M 5-V 32 K x 8 AutoStore nvSRAM LCC32-300 35 ns Military STK14C88-5L45M 5-V 32 K x 8 AutoStore nvSRAM LCC32-300 45 ns Military STK14C88-5C35M 5-V 32 K x 8 AutoStore nvSRAM CDIP32-300 35 ns Military STK14C88-5K45M 5-V 32 K x 8 AutoStore nvSRAM CDIP32-300 45 ns Military Commercial and Industrial Ordering Information STK14C88 - N F 45 I TR Packaging Option: Blank = Tube TR = Tape and Reel Temperature Range: Blank = Commercial (0 to 70 °C) I - Industrial (–40 to 85 °C) Speed: 25 = 25 ns 35 = 35 ns 45 = 45 ns Lead Finish F = 100% Sn (Matte Tin) Package N = Plastic 32-pin 300 mil SOIC C = Ceramic 32-pin 300 mil CDIP L = Ceramic 32-pad LCC Document Number: 001-52038 Rev. *F Page 14 of 21 STK14C88 Military Ordering Information STK14C88 - 5 C 45 M Temperature Range M = Military (–55 to 125 °C) Access Time 35 = 35 ns 45 = 45 ns Package L=Ceramic 32-pad LCC C=Ceramic 32-pin 300 mil CDIP K=Ceramic 32-pin 300 mil CDIP with solder dip finish Retention / Endurance 5 = Military (105 Cycles) Document Number: 001-52038 Rev. *F Page 15 of 21 STK14C88 Package Diagrams Figure 15. 32-Pin 300 mil SOIC Gull Wing (51-85127) 51-85127 *D Document Number: 001-52038 Rev. *F Page 16 of 21 STK14C88 Package Diagrams (continued) Figure 16. 32-Pin 300 mil Side Braze DIL (001-51694) 001-51694 *C Document Number: 001-52038 Rev. *F Page 17 of 21 STK14C88 Package Diagrams (continued) Figure 17. 32-Pad (450-Mil) LCC (51-80068) 51-80068 *C Document Number: 001-52038 Rev. *F Page 18 of 21 STK14C88 Acronyms Document Conventions Description Units of Measure nvSRAM nonvolatile static random access memory Symbol SSOP shrink small-outline package °C degrees Celsius SOIC small-outline integrated circuit Hz hertz TSOP II thin small outline package kbit 1024 bits FBGA fine-pitch ball grid array kHz kilohertz RoHS restriction of hazardous substances k kilohm I/O input/output A microampere CMOS complementary metal oxide semiconductor mA milliampere EIA electronic industries alliance F microfarad RWI read and write inhibited MHz megahertz s microsecond ms millisecond ns nanosecond pF picofarad V volt ohm W watt Acronym Document Number: 001-52038 Rev. *F Unit of Measure Page 19 of 21 STK14C88 Document History Page Document Title: STK14C88 32 K x 8 AutoStore nvSRAM Document Number: 001-52038 Rev. ECN No. Orig. of Change Submission Date Description of Change ** 2668632 GVCH 03/04/2009 *A 2718242 GVCH 06/12/09 *B 2821358 GVCH 12/04/2009 Added Note in Ordering Information mentioning that these parts are not recommended for new designs. Added “Not recommended for New Designs” watermark in the PDF. Added Contents on page 2. *C 3210316 GVCH 03/30/2011 Moved contents of page 14 to page 10. Updated package diagram. Added Acronyms and Document Conventions. *D 3530341 GVCH 02/20/2012 Removed inactive parts (STK14C88-NF35, STK14C88-NF25TR, STK14C88-NF35TR, STK14C88-NF45TR, STK14C88-NF35I, STK14C88-NF25ITR, STK14C88-NF35ITR and STK14C88-NF45ITR) from Ordering Information table. Updated Package Diagrams 51-85127 (from Rev *B to *C) and 51-80068 (from Rev *A to *B) *E 4579541 GVCH 11/25/2014 Added documentation related hyperlink in page 1 Removed pruned parts - STK14C88-NF25, STK14C88-NF45, STK14C88-NF25I, STK14C88-NF45I, STK14C88-5C45M and STK14C88-5K35M Updated package diagrams from 001-51694 *A to 001-51694 *B and 51-80068 *B to 51-80068 *C *F 4706588 GVCH 03/31/2015 Updated package diagram from 001-51694 *B to 001-51694 *C Updated package diagram from 51-85127 *C to 51-85127 *D Document Number: 001-52038 Rev. *F New data sheet Ordering Information description: Corrected typo Page 20 of 21 STK14C88 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing cypress.com/go/memory cypress.com/go/image PSoC Touch Sensing cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2009-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-52038 Rev. *F Revised March 31, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 21 of 21