SITRONIX ST8016S

ST8016S
COM/SEG LCD Driver
Datasheet
Version 0.24
2009/10/01
Note: This is not a final specification.
Some parameters are subject to change.
ST8016S
1.
FEATURES
Number of LCD drive outputs: 160
Supply voltage for LCD drive: +15.0 to +30.0 V
Supply voltage for the logic system: +2.5 to +5.5 V
Low power consumption
Low output impedance
(Segment mode)
Shift clock frequency
- 20 MHz (MAX.): VDD = +5.0 ± 0.5 V
- 15 MHz (MAX.): VDD = +3.0 to + 4.5 V
- 12 MHz (MAX.): VDD = +2.5 to + 3.0 V
Adopts a data bus system
4-bit/8-bit parallel input modes are
selectable with a mode (MD) pin
Automatic transfer function of an
enable signal
Automatic counting function which, in
the chip selection mode, causes the
internal clock to be stopped by
automatically counting 160 bits of
input data
Line latch circuits are reset when
/DISPOFF active
2.
(Common mode)
Shift clock frequency: 4 MHz (MAX.)
Built-in 160-bit bi-directional shift
register (divisible into 80 bits x 2)
Available in a single mode (160-bit
shift register) or in a dual mode
(80-bit shift register x 2)
Y1->Y160 Single mode
Y160->Y1 Single mode
Y1->Y80, Y81->Y160 Dual mode
Y160->Y81, Y80->Y1 Dual mode
The above 4 shift directions are
pin-selectable
Shift register circuits are reset when
/DISPOFF active
DESCRIPTION
The ST8016S is a 160-output segment/common driver IC suitable for driving large/medium scale
dot matrix LCD panels, and is used in personal computers/work stations. The ST8016S is good
both as a segment driver and a common driver, and it can create a low power consuming,
high-resolution LCD.
Preliminary Ver 0.24
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2009/10/01
ST8016S
3.
BLOCK DIAGRAM
V0R
FR
/DISPOFF
V12R
V43R
VSS
Y1
Y2
Y159
Y160
VSS
LEVEL
SHIFTER
160-BIT 4-LEVEL DRIVER
V43L
160
EIO1
EIO2
V12L
160-BIT LEVEL SHIFTER
ACTIVE
CONTROL
V0L
160
160-BIT LINE LATCH/SHIFT REGISTER
16
LP
XCK
16
16
8 BIT
DATA
LATCH
CONTROL
LOGIC
8
DATA LATCH CONTROL
L/R
MD
SP CONVERSION & DATA CONTROL
(4 to 8 or 8 to 8)
S/C
DI0
4.
DI1
DI2
DI3
DI4
DI5
DI6
DI7
VDD
VSS
FUNCTIONAL OPERATIONS OF EACH BLOCK
BLOCK
FUNCTION
In case of segment mode, controls the selection or non-selection of the chip.
Following an LP signal input, and after the chip selection signal is input, a selection
signal is generated internally until 160 bits of data have been read in.
Active Control
Once data input has been completed, a selection signal for cascade connection is
output, and the chip is non-selected.
In case of common mode, controls the input/output data of bi-directional pins.
In case of segment mode, keeps input data which are 2 clocks of XCK at 4-bit parallel
SP Conversion
input mode in latch circuit, or keeps input data which are 1 clock of XCK at 8-bit parallel
& Data Control
input mode in latch circuit; after that they are put on the internal data bus 8 bits at a time.
In case of segment mode, selects the state of the data latch which reads in the data bus
Data Latch Control signals. The shift direction is controlled by the control logic. For every 16 bits of data
read in, the selection signal shifts one bit based on the state of the control circuit.
In case of segment mode, latches the data on the data bus. The latch state of each LCD
Data Latch
drive output pin is controlled by the control logic and the data latch control; 160 bits of
data are read in 20 sets of 8 bits.
In case of segment mode, all 160 bits which have been read into the data latch are
simultaneously latched at the falling edge of the LP signal, and are output to the level
Line Latch/
Shift Register
shifter block. In case of common mode, shifts data from the data input pin at the falling
edge of the LP signal.
Level Shifter
The logic voltage signal is level-shifted to the LCD drive voltage level, and is output to
the driver block.
Drives the LCD drive output pins from the line latch/shift register data, and selects one of
4-Level Driver
4 levels (V0, V12, V43 or VSS) based on the S/C, FR and /DISPOFF signals.
Controls the operation of each block. In case of segment mode, when an LP signal has
been input, all blocks are reset and the control logic waits for the selection signal output
Control Logic
from the active control block. Once the selection signal has been output, operation of the
data latch and data transmission is controlled, 160 bits of data are read in, and the chip
is non-selected. In case of common mode, controls the direction of data shift.
Preliminary Ver 0.24
Page 3/26
2009/10/01
ST8016S
5.
INPUT/OUTPUT CIRCUITS
V DD
I
To Internal Circuit
Applicable Pins
L/R , S/C , DI6~DI0 ,
/DISPOFF , LP , FR , MD
GND (0V)
Figure 1 Input Circuit (1)
V DD
I
To Internal Circuit
Applicable Pins
DI7 , XCK
Control Signal
GND (0V)
GND (0V)
Figure 2 Input Circuit (2)
Preliminary Ver 0.24
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ST8016S
V DD
To Internal
Circuit
I/O
Control Signal
GND (0V)
GND (0V)
VDD
Output Signal
Application Pins
EIO1 , EIO2
Control Signal
GND(0V)
Figure 3 Input/Output Circuit
V0
V12
V0
Control Signal 1
Control Signal 2
Control Signal 3
Control Signal 4
O
GND(0V)
V43
GND (0V)
Application Pins
Y1~Y160
VSS
Figure 4 LCD Drive Output Circuit
Preliminary Ver 0.24
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ST8016S
6.
6.1
FUNCTIONAL DESCRIPTION
Pin Functions
(Segment mode)
SYMBOL
VDD
GND
LGND
VSS
V0L, V0R
V12L, V12R
V43L, V43R
DI7-DI0
XCK
LP
L/R
/DISPOFF
FR
MD
S/C
ElO1, EIO2
FUNCTION
Logic system power supply pin
Connected to +2.5 to +5.5 V.
Ground pin
Logic system power ground pin
Do not short LGND with GND and Vss by ITO on LCD panel
Connect it to GND on PCB or FPC.
Connect to GND by ITO on LCD panel.
Bias power supply pins for LCD drive voltage
Normally use the bias voltages set by a resistor divider
Ensure that voltages are set such that VSS < V43 < V12 < V0.
ViL and ViR (i = 0,12, 43) must connect to an external power supply, and supply regular
voltage which is assigned by specification for each power pin
Input pins for display data
In 4-bit parallel mode, DI3-DI0 are the display data input pins, and DI7-DI4 must be
connected to LGND or VDD.
In 8-bit parallel mode, All DI7-Dl0 pins are the display data input pins.
Refer to section 6.2.2.
Clock input pin for taking display data
Data is read at the falling edge of the clock pulse.
Latch pulse input pin for display data
Data is latched at the falling edge of the clock pulse.
Input pin for selecting the reading direction of display data
When set to LGND level "L", data is read sequentially from Y160 to Y1.
When set to VDD level "H", data is read sequentially from Y1 to Y160.
Refer to section 6.2.2.
Control input pin for output of non-select level
The input signal is level-shifted from logic voltage level to LCD drive voltage level, and
controls the LCD drive circuit.
When set to LGND level "L", the LCD drive output pins (Y1-Y160) are set to level Vss.
When set to "L", the contents of the line latch are reset, but the display data are read in
the
data latch regardless of the condition of /DISPOFF. When the /DISPOFF function is
canceled
the driver outputs non-select level (V12 or V43), then outputs the contents of the data
latch at the next falling edge of the LP. At that time, if /DISPOFF removal time does not
correspond to what is shown in AC characteristics, it cannot output the reading data
correctly.
Table of truth-values is shown in "TRUTH TABLE" in Functional Operations.
AC signal input pin for LCD drive waveform
The input signal is level-shifted from logic voltage level to LCD drive voltage level, and
controls the LCD drive circuit.
Normally it inputs a frame inversion signal.
The LCD drive output pins' output voltage levels can be set using the line latch output
signal and the FR signal.
Table of truth-values is shown in "TRUTH TABLE" in Functional Operations.
Mode selection pin
When set to LGND level "L", 4-bit parallel input mode is set.
When set to VDD level "H", 8-bit parallel input mode is set.
Refer to section 6.2.2.
Segment mode/common mode selection pin
When set to VDD level "H", segment mode is set.
Input/output pins for chip selection
When L/R input is at LGND level "L", ElO1 is set for output, and EIO2 is set for input.
Preliminary Ver 0.24
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ST8016S
Y1 -Y160
(Common mode)
SYMBOL
VDD
GND
LGND
VSS
V0L, V0R
V12L, V12R
V43L, V43R
ElO1
EIO2
LP
L/R
/DISPOFF
FR
When L/R input is at VDD level "H", ElO1 is set for input, and EIO2 is set for output.
During output, set to "H" while LP • XCK is "H" and after 160 bits of data have been
read, set
to "L” for one cycle (from falling edge to failing edge of XCK), after which it returns to
"H".
During input, the chip is selected while El is set to "L" after the LP signal is input. The
chip is non-selected after 160 bits of data have been read.
LCD drive output pins
Corresponding directly to each bit of the data latch, one level (V0, V12 or V43) is
selected and output.
Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
FUNCTION
Logic system power supply pin
Connected to +2.5 to +5.5 V.
Ground pin
Logic system power ground pin
Do not short LGND with GND and Vss by ITO on LCD panel
Connect it to GND on PCB or FPC.
Connect to GND by ITO on LCD panel.
Bias power supply pins for LCD drive voltage
Normally use the bias voltages set by a resistor divider.
Ensure that voltages are set such that VSS < V43 < V12 < V0.
ViL and ViR (i = 0,12, 43) must connect to an external power supply, and supply regular
voltage that is assigned by specification for each power pin.
Shift data input/output pin for bi-directional shift register
Output pin when L/R is at LGND level "L', input pin when L/R is at VDD level "H".
When L/R = H, ElO1 is used as input pin, it will be pulled down.
When L/R = L, ElO1 is used as output pin, it won't be pulled down.
Refer to section 6.2.2.
Shift data input/output pin for bi-directional shift register
Input pin when L/R is at LGND level "L", output pin when L/R is at VDD level "H".
When L/R = L, EIO2 is used as input pin, it will be pulled down.
When L/R = H, EIO2 is used as output pin, it won't be pulled down.
Refer to section 6.2.2.
Shift clock pulse input pin for bi-directional shift register
* Data is shifted at the falling edge of the clock pulse.
Input pin for selecting the shift direction of bi-directional shift register
Data is shifted from Y160 to Y1 when set to LGND level "L", and data is shifted from Y1 to
Y160 when set to VDD level "H".
Refer to section 6.2.2.
Control input pin for output of non-select level
The input signal is level-shifted from logic voltage level to LCD drive voltage level, and
controls the LCD drive circuit.
When set to LGND level "L", the LCD drive output pins (Y1-Y160) are set to level Vss.
When set to "L”, the contents of the shift register are reset to not reading data. When
the /DISPOFF function is canceled, the driver outputs non-select level (V12 or V43), and
the shift data is read at the next falling edge of the LP. At that time, if /DISPOFF
removal time does not correspond to what is shown in AC characteristics, the shift data
is not read correctly.
Table of truth-values is shown in "TRUTH TABLE" in Functional Operations.
AC signal input pin for LCD drive waveform
The input signal is level-shifted from logic voltage level to LCD drive voltage level, and
controls the LCD drive circuit.
Normally it inputs a frame inversion signal.
The LCD drive output pins' output voltage levels can be set using the shift register
output signal and the FR signal.
Table of truth-values is shown in "TRUTH TABLE" in Functional Operations.
Preliminary Ver 0.24
Page 7/26
2009/10/01
ST8016S
MD
DI7
S/C
DI6-DI0
XCK
Y1 -Y160
6.2
6.2.1
Mode selection pin
When set to LGND level "L", single mode operation is selected; when set to VDD level
"H" dual mode operation is selected.
Refer to section 6.2.2.
Dual mode data input pin
According to the data shift direction of the data shift register, data can be input starting
from the 81st bit.
When the chip is used in dual mode, DI7 will be pulled down.
When the chip is used in single mode, DI7 won't be pulled down(Connect to LGND or
VDD, avoiding floating.).
Refer to section 6.2.2.
Segment mode/common mode selection pin
When set to LGND level "L", common mode is set.
Not used
Connect DI6-DI0 to LGND or VDD, avoiding floating.
Not used
XCK is pulled down in common mode, so connect to LGND or open.
LCD drive output pins
Corresponding directly to each bit of the shift register, one level (V0, V12, V43, or VSS) is
selected and output.
Table of truth-values is shown in "TRUTH TABLE" in Functional Operations.
Functional Operations
Truth table
(Segment Mode)
FR
LATCH DATA
/DISPOFF
LCD DRIVE OUTPUT VOLTAGE LEVEL (Y1-Y160)
L
L
H
V43
L
H
H
VSS
H
L
H
V12
H
H
H
V0
X
X
L
VSS
(Common Mode)
FR
LATCH DATA
/DISPOFF
LCD DRIVE OUTPUT VOLTAGE LEVEL (Y1-Y160)
L
L
H
V43
L
H
H
V0
H
L
H
V12
H
H
H
VSS
X
X
L
VSS
NOTES:
VSS < V43 < V12 < V0
L : LGND (0 V), H : VDD (+2.5 to +5.5 V), X : Don't care
"Don't care" should be fixed to "H" or "L", avoiding floating.
There are two kinds of power supply (logic level voltage and LCD drive voltage) for the LCD driver.
Supply regular voltage that is assigned by specification for each power pin.
Preliminary Ver 0.24
Page 8/26
2009/10/01
ST8016S
6.2.2
Relationship between the display data and LCD drive output Pins
(Segment Mode)
(a) 4-bit Parallel Input Mode
MD
L/R
L
L
L
H
(b)
EIO1
EIO2
DATA
INPUT
DI0
Dl1
DI2
DI3
DI0
Dl1
DI2
DI3
Output Input
Input Output
40
39
CLOCK CLOCK
Y1
Y5
Y2
Y6
Y3
Y7
Y4
Y8
Y160
Y156
Y159
Y155
Y158
Y154
Y157
Y153
NUMBER OF CLOCKS
38
… 3 CLOCK 2 CLOCK 1 CLOCK
CLOCK
Y9
…
Y149
Y153
Y157
Y10
…
Y150
Y154
Y158
Y11
…
Y151
Y155
Y159
Y12
…
Y152
Y156
Y160
Y152
…
Y12
Y8
Y4
Y151
…
Y11
Y7
Y3
Y150
…
Y10
Y6
Y2
Y149
…
Y9
Y5
Y1
20
CLOCK
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y160
Y159
Y158
Y157
Y156
Y155
Y154
Y153
NUMBER OF CLOCKS
18
… 3 CLOCK 2 CLOCK 1 CLOCK
CLOCK
Y17
…
Y137
Y145
Y153
Y18
…
Y138
Y146
Y154
Y19
…
Y139
Y147
Y155
Y20
…
Y140
Y148
Y156
Y21
Y141
Y149
Y157
Y22
Y142
Y150
Y158
Y23
Y143
Y151
Y159
Y24
Y144
Y152
Y160
Y144
…
Y24
Y16
Y8
Y143
…
Y23
Y15
Y7
Y142
…
Y22
Y14
Y6
Y141
…
Y21
Y13
Y5
Y140
…
Y20
Y12
Y4
Y139
…
Y19
Y11
Y3
Y138
…
Y18
Y10
Y2
Y137
…
Y17
Y9
Y1
8-bit Parallel Input Mode
MD
L/R
H
L
H
H
EIO1
Output Input
Input Output
(Common Mode)
MD
L
(Single)
H
(Dual)
EIO2
L/R
L
H
L
H
DATA
INPUT
DI0
Dl1
DI2
DI3
DI4
DI5
DI6
DI7
DI0
Dl1
DI2
DI3
DI4
Dl5
DI6
DI7
19
CLOCK
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y152
Y151
Y150
Y149
Y148
Y147
Y146
Y145
DATA TRANSFER DIRECTION
Y160 → Y1
Y1 → Y160
Y160 → Y81
Y80 → Y1
Y1 → Y80
Y81 → Y160
EIO1
Output
Input
EIO2
Input
Output
DI7
X
X
Output
Input
Input
Input
Output
Input
NOTES:
L : LGND (0 V), H : VDD (+2.5 to +5.5 V), X : Don't care
"Don't care" should be fixed to "H" or "L", avoiding floating.
Preliminary Ver 0.24
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ST8016S
6.2.3
(a)
Connection examples of plural segment drivers
When L/R = “L”
Top data
Last data
Data flow
Y160
Y1
Y160
Y1
Y160
Y1
EIO2
EIO1
EIO2
EIO1
EIO2
EIO1
L/R
L/R
L/R
Y160
FR
DI7-DI0
Y1
MD
XCK
Y160
LP
DI7-DI0
Y1
FR
Y160
MD
Y1
LP
XCK
EIO2
XCK
DI7-DI0
EIO1
LP
DI7-DI0
EIO2
FR
EIO1
MD
EIO2
XCK
EIO1
XCK
LP
MD
FR
DI7-DI0
8
LGND
(b)
When L/R = “H”
VDD
XCK
LP
MD
FR
DI7-DI0
8
DI7-DI0
FR
MD
LP
L/R
XCK
DI7-DI0
FR
MD
LP
FR
MD
LP
XCK
L/R
LGND
L/R
Data flow
Last data
Top data
Preliminary Ver 0.24
Page 10/26
2009/10/01
ST8016S
6.2.4
Timing chart of 4-device cascade connection of segment drivers
FR
LP
XCK
TOP DATA
DI7 - DI 0
n*
1
2
LAST DATA
n*
device A
1
2
n*
device B
1
2
n*
device C
1
2
n*
1
2
device D
EI
(device A)
EO
(device A)
EO
(device B)
EO
(device C)
*n = 40 in 4-bit parallel input mode
*n = 20 in 8-bit parallel input mode
Preliminary Ver 0.24
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ST8016S
6.2.5
(a)
Connection examples for plural common drivers
Single Mode (L/R = ”L”)
Last
First
FLM
Y160
Y1
Y160
Y1
Y160
Y1
EIO2
EIO1
EIO2
EIO1
EIO2
EIO1
FR
L/R
/DISPOFF
DI7
MD
LP
FR
/DISPOFF
L/R
DI7
MD
LP
FR
/DISPOFF
MD
L/R
DI7
LP
LP
LGND(V DD)
LGND
/DISPOFF
FR
(b)
Single Mode (L/R = “H”)
FR
/DISPOFF
V DD
LGND
LGND(V DD)
LP
DI7
LP
L/R
Y1
EIO2
Y160
Last
First
Preliminary Ver 0.24
EIO1
MD
Y160
FR
EIO2
/DISPOFF
LP
MD
Y1
DI7
EIO1
L/R
Y160
FR
EIO2
/DISPOFF
LP
MD
DI7
Y1
/DISPOFF
EIO1
L/R
FR
FLM
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ST8016S
(c)
Dual Mode (L/R = “L”)
Last 1
First
Y160
Y1
EIO2
EIO1
FLM1
First 2
Y160 Y81
Y80
EIO2
Last 2
Y1
Y160
Y1
EIO1
EIO2
EIO1
FR
/DISPOFF
L/R
DI7
MD
LP
FR
L/R
/DISPOFF
DI7
MD
LP
FR
L/R
/DISPOFF
DI7
MD
LP
LP
FLM2
LGND (V DD)
V DD
VSS
/DISPOFF
FR
(d)
Dual mode (L/R = “H”)
FR
/DISPOFF
V DD
LGND
LGND (V DD)
FLM2
LP
DI7
Page 13/26
LP
Last 1 First 2
Y1
MD
Y81 Y160
/DISPOFF
Y1 Y80
EIO1
L/R
EIO2
FR
EIO1
LP
MD
DI7
/DISPOFF
Y160
L/R
EIO2
FR
Preliminary Ver 0.24
LP
First 1
MD
Y1
DI7
/DISPOFF
EIO1
L/R
FR
FLM1
EIO2
Y160
Last 2
2009/10/01
ST8016S
7.
PRECAUTIONS
Precautions when connecting or disconnecting the power supply
This IC has a high-voltage LCD driver, so a high current that may flow if voltage is supplied to the
LCD drive power supply while the logic system power supply is floating may permanently damage
it. The details are as follows,
When connecting the power supply, connect the LCD drive power after connecting the logic
system power. Furthermore, when disconnecting the power, disconnect the logic system power
after disconnecting the LCD drive power
It is advisable to connect the serial resistor (4.7Ω to 50Ω) or fuse to the LCD drive power V0 of
the system as a current limiter. Set up a suitable value of the resistor in consideration of the
display grade.
And when connecting the logic power supply, the logic condition of this IC inside is insecure.
Therefore connect the LCD drive power supply after resetting logic condition of this IC inside on
/DISPOFF function. After that, cancel the /DISPOFF function after the LCD drive power supply
has become stable. Furthermore, when disconnecting the power, set the LCD drive output pins to
level LGND on /DISPOFF function. Then disconnect the logic system power after disconnecting
the LCD drive power.
When connecting the power supply, follow the recommended sequence shown here
VDD
VDD
LGND
VDD
/DISPOFF
LGND
V0
V0
GND
.
Preliminary Ver 0.24
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2009/10/01
ST8016S
8.
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply voltage (1)
Supply voltage (2)
Input voltage
SYMBOL
VDD
V0
V12
V43
VI
APPLICABLE PINS
VDD
V0L, V0R
V12L, V12R
V43L, V43R
D17-DI0, XCK, LP, L/R, FR,
MD, S/C, EIO1, EIO2,
/DISPOFF
RATING
-0.3~ +7.0
-0.3 ~ +33.0
V0 -10~ V0 + 0.3
-0.3 ~ VSS + 10
UNIT
V
V
V
V
-0.3 to VDD + 0.3
V
NOTE
1,2
Storage temperature
TSTG
-45 to +125
°C
NOTES:
1. TA = +25 °C
2. The applicable voltage on logic pins with respect to LGND, high voltage pins with VSS (0 V).
3. Stress over the “Absolute Max. Ratings” conditions will damage the device permanently.
9.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
APPLICABLE PINS
MIN.
TYP. MAX. UNIT NOTE
Supply voltage (1)
VDD
VDD
+2.5
+5.5
V
1, 2
Supply voltage (2)
V0
V0L, V0R
+15.0
+30.0
V
°C
Operating temperature
TOPR
-25
+85
NOTES:
1. The applicable voltage on logic pins with respect to LGND, high voltage pins with VSS (0 V).
2. Ensure that voltages are set such that VSS < V43 < Vl2 < V0.
Preliminary Ver 0.24
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ST8016S
10.
10.1
ELECTRICAL CHARACTERISTICS
DC Characteristics
(Segment Mode)
PARAMETER
Input "Low" voltage
(LGND =VSS = 0 V, VDD = +2.5 to +5.5 V, V0 = + 15.0 to +30.0 V, TOPR = -25 to +85°C)
SYMBOL
CONDITIONS
APPLICABLE PINS
MIN. TYP. MAX. UNIT NOTE
VIL
DI7-DI0, XCK, LP, L/R
0.2VDD V
FR, MD, S/C, EIO1, EIO2,
V
Input "High" voltage
VIH
0.8VDD
/DISPOFF
Output "Low" voltage
V0L
IOL = +0.4 mA
+0.4
V
EIO1, EIO2
Output "High" voltage
V0H
IOH = -0.4 mA
VDD-0.4
V
ILIL
VI = LGND
DI7-DI0, XCK, LP, LIR,
-10
µA
Input leakage current
FR, MD, S/C, EIO1, EIO2,
ILIH
VI = VDD
+10
µA
/DISPOFF
|∆VON|
Output resistance
RON
V0 = 30 V
Y1-Y160
1.0
1.5
kΩ
=0.5V
Standby current
ISTB
LGND
50
µA
1
Supply current (1)
IDD1
VDD
2.0
mA
2
(Non-selection)
Supply current (2)
IDD2
VDD
7.0
mA
3
(Selection)
Supply current (3)
I0
V0L, V0R
0.9
mA
4
NOTES:
1. VDD = +5.0 V, V0 = +30.0 V, Vi = LGND.
2. VDD = +5.0 V, V0 = +30.0 V, fXCK = 8 MHz, no-load, El = VDD. The input data is turned over by data taking
clock (4-bit parallel input mode).
3. VDD = +5.0 V, V0 = +30.0 V, fXCK = 8 MHz, no-load, El = LGND. The input data is turned over by data taking
clock (4-bit parallel input mode).
4. VDD = +5.0 V, V0 = +30.0 V, fXCK = 8MHz, fLP = 19.2 kHz, fFR = 80 Hz, no-load. The input data is turned over
by data taking clock (4-bit parallel input mode).
(Common Mode)
(LGND =VSS = 0 V, VDD = +2.5 to +5.5 V, V0 = + 15.0 to +30.0 V, TOPR = -25 to +85 °C)
CONDITIONS
APPLICABL E PINS MIN. TYP. MAX. UNIT NOTE
PARAMETER
SYMBOL
Input "Low" voltage
VIL
DI7-DI0, XCK, LP, L/R
0.2VDD V
FR, MD, S/C, EIO1,
Input "High" voltage
VIH
V
0.8VDD
EIO2, /DISPOFF
Output "Low" voltage
V0L
IOL = +0.4 mA
+0.4
V
EIO1, EIO2
Output "High" voltage
V0H
IOH = -0.4 mA
VDD-0.4
V
DI7-DI0, XCK, LP,
LIR, FR, MD, S/C,
ILIL
VI = LGND
-10.0 µA
EIO1, EIO2,
Input leakage current
/DISPOFF
DI6-DI0, LP, L/R, FR,
ILIH
VI = VDD
+10.0 µA
MD, S/C, /DISPOFF
Input pull-down current
IPD
VI = VDD
DI7, XCK, EIO1, EIO2
100
µA
|∆VON|
Output resistance
RON
V0 = 30 V
Y1-Y160
1.0
1.5
kΩ
=0.5V
Standby current
ISPD
LGND
50
µA
1
Supply current (1)
IDD
VDD
80
µA
2
Supply current (2)
I0
V0L, V0R
130
µA
2
NOTES:
1. VDD = +5.0 V, V0 = +30.0 V, VI = LGND
2. VDD = +5.0 V, V0 = +30.0 V, fLP =19.2 kHz, fFR = 80 Hz, 1/240 duty operation, no-load.
Preliminary Ver 0.24
Page 16/26
2009/10/01
ST8016S
10.2
AC Characteristics
(Segment Mode 1)
(LGND =VSS = 0 V, VDD = +2.5 to +3.0 V, V0 = + 15.0 to +30.0 V, TOPR = -25 10+85 °C)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP. MAX. UNIT NOTE
Shift clock period
tWCK
tR,tF ≤ 11ns
125
ns
1
Shift clock "H" pulse width
tWCKH
51
ns
Shift clock "L" pulse width
tWCKL
51
ns
Data setup time
tDS
30
ns
Data hold time
tDH
40
ns
Latch pulse "H" pulse width
tWLPH
51
ns
Shift clock rise to latch pulse rise
tLD
0
ns
time
Shift clock fall to latch pulse fall
tSL
51
ns
time
Latch pulse rise to shift clock rise
tLS
51
ns
time
Latch pulse fall to shift clock fall
tLH
51
ns
time
Enable setup time
tS
36
ns
Input signal rise time
tR
50
ns
2
Input signal fall time
tF
50
ns
2
DISPOFF removal time
tSD
100
ns
DISPOFF "L" pulse width
tWDL
1.2
µs
Output delay time (1)
tD
CL = 15 pF
78
ns
Output delay time (2)
tPD1, t PD2
CL = 15 pF
1.2
µs
Output delay time (3)
t PD3
CL = 15 pF
1.2
µs
NOTES:
1. Takes the cascade connection into consideration.
2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation.
(Segment Mode 2)
(LGND =VSS = 0 V, VDD = +5.0±0.5 V, V0 = + 15.0 to +30.0 V, TOPR = -25 to +85 °C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP. MAX. UNIT NOTE
Shift clock period
tWCK
tR,tF ≤ 10ns
66
ns
1
Shift clock "H" pulse width
tWCKH
23
ns
Shift clock "L” pulse width
tWCKL
23
ns
Data setup time
tDS
15
ns
Data hold time
tDH
23
ns
Latch pulse "H" pulse width
tWLPH
30
ns
Shift clock rise to latch pulse rise
tLD
0
ns
time
Shift clock fall to latch pulse fall
tSL
50
ns
time
Latch pulse rise to shift clock rise
tLS
30
ns
time
Latch pulse fall to shift clock fall
tLH
30
ns
time
Enable setup time
tS
15
ns
Input signal rise time
tR
50
ns
2
Input signal fall time
tF
50
ns
2
DISPOFF removal time
tSD
100
ns
DISPOFF "L" pulse width
tWDL
1.2
µs
Output delay time (1)
tD
CL = 15 pF
41
ns
Output delay time (2)
tPD1, t PD2
CL = 15 pF
1.2
µs
Output delay time (3)
t PD3
CL = 15 pF
1.2
µs
NOTES:
1. Takes the cascade connection into consideration.
2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation.
Preliminary Ver 0.24
Page 17/26
2009/10/01
ST8016S
(Segment Mode 3)
(LGND =VSS = 0 V, VDD = +3.0 to +4.5 V, V0 = + 15.0 to +30.0 V, TOPR = -25 10+85 °C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP. MAX. UNIT NOTE
Shift clock period
tWCK
tR,tF ≤ 10ns
82
ns
1
Shift clock "H" pulse width
tWCKH
28
ns
Shift clock "L” pulse width
tWCKL
28
ns
Data setup time
tDS
20
ns
Data hold time
tDH
23
ns
Latch pulse "H" pulse width
tWLPH
30
ns
Shift clock rise to latch pulse rise
tLD
0
ns
time
Shift clock fall to latch pulse fall
tSL
51
ns
time
Latch pulse rise to shift clock rise
tLS
30
ns
time
Latch pulse fall to shift clock fall
tLH
30
ns
time
Enable setup time
tS
15
ns
Input signal rise time
tR
50
ns
2
Input signal fall time
tF
50
ns
2
DISPOFF removal time
tSD
100
ns
DISPOFF "L" pulse width
tWDL
1.2
µs
Output delay time (1)
tD
CL = 15 pF
57
ns
Output delay time (2)
tPD1, t PD2
CL = 15 pF
1.2
µs
Output delay time (3)
t PD3
CL = 15 pF
1.2
µs
NOTES:
1. Takes the cascade connection into consideration.
2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation.
(Common Mode)
(LGND =VSS = 0 V, VDD = +2.5 to +5.5 V, V0 = +15.0 to +30.0 V, TOPR = -25 to +85° C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Shift clock period
tWLP
tR,tF ≤ 20ns
250
ns
VDD = +5.0± 0.5V
15
ns
Shift clock "H" pulse width
tWLPH
30
ns
VDD = +2.5+ 4.5V
Data setup time
tSU
30
ns
Data hold time
tH
50
ns
Input signal rise time
tR
50
ns
Input signal fall time
tF
50
ns
DISPOFF removal time
tSD
100
ns
DISPOFF "L" pulse width
tWDL
1.2
µs
Output delay time (1)
tDL
CL = 15 pF
200
ns
Output delay time (2)
tPD1, t PD2
CL = 15 pF
1.2
µs
Output delay time (3)
t PD3
CL = 15 pF
1.2
µs
Preliminary Ver 0.24
Page 18/26
2009/10/01
ST8016S
10.3
Timing Chart of Segment Mode
tWLPH
LP
tLD
tSL
tLH
tLS
tWCKH
tWCKL
XCK
tR
tF
tWCK
tDS
LAST DATA
DI7 - DI0
tWDL
tDH
TOP DATA
tSD
DISPOFF
LP
XCK
1
n*
2
tS
EI
tD
EO
*n = 40 in 4-bit parallel input mode
*n = 20 in 8-bit parallel input mode
FR
tPD1
LP
tPD2
DISPOFF
tPD3
Y1 - Y160
Fig. 8 Timing Characteristics (3)
Preliminary Ver 0.24
Page 19/26
2009/10/01
ST8016S
10.4
Timing Chart of Common Mode
tWLP
LP
tR
tWLPH
tSU
tF
tH
EIO2
tDL
EIO1
tWDL
tSD
DISPOFF
FR
tPD1
LP
tPD2
DISPOFF
tPD3
Y1 - Y160
Preliminary Ver 0.24
Page 20/26
2009/10/01
ST8016S
11.
11.1
APPLICATION CIRCUIT
Application Circuit for Module
VEE
5
4.7~50 Ω
EIO2
MD
S/C
L/R
DI0~DI7
EIO1
Power GND
Y1~Y160
FR
LP
/DISPOFF
XCK
160 X 160 DOT LCD PANEL
ST8016S
Y1~Y160
10
MD
EIO2
FR
L/R
S/C
EIO1
DI0~DI7
CONTROLLER
FLM
AC
LP
/DISPOFF
XCK
LP
5
VDD
/DISPOFF
XCK
VSS
ST8016S
8
XD0~XD7
11.2
LCD Panel Layout Example
Pin Name
ITO Resistor Values Suggestion
Less than 75Ω when VDD ≧ 3.0V, and the smaller the better
LGND, GND, VDD, Vss
V0R, V0L
Less than 150Ω, and the smaller the better
V12R, V12L, V34R, V12L Less than 250Ω, and the smaller the better
PS : Above resistor value test on 3” LCD panel.
Preliminary Ver 0.24
Page 21/26
2009/10/01
ST8016S
12.
Note:
PAD DIAGRAM
Subtrate should be connected to GND.
Unit: um
PIN#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Name
VSS
GND
GND
LGND
L/R
VDD
VDD
S/C
EIO2
DUMMY
DI0
DI1
DI2
DI3
DI4
DI5
DUMMY
DUMMY
DUMMY
DUMMY
DI6
DI7
XCK
/DISPOFF
DUMMY
LP
EIO1
FR
MD
LGND
GND
GND
VSS
Preliminary Ver 0.24
X
-2857.500
-2733.000
-2622.850
-2521.550
-2410.100
-2310.675
-2220.450
-2103.600
-1935.850
-1682.850
-1337.575
-1218.950
-1100.250
-981.550
-862.850
-744.150
-450.500
-134.775
204.125
538.725
1053.350
1172.050
1291.050
1409.750
1608.650
1953.925
2121.600
2293.000
2411.700
2521.550
2622.850
2733.000
2857.500
Y
PIN#
-355.000 34
-383.100 35
-383.150 36
-383.150 37
-383.100 38
-383.350 39
-370.650 40
-383.100 41
-383.100 42
-383.100 43
-383.100 44
-383.100 45
-383.100 46
-383.100 47
-383.100 48
-383.100 49
-344.400 50
-347.675 51
-337.725 52
-337.725 53
-383.100 54
-383.100 55
-383.100 56
-383.100 57
-383.100 58
-383.100 59
-383.100 60
-383.100 61
-383.100 62
-383.150 63
-383.150 64
-383.100 65
-355.000 66
Page 22/26
Name
VSS
V34R
V12R
V0R
V0R
V0R
DUMMY
DUMMY
DUMMY
DUMMY
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
X
2845.000
2845.000
2845.000
2845.000
2845.000
2857.500
2788.700
2755.700
2722.700
2689.700
2656.700
2623.700
2590.700
2557.700
2524.700
2491.700
2458.700
2425.700
2392.700
2359.700
2326.700
2293.700
2260.700
2227.700
2194.700
2161.700
2128.700
2095.700
2062.700
2029.700
1996.700
1963.700
1930.700
Y
16.500
82.500
148.500
214.500
264.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
2009/10/01
ST8016S
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
Y24
Y25
Y26
Y27
Y28
Y29
Y30
Y31
Y32
Y33
Y34
Y35
Y36
Y37
Y38
Y39
Y40
Y41
Y42
Y43
Y44
Y45
Y46
Y47
Y48
Y49
Y50
Y51
Y52
Y53
Y54
Y55
Y56
Y57
Y58
Y59
Y60
Y61
Y62
Y63
Y64
Y65
Y66
Y67
Y68
Y69
Y70
Preliminary Ver 0.24
1897.700
1864.700
1831.700
1798.700
1765.700
1732.700
1699.700
1666.700
1633.700
1600.700
1567.700
1534.700
1501.700
1468.700
1435.700
1402.700
1369.700
1336.700
1303.700
1270.700
1237.700
1204.700
1171.700
1138.700
1105.700
1072.700
1039.700
1006.700
973.700
940.700
907.700
874.700
841.700
808.700
775.700
742.700
709.700
676.700
643.700
610.700
577.700
544.700
511.700
478.700
445.700
412.700
379.700
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
Page 23/26
Y71
Y72
Y73
Y74
Y75
Y76
Y77
Y78
Y79
Y80
DUMMY
DUMMY
Y81
Y82
Y83
Y84
Y85
Y86
Y87
Y88
Y89
Y90
Y91
Y92
Y93
Y94
Y95
Y96
Y97
Y98
Y99
Y100
Y101
Y102
Y103
Y104
Y105
Y106
Y107
Y108
Y109
Y110
Y111
Y112
Y113
Y114
Y115
346.700
313.700
280.700
247.700
214.700
181.700
148.700
115.700
82.700
49.700
16.700
-16.700
-49.700
-82.700
-115.700
-148.700
-181.700
-214.700
-247.700
-280.700
-313.700
-346.700
-379.700
-412.700
-445.700
-478.700
-511.700
-544.700
-577.700
-610.700
-643.700
-676.700
-709.700
-742.700
-775.700
-808.700
-841.700
-874.700
-907.700
-940.700
-973.700
-1006.700
-1039.700
-1072.700
-1105.700
-1138.700
-1171.700
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
2009/10/01
ST8016S
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
12.1
Y116
Y117
Y118
Y119
Y120
Y121
Y122
Y123
Y124
Y125
Y126
Y127
Y128
Y129
Y130
Y131
Y132
Y133
Y134
Y135
Y136
Y137
Y138
Y139
Y140
Y141
Y142
Y143
-1204.700
-1237.700
-1270.700
-1303.700
-1336.700
-1369.700
-1402.700
-1435.700
-1468.700
-1501.700
-1534.700
-1567.700
-1600.700
-1633.700
-1666.700
-1699.700
-1732.700
-1765.700
-1798.700
-1831.700
-1864.700
-1897.700
-1930.700
-1963.700
-1996.700
-2029.700
-2062.700
-2095.700
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
Y144
Y145
Y146
Y147
Y148
Y149
Y150
Y151
Y152
Y153
Y154
Y155
Y156
Y157
Y158
Y159
Y160
DUMMY
DUMMY
DUMMY
DUMMY
V0L
V0L
V0L
V12L
V34L
VSS
-2128.700
-2161.700
-2194.700
-2227.700
-2260.700
-2293.700
-2326.700
-2359.700
-2392.700
-2425.700
-2458.700
-2491.700
-2524.700
-2557.700
-2590.700
-2623.700
-2656.700
-2689.700
-2722.700
-2755.700
-2788.700
-2857.500
-2845.000
-2845.000
-2845.000
-2845.000
-2845.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
350.000
264.000
214.500
148.500
82.500
16.500
Gold Bump size (unit: um)
Pad No.
X
Y
Area (um2)
1,33
87.00
112.00
9744.0000
6
59.75
42.90
2563.2750
7
80.70
42.40
3421.6800
2,32
99.00
42.40
4197.6000
3,4,30,31
81.30
42.30
3438.9900
5,8,9,12~16,21~24,27~29
88.70
42.40
3760.8800
10,25
100.20
42.40
4248.4800
11,26
88.55
42.40
3754.5200
17
43.30
44.40
1922.5200
18
52.85
37.85
2000.3725
19,20
34.65
57.75
2001.0375
40~209
18.00
122.00
2196.0000
38,211
112.00
18.00
2016.0000
39,210
87.00
122.00
10614.0000
34~37,212~215
112.00
51.00
5712.0000
Wafer Thickness = 480.0±20um, Bump pad height (pad 1~215) = 15um, strength=30g
Preliminary Ver 0.24
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2009/10/01
ST8016S
13.
APPLICATION NOTE(REFERENCE ONLY)
13.1 Adjust V1 and V4 voltage to keep the V0-V1 = V4-VSS relation to get better display quality. The
(V0-V1)-(V4-VSS) value had better less than 100mV.
13.2 Add 0.1uF high frequency by-pass capacitor to filter the noise on V0~V4 to VSS.
13.3 When OP follower circuit is used, please be sure the OP power is higher than V0 at least 1.5V.
13.4 EIO1 and EIO2 is enable pin for driver, please pay attention to the distance to avoid noise when
cascade function is used. Two chip connecting distance is as shorter as better.
Preliminary Ver 0.24
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2009/10/01
ST8016S
14.
REVISION
REVISION
0.10
0.11
0.12
0.13
0.14
0.15
0.16
0.17
0.18
0.19
0.20
0.21
0.22
0.23
0.24
DESCRIPTION
First release
Delete TCP information
Add LGND definition, and re-define the pin function
Modify suggestion resistor value for V0 and bond pad height to
18um.
Add alignment mark data and LCD Panel Layout Example.
Modify LCD panel layout example S/C of COM to connect to
LGND, and add the ITO resistor value suggestion.
Modify the center of pad coordinate to the IC center.
Modify the Bump pad height and add wafer thickness.
Modify all Vss for logic setting pins to LGND
Modify Description of LGND
Change Sitronix Logo and Modify description of LGND for
COM mode
Modify arrangement
Modify Chip size and thickness with scribe line
Modify “ABSOLUTE MAXIMUM RATINGS” max value
Modify “Output resistance” test condition
Modify all the data about absolute max voltage and recommend max
voltage
Modify the ITO resistor value suggestion
Add application note
Modify LCD Panel Layout Example
PAGE
1-25
1-25
1-25
21-22
DATE
2005/8/4
2005/9/8
2005/11/22
2006/4/4
21
2006/5/23
22-24
24
21-24
1-25
1-25
2006/5/30
2006/6/7
2006/7/21
2006/7/21
2006/7/21
1-25
15,22,24
2006/8/3
2006/10/26
2,16-18
2007/5/25
21,26
2008/5/05
21
2009/10/01
The above information is the exclusive intellectual property of Sitronix Technology Corp. and shall not be disclosed, distributed or reproduced without
permission from Sitronix.
Preliminary Ver 0.24
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2009/10/01