KS0794 160 COM / 160 SEG DRIVER FOR STN LCD August.1999. Ver. 1.1 Prepared by: Gyeong-Nam, Kim [email protected] Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team. 160 COM / SEG DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.1 KS0794 KS0794 Specification Revision History Version 2 Content Date 0.0 l Original Apr.1999 1.0 l Including application note. Jul.1999 1.1 l p6, p16 revision. Aug.1999 KS0794 PRELIMINARY SPEC. VER. 1.1 160 COM / SEG DRIVER FOR STN LCD CONTENTS INTRODUCTION ..................................................................................................................................................4 FEATURES ..........................................................................................................................................................4 BLOCK DIAGRAM ...............................................................................................................................................5 PAD CONFIGURATION .......................................................................................................................................6 PAD CENTER COORDINATES............................................................................................................................7 PIN DESCRIPTION ..............................................................................................................................................9 FUNCTIONAL DESCRIPTION............................................................................................................................10 BLOCK FUNCTION.....................................................................................................................................10 PIN FUNCTION...........................................................................................................................................11 FUNCTIONAL OPERATIONS......................................................................................................................15 SPECIFICATIONS..............................................................................................................................................18 ABSOLUTE MAXIMUM RATINGS...............................................................................................................18 RECOMMENDED OPERATING CONDITIONS ...........................................................................................18 DC CHARACTERISTICS.............................................................................................................................19 AC CHARACTERISTICS .............................................................................................................................21 PRECAUTION ....................................................................................................................................................27 CONNECTION EXAMPLES OF PLURAL SEGMENT DRIVERS ........................................................................28 TIMING CHART OF 4-DEVICE CASECADE CONNECTION OF SEGMENT DRIVERS......................................29 CONNECTION EXAMPLES OF PLURAL COMMON DRIVERS .........................................................................30 3 160 COM / SEG DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.1 KS0794 INTRODUCTION The KS0794 is a 160-output segment / common driver LSI suitable for driving large scale dot matrix LC panels using as personal computers / work stations. Through the use of SST (Super Slim TCP) technology, it is ideal for substantially decreasing the size of the frame section of the LC module. The KS0794 is good both segment driver and common driver, and a low power consuming, high-precision LC panel display can be assembled. In case of segment mode, the data input is selected 4bit parallel input mode and 8bit parallel input mode by a mode (MD) pin. In case of common mode, data input/output pins are bi-directional, four data shift directions are pin-selectable. FEATURES BOTH SEGMENT MODE AND COMMON MODE - Supply voltage for LC driver: +15.0 to +32.0V - Number of LC driver outputs: 160 - Low output impedance - Low power consumption - Supply voltage for the logic system: +2.4V to +5.5V - CMOS silicon gate process (P-type silicon substrate) - Package: 190-pin TCP (Tape Carrier Package) & Au bump chip Segment Mode - Shift clock frequency: 14MHz (Max.) (Vdd = +5V ± 10%) 8MHz (Max.) (Vdd = +2.4V to +4.5V) - Adopts a data bus system - 4-bit / 8-bit parallel input modes are selectable with a mode (MD) pin - Automatic transfer function of an enable signal - Automatic counting function which, in the chip select, causes the internal clock to be stopped by automatically counting 160 of input data - Line latch circuit reset function when DISPOFFB active Common Mode - Shift clock frequency: 4.0MHz (Max.) (Vdd = +2.4V to +5.5V) - Built-in 160 bits bi-directional shift register (divisible into 80-bits ×2) - Available in a single mode (160 bits shift register) or in a dual mode (80 bits shift register ×2) - Shift register circuit reset function when DISPOFFB active 4 KS0794 PRELIMINARY SPEC. VER. 1.1 160 COM / SEG DRIVER FOR STN LCD BLOCK DIAGRAM FR DISPOFFB 182 179 V OR V 12R V 43R 190 189 188 V 5L Y1 Y2 1 2 164 LEVEL SHIFTER Y 159 Y 160 159 160 160 BITS 4-LEVEL DRIVER 160 EIO1 181 EIO2 169 LP 180 XCK 178 L/R 166 MD 183 S/C 168 187 V 5L 163 V 43L 162 V 12L 161 V OL 160 BITS LEVEL SHIFTER ACTIVE CONTROL 160 160 BITS LINE LATCH/SHIFTER REGISTER 16 CONTROL LOGIC 16 16 16 16 16 16 16 16 16 8BITS*2 DATA LATCH DATA LATCH CONTROL 8 SP CONVERSION & DATA CONTROL (4 to 8 or 8to 8) 170 171 172 173 174 175 176 177 167 165 186 D I0 D I1 D I2 D I3 DI4 DI5 DI6 DI7 V DD V SS V SS Figure 1. Block Diagram 5 160 COM / SEG DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.1 KS0794 PAD CONFIGURATION 160 1 ððððððððððððððððððððð - - - - - - - - - - ðððððððððððððððððððð ð ð ð ð ð ð ð ð 161 Y KS0794 X (TOP VIEW,Pad up) (0,0) Dummy 165 164 186 Dummy ðððððððððððððð ðððððððððð 187 Figure 2. KS0794 Chip Configuration Table 1. KS0794 Pad Dimensions Item Pad No. Chip size - Pad pitch Bumped pad size Bumped pad height 6 190 Size X Y 11000 1100 1 to 160 65 (Min.) 161 to 190 260 (Min.) 1 to 160 43 108 161 to 164 187 to 190 76 58 165 to 186 58 76 1 to 190 14 (Typ.) Unit µm KS0794 PRELIMINARY SPEC. VER. 1.1 160 COM / SEG DRIVER FOR STN LCD PAD CENTER COORDINATES Table 2. Pad Location [Unit: µm] NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NAME Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 Y31 Y32 Y33 Y34 Y35 Y36 Y37 Y38 Y39 Y40 Y41 Y42 Y43 Y44 Y45 Y46 Y47 Y48 Y49 Y50 X 5167.5 5102.5 5037.5 4972.5 4907.5 4842.5 4777.5 4712.5 4647.5 4582.5 4517.5 4452.5 4387.5 4322.5 4257.5 4192.5 4127.5 4062.5 3997.5 3932.5 3867.5 3802.5 3737.5 3672.5 3607.5 3542.5 3477.5 3412.5 3347.5 3282.5 3217.5 3152.5 3087.5 3022.5 2957.5 2892.5 2827.5 2762.5 2697.5 2632.5 2567.5 2502.5 2437.5 2372.5 2307.5 2242.5 2177.5 2112.5 2047.5 1982.5 Y NO 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 NAME Y51 Y52 Y53 Y54 Y55 Y56 Y57 Y58 Y59 Y60 Y61 Y62 Y63 Y64 Y65 Y66 Y67 Y68 Y69 Y70 Y71 Y72 Y73 Y74 Y75 Y76 Y77 Y78 Y79 Y80 Y81 Y82 Y83 Y84 Y85 Y86 Y87 Y88 Y89 Y90 Y91 Y92 Y93 Y94 Y95 Y96 Y97 Y98 Y99 Y100 X 1917.5 1852.5 1787.5 1722.5 1657.5 1592.5 1527.5 1462.5 1397.5 1332.5 1267.5 1202.5 1137.5 1072.5 1007.5 942.5 877.5 812.5 747.5 682.5 617.5 552.5 487.5 422.5 357.5 292.5 227.5 162.5 97.5 32.5 -32.5 -97.5 -162.5 -227.5 -292.5 -357.5 -422.5 -487.5 -552.5 -617.5 -682.5 -747.5 -812.5 -877.5 -942.5 -1007.5 -1072.5 -1137.5 -1202.5 -1267.5 Y NO 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 NAME Y101 Y102 Y103 Y104 Y105 Y106 Y107 Y108 Y109 Y110 Y111 Y112 Y113 Y114 Y115 Y116 Y117 Y118 Y119 Y120 Y121 Y122 Y123 Y124 Y125 Y126 Y127 Y128 Y129 Y130 Y131 Y132 Y133 Y134 Y135 Y136 Y137 Y138 Y139 Y140 Y141 Y142 Y143 Y144 Y145 Y146 Y147 Y148 Y149 Y150 X -1332.5 -1397.5 -1462.5 -1527.5 -1592.5 -1657.5 -1722.5 -1787.5 -1852.5 -1917.5 -1982.5 -2047.5 -2112.5 -2177.5 -2242.5 -2307.5 -2372.5 -2437.5 -2502.5 -2567.5 -2632.5 -2697.5 -2762.5 -2827.5 -2892.5 -2957.5 -3022.5 -3087.5 -3152.5 -3217.5 -3282.5 -3347.5 -3412.5 -3477.5 -3542.5 -3607.5 -3672.5 -3737.5 -3802.5 -3867.5 -3932.5 -3997.5 -4062.5 -4127.5 -4192.5 -4257.5 -4322.5 -4387.5 -4452.5 -4517.5 Y 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 7 160 COM / SEG DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.1 KS0794 Table 2. Pad Location (Continued) [Unit: µm] NO NAME 151 152 153 154 155 156 157 158 159 160 161 162 163 164 Y151 Y152 Y153 Y154 Y155 Y156 Y157 Y158 Y159 Y160 VOL V12L V43L V5L DUMMY1 VSS LR VDD SC EIO2 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 XCK DISPOFFB LP EIO1 FR MD NC NC VSS DUMMY2 V5R V43R V12R V0R 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 8 X -4582.5 -4647.5 -4712.5 -4777.5 -4842.5 -4907.5 -4972.5 -5037.5 -5102.5 -5167.5 -5369 -5369 -5369 -5369 -4860 -4600 -4340 -4080 -3820 -3560 -3300 -3040 -2780 -2520 -2260 -2000 -1740 -1480 2290 2550 2810 3070 3330 3590 3850 4110 4370 4630 5369 5369 5369 5369 Y 395 395 395 395 395 395 395 395 395 395 330 90 -120 -330 -419 -419 -419 -419 -419 -419 -419 -419 -419 -419 -419 -419 -419 -419 -419 -419 -419 -419 -419 -419 -419 -419 -419 -419 -330 -120 90 330 KS0794 PRELIMINARY SPEC. VER. 1.1 160 COM / SEG DRIVER FOR STN LCD PIN DESCRIPTION Table 3. Pin Description Pin No. Symbol I/O Description 1 to 160 Y1 – Y160 O LC driver output 161, 190 V0L, V0R - Power supply for LC driver 162, 189 V12L, V12R - Power supply for LC driver 163, 188 V43L, V43R - Power supply for LC driver 164, 187 V5L, V5R - Power supply for LC driver 166 L/R I Display data shift direction selection 167 VDD - Power supply for logic system (+2.4 to +5.5V) 168 S/C I Segment mode/common mode selection 169 EIO2 I/O 170 to 176 DI0 – DI6 I Display data input for segment mode 177 DI7 I Display data input for segment mode / dual mode data input 178 XCK I Display data shift clock input for segment mode 179 DISPOFFB I Control input for deselect output level 180 LP I Latch pulse input / shift clock input for shift register 181 EIO1 I/O Input/output for chip select or data of shift register 182 FR I AC-converting signal input for LC driver waveform 183 MD I Mode selection input 165, 186 VSS - Ground (0V) Input / output for chip select or data of shift register 9 160 COM / SEG DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.1 KS0794 FUNCTIONAL DESCRIPTION BLOCK FUNCTION . Active Control In case of segment mode, controls the selection or deselection of the chip. Following a LP signal, and after the chip select signal is input, a select signal is generated internally until 160 bits of data have been read in. Once data input has been completed, a select signal for cascade connection is output, and the chip is deselected. In case of common mode, controls the input/output data of bidirectional pins. . SP Conversion & Data Control In case of segment mode, keep input data which are 2 clocks of XCK at 4-bit parallel mode into latch circuit, or keep input data which are 1 clock of XCK at 8-bits parallel mode into latch circuit, after that they are put on the internal data bus 8 bits at a time. . Data Latch Control In case of segment mode, selects the state of the data latch which reads in the data bus signals. The shift direction is controlled by the control logic, for every 16 bits of data read in, the selection signal shifts one bit based on the state of the control circuit. . Data Latch In case of segment mode, latches the data on the data bus. The latched state of each LC driver output pin is controlled by the control logic and the data latch control, 160 bits of data are read in 20 sets of 8 bits. . Line Latch / Shift Register In case of segment mode, all 160 bits which have been read into the data latch are simultaneously latched on the falling edge of the LP signal, and output to the level shifter block. In case of common mode, shifts data from the data input pin on the falling edge of the LP signal. . Level Shifter The logic voltage signal is level-shifted to the LC driver voltage level, and output to the driver block. . 4-level Driver Driver the LC driver output pins from the line latch/shift register data, selecting one of 4 levels (V0, V12, V43, V5) based on the S/C, FR and DISPOFFB signals. . Control Logic Controls the operation of each block. In case of segment mode, when a LP signal has been input, all blocks are reset and the control logic waits for the selection signal output from the active control block. Once the selection signal has been output, operation of the data latch and data transmission are controlled, 160 bits of data are read in, and the chip is deselected. In case of common mode, controls the direction of data shift. 10 KS0794 PRELIMINARY SPEC. VER. 1.1 160 COM / SEG DRIVER FOR STN LCD PIN FUNCTION Segment Mode Symbol VDD VSS V0R, V0L V12R , V12L V43R , V43L DI0 – DI7 XCK LP L/R Function Logic system power supply pin connects to +2.4 to +5.5V Ground pin connects to 0 V Power supply pin for LC driver voltage bias. . Normally, the bias voltage used is set by a resistor divider. . Ensure that voltage are set such that VSS<V43<V12<V0. . To further reduce the difference between the output waveforms of LC driver output pins Y1 and Y160, externally connect ViR and ViL (I = 0, 12, 43) Input pin for display data . In 4-bit parallel input mode, input data into the 4 pins DI0 - DI3. Connect DI4 - DI7 to VSS or VDD. . In 8-bit parallel input mode, input data into the 8 pins DI0 - DI7. Clock input pin for taking display data . Data is read on the falling edge of the clock pulse. Latch pulse input pin for display data . Data is latched on the falling edge of the clock pulse. Direction selection pin for reading display data . When set to VSS level “L”, data is read sequentially from Y160 to Y1. . When set to VDD level H”, data is read sequentially from Y1 to Y160. Control input pin for output deselect level . The input signal is level-shifted from logic voltage level to LC drive voltage level, and controls LC drive circuit. . When set to VSS level “L”, the LC drive output pins (Y1 - Y160) are set to level VSS. DISPOFFB . While set to “L”, the contents of the line latch are reset, but read the display data in the data latch regardless of condition of DISPOFFB. When the DISPOFFB function is canceled, the driver outputs deselect level (V12 or V43), then outputs the contents of the data latch on the next falling edge of the LP. That time, if DISPOFFB removal time can not keep regulation what is shown AC characteristics (page 21), can not output the reading data correctly. 11 160 COM / SEG DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.1 KS0794 Segment Mode (Continued) FR AC signal input for LC driving waveform . The input signal is level-shifted from logic voltage level to LC drive voltage level, and controls LC drive circuit. . Normally, inputs a frame inversion signal. . The LC driver output pin’s output voltage level can be set using the line latch output signal and the FR signal. Table of truth values is shown in table 4. MD Mode selection pin . When set to VSS level “L”, 4-bit parallel input mode is set. . When set to VDD level “H”, 8-bit parallel input mode is set. . The relationship between the display data and driver output pins is shown in table 5. S/C EIO1 EIO2 Y1 – Y160 12 Segment mode / common mode selection pin . When set to VDD level ‘H”, segment mode is set. Input / output pin for chip selection . When L/R input is at VSS level ‘L”, EIO1 is set for output, and EIO2 is set for input. . When L/R input is at VDD level ‘H”, EIO1 is set for input, and EIO2 is set for output. . During output. set to “H” while LP*XCLKB is ‘H” and after 160-bits of data have been read, set to “L” for one cycle (from falling edge to falling edge of XCK), after which it returns to “H”. . During input, after the LP signal is input, the chip is selected while EI is set to “L”. After 160-bits of data have been read, the chip is deselected. LC driver output pins . Corresponding directly to each bit of the data latch, one level (V0, V12, V43, or VSS) is selected and output. Table of truth values are shown in table 4. KS0794 PRELIMINARY SPEC. VER. 1.1 160 COM / SEG DRIVER FOR STN LCD Common Mode Symbol VDD VSS V0R, V0L V12R , V12L V43R , V43L EIO1 EIO2 LP L/R Function Logic system power supply pin connects to +2.4 to +5.5V Ground pin connects to 0 V Power supply pin for LC driver voltage bias. . Normally, the bias voltage used is set by a resistor divider. . Ensure that voltage are set such that VSS<V43<V12<V0. . To further reduce the difference between the output waveforms of LC driver output pins Y1 and Y160, externally connect ViR and ViL (I = 0, 12, 43) Bidirectional shift register shift data input/output pin . Output pin when L/R is at VSS level “L”, input pin when L/R is at VDD level “H”. . When EIO1 is used as input pin, it will be pull-down. . When EIO1 is used as output pin, it won’t be pull-down. Bidirectional shift register shift data input / output pin . Input pin when L/R is at VSS level “L”, output pin when L/R is at VDD level “H”. . When EIO2 is used as input pin, it will be pull-down. . When EIO2 is used as output pin, it won’t be pull-down. Bidirectional shift register shift clock pulse input pin . Data is shifted on the falling edge of the clock pulse. Bidirectional shift register shift direction selection pin . Data is shifted from Y160 to Y1 when set to VSS to level “L”, and data is shifted from Y1 to Y160 when set to VDD level “H”. 13 160 COM / SEG DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.1 KS0794 Common Mode (Continued) Control input pin for output deselect level . The input signal is level-shifted from logic voltage level to LC drive voltage level, and controls LC drive circuit. . When set to VSS level “L”, the LC drive output pins (Y1 - Y160) are set to level VSS. DISPOFFB . While set to “L”, the contents of the shift resister are reset not reading data. When the DISPOFFB function is canceled, the driver outputs deselect Level (V12 or V43), and the shift data is reading on the falling edge of the LP. That time, if DISPOFFB removal time can not keep regulation what is shown AC characteristics (page 25), the shift data is not reading correctly. AC signal input for LC driving waveform . The input signal is level-shifted from logic voltage level to LC drive voltage level, and controls LC drive circuit. FR . Normally, input a frame inversion signal. . The LC driver output pin’s output voltage level can be set using the shift register output signal and the FR signal. Table of truth values are shown in table 4. Mode selection pin MD . When set to VSS level “L”, Single mode operation is selected, when set to VDD level “H”, Dual mode operation is selected. Dual Mode data input pin . According to the data shift direction of the data shift register, data can be input starting from the 81st bit. DI7 When the chip is used as Dual mode, DI7 will be pull-down. When the chip is used as Single mode, DI7 won’t be pull-down. Segment mode / Common mode selection pin S/C . When set to VSS level ‘L”, common mode is set. Not used DI0 – DI6 . Connect DI0 - DI6 to VSS or VDD. Avoiding floating. Not used XCK . XCK is pull-down in common mode, so connect to VSS or open. LC driver output pins Y1 – Y160 . Corresponding directly to each bit of the shift register, one level (V0, V12, V43, or VSS) is selected and output. Table of truth values are shown in table 4. 14 KS0794 PRELIMINARY SPEC. VER. 1.1 160 COM / SEG DRIVER FOR STN LCD FUNCTIONAL OPERATIONS Segment Mode Table 4-1. Truth Table FR Latch data DISPOFFB Driver output voltage level (Y1 – Y160) L L H H x L H L H X H H H H L V43 V5 V12 V0 V5 Here, VSS≤V5<V43<V12<V0, H: VDD (+2.4V to +5.5V), L: VSS (0V), x: Don’t care Common Mode Table 4-2. Truth Table FR Latch data DISPOFFB Driver output voltage level (Y1 – Y160) L L H H x L H L H x H H H H L V43 V0 V12 V5 V5 Here, VSS≤V5<V43<V12<V0, H: VDD (+2.4V to +5.5V), L: VSS (0V), x: Don’t care Note: There are two kinds of power supply (logic level voltage, LC drive voltage) for LCD driver, please supply regular voltage which assigned by specification for each power pin. That time ‘Don’t care” should be fixed to ‘H” or “L “, avoiding floating. 15 160 COM / SEG DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.1 KS0794 RELATIONSHIP BETWEEN THE DISPLAY DATA AND DRIVER OUTPUT PINS Segment Mode 4-bit Parallel Mode Table 5-1. 4-bit Parallel Mode MD L L L/R L H EIO1 Output Input EIO2 Input Output Figure of clock Data Input 1st 2nd 3rd .. 38th 39th 40th DI0 Y157 Y153 Y149 .. Y9 Y5 Y1 DI1 Y158 Y154 Y150 .. Y10 Y6 Y2 DI2 Y159 Y155 Y151 .. Y11 Y7 Y3 DI3 Y160 Y156 Y152 .. Y12 Y8 Y4 DI0 Y4 Y8 Y12 .. Y152 Y156 Y160 DI1 Y3 Y7 Y11 .. Y151 Y155 Y159 DI2 Y2 Y6 Y10 .. Y150 Y154 Y158 DI3 Y1 Y5 Y9 .. Y149 Y153 Y157 8-bit Parallel Mode Table 5-2. 5-bit Parallel Mode MD H H 16 L/R L H EIO1 Output Input EIO2 Input Output Data Figure of clock Input 1st 2nd 3rd .. 18th 19th 20th DI0 Y153 Y145 Y137 .. Y17 Y9 Y1 DI1 Y154 Y146 Y138 .. Y18 Y10 Y2 DI2 Y155 Y147 Y139 .. Y19 Y11 Y3 DI3 Y156 Y148 Y140 .. Y20 Y12 Y4 DI4 Y157 Y149 Y141 .. Y21 Y13 Y5 DI5 Y158 Y150 Y142 .. Y22 Y14 Y6 DI6 Y159 Y151 Y143 .. Y23 Y15 Y7 DI7 Y160 Y152 Y144 .. Y24 Y16 Y8 DI0 Y8 Y16 Y24 .. Y144 Y152 Y160 DI1 Y7 Y15 Y23 .. Y143 Y151 Y159 DI2 Y6 Y14 Y22 .. Y142 Y150 Y158 DI3 Y5 Y13 Y21 .. Y141 Y149 Y157 DI4 Y4 Y12 Y20 .. Y140 Y148 Y156 DI5 Y3 Y11 Y19 .. Y139 Y147 Y155 DI6 Y2 Y10 Y18 .. Y138 Y146 Y154 DI7 Y1 Y9 Y17 .. Y137 Y145 Y153 KS0794 PRELIMINARY SPEC. VER. 1.1 160 COM / SEG DRIVER FOR STN LCD Common Mode Table 5-3. Common Mode MD L/R Data transfer direction EIO1 EIO2 DI7 L L(shift to left) Y160 → Y1 Output Input X (Single) H(shift to right) Y1 → Y160 Input Output X Output Input Input Input Output Input L(shift to left) H (Dual) H(shift to right) Y160 → Y81 Y80 → Y1 Y1 → Y80 Y81 → Y160 Here, L: VSS(0V), H: VDD(+2.4V to +5.5V), X: Don’t care NOTE: “Don’t care” should be fixed to “H” or “L”, avoid floating. 17 160 COM / SEG DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.1 KS0794 SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Table 6. Absolute Maximum Ratings Parameter Symbol Supply voltage (1) VDD V0 Supply voltage (2) V12 V43 V5 Input voltage VI Storage temperature TSTG Conditions Applicable pins Ratings Unit VDD -0.3 to +6.5 V V0L, V0R -0.3 to +35 V V12L, V12R -0.3 to V0+0.3 V V43L, V43R -0.3 to V0+0.3 V V5L, V5R -0.3 to V0+0.3 V DI0 –DI7, XCK, LP, L/R, MD, S/C, EIO1, EIO2, DISPOFFB -0.3 to VDD+0.3 V - -45 to 125 °C Ta=25 °C Referenced to VSS(0V) - RECOMMENDED OPERATING CONDITIONS Table 7. Recommended Operating Conditions Parameter Supply voltage (1) Supply voltage (2) Symbol VDD V0 Conditions Referenced to VSS(0V) Applicable pins VDD V0L, V0R Min. +2.4 +15 Operating temperature TOPR - - -20 NOTE: Ensure that voltage are set such that VSS≤V5<V43<V12<V0 18 Typ. Max. +5.5 +32 Unit V V +85 °C KS0794 PRELIMINARY SPEC. VER. 1.1 160 COM / SEG DRIVER FOR STN LCD DC CHARACTERISTICS Segment Mode Parameter Symbol Table 8-1. DC Characteristics for Segment Mode (VSS = V5 = 0V, VDD = +2.4 to 5.5V, V0 = +15 to +32V, Ta = -20~85°C) Conditions Applicable pins Min. Typ. Max. Unit DI0 -DI7, XCK, LP, L/R, FR, MD, S/C,EIO1, EIO2, DISPOFFB VIH Input voltage Output voltage Input leakage current VIL VOH IOH=-0.4mA VOL IOL=+0.4mA ILIH VI=VDD ILIL VI=VSS V 0.2VDD VDD-0.4 V DI0 -DI7, XCK, LP, L/R, FR, MD, S/C,EIO1, EIO2, DISPOFFB V0=+30V V +0.4 V +10 uA -10 uA 1.0 1.5 1.5 2.0 Output resistance RON Stand-by current ISTB *1 VSS 50.0 uA IDD1 *2 VDD 2.0 mA IDD2 *3 VDD 8.0 mA I0 *4 V0 1.0 mA Consumed current(1) (Deselection) Consumed current(2) |∆VON| =0.5V EIO1, EIO2 0.8VDD Y1- Y160 V0=+20V kΩ (Selection) Consumed current NOTE : 1. VDD = +5V, V0 = +32V, VI = VSS 2. VDD = +5V, V0 = +32V, f XCK = 14MHz, No-load, EI = VDD The input data is turned over by data taking clock (4-bit parallel input mode) 3. VDD = +5V, V0 = +32V, f XCK = 14MHz, No-load, EI = VSS The input data is turned over by data taking clock (4-bit parallel input mode) 4. VDD = +5V, V0 = +32V, f XCK = 14MHz, f LP = 41.6kHz, f FR = 80Hz, No-load The input data is turned over by data taking clock (4-bit parallel input mode) 19 160 COM / SEG DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.1 KS0794 Common Mode Parameter Input voltage Output voltage Input leakage current Output resistance Symbol VIH VIL VOH VOL ILIH ILIL RON Table 8-2. DC Characteristics for Common Mode (VSS = V5 = 0V, VDD = +2.4 to 5.5V, V0 = +15 to +32V, Ta = -20~85°C) Conditions Applicable pins Min. Typ. Max. Unit 0.8VDD V DI0 -DI7, XCK, LP, L/R, FR, MD, S/C,EIO1, EIO2, 0.2VD V DISPOFFB D IOH = -0.4mA VDD-0.4 V EIO1, EIO2 IOL = +0.4mA +0.4 V DI 0 -DI7, XCK, LP, L/R, VI = VDD +10 uA FR, MD, S/C,EIO1, EIO2, VI = VSS -10 uA DISPOFFB |∆VON| = 0.5V V0 = +30V 1.0 1.5 1.5 2.0 Y1 - Y160 V0 = +20V kΩ Input pullIPD VI = VDD XCK, EIO1, EIO2, DI7 100.0 down current Stand-by ISTB *1 VSS 50.0 current Consumed IDD *2 VDD 80.0 current(1) Consumed I0 *2 V0 160.0 current(2) NOTE: 1. VDD = +5V, V0 = +32V, VI = VSS 2. VDD = +5V, V0 = +32V, f LP = 41.6kHz, fFR = 80Hz in case of 1/320 duty operation, No-load 20 uA uA uA uA KS0794 PRELIMINARY SPEC. VER. 1.1 160 COM / SEG DRIVER FOR STN LCD AC CHARACTERISTICS Segment Mode 1 Table 9-1. AC Characteristics for Segment Mode (VSS = V5 = 0V, VDD = +4.5 to +5.5V, V0 = +15 to +32V, Ta = -20~85°C) Symbol Conditions Min. Typ. Max. Unit Parameter Shift clock period *1 TR, TF≤10 ns 71 ns TWCKH 23 ns TWCKL 23 ns Data setup time TDS 10 ns Data hold time TDH 20 ns Latch pulse “H” pulse width TWLPH 23 ns Shift clock rise to latch pulse rise time TLD 0 ns 25 ns Shift clock “H” pulse width Shift clock “L” pulse width Shift clock fall to latch pulse fall time TWCK TSL Latch pulse rise to shift clock rise time TLS 25 ns Latch pulse fall to shift clock fall time TLH 25 ns Input signal rise time *2 TR 50 ns Input signal fall time *2 TF 50 ns Enable setup time TS 21 ns DISPOFFB removal time TSD 100 ns DISPOFFB “L” pulse width TWDL 1.2 us Output delay time (1) TD CL = 15pF 40 ns Output delay time (2) TPD1, TPD2 CL = 15pF 1.2 us 1.2 us Output delay time (3) TPD3 CL = 15pF NOTES: 1. Take the cascade connection into consideration. 2. (TWCK – TWCKH – TWCKL) / 2 is maximum in the case of high speed operation. 21 160 COM / SEG DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.1 KS0794 Segment Mode 2 Table 9-2. AC Characteristics for Segment Mode (VSS = V5 = 0V, VDD = +2.4V to +4.5V, V0 = +15 to +32V, Ta = -20~85°C) Symbol Conditions Min. Typ. Max. Unit Parameter Shift clock period *1 TR, TF≤10 ns 125 ns TWCKH 51 ns TWCKL 51 ns Data setup time TDS 30 ns Data hold time TDH 40 ns Latch pulse “H” pulse width TWLPH 51 ns Shift clock rise to latch pulse rise time TLD 0 ns 51 ns Shift clock “H” pulse width Shift clock “L” pulse width Shift clock fall to latch pulse fall time TWCK TSL Latch pulse rise to shift clock rise time TLS 51 ns Latch pulse fall to shift clock fall time TLH 51 ns Input signal rise time *2 TR 50 ns Input signal fall time *2 TF 50 ns Enable setup time TS 36 ns DISPOFFB removal time TSD 100 ns DISPOFFB “L” pulse width TWDL 1.2 us Output delay time (1) TD CL = 15pF 78 ns Output delay time (2) TPD1, TPD2 CL = 15pF 1.2 us 1.2 us Output delay time (3) TPD3 CL = 15pF NOTES: 1. Take the cascade connection into consideration. 2. (TWCK – TWCKH – TWCKL) / 2 is maximum in the case of high speed operation. 22 KS0794 PRELIMINARY SPEC. VER. 1.1 160 COM / SEG DRIVER FOR STN LCD TIMING CHARACTERISTICS OF SEGMENT MODE TWLPH LP TSL TLS TLD TLH TWCKH TWCKL XCK TR TF TDS TWCK DI0 - DI7 LAST DATA DISPOFFB TDH TOP DATA TWDL TSD Figure 3-1. Timing Characteristics of Segment Mode LP (*) XCK 1 2 n TS EI TD EO (*) n : 4 - bit parallel mode 40 8 - bit parallel mode 20 Figure 3-2. Timing Characteristics of Segment Mode 23 160 COM / SEG DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.1 FR TPD1 LP TPD2 DISPOFFB TPD3 Y1 ~Y160 [L/R="L"] Figure 3-3. Timing Characteristics of Segment Mode 24 KS0794 KS0794 PRELIMINARY SPEC. VER. 1.1 160 COM / SEG DRIVER FOR STN LCD Common Mode Table 10. AC Characteristics of Common Mode (VSS = V5 = 0V, VDD = +2.4V to +4.5V, V0 = +15 to +32V, Ta = -20~85°C) Symbol Condition Min. Typ. Max. Unit Parameter Shift clock period TWLP TR, TF≤20ns 250 ns Shift “H” pulse width TWLPH VDD=+5.0V±10% 15 ns VDD=+2.5V~+4.5V 30 ns Data setup time TSU 30 ns Data hold time TH 50 ns Input signal rise time TR 50 ns Input signal fall time TF 50 ns DISPOFFB removal time TSD 100 ns DISPOFFB ‘L” pulse width TWDL 1.2 us Output delay time (1) TDL CL=15pF 200 ns Output delay time (2) TPD1,TPD2 CL=15pF 1.2 us Output delay time (3) TPD3 CL=15pF 1.2 us Timing Characteristics of Common Mode TWLP LP TR TWLPH TSU TF TH EIO2 (DI7) TDL EIO1 DISPOFFB TWDL TSD Figure 4-1. Timing Characteristics of Common Mode 25 160 COM / SEG DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.1 FR TPD1 LP TPD2 DISPOFFB TPD3 Y1~ Y160 [L/R="L"] Figure 4-2. Timing Characteristics of Common Mode 26 KS0794 KS0794 PRELIMINARY SPEC. VER. 1.1 160 COM / SEG DRIVER FOR STN LCD PRECAUTION . Precaution when Connecting or Disconnecting the Power This LSI has a high-voltage LC driver, so it may be permanently damaged by a high current which may flow if a voltage is supplied to the LC driver power supply while the logic system power supply is floating. The detail is as follows. . When connecting the power supply, connect the LC drive power after connecting the logic system power. Furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the LC driver power. . We recommend you connecting the serial resistor (50~100Ω) or fuse to the LC drive power V0 of the system as a current limiter. And set up the suitable of the resistor in consideration of LC display grade. And when connecting the logic power supply, the logic condition of this LSI inside is insecurity. Therefore connect the LC driver power supply after resetting logic condition of this LSI inside on DISPOFFB function. After that, cancel the DISPOFFB function after the LC driver power supply has become stable. Furthermore, when disconnecting the power, set the LC drive output pins to level V5 on DISPOFFB function. After that, disconnect the logic system power after disconnecting the LC drive power. When connecting the power supply, show the following recommend sequence. VDD VDD VSS VDD DISPOFFB VSS V0 V0 VSS Figure 5. Connecting the Power Supply 27 160 COM / SEG DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.1 KS0794 CONNECTION EXAMPLES OF PLURAL SEGMENT DRIVERS (a) CASE OF L/R = "L" top data last data Y1 Y160 EIO 2 Y1 Y160 EIO 1 EIO 2 EIO 1 L/R X C K L P M D F R D D I -I O O 0 7 Y1 Y160 EIO 2 EIO 1 L/R X C K XCK LP MD FR DIO 0 - DIO 7 L P M D F R D D I -I O O 0 7 L/R X C K L P M D F R D D I -I O O 0 7 8 VSS (b) CASE OF L/R = "H" VDD 8 DIO 0 - DIO 7 FR MD LP XCK X C K L P M D F R D D I -I O O 0 X C K L P M D F R D D I -I O O 0 7 EIO 1 Y1 EIO 2 Y160 EIO 1 EIO 2 Y1 Y160 top data L P M D F R D D I -I O O 0 7 L/R EIO 1 Y1 EIO 2 Y160 last data Figure 6 28 7 L/R L/R VSS X C K KS0794 PRELIMINARY SPEC. VER. 1.1 160 COM / SEG DRIVER FOR STN LCD TIMING CHART OF 4-DEVICE CASECADE CONNECTION OF SEGMENT DRIVERS FR LP XCK TOP DATA DI0-DI 7 n 1 2 device A LAST DATA (*) n12 device B n12 n12 device C EI (device A) n12 device D Low EO (device A) EO (device B) EO (device C) (*) n:4-bit parallel mode 40 8-bit parallel mode 20 Figure 7 29 160 COM / SEG DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.1 KS0794 CONNECTION EXAMPLES OF PLURAL COMMON DRIVERS (a) SINGLE MODE(SHIFTING TOWARD LEFT) first last Y1 Y160 DI EIO 2 D I EIO 1 L P 7 M D D I S P O F F B F R Y1 Y160 EIO 2 EIO 1 L/R D I L P 7 M D D I S P O F F B F R Y1 Y160 EIO 2 EIO 1 L/R D I L P 7 M D D I S P O F F B F R L/R VSS (VDD) LP VSS FR DISPOFFB VSS (b) SINGLE MODE(SHIFTING TOWARD RIGHT) VDD DISPOFFB FR VSS LP VSS (VDD) D I 7 DI EIO 1 Y1 L P M D F R D I S P O F F B D I L P M D F R 7 L/R EIO 2 Y160 EIO 1 D I S P O F F B D I 7 L/R EIO 2 Y1 Y160 EIO 1 Y1 L P M D F R D I S P O F F B L/R EIO 2 Y160 last first Figure 8 30 KS0794 PRELIMINARY SPEC. VER. 1.1 160 COM / SEG DRIVER FOR STN LCD (c)DUAL MODE(SHIFTING TOWARD LEFT) first1 last1 first2 Y1 Y160 DI1 EIO 2 D I 7 EIO 1 L P M D F R D I S P O F F B Y160 Y81 last2 Y1 Y80 EIO 2 EIO 1 L/R D I 7 L P M D F R D I S P O F F B Y1 Y160 EIO 2 EIO 1 L/R D I 7 L P M D F R L/R D I S P O F F B VSS (VDD) LP VSS FR DISPOFFB VDD VSS DI2 (d)DUAL MODE(SHIFTING TOWARD RIGHT) DI2 VDD VDD DISPOFFB FR VSS LP VSS (VDD) D I 7 DI1 EIO 1 Y1 L P M D F R D I S P O F F B D I L P M D F R 7 L/R EIO 2 Y160 EIO 1 Y1 D I S P O F F B D I 7 L/R EIO 2 Y80 Y81 Y160 EIO 1 Y1 L P M D F R D I S P O F F B L/R EIO 2 Y160 last2 first1 last1 first2 Figure 9 31