ETC NT7704H-BDT

NT7704
240 Output LCD Segment/Common Driver
Features
! Available in a single mode (240-bits shift register) or in a
dual mode(120-bits shift register x 2)
1. Y1 → Y240
Single mode
2. Y240 → Y1
Single mode
3. Y1 → Y120, Y121 → Y240
Dual mode
4. Y240 → Y121, Y120 → Y1
Dual mode
The above 4 shift directions are pin-selectable
(Segment mode)
! Shift Clock frequency:
20 MHz (Max.) (VDD = 5 V ± 10%)
12 MHz (Max.) (VDD = 2.5V - 4.5V)
! Adopts a data bus system
! 4-bit/8-bit parallel input modes are selectable with a
mode (MD) pin
! Automatic transfer function with an enable signal
! Automatic counting function when in "chip select" mode,
which causes the internal clock to be stopped by
automatically counting 240 bits of input data
(Both for segment mode and common mode)
!
!
!
!
!
!
!
Supply voltage for LCD driver: 15.0 to 30.0 V
Number of LCD driver outputs: 240
Low output impedance
Low power consumption
Supply voltage for the logic system: +2.5 to +5.5 V
COMS process
Package: Gold bump die / 272 Pin TCP(Tape Carrier
Package)
! Not designed or rated as radiation hardened
(Common mode)
! Shift clock frequency :
4.0 MHz (Max.)
! Built-in 240-bits bidirectional shift register (divisible into
120-bits x 2)
General Description
The NT7704 is a 240-bit output segment/common driver LSI
suitable for driving large scale dot matrix LCD panels used
by PDA's, personal computers and work stations for
example. Through the use of COG technology, it is ideal for
substantially decreasing the size of the frame section of the
LCD module. The NT7704 is good as both a segment driver
and as a common driver, and a low power consuming, high-
precision LCD panel display can be assembled using the
NT7704. In the segment mode, the data input is selected as
4bit parallel input mode or as 8bit parallel input mode by a
mode (MD) pin. In the common mode, the data input/output
pins are bi-directional and the four data shift directions are
pin-selectable.
Pin Configuration
D
U
M
M
Y
Y
2
4
0
Y
2
3
9
Y
2
3
8
Y
2
3
7
Y
2
3
6
Y
1
2
3
272 271 270 269 268
Y
1
2
2
Y
1
2
1
Y
1
2
0
Y
1
1
9
Y
1
1
8
155 154 153 152 151 150
Y
5
Y
4
Y
3
Y
2
Y
1
D
U
M
M
Y
37 36 35 34 33
NT7704
2
3
4
D V V
U 0 0
M L L
M
Y
1
V
1
2
L
V V V V S E D D D D D D D D X D L E F L M N V N V V V V V D
4 5 S D / I 0 1 2 3 4 5 6 7 C I P I R / D C S C 5 4 1 0 0 U
R 3 2 R R M
R
S
O
3 L S D C O
K S
M
R R
1
2
L
P
Y
O
F
F
5
6
7
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1
V1.0
NT7704
Pad Configuration
432
225
x
x
x
x
433
224
448
x
NT7704
Dummy Pad
209
ALK_R
x
x
ALK_L
1
208
Block Diagram
V0R
V12R V43R
V5R
Y1
Y2
Y239 Y240
V5L
FR
240 Bits 4 Level Driver
Level
Shifter
V43L
V12L
DISPOFF
/240
V0L
240 Bits Level Shifter
EIO1
/240
Active
Control
240 Bits Line Latch/Shift Register
EIO2
/16
LP
/16
/16
/16
/16
8Bits2
Data
Latch
Control
Logic
XCK
Data Latch Control
L/R
/8
MD
SP Conversion & Data Control
(4 to 8 or 8 to 8)
S/C
D0
D1
D2
D3
D4
D5
D6
D7
2
VDD
VSS VSS
NT7704
Pad Description
Pad No.
Designation
I/O
Description
1 - 12
V0L
P
Power supply for LCD driver
13 - 20
V12L
P
Power supply for LCD driver
21 -28
V43L
P
Power supply for LCD driver
29 - 40
V5L
P
Power supply for LCD driver
41 - 66
VSS
P
Ground (0V), these pads must be connected to each other
67 - 92
VDD
P
Power supply for the logic system (+2.5 to +5.5V)
93 - 94
S/C
I
Segment mode/common mode selection
95 - 97
EIO2
I/O
98, 99, 100 116, 117, 118
D0 - D6
I
Display data input for segment mode
119 - 121
D7
I
Display data input for Segment mode/ Dual mode data input
122 - 124
XCK
I
Display data shift clock input for segment mode
125 - 127
DISPOFF
I
Control input for deselect output level
128 - 130
LP
I
Latch pulse input/shift clock input for the shift register
131 - 133
EIO1
I/O
Input/output for chip select or data of the shift register
134 - 136
FR
I
AC-converting signal input for LCD driver waveform
137 - 139
L/R
I
Display data shift direction selection
140 - 142
MD
I
Mode selection input
143 - 168
VSS
P
Ground (0V), these pads must be connected to each other
169 - 180
V5R
P
Power supply for LCD driver
181 - 188
V43R
P
Power supply for LCD driver
189 - 196
V12R
P
Power supply for LCD driver
197 - 208
V0R
P
Power supply for LCD driver
209 - 448
Y1 - Y240
O
LCD driver output
Input/output for chip select or data of the shift register
3
NT7704
Input / Output Circuits
VDD
I
Input Signal
Applicable Pins
L/R, S/C, D0 - D6,
DISPOFF , LP, FR, MD
VSS
Input Circuit (1)
VDD
I
Input Signal
Control Signal
VSS
VSS
Input Circuit (2)
4
Applicable Pins
D7, XCK
NT7704
VDD
Input Signal
Control Signal
VSS
VDD
VSS
Output Signal
I/O
Control Signal
Applicable Pins
EIO1, EIO2
VSS
Input / Output Circuit
V0
V12
Control Signal 1
Control Signal 2
Control Signal 3
Control Signal 4
O
Applicable Pins
Y1 to Y240
V43
VSS
LCD Driver Output circuit
5
V5
NT7704
Pad Description
Segment mode
Symbol
Function
VDD
Logic system power supply pin connects from +2.5 to +5.5V
VSS
Ground pin connects to 0V
VOR, VOL
V12R, V12L
V43R, V43L
V5R, V5L
D0 - D7
XCK
Power supply pin for LCD driver voltage bias
" Normally, the bias voltage used is set by a resistor divider
" Ensure that the voltages are set such that VSS ≤ V5 < V43 < V12 < V0
" To further reduce the differences between the output waveforms of the LCD driver output pins Y1 and Y240,
externally connect ViR and ViL (I = 0, 12, 43, 5)
Input pin for display data
" In 4-bit parallel input mode, input data into the 4 pins D0 - D3. Connect D4 - D7 to VSS or VDD
" In 8-bit parallel input mode, input data into the 8 pins D0 - D
Clock input pin for taking display data
" Data is read on the falling edge of the clock pulse
LP
Latch pulse input pin for display data
" Data is latched on the falling edge of the clock pulse
L/R
Direction selection pin for reading display data
" When set to VSS level "L", data is read sequentially from Y240 to Y1
" When set to VDD level "H", data is read sequentially from Y1 to Y240
Control input pin for output deselect level
" The input signal is level-shifted from the logic voltage level to the LCD driver voltage level, and controls the
LCD driver circuit.
" When set to VSS level “L”, the LCD driver output pins (Y1-Y240) are set to level V5
DISPOFF
" When DISPOFF is set to “L”, the contents of the line latch are reset, but the display data in the data
latch are read regardless of the condition of DISPOFF . When the DISPOFF function is canceled,
the driver outputs deselect level (V12 or V43), then outputs the contents of the date latch onto the next
falling edge of the LP. At that time, if the DISPOFF removal time can not keep regulation with what is
shown on the AC characteristics, then it can not output the reading data correctly.
FR
AC signal input for LCD driving waveform
" The input signal is level-shifted from the logic voltage level to the driver voltage level and controls
the LCD driver circuit.
" It normally inputs a frame inversion signal
The LCD driver output pin’s output voltage level can be set to the line latch output signal and the FR signal
MD
Mode selection pin
" When set to VSS level “L”, 8-bit parallel input mode is set
" When set to VDD level “H", 4-bit parallel input mode is set
6
NT7704
Segment mode continued
Symbol
S/C
EIO1, EIO2
Y1 - Y240
Function
Segment mode/common mode selection pin
" When set to VDD level "H", segment mode is set
" When set to VSS level "L", common mode is set
Input/output pin for chip selection
" When L/R input is at VSS level “L”, EIO1 is set for output, and EIO2 is set for input
" When L/R input is at VDD level “H”, EIO1 is set for input, and EIO2 is set for output
" During output, it is set to “H” while LP* XCK is “H” and then after 240-bits of data have been read,
it is set to “L” for one cycle (from falling edge to falling edge of XCK), after which it returns to “H”
" During input, after the LP signal is input, the chip is selected while EI is set to “L”. After 240-bits of
data have been read, the chip is deselected
LCD driver output pins
These correspond directly to each bit of the data latch, one level (V0, V12, V43, or V5) is selected and
output
Common mode
Symbol
Function
VDD
Logic system power supply pin connects to +2.5 to +5.5V
VSS
Ground pin connects to 0V
V0R, V0L
V12R, V12L
V43R, V43L
V5R, V5L
Power supply pin for LCD driver voltage bias.
" Normally, the bias voltage used is set by a resistor divider
" Ensure the voltages are set such that VSS ≤ V5 <V43 < V12 < V0
To further reduce the differences between the output waveforms of the LCD driver output pins Y1 and
Y240, externally connect ViR and ViL (I = 0, 12, 43, 5)
EIO1
Bi-directional shift register shift data input/output pin
" Is an output pin when L/R is at VSS level “L” and is an input pin when L/R is at VDD level “H”
" When EIO1 is used as an input pin, it will be pulled-down
" When EIO1 is used as an output pin, it won’t be pulled-down
EIO2
Bi-directional shift register shift data input/output pin
" Is an input pin when L/R is at VSS level “L” and is an output pin when L/R is at VDD level “H”
" When EIO2 is used as an input pin, it will be pulled-down
" When EIO2 is used as an output pin, it won’t be pulled-down
LP
Bi-directional shift register shift clock pulse input pin
" Data is shifted on the falling edge of the clock pulse
L/R
Bi-directional shift register shift direction selection pin
" Data is shifted from Y240 to Y1 when it is set to VSS level “L”, and data is shifted from Y1 to Y240 when it is
set to VDD level “H”
7
NT7704
Common mode continued
Symbol
Function
DISPOFF
Control input pin for output deselect level
" The input signal is level-shifted from the logic voltage level to the LCD driver voltage level, and controls
the LCD driver circuit
" When set to VSS level “L”, the LCD driver output pins (Y1-Y240) are set to level V5
" While set to “L”, the contents of the shift resister are reset and are not reading data. When the DISPOFF
function is canceled, the driver outputs deselect level (V12 or V43), and the shift data is read on the falling
edge of the LP. At that time, if the DISPOFF removal time can not keep regulation with what is shown on
the AC characteristics, the shift data is not read correctly
FR
AC signal input for LCD driving waveform
" The input signal is level-shifted from logic voltage level to the LCD driver voltage level, and it controls the
LCD driver circuit
" Normally, it inputs a frame inversion signal
The LCD driver output pin’s output voltage level can be set using the shift register output signal and the FR
signal
MD
Mode selection pin
" When set to VSS level “L”, Single Mode operation is selected. When set to VDD level “H”, Dual Mode
operation is selected
D7
Dual Mode data input pin
" According to the data shift direction of the data shift register, data can be input starting from the 121st bit
When the chip is used in Dual Mode, D7 will be pulled-down
When the chip is used in Single Mode, D7 won’t be pulled-down
S/C
Segment mode/common mode selection pin
" When set to VSS level “L”, common mode is set
D0 - D6
XCK
Y1 - Y240
Not used
" Connect D0-D6 to VSS or VDD. Avoid floating
Not used
" XCK is pull-down in common mode, so connect to VSS or leave open
LCD driver output pins
" These correspond directly to each bit of the shift register, one level (V0, V12, V43, or V5) is selected and
output
8
NT7704
Functional Description
1. Block description
1.1 Active Control
1.5. Line Latch/Shift Register
In segment mode, it controls the selection or deselection of
the chip. Following a LP signal input, and after the select
signal is input, a select signal is generated internally until 240
bits of data have been read in. Once data input has been
completed, a select signal for cascade connection is output,
and the chip is deselected.
In segment mode, it ensures all 240 bits which have been
read into the data latch, are simultaneously latched on to the
falling edge of the LP signal, and output to the level shift
block.
In common mode, it shifts data from the data input pin on to
the falling edge of the LP signal.
In common mode, it controls the input/output data of the bidirectional pins.
1.6. Level Shifter
1.2. SP Conversion & Data Control
It ensures the logic voltage signal is level-shifted to the LCD
driver voltage level, and output to the driver block.
In segment mode, it keeps input data which are 2 clocks of
XCK at 4-bit parallel mode into latch circuit, or keeps input
data which are 1 clock of XCK at 8-bit parallel mode into
latch circuit, after that they are put on the internal data bus 8
bits at a time.
1.7. 4-Level Driver
It drives the LCD driver output pins from the line latch/shift
register data, selecting one of 4 levels (V0, V12, V43, V5)
based on the S/C, FR and DISPOFF signals.
1.3. Data Latch Control
1.8. Control Logic
In segment mode, it selects the state of the data latch, which
reads in the data bus signals. The shift direction is controlled
by the control logic and for every 16 bits of data read in, the
selection signal shifts one bit, based on the state of the
control circuit.
Controls the operation of each block. In segment mode,
when an LP signal has been input, all blocks are reset and
the control logic waits for the selection signal output from the
active control block. Once the selection signal has been
output, operation of the data latch and data transmission are
controlled, 240 bits of data are read in, and the chip is
deselected.
1.4. Data Latch
In segment mode, it latches the data on the data bus. The
latched state of each LCD driver output pin is controlled by
the control logic and the data latch control. 240 bits of data
are read in 20 sets of 8 bits.
In common mode, it controls the direction of data shift.
9
NT7704
2. LCD Driver Output Voltage Level
The relationship between the data bus signal, AC converted signal FR and LCD driver output voltage is as shown in the table
below:
2.1. Segment Mode
FR
Latch Data
DISPOFF
Driver Output Voltage Level (Y1 - Y240)
L
L
H
V43
L
H
H
V5
H
L
H
V12
H
H
H
V0
X
X
L
V5
Here, VSS ≤ V5 < V43 < V12 < V0, H: VDD (+2.5 to +5.5V), L: VSS (0V), X: Don't care
2.2. Common Mode
FR
Latch Data
DISPOFF
Driver Output Voltage Level (Y1 - Y240)
L
L
H
V43
L
H
H
V0
H
L
H
V12
H
H
H
V5
X
X
L
V5
Here, VSS ≤ V5 < V43 < V12 < V0, H: VDD (+2.5 to +5.5V), L: VSS (0V), X: Don't care
Note: There are two kinds of power supply (logic level voltage, LCD driver voltage) for the LCD driver. Please supply regular
voltage which is assigned by specification for each power pin.
That time "Don't care" should be fixed to "H" or "L", avoiding floating.
10
NT7704
3. Relationship between the Display Data and Driver Output pins
3.1. Segment Mode:
(a) 4-bit Parallel Mode
MD
H
H
L/R
L
H
EIO1
Output
Input
EIO2
Input
Output
Data
Input
Number of Clock
60clock
59clock
58clcok
~
3clock
2clock
1clock
D0
Y1
Y5
Y9
~
Y229
Y233
Y237
D1
Y2
Y6
Y10
~
Y230
Y234
Y238
D2
Y3
Y7
Y11
~
Y231
Y235
Y239
D3
Y4
Y8
Y12
~
Y232
Y236
Y240
D0
Y240
Y236
Y232
~
Y12
Y8
Y4
D1
Y239
Y235
Y231
~
Y11
Y7
Y3
D2
Y238
Y234
Y230
~
Y10
Y6
Y2
D3
Y237
Y233
Y229
~
Y9
Y5
Y1
~
3clock
2clock
1clock
(b) 8-bit Parallel Mode
MD
L
L
L/R
L
H
EIO1
Output
Input
EIO2
Input
Output
Data
Input
Number of Clock
30clock
29clock
28clcok
D0
Y1
Y9
Y17
~
Y217
Y225
Y233
D1
Y2
Y10
Y18
~
Y218
Y226
Y234
D2
Y3
Y11
Y19
~
Y219
Y227
Y235
D3
Y4
Y12
Y20
~
Y220
Y228
Y236
D4
Y5
Y13
Y21
~
Y221
Y229
Y237
D5
Y6
Y14
Y22
~
Y222
Y230
Y238
D6
Y7
Y15
Y23
~
Y223
Y231
Y239
D7
Y8
Y16
Y24
~
Y224
Y232
Y240
D0
Y240
Y232
Y224
~
Y24
Y16
Y8
D1
Y239
Y231
Y223
~
Y23
Y15
Y7
D2
Y238
Y230
Y222
~
Y22
Y14
Y6
D3
Y237
Y229
Y221
~
Y21
Y13
Y5
D4
Y236
Y228
Y220
~
Y20
Y12
Y4
D5
Y235
Y227
Y219
~
Y19
Y11
Y3
D6
Y234
Y226
Y218
~
Y18
Y10
Y2
D7
Y233
Y225
Y217
~
Y17
Y9
Y1
11
NT7704
3.2. Common Mode
MD
L/R
Data Transfer Direction
EIO1
EIO2
D7
L
(Single)
L (shift to left)
Y240 to Y1
Output
Input
X
H (shift to right)
Y1 to Y240
Input
Output
X
L (shift to left)
Y240 to Y121
Y120 to Y1
Output
Input
Input
H (shift to right)
Y1 to Y120
Y121 to Y240
Input
Output
Input
H
(Dual)
Here, L: VSS (0V), H: VDD (+2.5V to +5.5V), X: Don't care
Note: "Don't care" should be fixed to "H" or "L", avoiding floating.
12
NT7704
4. Connection Examples of Segment Drivers
4.1. Case of L/R = “L”
last data
first data
(data taking flow)
Y240 ----------------------->Y1
Y240 ---------------------->Y1
Y240 ---------------------->Y1
EIO2
EIO2
EIO2
EIO1
EIO1
D0 - D7
FR
MD
L/R
LP
D0 - D7
FR
LP
MD
L/R
XCK
D0 - D7
FR
MD
LP
XCK
L/R
XCK
EIO1
XCK
LP
MD
FR
D0 - D7
/8
VSS
4.2. Case of L/R = “H”
VDD
/8
D0 - D7
FR
MD
LP
L/R
VSS
L/R
EIO1
EIO2
Y1 ---------------------->Y240
XCK
LP
MD
FR
D0 - D7
XCK
LP
MD
FR
D0 - D7
XCK
LP
MD
FR
D0 - D7
XCK
L/R
EIO1
EIO2
Y1 ---------------------->Y240
EIO1
EIO2
Y1 ---------------------->Y240
(data taking flow)
first data
last data
13
NT7704
5. Timing waveform of 4-Device cascade Connection of Segment Drivers
FR
LP
XCK
First data
D0~D7
n 1 2
Last data
n 1 2
device A
n 1 2
device B
n 1 2
device C
EI
(device A)
n 1 2
device D
H
L
EO
(device A)
EO
(device B)
EO
(device C)
n: 4-bit parallel mode 60
8-bit parallel mode 30
14
NT7704
6. Connection Examples for Common Drivers
Last
First
Y240
CS
DISPOFF
L/R
MD
EIO1
D7
EIO2
LP
FR
CS
DISPOFF
L/R
D7
MD
EIO1
Y1
FR
Y1
EIO2
FR
CS
DISPOFF
L/R
MD
EIO1
D7
EIO2
LP
D
Y240
Y1
LP
Y240
LP
VSS (VDD)
VSS
VSS
DISPOFF
CS
FR
Single Mode (Shifting towards the left)
FR
DISPOFF
VDD
VSS
VSS (VDD)
D
LP
D7
MD
L/R
DISPOFF
FR
LP
D7
MD
L/R
DISPOFF
FR
LP
D7
MD
L/R
DISPOFF
FR
LP
EIO1
EIO2
EIO1
EIO2
EIO1
EIO2
Y1
Y240
Y1
Y240
Y1
Y240
Last
First
Single Mode (Sifting towards the right)
15
NT7704
Last2
DISPOFF
D7
FR
L/R
MD
EIO1
MD
EIO2
L/R
EIO1
D7
Y1
DISPOFF
Y240
LP
Y1
FR
DISPOFF
L/R
MD
Y121 Y120
D7
LP
EIO2
FR
EIO1
DISPOFF
EIO2
L/R
Y240
MD
Y1
D7
Y240
LP
D1
Last1 First2
FR
First1
LP
D2
VSS (VDD)
VDD
VSS
DISPOFF
FR
Dual mode (Shifting towards the left)
FR
DISPOFF
VDD
VDD
VSS (VDD)
D2
D1
EIO1
EIO2
EIO1
Y1
Y240
Y1
First1
EIO2
Y120 Y121
Y240
Last1 First2
Dual mode (Shifting towards the right)
16
LP
LP
D7
MD
L/R
DISPOFF
FR
LP
D7
MD
L/R
DISPOFF
FR
LP
EIO1
EIO2
Y1
Y240
Last2
NT7704
7. Precaution
Be careful when connecting or disconnecting the power
This LSI has a high-voltage LCD driver, so it may be permanently damaged by a high current, which may occur if voltage is
supplied to the LCD driver power supply while the logic system power supply is floating.
The details are as follows:
! When connecting the power supply, connect the LCD driver power after connecting the logic system power. Furthermore,
when disconnecting the power, disconnect the logic system power after disconnecting the LCD driver power.
! We recommend that you connect a serial resistor (50-100 Ω) or fuse to the LCD driver power V0 of the system as a current
limiting device. Also, set a suitable value of the resistor in consideration of LCD display grade.
In addition, when connecting the logic power supply, the logic condition of the LSI inside is insecure. Therefore, connect the
LCD driver power supply only after resetting the logic condition of this LSI inside to the DISPOFF function. After that, the
DISPOFF cancel the function after the LCD driver power supply has become stable. Furthermore, when disconnecting the
power, set the LCD driver output pins to level V5 on the DISPOFF function. After that, disconnect the logic system power after
disconnecting the LCD driver power.
When connecting the power supply, follow the recommended sequence shown.
VDD
VDD
VSS
VDD
DISPOFF
VSS
V0
V0
VSS
17
NT7704
Absolute Maximum Rating*
*Comments
DC Supply Voltage VDD . . . . . . . . . . . . . -0.3V to +7.0V
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device under these or any other conditions above those
indicated in the operational sections of this specification is
not implied or intended. Exposure to the absolute maximum
rating conditions for extended periods may affect device
reliability.
DC Supply Voltage V0 . . . . . . . . . . . . . . -0.3V to +30V
Input Voltage . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V
Operating Ambient Temperature . . . . -30°C to +85°C
Storage Temperature . . . . . . . . . . . . .-45°C to +125°C
Electrical Characteristics
DC Characteristics
Segment Mode (VSS = V5 = 0V, VDD = 2.5 - 5.5V, V0 = 15 to 30 V, and TA = -30 to +85°C, unless otherwise noted)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Operating Voltage 1
VDD
2.5
-
5.5
V
Operating Voltage 2
V0
15
-
30
V
Input high voltage
VIH
0.8 VDD
-
-
V
Input low voltage
VIL
-
-
0.2 VDD
V
D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1,
EIO2, DISPOFF pins
Output high voltage
VOH
VDD - 0.4
-
-
V
EIO1, EIO2 pins, IOH = -0.4mA
Output low voltage
VOL
-
-
+0.4
V
EIO1, EIO2 pins, IOL = +0.4mA
Input leakage current 1
IIH
-
-
+1.0
µA
D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1,
EIO2, DISPOFF pins, VI = VDD
Input leakage current 2
IIL
-
-
-1.0
µA
D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1,
EIO2, DISPOFF pins, VI = VSS
-
1.5
2.0
Output resistance
RON
-
2.0
2.5
Condition
V0 = +30.0V
kΩ
V0 = +20.0V
Stand-by current
ISB
-
-
10
µA
VSS pin, Note 1
Consumed current (1)
(Deselection)
IDD1
-
-
2
mA
VDD pin, Note 2
Consumed current (2)
(Selection)
IDD2
-
-
12
mA
VDD pin, Note 3
I0
-
-
1.5
mA
V0 pin, Note 4
Consumed current
Note:
1. VDD = +5.0V, V0 = +30V, VI = VSS
2. VDD = +5.0V, V0 = +30V, fXCK = 20MHz, No-load, EI = VDD
The input data is turned over by the data taking clock (4-bit Parallel input mode)
3. VDD = +5.0V, V0 = +30V, fXCK = 20MHz, No-load. EI = VSS
The input data is turned over by the data taking clock (4-bit parallel input mode)
4. VDD = +5.0V, V0 = +30V, fXCK = 20MHz, fLP = 41.6kHz. fFR = 80 Hz, No-load
The input data is turned over by the data taking clock (4-bit parallel-input mode)
18
Y1 - Y240 pins,
∆V O N = 0.5V
NT7704
Common Mode (VSS = V5 = 0V, VDD = 2.5 - 5.5V, V0 = 15 to 30 V, and TA = -30 to +85°C, unless otherwise noted)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Operating Voltage
VDD
2.5
-
5.5
V
Operating Voltage
V0
15
-
30
V
Input high voltage
VIH
0.8 VDD
-
-
V
Input low voltage
VIL
-
-
0.2 VDD
V
D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1,
EIO2, DISPOFF pins
Output high voltage
VOH
VDD - 0.4
-
-
V
EIO1, EIO2 pins, IOH = -0.4mA
Output low voltage
VOL
-
-
+0.4
V
EIO1, EIO2 pins, IOL = +0.4mA
Input leakage current 1
IIH
-
-
+1.0
µA
D0 - 6, LP, L/R, FR, MD, S/C and
DISPOFF pins, VI = VDD
Input leakage current 2
IIL
-
-
-1.0
µA
D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1,
EIO2, DISPOFF pins, VI = VSS
Input pull down current
IPD
-
-
100
µA
XCK, EIO1, EIO2, D7 pins
-
1.5
2.0
Output resistance
RON
-
2.0
2.5
Condition
V0 = +30.0V
kΩ
V0 = +20.0V
Stand-by current
ISB
-
-
10
µA
VSS pin, Note 1
Consumed current (1)
IDD
-
-
120
µA
VDD pin, Note 2
Consumed current (2)
I0
-
-
240
µA
V0 pin, Note 2
Note:
1. VDD = +5.0V, V0 = +30.0V, VI = VSS
2. VDD = +5.0V, V0 = +30.0V, fLP = 41.6KHz, fFR = 80Hz, case of 1/480 duty operation, No-load
19
Y1 - Y240 pins,
∆V O N = 0.5V
NT7704
AC Characteristics
Segment Mode 1 (VSS = V5 = 0V, VDD = 4.5 - 5.5V, V0 = 15 to 30V, and TA = -30 to +85°C, unless otherwise noted)
Parameter
Symbol
Min.
Typ.
Shift clock period
tWCK
50
-
ns
Shift clock "H" pulse width
tWCKH
15
-
ns
Shift clock "L" pulse width
tWCKL
15
-
ns
Data setup time
tDS
10
-
ns
Data hole time
tDH
12
-
ns
tWLPH
15
-
ns
Shift clock rise to Latch pulse rise time
tLD
0
-
ns
Shift clock fall to Latch pulse fall time
tSL
30
-
ns
Latch pulse rise to Shift clock rise time
tLS
25
-
ns
Latch pulse fall to Shift clock rise time
tLH
25
-
ns
Latch pulse "H" pulse width
Max.
Unit
Condition
tr, tf 10ns, Note 1
Input signal rise time
tr
-
50
ns
Note 2
Input signal fall time
tf
-
50
ns
Note 2
Enable setup time
tS
10
-
ns
DISPOFF Removal time
tSD
100
-
ns
tWDL
1.2
-
µs
DISPOFF enable pulse width
Output delay time (1)
tD
-
30
ns
CL = 15pF
Output delay time (2)
tpd1, tpd2
-
1.2
µs
CL = 15pF
Output delay time (3)
tpd3
-
1.2
µs
CL = 15pF
Note:
1. Take the cascade connection into consideration.
2. (tCK-tWCKII-twckl)/2 is the maximum in the case of high speed operation.
20
NT7704
Segment Mode 2 (VSS = V5 = 0V, VDD = 3.0 - 4.5V, V0 = 15 to 30V, and TA = -30 to +85°C, unless otherwise noted)
Parameter
Symbol
Min.
Typ.
Shift clock period
tWCK
66
-
ns
Shift clock "H" pulse width
tWCKH
23
-
ns
Shift clock "L" pulse width
tWCKL
23
-
ns
Data setup time
tDS
15
-
ns
Data hole time
tDH
23
-
ns
tWLPH
30
-
ns
Shift clock rise to Latch pulse rise time
tLD
0
-
ns
Shift clock fall to Latch pulse fall time
tSL
50
-
ns
Latch pulse rise to Shift clock rise time
tLS
30
-
ns
Latch pulse fall to Shift clock fall time
tLH
30
-
ns
Latch pulse "H" pulse width
Max.
Unit
Condition
tr, tf 10ns, Note 1
Input signal rise time
tr
-
50
ns
Note 2
Input signal fall time
tf
-
50
ns
Note 2
Enable setup time
tS
15
-
ns
DISPOFF Removal time
tSD
100
-
ns
tWDL
1.2
-
µs
DISPOFF enable pulse width
Output delay time (1)
tD
-
41
ns
CL = 15pF
Output delay time (2)
tpd1, tpd2
-
1.2
µs
CL = 15pF
Output delay time (3)
tpd3
-
1.2
µs
CL = 15pF
Note:
1. Take the cascade connection into consideration.
2. (tCK-tWCKII-tWCKL)/2 is the maximum in the case of high speed operation.
21
NT7704
Segment Mode 3 (VSS = V5 = 0V, VDD = 2.5 - 3.0V, V0 = 15 to 30V, and TA = -30 to +85°C, unless otherwise noted)
Parameter
Symbol
Min.
Typ.
Shift clock period
tWCK
82
-
ns
Shift clock "H" pulse width
tWCKH
28
-
ns
Shift clock "L" pulse width
tWCKL
28
-
ns
Data setup time
tDS
20
-
ns
Data hole time
tDH
23
-
ns
tWLPH
30
-
ns
Shift clock rise to Latch pulse rise time
tLD
0
-
ns
Shift clock fall to Latch pulse fall time
tSL
65
-
ns
Latch pulse rise to Shift clock rise time
tLS
30
-
ns
Latch pulse fall to Shift clock fall time
tLH
30
-
ns
Latch pulse "H" pulse width
Max.
Unit
Condition
tr, tf 10ns, Note 1
Input signal rise time
tr
-
50
ns
Note 2
Input signal fall time
tf
-
50
ns
Note 2
Enable setup time
tS
15
-
ns
DISPOFF Removal time
tSD
100
-
ns
tWDL
1.2
-
µs
DISPOFF enable pulse width
Output delay time (1)
tD
-
57
ns
CL = 15pF
Output delay time (2)
tpd1, tpd2
-
1.2
µs
CL = 15pF
Output delay time (3)
tpd3
-
1.2
µs
CL = 15pF
Note:
1. Take the cascade connection into consideration.
2. (tCK-tWCKII-tWCKL)/2 is the maximum in the case of high speed operation.
22
NT7704
Timing waveform of the Segment Mode
tWLPH
LP
tLD
tSL
tLH
tLS
tWCKH
tWCKL
XCK
D0 - D7
tr
tr
tWCK
tDS
LAST DATA
tDH
TOP DATA
tWDL
tSD
DISPOFF
LP
1
2
n
XCK
tS
EI
tD
EO
n: 4-bit parallel mode 60
8-bit parallel mode 30
FR
tpd1
LP
tpd2
DISPOFF
tpd3
Y1 - Y240
23
NT7704
Common Mode (VSS = V5 = 0V, VDD = 2.5 - 5.5V, V0 = 15 to 30V and TA = -30 to +85°C, unless otherwise noted)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Condition
Shift clock period
tWLP
250
-
-
ns
tr, tf 20ns
15
-
-
ns
VDD = +5.0V 10%
Shift clock "H" pulse width
tWLPH
30
-
-
ns
VDD = +2.5 - +4.5V
Data setup time
tSU
30
-
-
ns
Data hole time
tH
50
-
-
ns
Input signal rise time
tr
-
50
ns
Input signal fall time
tf
-
50
ns
tSD
100
-
-
ns
tWDL
1.2
-
-
µs
Output delay time (1)
tDL
-
-
200
ns
CL = 15pF
Output delay time (2)
tpd1, tpd2
-
-
1.2
µs
CL = 15pF
Output delay time (3)
tpd3
-
-
1.2
µs
CL = 15pF
DISPOFF Removal time
DISPOFF enable pulse width
24
NT7704
Timing Characteristics of Common Mode
tWLP
LP
tr
tWLPH
tSU
tf
tH
EIO2
(DI7)
tDL
EIO1
tWDL
tSD
DISPOFF
FR
tpd1
LP
tpd2
DISPOFF
tpd3
Y1 - Y240
25
NT7704
Application Circuit (for reference only)
SEG960
SEG959
EIO1
Y1 - Y240
MD
FR
S/C
LP
L/R
DISPOFF
XCK
D0 - D7
EIO2
EIO1
Y1 - Y240
MD
FR
S/C
L/R
DISPOFF
960*480 DOT MATRIX
LCD PANEL
XCK
D0 - D7
NT7704*4
LP
EIO2
EIO1
Y1 - Y240
MD
FR
S/C
LP
L/R
DISPOFF
XCK
D0 - D7
EIO2
EIO1
Y1 - Y240
MD
SEG3
SEG2
FR
S/C
SEG1
C
O
M
3
L/R
DISPOFF
XCK
D0 - D7
EIO2
XCK
EIO2
LP
DISPOFF
D0 - D7
L/R
Y1 - Y240
FR
S/C
EIO1
XCK
EIO2
LP
DISPOFF
L/R
D0 - D7
FR
S/C
MD
EIO1
NT7704*2
LP
C
O
M
4
8
0
/8
MD
C
O
M
2
Y1 - Y240
C
O
M
1
C
O
M
4
7
9
/5
/5
V4
VSS
V0
R
R
(n-4)R
R
R
Note: V0-V1>1.5V
V5
VDD
VSS
26
LP
FR
YD
XCK
LCD controller
XD0 - XD7
V3
DISPOFF
V2
(case of 1/n bias)
/8
V1
V0
NT7704
Bonding Diagram
12968um
432
225
x
x
433
x
x
224
Y
448
x
NT7704
X
(0,0)
Dummy Pad
1168um
209
ALK_R
x
x
ALK_L
1
208
Pad Location
Pad No.
Designation
X
Y
Pad No.
Designation
X
Y
1
V0L
-6220
-521
31
V5L
-4410
-521
2
V0L
-6150
-521
32
V5L
-4350
-521
3
V0L
-6090
-521
33
V5L
-4290
-521
4
V0L
-6030
-521
34
V5L
-4230
-521
5
V0L
-5970
-521
35
V5L
-4170
-521
6
V0L
-5910
-521
36
V5L
-4110
-521
7
V0L
-5850
-521
37
V5L
-4050
-521
8
V0L
-5790
-521
38
V5L
-3990
-521
9
V0L
-5730
-521
39
V5L
-3930
-521
10
V0L
-5670
-521
40
V5L
-3870
-521
11
V0L
-5610
-521
41
VSS
-3810
-521
12
V0L
-5550
-521
42
VSS
-3750
-521
13
V12L
-5490
-521
43
VSS
-3690
-521
14
V12L
-5430
-521
44
VSS
-3630
-521
15
V12L
-5370
-521
45
VSS
-3570
-521
16
V12L
-5310
-521
46
VSS
-3510
-521
17
V12L
-5250
-521
47
VSS
-3450
-521
18
V12L
-5190
-521
48
VSS
-3390
-521
19
V12L
-5130
-521
49
VSS
-3330
-521
20
V12L
-5070
-521
50
VSS
-3270
-521
21
V43L
-5010
-521
51
VSS
-3210
-521
22
V43L
-4950
-521
52
VSS
-3150
-521
23
V43L
-4890
-521
53
VSS
-3090
-521
24
V43L
-4830
-521
54
VSS
-3030
-521
25
V43L
-4770
-521
55
VSS
-2970
-521
26
V43L
-4710
-521
56
VSS
-2910
-521
27
V43L
-4650
-521
57
VSS
-2850
-521
28
V43L
-4590
-521
58
VSS
-2790
-521
29
V5L
-4530
-521
59
VSS
-2730
-521
30
V5L
-4470
-521
60
VSS
-2670
-521
27
NT7704
Pad Location (continued)
Pad No.
Designation
X
Y
Pad No.
Designation
X
Y
61
VSS
-2610
-521
101
D1
-210
-521
62
VSS
-2550
-521
102
D1
-150
-521
63
VSS
-2490
-521
103
D1
-90
-521
64
VSS
-2430
-521
104
D2
-30
-521
65
VSS
-2370
-521
105
D2
30
-521
66
VSS
-2310
-521
106
D2
90
-521
67
VDD
-2250
-521
107
D3
150
-521
68
VDD
-2190
-521
108
D3
210
-521
69
VDD
-2130
-521
109
D3
270
-521
70
VDD
-2070
-521
110
D4
330
-521
71
VDD
-2010
-521
111
D4
390
-521
72
VDD
-1950
-521
112
D4
450
-521
73
VDD
-1890
-521
113
D5
510
-521
74
VDD
-1830
-521
114
D5
570
-521
75
VDD
-1770
-521
115
D5
630
-521
76
VDD
-1710
-521
116
D6
690
-521
77
VDD
-1650
-521
117
D6
750
-521
78
VDD
-1590
-521
118
D6
810
-521
79
VDD
-1530
-521
119
D7
870
-521
80
VDD
-1470
-521
120
D7
930
-521
81
VDD
-1410
-521
121
D7
990
-521
82
VDD
-1350
-521
122
XCK
1050
-521
83
VDD
-1290
-521
123
XCK
1110
-521
84
VDD
-1230
-521
124
XCK
1170
-521
85
VDD
-1170
-521
125
DISPOFF
1230
-521
86
VDD
-1110
-521
126
DISPOFF
1290
-521
87
VDD
-1050
-521
127
DISPOFF
1350
-521
88
VDD
-990
-521
128
LP
1410
-521
89
VDD
-930
-521
129
LP
1470
-521
90
VDD
-870
-521
130
LP
1530
-521
91
VDD
-810
-521
131
EIO1
1590
-521
92
VDD
-750
-521
132
EIO1
1650
-521
93
S/C
-690
-521
133
EIO1
1710
-521
94
S/C
-630
-521
134
FR
1770
-521
95
EIO2
-570
-521
135
FR
1830
-521
96
EIO2
-510
-521
136
FR
1890
-521
97
EIO2
-450
-521
137
L/R
1950
-521
98
D0
-390
-521
139
L/R
2010
-521
99
D0
-330
-521
139
L/R
2070
-521
100
D0
-270
-521
140
MD
2130
-521
28
NT7704
Pad Location (continued)
Pad No.
Designation
X
Y
Pad No.
Designation
X
Y
141
MD
2190
-521
181
V43R
4590
-521
142
MD
2250
-521
182
V43R
4650
-521
143
VSS
2310
-521
183
V43R
4710
-521
144
VSS
2370
-521
184
V43R
4770
-521
145
VSS
2430
-521
185
V43R
4830
-521
146
VSS
2490
-521
186
V43R
4890
-521
147
VSS
2550
-521
187
V43R
4950
-521
148
VSS
2610
-521
188
V43R
5010
-521
149
VSS
2670
-521
189
V12R
5070
-521
150
VSS
2730
-521
190
V12R
5130
-521
151
VSS
2790
-521
191
V12R
5190
-521
152
VSS
2850
-521
192
V12R
5250
-521
153
VSS
2910
-521
193
V12R
5310
-521
154
VSS
2970
-521
194
V12R
5370
-521
155
VSS
3030
-521
195
V12R
5430
-521
156
VSS
3090
-521
196
V12R
5490
-521
157
VSS
3150
-521
197
V0R
5550
-521
158
VSS
3210
-521
198
V0R
5610
-521
159
VSS
3270
-521
199
V0R
5670
-521
160
VSS
3330
-521
200
V0R
5730
-521
161
VSS
3390
-521
201
V0R
5790
-521
162
VSS
3450
-521
202
V0R
5850
-521
163
VSS
3510
-521
203
V0R
5910
-521
164
VSS
3570
-521
204
V0R
5970
-521
165
VSS
3630
-521
205
V0R
6030
-521
166
VSS
3690
-521
206
V0R
6090
-521
167
VSS
3750
-521
207
V0R
6150
-521
168
VSS
3810
-521
208
V0R
6220
-521
169
V5R
3870
-521
209
Y1
6430
-450
170
V5R
3930
-521
210
Y2
6430
-390
171
V5R
3990
-521
211
Y3
6430
-330
172
V5R
4050
-521
212
Y4
6430
-270
173
V5R
4110
-521
213
Y5
6430
-210
174
V5R
4170
-521
214
Y6
6430
-150
175
V5R
4230
-521
215
Y7
6430
-90
176
V5R
4290
-521
216
Y8
6430
-30
177
V5R
4350
-521
217
Y9
6430
30
178
V5R
4410
-521
218
Y10
6430
90
179
V5R
4470
-521
219
Y11
6430
150
180
V5R
4530
-521
220
Y12
6430
210
29
NT7704
Pad Location (continued)
Pad No.
Designation
X
Y
Pad No.
Designation
X
Y
221
Y13
6430
270
261
Y53
4050
529
222
Y14
6430
330
262
Y54
3990
529
223
Y15
6430
390
263
Y55
3930
529
224
Y16
6430
450
264
Y56
3870
529
225
Y17
6210
529
265
Y57
3810
529
226
Y18
6150
529
266
Y58
3750
529
227
Y19
6090
529
267
Y59
3690
529
228
Y20
6030
529
268
Y60
3630
529
229
Y21
5970
529
269
Y61
3570
529
230
Y22
5910
529
270
Y62
3510
529
231
Y23
5850
529
271
Y63
3450
529
232
Y24
5790
529
272
Y64
3390
529
233
Y25
5730
529
273
Y65
3330
529
234
Y26
5670
529
274
Y66
3270
529
235
Y27
5610
529
275
Y67
3210
529
236
Y28
5550
529
276
Y68
3150
529
237
Y29
5490
529
277
Y69
3090
529
238
Y30
5430
529
278
Y70
3030
529
239
Y31
5370
529
279
Y71
2970
529
240
Y32
5310
529
280
Y72
2910
529
241
Y33
5250
529
281
Y73
2850
529
242
Y34
5190
529
282
Y74
2790
529
243
Y35
5130
529
283
Y75
2730
529
244
Y36
5070
529
284
Y76
2670
529
245
Y37
5010
529
285
Y77
2610
529
246
Y38
4950
529
286
Y78
2550
529
247
Y39
4890
529
287
Y79
2490
529
248
Y40
4830
529
288
Y80
2430
529
249
Y41
4770
529
289
Y81
2370
529
250
Y42
4710
529
290
Y82
2310
529
251
Y43
4650
529
291
Y83
2250
529
252
Y44
4590
529
292
Y84
2190
529
253
Y45
4530
529
293
Y85
2130
529
254
Y46
4470
529
294
Y86
2070
529
255
Y47
4410
529
295
Y87
2010
529
256
Y48
4350
529
296
Y88
1950
529
257
Y49
4290
529
297
Y89
1890
529
258
Y50
4230
529
298
Y90
1830
529
259
Y51
4170
529
299
Y91
1770
529
260
Y52
4110
529
300
Y92
1710
529
30
NT7704
Pad Location (continued)
Pad No.
Designation
X
Y
Pad No.
Designation
X
Y
301
Y93
1650
529
341
Y133
-750
529
302
Y94
1590
529
342
Y134
-810
529
303
Y95
1530
529
343
Y135
-870
529
304
Y96
1470
529
344
Y136
-930
529
305
Y97
1410
529
345
Y137
-990
529
306
Y98
1350
529
346
Y138
-1050
529
307
Y99
1290
529
347
Y139
-1110
529
308
Y100
1230
529
348
Y140
-1170
529
309
Y101
1170
529
349
Y141
-1230
529
310
Y102
1110
529
350
Y142
-1290
529
311
Y103
1050
529
351
Y143
-1350
529
312
Y104
990
529
352
Y144
-1410
529
313
Y105
930
529
353
Y145
-1470
529
314
Y106
870
529
354
Y146
-1530
529
315
Y107
810
529
355
Y147
-1590
529
316
Y108
750
529
356
Y148
-1650
529
317
Y109
690
529
357
Y149
-1710
529
318
Y110
630
529
358
Y150
-1770
529
319
Y111
570
529
359
Y151
-1830
529
320
Y112
510
529
360
Y152
-1890
529
321
Y113
450
529
361
Y153
-1950
529
322
Y114
390
529
362
Y154
-2010
529
323
Y115
330
529
363
Y155
-2070
529
324
Y116
270
529
364
Y156
-2130
529
325
Y117
210
529
365
Y157
-2190
529
326
Y118
150
529
366
Y158
-2250
529
327
Y119
90
529
367
Y159
-2310
529
328
Y120
30
529
368
Y160
-2370
529
329
Y121
-30
529
369
Y161
-2430
529
330
Y122
-90
529
370
Y162
-2490
529
331
Y123
-150
529
371
Y163
-2550
529
332
Y124
-210
529
372
Y164
-2610
529
333
Y125
-270
529
373
Y165
-2670
529
334
Y126
-330
529
374
Y166
-2730
529
335
Y127
-390
529
375
Y167
-2790
529
336
Y128
-450
529
376
Y168
-2850
529
337
Y129
-510
529
377
Y169
-2910
529
338
Y130
-570
529
378
Y170
-2970
529
339
Y131
-630
529
379
Y171
-3030
529
340
Y132
-690
529
380
Y172
-3090
529
31
NT7704
Pad Location (continued)
Pad No.
Designation
X
Y
Pad No.
Designation
X
Y
381
Y173
-3150
529
416
Y208
-5250
529
382
Y174
-3210
529
417
Y209
-5310
529
383
Y175
-3270
529
418
Y210
-5370
529
384
Y176
-3330
529
419
Y211
-5430
529
385
Y177
-3390
529
420
Y212
-5490
529
386
Y178
-3450
529
421
Y213
-5550
529
387
Y179
-3510
529
422
Y214
-5610
529
388
Y180
-3570
529
423
Y215
-5670
529
389
Y181
-3630
529
424
Y216
-5730
529
390
Y182
-3690
529
425
Y217
-5790
529
391
Y183
-3750
529
426
Y218
-5850
529
392
Y184
-3810
529
427
Y219
-5910
529
393
Y185
-3870
529
428
Y220
-5970
529
394
Y186
-3930
529
429
Y221
-6030
529
395
Y187
-3990
529
430
Y222
-6090
529
396
Y188
-4050
529
431
Y223
-6150
529
397
Y189
-4110
529
432
Y224
-6210
529
398
Y190
-4170
529
433
Y225
-6430
450
399
Y191
-4230
529
434
Y226
-6430
390
400
Y192
-4290
529
435
Y227
-6430
330
401
Y193
-4350
529
436
Y228
-6430
270
402
Y194
-4410
529
437
Y229
-6430
210
403
Y195
-4470
529
438
Y230
-6430
150
404
Y196
-4530
529
439
Y231
-6430
90
405
Y197
-4590
529
440
Y232
-6430
30
406
Y198
-4650
529
441
Y233
-6430
-30
407
Y199
-4710
529
442
Y234
-6430
-90
408
Y200
-4770
529
443
Y235
-6430
-150
409
Y201
-4830
529
444
Y236
-6430
-210
410
Y202
-4890
529
445
Y237
-6430
-270
411
Y203
-4950
529
446
Y238
-6430
-330
412
Y204
-5010
529
447
Y239
-6430
-390
413
Y205
-5070
529
448
Y240
-6430
-450
414
Y206
-5130
529
ALK_L
-6318
-533
415
Y207
-5190
529
ALK_R
6318
-533
32
NT7704
Dummy Pad Location (Total: 6 pin)
NO.
X
Y
NO.
X
Y
1
6430
-520
4
-6280
529
2
6430
520
5
-6430
520
3
6280
529
6
-6430
-520
33
NT7704
Package Information
A1
D1
D1
A2
208m1n1
A1
D2
C1
A2
C2
C1
n1
D1
D1
m1
D2
D2
m2
n1
16n1m1
NT7704
r
n1
n1
m2
4n1m2
16n1m1
r
2m2n1
m3
n1
m3
m1
m1
m2
m1
D1
C1
m1
n2
m2
D1
n2
C3
H
C3
65m1n2 (L)
J
B
D2
76m3n2
D2
D1
H
65m1n2 (R)
D1
Chip Outline Dimensions
C1
J
B
unit: um
Symbol
Dimensions in um
Symbol
Dimensions in um
A1
204
H
51
A2
54
J
166
B
264
m1
39
C1
64
m2
55
C2
55
m3
38
C3
63
n1
72
D1
70
n2
90
D2
60
r
35
34
NT7704
TCP Pin Layout
DUMMY
Y1
33
Y2
34
Y3
35
Y4
36
Y5
37
Y118
150
Y119
151
Y120
152
Y121
153
Y122
154
Y123
155
NT7704
DUMMY
32
V0R
31
V0R
30
V12R
29
V43R
28
V5R
27
NC
26
VSS
25
NC
24
MD
23
L/R
22
FR
21
EIO1
20
LP
19
DISPOFF
18
XCK
17
D7
16
D6
15
D5
14
D4
13
D3
12
D2
11
D1
10
D0
9
EIO2
8
S/C
7
VDD
6
VSS
5
V5L
4
V43L
3
V12L
2
V0L
1
V0L
DUMMY
Y236
268
Y237
269
Y238
270
Y239
271
Y240
272
DUMMY
(COPPER SIDE VIEW)
35
NT7704
H -T
704
N T7
AB
F4
External View of TCP Pins
36
NT7704
Cautions concerning storage:
1. When storing the product, it is recommended that it be left in its shipping package.
After the seal of the packing bag has been broke, store the products in a nitrogen atmosphere.
2. Storage conditions :
Storage state
unopened (less than 90 days)
Storage conditions
Temperature: 5 to 30; humidity: 80%RH or less
After seal of broken (less than 30 days)
Room temperature, dry nitrogen atmosphere
3. Don't store in a location exposed to corrosive gas or excessive dust.
4. Don't store in a location exposed to direct sunlight of subject to sharp changes in temperature.
5. Don't store the product such that it is subjected to an excessive load weight, such as by stacking.
6. Deterioration of the plating may occur after long-term storage, so special care is required.
It is recommended that the products be inspected before use.
37
NT7704
Tray Information
f
H30-52359-25
425=100
X
c
W1
X
W2
T2
T1
SECTION Y-Y
Y
e
d
Y
g
h
W1
W2
a
b
e
g
f
h
T2
T1
SECTION X-X
Tray Outline Dimensions
unit: mm
Symbol
Dimensions in mm
Symbol
Dimensions in mm
a
1.30
g
0.64
b
2.67
h
4.20
c
13.30
W1
76.0
d
16.26
W2
68.0
e
1.60
T1
71.0
f
1.40
T2
68.3
38
NT7704
Ordering Information
Part No.
NT7704H-BDT
NT7704H-TABF4
Package
Au bump on chip tray
TCP Form
39
NT7704
Product Spec. Change Notice
NT7704 Specification Revision History
Version
Content
Date
1.0
TCP and tray information addition (Page 36-39)
Dec. 2001
0.2
Gold Bump Size revision (Page 34)
m1: 45 → 39, m2: 58 → 55
Sep. 2001
0.1
Pad Location Addition
Nov. 2000
0.0
Original
Nov. 2000
40