ST ST7735R 262K Color Single-Chip TFT Controller/Driver 1 Introduction The ST7735R is a single-chip controller/driver for 262K-color, graphic type TFT-LCD. It consists of 396 source line and 162 gate line driving circuits. This chip is capable of connecting directly to an external microprocessor, and accepts Serial Peripheral Interface (SPI), 8-bit/9-bit/16-bit/18-bit parallel interface. Display data can be stored in the on-chip display data RAM of 132 x 162 x 18 bits. It can perform display data RAM read/write operation with no external operation clock to minimize power consumption. In addition, because of the integrated power supply circuits necessary to drive liquid crystal, it is possible to make a display system with fewer components. 2 Features Single chip TFT-LCD Controller/Driver with RAM On-chip Display Data RAM (i.e. Frame Memory) 132 (H) x RGB x 162 (V) bits Built-in Circuits DC/DC converter Adjustable VCOM generation Non-volatile (NV) memory to store initial register setting Oscillator for display clock generation Factory default value (module ID, module version, etc) are stored in NV memory Timing controller LCD Driver Output Circuits: Source Outputs: 132 RGB channels Gate Outputs: 162 channels Common electrode output Built-in NV Memory for LCD Initial Register Setting 7-bits for ID2 8-bits for ID3 7-bits for VCOM adjustment Display Colors (Color Mode) Full Color: 262K, RGB=(666) max., Idle Mode OFF Color Reduce: 8-color, RGB=(111), Idle Mode ON Programmable Pixel Color Format (Color Depth) for Various Display Data input Format 12-bit/pixel: RGB=(444) using the 384k-bit frame memory and LUT 16-bit/pixel: RGB=(565) using the 384k-bit frame memory and LUT 18-bit/pixel: RGB=(666) using the 384k-bit frame memory and LUT Wide Supply Voltage Range I/O Voltage (VDDI to DGND): 1.65V~3.7V (VDDI ≤ VDD) Analog Voltage (VDD to AGND): 2.3V~4.8V On-Chip Power System Source Voltage (GVDD to AGND): 3.0V~4.5V VCOM level (VCOM to AGND): -0.4V to -2.0V Gate driver HIGH level (VGH to AGND): +10.0V to +15V Gate driver LOW level (VGL to AGND): -13V to -7.5V Various Interfaces Parallel 8080-series MCU Interface (8-bit, 9-bit, 16-bit & 18-bit) Parallel 6800-series MCU Interface (8-bit, 9-bit, 16-bit & 18-bit) 3-line serial interface 4-line serial interface Operating Temperature: -30°C to +85°C Display Features Support both normal-black & normal-white LC Software programmable color depth mode ST7735R Parallel Interface: 8080,6800(8-bit/9-bit/16-bit/18-bit) Serial Interface: 3-line, 4-line Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice. V0.2 1 2009-8-5 ST7735R 3 Pad arrangement 3.1 Output Bump Dimension Boundary (Include scribe Lane) C L K H J A V0.2 Item Symbol Size Bump pitch A 16 um Bump width C 16 um Bump height H 98 um Bump gap1 (Vertical) J 19 um Bump gap2 (Horizontal) K 16 um Bump area CxH 1568 um2 Chip Boundary (include scribe Lane) L 59 um 2 2009-08-05 ST7735R 3.2 Input Bump Dimension C2 C2 A1 A2 C1 H K K2 K1 K1 L Boundary (Include scribe Lane) V0.2 Item Symbol Size Bump pitch 1 A1 67 um Bump pitch 2 A2 50 um Bump width 1 C1 33 um Bump width 2 C2 38 um Bump height H 88 um Bump gap K 22 um Bump gap1 K1 17 um Bump gap2 K2 34 um Bump area 1 C1 X H 2904 um2 Bump area 2 C2 X H 3344 um2 Chip Boundary(include scribe Lane) L 59 um 3 2009-08-05 ST7735R 3.3 Alignment Mark Dimension 10 5 5 10 80 15 15 15 15 20 20 15 15 15 15 80 15 15 20 15 15 15 15 80 V0.2 20 15 15 80 4 2009-08-05 ST7735R 3.4 Chip Information Chip size (um x um): 10080 x 670 PAD coordinate: pad center Coordinate origin: chip center Chip thickness (um): 300(TYP) Bump height (um): 15(TYP) Bump hardness (HV): 75(TYP) V0.2 No.186 No.185 No.759 No.1 5 2009-08-05 ST7735R 4 Pad Center Coordinates No. PAD Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Dummy VDDIO EXTC DGNDO IM[0] VDDIO IM[1] DGNDO P68 VDDIO TEST1P DGNDO TEST2P VDDIO SRGB DGNDO SMX VDDIO SMY DGNDO Dummy VDDIO Dummy DGNDO Dummy VDDIO Dummy DGNDO Dummy VDDIO LCM DGNDO Dummy VDDIO Dummy DGNDO GM[1] VDDIO GM[0] DGNDO Dummy GS SPI4W VDDIO TESTOP[8] TESTOP[7] TESTOP[6] TESTOP[5] TESTOP[4] OSC V0.2 X Y No. PAD Name -4750 -4700 -4650 -4600 -4550 -4500 -4450 -4400 -4350 -4300 -4250 -4200 -4150 -4100 -4050 -4000 -3950 -3900 -3850 -3800 -3750 -3700 -3650 -3600 -3550 -3500 -3450 -3400 -3350 -3300 -3250 -3200 -3150 -3100 -3050 -3000 -2950 -2900 -2850 -2800 -2750 -2700 -2650 -2600 -2550 -2500 -2450 -2400 -2350 -2300 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 VDD VDD VDD VDD VDD VDD AGND AGND AGND AGND AGND AGND RDX D_CX TESEL DGNDO D[17] D[16] D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[1] D[3] D[5] D[7] TE RESX CSX D[6] D[4] D[2] IM[2] D[0] WRX Dummy Dummy Dummy Dummy TESTOP[3] TESTOP[2] TESTOP[1] DGND DGND DGND DGND X Y No. -2250 -2200 -2150 -2100 -2050 -2000 -1950 -1900 -1850 -1800 -1750 -1700 -1630 -1570 -1510 -1450 -1390 -1330 -1270 -1210 -1150 -1090 -1030 -970 -910 -850 -790 -730 -670 -610 -550 -490 -430 -370 -310 -250 -190 -130 -70 0 50 100 150 200 250 300 350 400 450 500 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 6 PAD Name DGND DGND VDDI VDDI VDDI VDDI VDDI VDDI VPP VPP VPP GVDD GVDD GVDD VCC Dummy Dummy GVCL Dummy AVDD AVDD AVDD AVDD AVDD Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy AGND AGND AGND AVCL AVCL X Y 550 600 650 700 750 800 850 900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 1450 1500 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 2650 2700 2750 2800 2850 2900 2950 3000 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 2009-08-05 ST7735R No. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 PAD Name AVCL Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy VGL Dummy Dummy VGH Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy VCOM VCOM VCOM Dummy Dummy Dummy G162 G160 G158 G156 G154 G152 G150 G148 G146 G144 G142 G140 G138 V0.2 X Y No. 3050 3100 3150 3200 3250 3300 3350 3400 3450 3500 3550 3600 3650 3700 3750 3800 3850 3900 3950 4000 4050 4100 4150 4200 4250 4300 4350 4400 4450 4500 4550 4600 4650 4700 4750 4772 4756 4740 4724 4708 4692 4676 4660 4644 4628 4612 4596 4580 4564 4548 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 PAD Name G136 G134 G132 G130 G128 G126 G124 G122 G120 G118 G116 G114 G112 G110 G108 G106 G104 G102 G100 G98 G96 G94 G92 G90 G88 G86 G84 G82 G80 G78 G76 G74 G72 G70 G68 G66 G64 G62 G60 G58 G56 G54 G52 G50 G48 G46 G44 G42 G40 G38 X Y No. 4532 4516 4500 4484 4468 4452 4436 4420 4404 4388 4372 4356 4340 4324 4308 4292 4276 4260 4244 4228 4212 4196 4180 4164 4148 4132 4116 4100 4084 4068 4052 4036 4020 4004 3988 3972 3956 3940 3924 3908 3892 3876 3860 3844 3828 3812 3796 3780 3764 3748 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 7 PAD Name G36 G34 G32 G30 G28 G26 G24 G22 G20 G18 G16 G14 G12 G10 G8 G6 G4 G2 Dummy Dummy Dummy Dummy S396 S395 S394 S393 S392 S391 S390 S389 S388 S387 S386 S385 S384 S383 S382 S381 S380 S379 S378 S377 S376 S375 S374 S373 S372 S371 S370 S369 X Y 3732 3716 3700 3684 3668 3652 3636 3620 3604 3588 3572 3556 3540 3524 3508 3492 3476 3460 3444 3428 3412 3396 3380 3364 3348 3332 3316 3300 3284 3268 3252 3236 3220 3204 3188 3172 3156 3140 3124 3108 3092 3076 3060 3044 3028 3012 2996 2980 2964 2948 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 2009-08-05 ST7735R No. 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 PAD Name S368 S367 S366 S365 S364 S363 S362 S361 S360 S359 S358 S357 S356 S355 S354 S353 S352 S351 S350 S349 S348 S347 S346 S345 S344 S343 S342 S341 S340 S339 S338 S337 S336 S335 S334 S333 S332 S331 S330 S329 S328 S327 S326 S325 S324 S323 S322 S321 S320 S319 V0.2 X 2932 2916 2900 2884 2868 2852 2836 2820 2804 2788 2772 2756 2740 2724 2708 2692 2676 2660 2644 2628 2612 2596 2580 2564 2548 2532 2516 2500 2484 2468 2452 2436 2420 2404 2388 2372 2356 2340 2324 2308 2292 2276 2260 2244 2228 2212 2196 2180 2164 2148 Y 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 No. 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 PAD Name S318 S317 S316 S315 S314 S313 S312 S311 S310 S309 S308 S307 S306 S305 S304 S303 S302 S301 S300 S299 S298 S297 S296 S295 S294 S293 S292 S291 S290 S289 S288 S287 S286 S285 S284 S283 S282 S281 S280 S279 S278 S277 S276 S275 S274 S273 S272 S271 S270 S269 X 2132 2116 2100 2084 2068 2052 2036 2020 2004 1988 1972 1956 1940 1924 1908 1892 1876 1860 1844 1828 1812 1796 1780 1764 1748 1732 1716 1700 1684 1668 1652 1636 1620 1604 1588 1572 1556 1540 1524 1508 1492 1476 1460 1444 1428 1412 1396 1380 1364 1348 8 Y 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 No. 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 PAD Name S268 S267 S266 S265 S264 S263 S262 S261 S260 S259 S258 S257 S256 S255 S254 S253 S252 S251 S250 S249 S248 S247 S246 S245 S244 S243 S242 S241 S240 S239 S238 S237 S236 S235 S234 S233 S232 S231 S230 S229 S228 S227 S226 S225 S224 S223 S222 S221 S220 S219 X Y 1332 1316 1300 1284 1268 1252 1236 1220 1204 1188 1172 1156 1140 1124 1108 1092 1076 1060 1044 1028 1012 996 980 964 948 932 916 900 884 868 852 836 820 804 788 772 756 740 724 708 692 676 660 644 628 612 596 580 564 548 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 2009-08-05 ST7735R No. 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 PAD Name S218 S217 S216 S215 S214 S213 S212 S211 S210 S209 S208 S207 S206 S205 S204 S203 S202 S201 S200 S199 Dummy Dummy Dummy Dummy S198 S197 S196 S195 S194 S193 S192 S191 S190 S189 S188 S187 S186 S185 S184 S183 S182 S181 S180 S179 S178 S177 S176 S175 S174 S173 V0.2 X 532 516 500 484 468 452 436 420 404 388 372 356 340 324 308 292 276 260 244 228 212 196 -196 -212 -228 -244 -260 -276 -292 -308 -324 -340 -356 -372 -388 -404 -420 -436 -452 -468 -484 -500 -516 -532 -548 -564 -580 -596 -612 -628 Y 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 No. 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 PAD Name S172 S171 S170 S169 S168 S167 S166 S165 S164 S163 S162 S161 S160 S159 S158 S157 S156 S155 S154 S153 S152 S151 S150 S149 S148 S147 S146 S145 S144 S143 S142 S141 S140 S139 S138 S137 S136 S135 S134 S133 S132 S131 S130 S129 S128 S127 S126 S125 S124 S123 X -644 -660 -676 -692 -708 -724 -740 -756 -772 -788 -804 -820 -836 -852 -868 -884 -900 -916 -932 -948 -964 -980 -996 -1012 -1028 -1044 -1060 -1076 -1092 -1108 -1124 -1140 -1156 -1172 -1188 -1204 -1220 -1236 -1252 -1268 -1284 -1300 -1316 -1332 -1348 -1364 -1380 -1396 -1412 -1428 9 Y 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 No. 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 PAD Name S122 S121 S120 S119 S118 S117 S116 S115 S114 S113 S112 S111 S110 S109 S108 S107 S106 S105 S104 S103 S102 S101 S100 S99 S98 S97 S96 S95 S94 S93 S92 S91 S90 S89 S88 S87 S86 S85 S84 S83 S82 S81 S80 S79 S78 S77 S76 S75 S74 S73 X Y -1444 -1460 -1476 -1492 -1508 -1524 -1540 -1556 -1572 -1588 -1604 -1620 -1636 -1652 -1668 -1684 -1700 -1716 -1732 -1748 -1764 -1780 -1796 -1812 -1828 -1844 -1860 -1876 -1892 -1908 -1924 -1940 -1956 -1972 -1988 -2004 -2020 -2036 -2052 -2068 -2084 -2100 -2116 -2132 -2148 -2164 -2180 -2196 -2212 -2228 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 2009-08-05 ST7735R No. 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 PAD Name S72 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 V0.2 X -2244 -2260 -2276 -2292 -2308 -2324 -2340 -2356 -2372 -2388 -2404 -2420 -2436 -2452 -2468 -2484 -2500 -2516 -2532 -2548 -2564 -2580 -2596 -2612 -2628 -2644 -2660 -2676 -2692 -2708 -2724 -2740 -2756 -2772 -2788 -2804 -2820 -2836 -2852 -2868 -2884 -2900 -2916 -2932 -2948 -2964 -2980 -2996 -3012 -3028 Y 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 No. 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 PAD Name S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 Dummy Dummy Dummy Dummy G1 G3 G5 G7 G9 G11 G13 G15 G17 G19 G21 G23 G25 G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 X -3044 -3060 -3076 -3092 -3108 -3124 -3140 -3156 -3172 -3188 -3204 -3220 -3236 -3252 -3268 -3284 -3300 -3316 -3332 -3348 -3364 -3380 -3396 -3412 -3428 -3444 -3460 -3476 -3492 -3508 -3524 -3540 -3556 -3572 -3588 -3604 -3620 -3636 -3652 -3668 -3684 -3700 -3716 -3732 -3748 -3764 -3780 -3796 -3812 -3828 10 Y 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 No. 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 PAD Name G49 G51 G53 G55 G57 G59 G61 G63 G65 G67 G69 G71 G73 G75 G77 G79 G81 G83 G85 G87 G89 G91 G93 G95 G97 G99 G101 G103 G105 G107 G109 G111 G113 G115 G117 G119 G121 G123 G125 G127 G129 G131 G133 G135 G137 G139 G141 G143 G145 G147 X Y -3844 -3860 -3876 -3892 -3908 -3924 -3940 -3956 -3972 -3988 -4004 -4020 -4036 -4052 -4068 -4084 -4100 -4116 -4132 -4148 -4164 -4180 -4196 -4212 -4228 -4244 -4260 -4276 -4292 -4308 -4324 -4340 -4356 -4372 -4388 -4404 -4420 -4436 -4452 -4468 -4484 -4500 -4516 -4532 -4548 -4564 -4580 -4596 -4612 -4628 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 2009-08-05 ST7735R No. 751 752 753 754 755 756 757 758 759 X Y G149 G151 G153 G155 G157 G159 G161 Dummy Dummy PAD Name -4644 -4660 -4676 -4692 -4708 -4724 -4740 -4756 -4772 110 227 110 227 110 227 110 227 110 ALIGNMENT_R ALIGNMENT_L 4841 -4841 -220 -220 V0.2 11 2009-08-05 ST7735R GVDD Block diagram GVCL 5 162 Gate Buffer Voltage Reference 396 Source Buffer Level Shifter DAC Gamma Circuit Gate Decoder Level Shifter Data Latch Gamma Table Display Ram 132 x 162 x 18 bits Vcom generator Display control Color conversion LUT table Instruction Register VCOM OSC NVM Booster 1/2/4 MCU IF VDD VDDI AVDD AVCL VGH VGL SMY EXTC SMX DC/X (SCL) 12 IM [2:0] CSX RDX (E) GS WRX (R/WX) LCM SRGB TESEL D[17:0] SDA V0.2 2009-08-05 ST7735R 6 Driver IC Pin Description 6.1 Power Supply Pin Name I/O Description Connect pin VDD I Power supply for analog, digital system and booster circuit. VDD VDDI I Power supply for I/O system. VDDI AGND I System ground for analog system and booster circuit. GND DGND I System ground for I/O system and digital system. GND 6.2 Interface logic pin Name I/O Description Connect pin -8080/6800 MCU interface mode select. P68 I -P68=’1’, select 6800 MCU parallel interface. -P68=’0’, select 8080 MCU parallel interface. DGND/VDDI -If not used, please fix this pin at DGND level. MCU Parallel interface bus and Serial interface select IM2 I IM2=’1’, Parallel interface DGND/VDDI IM2=’0’, Serial interface - MCU parallel interface type selection -If not used, please fix this pin at VDDI or DGND level. IM1,IM0 I IM1 IM0 Parallel interface 0 0 MCU 8-bit parallel 0 1 MCU 16-bit parallel 1 0 MCU 9-bit parallel 1 1 MCU 18-bit parallel DGND/VDDI - SPI4W=’0’, 3-line SPI enable. SPI4W I - SPI4W=’1’, 4-line SPI enable. DGND/VDDI -If not used, please fix this pin at DGND level. -This signal will reset the device and it must be applied to properly RESX I initialize the chip. MCU -Signal is active low. CSX I -Chip selection pin MCU -Low enable. -Display data/command selection pin in MCU interface. D/CX (SCL) -D/CX=’1’: display data or parameter. I -D/CX=’0’: command data. MCU -In serial interface, this is used as SCL. -If not used, please fix this pin at VDDI or DGND level. RDX V0.2 I -Read enable in 8080 MCU parallel interface. -If not used, please fix this pin at VDDI or DGND level. 13 MCU 2009-08-05 ST7735R WRX (D/CX) -Write enable in MCU parallel interface. I -In 4-line SPI, this pin is used as D/CX (data/ command selection). MCU -If not used, please fix this pin at VDDI or DGND level. -D[17:0] are used as MCU parallel interface data bus. D[17:0] I/O -D0 is the serial input/output signal in serial interface mode. -In serial interface, D[17:1] are not used and should be fixed at VDDI or MCU DGND level. -Tearing effect output pin to synchronies MCU to frame rate, activated TE O by S/W command. MCU -If not used, please open this pin. -Monitoring pin of internal oscillator clock and is turned ON/OFF by OSC O S/W command. -When this pin is inactive (function OFF), this pin is DGND level. - -If not used, please open this pin. Note1. When in parallel mode, no use data pin must be connected to “1” or “0”. Note2. When CSX=”1”, there is no influence to the parallel and serial interface. V0.2 14 2009-08-05 ST7735R 6.3 Mode selection pin Name I/O Description Connect pin -During normal operation, please open this pin. EXTC EXTC Enable/disable modification of extend command 0 Normal operation mode 1 Use NVM command set I Open -Panel resolution selection pins. GM1, GM0 I G G M M 1 0 0 0 132RGB x 162 (S1~S396 & G1~G162 output) 1 1 128RGB x 160 (S7~S390 & G2~G161 output) Selection of panel resolution VDDI/DGND -RGB direction select H/W pin for color filter setting. SRGB I SRGB RGB arrangement 0 S1, S2, S3 filter order = ’R’, ’G’, ’B’ 1 S1, S2, S3 filter order = ‘B’, ‘G’, ‘R’ VDDI/DGND -Module source output direction H/W selection pin. SMX SMX Scanning direction of source output GM= ‘00’ GM= ‘11’ 0 S1 -> S396 S7 -> S390 1 S396 -> S1 S390 -> S7 I VDDI/DGND -Module Gate output direction H/W selection pin. SMY SMY Scanning direction of gate output GM= ‘00’ GM= ‘11’ 0 G1 -> G162 G2 -> G161 1 G162 -> G1 G161 -> G2 I VDDI/DGND -Liquid crystal (LC) type selection pins. LCM I LCM Selection of LC type 0 Normally white LC type 1 Normally black LC type VDDI/DGND -Gamma curve selection pin. GS V0.2 I GS Selection of gamma curve 0 GC0=1.0, GC1=2.5, GC2=2.2, GC3=1.8 1 GC0=2.2, GC1=1.8, GC2=2.5, GC3=1.0 15 VDDI/DGND 2009-08-05 ST7735R VPP I When writing NVM, it needs external power supply voltage (7.5V). Input pin to select horizontal line number in TE signal. This pin is only for GM[1:0]=’00’ mode TESEL I TESEL Selection of gamma curve 0 TE output 162 lines 1 TE output 160 lines VDDI/DGND 6.4 Driver output pins Name I/O Description S1 to S396 O - Source driver output pins. - G1 to G162 O - Gate driver output pins. - AVDD O AVCL O VGH O - Power output pin for gate driver VGL O - Power output (Negative) pin for gate driver Power pin for analog circuits. Connect a capacitor for stabilization. Connect pin Capacitor - A power supply pin for generating GVCL. - Connect a capacitor for stabilization. Capacitor - A power output of grayscale voltage generator. GVDD O - When internal GVDD generator is not used, connect an external power supply (AVDD-0.5V) to this pin. - A power output(Negative) of grayscale voltage generator. GVCL O - When internal GVCL generator is not used, connect an external - power supply (AVCL+0.5V) to this pin. O VCC O VDDIO O - VDDI voltage output level for monitoring. - DGNDO O - DGND voltage output level for monitoring. - V0.2 - A power supply for the TFT-LCD common electrode. Common VCOM electrode - Monitoring pin of internal digital reference voltage. - Please open these pins. 16 2009-08-05 ST7735R 6.5 Test pins Name TEST2P TEST1P I/O Description Connect pin -These test pins for Driver vender test used. I -Please connect these pins to DGND. DGND TESTOP[8] TESTOP[7] TESTOP[6] TESTOP[5] TESTOP[4] -These test pins for Driver vender test used. O Open -Please open these pins. TESTOP[3] TESTOP[2] TESTOP[1] -These pins are dummy (have no function inside). Dummy - -Can allow signal traces pass through these pads on TFT glass. Open -Please open these pins. V0.2 17 2009-08-05 ST7735R 7 Driver electrical characteristics 7.1 Absolute operation range Item Symbol Rating Unit Supply voltage VDD - 0.3 ~ +4.6 V Supply voltage (Logic) VDDI - 0.3 ~ +4.6 V Supply voltage (Digital) VCC -0.3 ~ +1.95 V Driver supply voltage VGH-VGL -0.3 ~ +30.0 V Logic input voltage range VIN 0.3 ~ VDDI + 0.3 V Logic output voltage range VO 0.3 ~ VDDI + 0.3 V Operating temperature range TOPR -30 ~ +85 ℃ Storage temperature range TSTG -40 ~ +125 ℃ Note: If one of the above items is exceeded its maximum limitation momentarily, the quality of the product may be degraded. Absolute maximum limitation, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the recommend range. V0.2 18 2009-08-05 ST7735R 7.2 DC characteristic Parameter Symbo Specification Condition l Min Uni Related Pins Typ Max t Power & operation voltage System voltage Interface operation voltage VDD Operating voltage 2.3 2.75 4.8 V VDDI I/O supply voltage 1.65 1.8 3.7 V Gate driver high voltage VGH 10 15 V Gate driver low voltage VGL -12.4 -7.5 V 17.5 27.5 V Gate driver supply voltage | VGH-VGL | Input / Output Logic-high input voltage VIH 0.7VDDI VDDI V Note 1 Logic-low input voltage VIL VSS 0.3VDDI V Note 1 Logic-high output voltage VOH IOH = -1.0mA 0.8VDDI VDDI V Note 1 Logic-low output voltage VOL IOL = +1.0mA VSS 0.2VDDI V Note 1 Logic-high input current IIH VIN = VDDI 1 uA Note 1 Logic-low input current IIL VIN = VSS -1 uA Note 1 Input leakage current IIL IOH = -1.0mA -0.1 +0.1 uA Note 1 -2 -0.425 V VCOM voltage VCOM amplitude VCOM Source driver Source output range Vsout 0.1 GVDD V Gamma reference voltage GVDD 3.0 5.0 V 20 us Note 2 35 mV Note 3 Source output settling time Output offset voltage Tr Below with 99% precision Voffset Notes: 1. TA= -30 to 85℃. 2. Source channel loading= 2KΩ+12pF/channel, Gate channel loading=5KΩ+40pF/channel. 3. The Max. value is between measured point of source output and gamma setting value. V0.2 19 2009-08-05 ST7735R 7.3 Power consumption Ta=25℃, Frame rate = 60Hz, the registers setting are IC default setting. Current consumption Operation mode Normal mode Partial + Idle mode (40 lines) Sleep-in mode Typical Image Maximum IDDI IDD IDDI IDD (mA) (mA) (mA) (mA) Note 1 TBD TBD TBD TBD Note 2 TBD TBD TBD TBD Note 1 TBD TBD TBD TBD Note 2 TBD TBD TBD TBD N/A TBD TBD TBD TBD Notes: 1. All pixels black. 2. All pixels white. 3. The Current Consumption is DC characteristics of ST7735R. 4. Typical: VDDI=1.8V, VDD=2.75V; Maximum: VDDI=1.65 to 3.7V, VDD=2.3 to 4.8V V0.2 20 2009-08-05 ST7735R 8 Timing chart 8.1 Parallel interface characteristics: 18, 16, 9 or 8-bit bus (8080 series MCU interface) Figure 8.1.1 Parallel interface timing characteristics (8080 series MCU interface) Ta=25 ℃, VDDI=1.65~3.7V, VDD=2.3~4.8V Signal Symbol Parameter TAST Address setup time D/CX TAHT Address hold time (Write/Read) TCHW Chip select “H” pulse width TCS Chip select setup time (Write) TRCS Chip select setup time (Read ID) CSX TRCSFM Chip select setup time (Read FM) TCSF Chip select wait time (Write/Read) TCSH Chip select hold time TWC Write cycle WRX TWRH Control pulse “H” duration TWRL Control pulse “L” duration TRC Read cycle (ID) RDX (ID) TRDH Control pulse “H” duration (ID) TRDL Control pulse “L” duration (ID) TRCFM Read cycle (FM) RDX (FM) TRDHFM Control pulse “H” duration (FM) TRDLFM Control pulse “L” duration (FM) TDST Data setup time TDHT Data hold time D[17:0] TRAT Read access time (ID) TRATFM Read access time (FM) TODH Output disable time Min 10 10 0 15 45 355 10 10 66 15 15 160 90 45 450 90 355 10 10 20 Max 40 340 80 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description - - When read ID data When read from frame memory For CL=30pF Table 8.1.1 8080 parallel Interface Characteristics V0.2 21 2009-08-05 ST7735R Figure 8.1.2 Rising and falling timing for input and output signal Figure 8.1.3 Chip selection (CSX) timing Figure 8.1.4 Write-to-read and read-to-write timing Note: The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals. V0.2 22 2009-08-05 ST7735R 8.2 Parallel interface characteristics: 18, 16, 9 or 8-bit bus (6800 series MCU interface) Figure 8.2.1Parallel interface timing characteristics (6800-series MCU interface) Ta=25 ℃, VDDI=1.65~3.7V, VDD=2.3~4.8V Signal Symbol Parameter TAST Address setup time D/CX TAHT Address hold time (Write/Read) TCHW Chip select “H” pulse width TCS Chip select setup time (Write) TRCS Chip select setup time (Read ID) CSX TRCSFM Chip select setup time (Read FM) TCSF Chip select wait time (Write/Read) TCSH Chip select hold time TWC Write cycle WRX TWRH Control pulse “H” duration TWRL Control pulse “L” duration TRC Read cycle (ID) RDX (ID) TRDH Control pulse “H” duration (ID) TRDL Control pulse “L” duration (ID) TRCFM Read cycle (FM) RDX (FM) TRDHFM Control pulse “H” duration (FM) TRDLFM Control pulse “L” duration (FM) TDST Data setup time D[17:0] TDHT Data hold time TODH Output disable time Min 10 10 0 15 45 355 10 10 66 15 15 160 90 45 450 90 355 10 10 20 Max 80 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description - - When read ID data When read from frame memory For maximum CL=30pF For minimum CL=8pF Table 8.2.1 6800 parallel Interface Characteristics Note: The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals. V0.2 23 2009-08-05 ST7735R 8.3 Serial interface characteristics (3-line serial) CSX VIH TCHW VIL TSCYCW/TSCYCR TCSH TCSS TSLW/TSLR SCL TSHW/TSHR TSDS SDA TSCC VIH VIL TSDH VIH VIL TACC TOH VIH VIL VIH SDA (DOUT) VIL Figure 8.3.1 3-line serial interface timing Ta=25 ℃, VDDI=1.65~3.7V, VDD=2.3~4.8V Signal Symbol Parameter TCSS Chip select setup time (write) TCSH Chip select hold time (write) CSX TCSS Chip select setup time (read) TSCC Chip select hold time (read) TCHW Chip select “H” pulse width TSCYCW Serial clock cycle (Write) TSHW SCL “H” pulse width (Write) TSLW SCL “L” pulse width (Write) SCL TSCYCR Serial clock cycle (Read) TSHR SCL “H” pulse width (Read) TSLR SCL “L” pulse width (Read) TSDS Data setup time SDA TSDH Data hold time (DIN) TACC Access time (DOUT) TOH Output disable time Min 15 15 60 65 40 66 15 15 150 60 60 10 10 10 15 Max 50 50 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description For maximum CL=30pF For minimum CL=8pF Table 8.3.1 3-line Serial Interface Characteristics Note : The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals. V0.2 24 2009-08-05 ST7735R 8.4 Serial interface characteristics (4-line serial) Figure 8.4.1 4-line serial interface timing Ta=25 ℃, VDDI=1.65~3.7V, VDD=2.3~4.8V Signal Symbol Parameter TCSS Chip select setup time (write) TCSH Chip select hold time (write) CSX TCSS Chip select setup time (read) TSCC Chip select hold time (read) TCHW Chip select “H” pulse width TSCYCW Serial clock cycle (Write) TSHW SCL “H” pulse width (Write) TSLW SCL “L” pulse width (Write) SCL TSCYCR Serial clock cycle (Read) TSHR SCL “H” pulse width (Read) TSLR SCL “L” pulse width (Read) TDCS D/CX setup time D/CX TDCH D/CX hold time TSDS Data setup time SDA TSDH Data hold time (DIN) TACC Access time (DOUT) TOH Output disable time MIN 45 45 60 65 40 66 15 15 150 60 60 10 10 10 10 10 15 MAX 50 50 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description -write command & data ram -read command & data ram For maximum CL=30pF For minimum CL=8pF Table 8.4.1 4-line Serial Interface Characteristics Note : The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals. V0.2 25 2009-08-05 ST7735R 9 Function description 9.1 Interface type selection The selection of given interfaces are done by setting IM2, IM1, and IM0 pins as shown in following table. P68 IM2 IM1 IM0 Interface Read back selection 0 3-line serial interface Via the read instruction 0 1 0 0 8080 MCU 8-bit parallel RDX strobe (8-bit read data and 8-bit read parameter) 0 1 0 1 8080 MCU 16-bit parallel RDX strobe (16-bit read data and 8-bit read parameter) 0 1 1 0 8080 MCU 9-bit parallel RDX strobe (9-bit read data and 8-bit read parameter) 0 1 1 1 8080 MCU 18-bit parallel RDX strobe (18-bit read data and 8-bit read parameter) 0 3-line serial interface Via the read instruction 1 1 0 0 6800 MCU 8-bit parallel E strobe (8-bit read data and 8-bit read parameter) 1 1 0 1 6800 MCU 16-bit parallel E strobe (16-bit read data and 8-bit read parameter) 1 1 1 0 6800 MCU 9-bit parallel E strobe (9-bit read data and 8-bit read parameter) 1 1 1 1 6800 MCU 18-bit parallel E strobe (18-bit read data and 8-bit read parameter) Table 9.1.1 Selection of MCU interface P68 0 IM2 0 1 IM1 0 IM0 0 Interface 3-line serial interface 8080 8-bit parallel RDX Note1 RDX WRX Note1 WRX D/CX SCL D/CX 0 1 0 1 8080 16-bit parallel RDX WRX D/CX 0 0 1 1 1 0 1 1 1 0 0 1 0 8080 9-bit parallel 8080 18-bit parallel 3-line serial interface 6800 8-bit parallel RDX RDX Note1 E WRX WRX D/CX WRX D/CX D/CX SCL RS 1 1 0 1 6800 16-bit parallel E WRX RS 1 1 1 1 1 1 0 1 6800 9-bit parallel 6800 18-bit parallel E E WRX WRX RS RS Read back selection D[17:1]: unused, D0: SDA D[17:8]: unused, D7-D0: 8-bit data D[17:16]: unused, D15-D0: 16-bit data D[17:9]: unused, D8-D0: 9-bit data D17-D0: 18-bit data D[17:1]: unused, D0: SDA D[17:8]: unused, D7-D0: 8-bit data D[17:16]: unused, D15-D0: 16-bit data D[17:9]: unused, D8-D0: 9-bit data D17-D0: 18-bit data Table 9.1.2 Pin connection according to various MCU interface Note: Unused pins can be open, or connected to DGND or VDDI. V0.2 26 2009-08-05 ST7735R 9.2 8080-series MCU parallel interface (P68 = ‘0’) The MCU can use one of following interfaces: 11-lines with 8-data parallel interface, 12-lines with 9-data parallel interface, 19-line with 16-data parallel interface or 21-lines with 18-data parallel interface. The chip-select CSX (active low) enables/disables the parallel interface. RESX (active low) is an external reset signal. WRX is the parallel data write enable, RDX is the parallel data read enable and D[17:0] is parallel data bus. The LCD driver reads the data at the rising edge of WRX signal. The D/CX is the data/command flag. When D/CX=’1’, D[17:0] bits is either display data or command parameter. When D/C=’0’, D[17:0] bits is command. The interface functions of 8080-series parallel interface are given in following table. IM2 1 1 1 1 IM1 0 0 1 1 IM0 0 1 0 1 Interface 8-bit parallel 16-bit parallel 9-bit parallel 18-bit parallel D/CX RDX WRX Read back selection 0 1 ↑ Write 8-bit command (D7 to D0) 1 1 ↑ Write 8-bit display data or 8-bit parameter (D7 to D0) 1 ↑ 1 Read 8-bit display data (D7 to D0) Read 8-bit parameter or status (D7 to D0) 1 ↑ 1 0 1 ↑ Write 8-bit command (D7 to D0) 1 1 ↑ Write 16-bit display data or 8-bit parameter (D15 to D0) 1 ↑ 1 Read 16-bit display data (D15 to D0) 1 ↑ 1 Read 8-bit parameter or status (D7 to D0) 0 1 ↑ Write 8-bit command (D7 to D0) 1 1 ↑ Write 9-bit display data or 8-bit parameter (D8 to D0) 1 ↑ 1 Read 9-bit display data (D8 to D0) 1 ↑ 1 Read 8-bit parameter or status (D7 to D0) 0 1 ↑ Write 8-bit command (D7 to D0) 1 1 ↑ Write 18-bit display data or 8-bit parameter (D17 to D0) 1 ↑ 1 Read 18-bit display data (D17 to D0) 1 ↑ 1 Read 8-bit parameter or status (D7 to D0) Table 9.2.1 the function of 8080-series parallel interface Note: applied for command code: DAh, DBh, DCh, 04h, 09h, 0Ah, 0Bh, 0Ch, 0Dh, 0Eh, 0Fh V0.2 27 2009-08-05 ST7735R 9.2.1 Write cycle sequence The write cycle means that the host writes information (command or/and data) to the display via the interface. Each write cycle (WRX high-low-high sequence) consists of 3 control signals (D/CX, RDX, WRX) and data signals (D[17:0]). D/CX bit is a control signal, which tells if the data is a command or a data. The data signals are the command if the control signal is low (=’0’) and vice versa it is data (=’1’). WRX D[17:0] The host starts to control D[17:0] lines when there is a falling edge of the WRX. The display writes D[17:0] lines when there is a rising edge of WRX. The host stops to control D[17:0] lines. Figure 9.2.1 8080-series WRX protocol Note: WRX is an unsynchronized signal (It can be stopped). 1-byte command D[17:0] S 2-byte command N-byte command CMD CMD PA1 CMD PA1 PAN-2 PAN-1 P RESX “1” CSX D/CX RDX “1” WRX D[17:0] S CMD CMD PA1 CMD PA1 PAN-2 PAN-1 P Host D[17:0] Host to LCD S CMD CMD PA1 CMD PA1 PAN-2 PAN-1 P Driver D[17:0] LCD to Host Hi-Z Signals on D[17:0], D/CX, R/WX, E pins during CSX=1 are ignored. CMD: write command code PA: parameter or display data Figure 9.2.2 8080-series parallel bus protocol, write to register or display RAM V0.2 28 2009-08-05 ST7735R 9.2.2 Read cycle sequence The read cycle (RDX high-low-high sequence) means that the host reads information from LCD driver via interface. The driver sends data (D[17:0]) to the host when there is a falling edge of RDX and the host reads data when there is a rising edge of RDX. Figure 9.2.3 8080-series RDX protocol Note: RDX is an unsynchronized signal (It can be stopped). Read parameter D[17:0] Read display data S CMD DM PA CMD DM & data Data Data P D[17:0] S CMD DM PA CMD DM & data Data Data P Host D[17:0] Host to LCD S CMD Driver D[17:0] LCD to Host S RESX “1” CSX D/CX RDX WRX Hi-Z Hi-Z DM CMD PA1 Hi-Z Hi-Z P DM & data PAN-2 PAN-1 P Signals on D[17:0], D/CX, R/WX, E pins during CSX=1 are ignored. CMD: write command code PA: parameter or display data Figure 9.2.4 8080-series parallel bus protocol, read data from register or display RAM V0.2 29 2009-08-05 ST7735R 9.3 6800-series MCU parallel interface (P68 = ‘1’) The MCU uses one of following interface: 11-lines with 8-data parallel interface, 12-lines with 9-data parallel interface, 19-lines with 16-data parallel interface, or 21-lines with 18-data parallel interface. The chip-select CSX(active low) enables and disables the parallel interface. RESX (active low) is an external reset signal. The R/WX is the Read/Write flag and D[17:0] is parallel data bus. The LCD driver reads the data at the falling edge of E signal when R/WX= ‘1’ and Writes the data at the falling of the E signal when R/WX=’0’. The D/CX is the data/command flag. When D/CX=’1’, D[17:0] bits are display RAM data or command parameters. When D/C= ‘0’, D[17:0] bits are commands. The 6800-series bi-directional interface can be used for communication between the micro controller and LCD driver. The selection of this interface is done when P68 pin is high state (VDDI). Interface bus width can be selected with IM2, IM1 and IM0.The interface functions of 6800-series parallel interface are given in Table 8.1.1. P68 IM2 IM1 IM0 Interface 1 1 0 0 8-bit Parallel 1 1 0 1 16-bit Parallel 1 1 1 0 9-bit Parallel 1 1 1 1 18-bit Parallel D/CX 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 R/WX 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 E ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ Function Write 8-bit command (D7 to D0) Write 8-bit display data or 8-bit parameter (D7 to D0) Read 8-bit Display data (D7 to D0) Read 8-bit parameter or status (D7 to D0) Write 8-bit command (D7 to D0) Write 16-bit display data or 8-bit parameter (D15 to D0) Read 16-bit Display data (D15 to D0) Read 8-bit parameter or status (D7 to D0) Write 8-bit command (D7 to D0) Write 9-bit display data or 8-bit parameter (D8 to D0) Read 9-bit Display data (D8 to D0) Read 8-bit parameter or status (D7 to D0) Write 8-bit command (D7 to D0) Write 18-bit display data or 8-bit parameter (D17 to D0) Read 18-bit Display data (D17 to D0) Read 8-bit parameter or status (D7 to D0) Table 9.3.1 The function of 6800-series parallel interface Note: applied for command code: DAh, DBh, DCh, 04h, 09h, 0Ah, 0Bh, 0Ch, 0Dh, 0Eh, 0Fh. 9.3.1 Write cycle sequence The write cycle means that the host writes information (command or/and data) to the display via the interface. Each write cycle (E low-high-low sequence) consists of 3 control signals (D/CX, E, R/WX) and data signals (D[17:0]). D/CX bit is a control signal, which tells if the data is a command or a data. The data signals are the command if the control signal is low (=’0’) and vice versa it is data (=’1’). Figure 9.3.1 6800-Series Write Protocol Note: E is an unsynchronized signal (It can be stopped) V0.2 30 2009-08-05 ST7735R Figure 9.3.2 6800-series parallel bus protocol, write to register or display RAM V0.2 31 2009-08-05 ST7735R 9.3.2 9.3.2 Read cycle sequence The read cycle (E low-high-low sequence) means that the host reads information from LCD driver via interface. The driver sends data (D[17:0]) to the host when there is a rising edge of E and the host reads data when there is a falling edge of E. Figure 9.3.3 6800-series read protocol Note: E is an unsynchronized signal (It can be stopped) Figure 9.3.4 6800-series parallel bus protocol, read data form register or display RAM V0.2 32 2009-08-05 ST7735R 9.4 Serial interface The selection of this interface is done by IM2. See the Table 9.4.1. IM2 4WSPI Interface Read back selection 0 0 3-line serial interface Via the read instruction (8-bit, 24-bit and 32-bit read parameter) 0 1 4-line serial interface Via the read instruction (8-bit, 24-bit and 32-bit read parameter) Table 9.4.2 Selection of serial interface The serial interface is either 3-lines/9-bits or 4-lines/8-bts bi-directional interface for communication between the micro controller and the LCD driver. The 3-lines serial interface use: CSX (chip enable), SCL (serial clock) and SDA (serial data input/output), and the 4-lines serial interface use: CSX (chip enable), D/CX (data/ command flag), SCL (serial clock) and SDA (serial data input/output). Serial clock (SCL) is used for interface with MCU only, so it can be stopped when no communication is necessary. 9.4.1 Command Write Mode The write mode of the interface means the micro controller writes commands and data to the LCD driver. 3-lines serial data packet contains a control bit D/CX and a transmission byte. In 4-lines serial interface, data packet contains just transmission byte and control bit D/CX is transferred by the D/CX pin. If D/CX is “low”, the transmission byte is interpreted as a command byte. If D/CX is “high”, the transmission byte is stored in the display data RAM (memory write command), or command register as parameter. Any instruction can be sent in any order to the driver. The MSB is transmitted first. The serial interface is initialized when CSX is high. In this state, SCL clock pulse or SDA data have no effect. A falling edge on CSX enables the serial interface and indicates the start of data transmission. Figure 9.4.1 Serial interface data stream format When CSX is “high”, SCL clock is ignored. During the high period of CSX the serial interface is initialized. At the falling edge of CSX, SCL can be high or low (see Figure 9.4.2). SDA is sampled at the rising edge of SCL. D/CX indicates whether the byte is command (D/CX=’0’) or parameter/RAM data (D/CX=’1’). D/CX is sampled when first rising edge of SCL (3-lines serial interface) or 8th rising edge of SCL (4-lines serial interface). If CSX stays low after the last bit of command/data byte, the serial interface expects the D/CX bit (3-lines serial interface) or D7 (4-lines serial interface) of the next byte at the next rising edge of SCL.. V0.2 33 2009-08-05 ST7735R Figure 9.4.3 3-line serial interface write protocol (write to register with control bit in transmission) Figure 9.4.4 9.4.2 4-line serial interface write protocol (write to register with control bit in transmission) Read Functions The read mode of the interface means that the micro controller reads register value from the driver. To achieve read function, the micro controller first has to send a command (read ID or register command) and then the following byte is transmitted in the opposite direction. After that CSX is required to go to high before a new command is send (see the below figure). The driver samples the SDA (input data) at rising edge of SCL, but shifts SDA (output data) at the falling edge of SCL. Thus the micro controller is supported to read at the rising edge of SCL. After the read status command has been sent, the SDA line must be set to tri-state no later than at the falling edge of SCL of the last bit. V0.2 34 2009-08-05 ST7735R 9.4.3 3-line serial protocol 3-line serial protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh command: 8-bit read): 3-line serial protocol (for RDDID command: 24-bit read) 3-line Serial Protocol (for RDDST command: 32-bit read) Figure 9.4.5 V0.2 3-line serial interface read protocol 35 2009-08-05 ST7735R 9.4.4 4-line serial protocol 4-line serial protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh command: 8-bit read): 4-line serial protocol (for RDDID command: 24-bit read) 4-line Serial Protocol (for RDDST command: 32-bit read) Host Driver Figure 9.4.6 V0.2 4-line serial interface read protocol 36 2009-08-05 ST7735R 9.5 Data Transfer Break and Recovery If there is a break in data transmission by RESX pulse, while transferring a command or frame memory data or multiple parameter command data, before Bit D0 of the byte has been completed, then driver will reject the previous bits and have reset the interface such that it will be ready to receive command data again when the chip select line (CSX) is next activated after RESX have been HIGH state. See the following example Host (MCU to driver) Figure 9.5.1 Serial bus protocol, write mode – interrupted by RESX If there is a break in data transmission by CSX pulse, while transferring a command or frame memory data or multiple parameter command data, before Bit D0 of the byte has been completed, then driver will reject the previous bits and have reset the interface such that it will be ready to receive the same byte re-transmitted when the chip select line (CSX) is next activated. See the following example Figure 9.5.2 Serial bus protocol, write mode – interrupted by CSX If 1, 2 or more parameter commands are being sent and a break occurs while sending any parameter before the last one and if the host then sends a new command rather than re-transmitting the parameter that was interrupted, then the parameters that were successfully sent are stored and the parameter where the break occurred is rejected. The interface is ready to receive next byte as shown below. V0.2 37 2009-08-05 ST7735R Figure 9.5.3 Write interrupts recovery (serial interface) If a 2 or more parameter commands are being sent and a break occurs by the other command before the last one is sent, then the parameters that were successfully sent are stored and the other parameter of that command remains previous value. Figure 9.5.4 Write interrupts recovery (both serial and parallel Interface) V0.2 38 2009-08-05 ST7735R 9.6 Data transfer pause It will be possible when transferring a command, frame memory data or multiple parameter data to invoke a pause in the data transmission. If the chip select line is released after a whole byte of a frame memory data or multiple parameter data has been completed, then driver will wait and continue the frame memory data or parameter data transmission from the point where it was paused. If the chip select Line is released after a whole byte of a command has been completed, then the display module will receive either the command‘s parameters (if appropriate) or a new command when the chip select line is next enabled as shown below. This applies to the following 4 conditions: 1) Command-Pause-Command 2) Command-Pause-Parameter 3) Parameter-Pause-Command 4) Parameter-Pause-Parameter 9.6.1 Serial interface pause Figure 9.6.1 Serial interface pause protocol (pause by CSX) 9.6.2 Parallel interface pause Figure 9.6.2 Parallel bus pause protocol (paused by CSX) V0.2 39 2009-08-05 ST7735R 9.7 Data Transfer Modes The module has three kinds color modes for transferring data to the display RAM. These are 12-bit color per pixel, 16-bit color per pixel and 18-bit color per pixel. The data format is described for each interface. Data can be downloaded to the frame memory by 2 methods. 9.7.1 Method 1 The image data is sent to the frame memory in successive frame writes, each time the frame memory is filled, the frame memory pointer is reset to the start point and the next frame is written. 9.7.2 Method 2 The image data is sent and at the end of each frame memory download, a command is sent to stop frame memory write. Then start memory write command is sent, and a new frame is downloaded. Note 1: These apply to all data transfer Color modes on both serial and parallel interfaces. Note 2: The frame memory can contain both odd and even number of pixels for both methods. Only complete pixel data will be stored in the frame memory. V0.2 40 2009-08-05 ST7735R 9.8 Data Color Coding 9.8.1 8-bit Parallel Interface (IM2, IM1, IM0= “100”) Different display data formats are available for three Colors depth supported by listed below. - 4k colors, RGB 4,4,4-bit input. - 65k colors, RGB 5,6,5-bit input. - 262k colors, RGB 6,6,6-bit input. 9.8.2 8-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH= “03h” RESX IM[2:0] “ 1” “100” ” CSX D/CX WRX RDX “1” ” 8080-series control pins D7 0 R1, Bit 3 B1, Bit 3 G2, Bit 3 R3, Bit 3 D6 0 R1, Bit 2 B1, Bit 2 G2, Bit 2 R3, Bit 2 D5 1 R1, Bit 1 B1, Bit 1 G2, Bit 1 R3, Bit 1 D4 0 R1, Bit 0 B1, Bit 0 G2, Bit 0 R3, Bit 0 D3 1 G1, Bit 3 R2, Bit 3 B2, Bit 3 G3, Bit 3 D2 1 G1, Bit 2 R2, Bit 2 B2, Bit 2 G3, Bit 2 D1 0 G1, Bit 1 R2, Bit 1 B2, Bit 1 G3, Bit 1 D0 0 G1, Bit 0 R2, Bit 0 B2, Bit 0 G3, Bit 0 Pixel n Pixel n+1 12 bits 12 bits Look-up table for 4096 color data mapping (12 bits to 18 bits) 18 bits Frame memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Note 1: The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data. Note 2: 3-time transfer is used to transmit 1 pixel data with the 12-bit color depth information. Note 3: ‘-‘ = Don't care - Can be set to '0' or '1' V0.2 41 2009-08-05 ST7735R 9.8.3 8-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH= “05h” There is 1 pixel (3 sub-pixels) per 2-byte RESX “1” ” “ 100” ” IM[2:0] CSX D/CX WRX RDX “1” ” 8080-series control pins D7 0 R1, Bit 4 G1, Bit 2 R2, Bit 4 G2, Bit 2 D6 0 R1, Bit 3 G1, Bit 1 R2, Bit 3 G2, Bit 1 D5 1 R1, Bit 2 G1, Bit 0 R2, Bit 2 G2, Bit 0 D4 0 R1, Bit 1 B1, Bit 4 R2, Bit 1 B2, Bit 4 D3 1 R1, Bit 0 B1, Bit 3 R2, Bit 0 B2, Bit 3 D2 1 G1, Bit 5 B1, Bit 2 G2, Bit 5 B2, Bit 2 D1 0 G1, Bit 4 B1, Bit 1 G2, Bit 4 B2, Bit 1 D0 0 G1, Bit 3 B1, Bit 0 G2, Bit 3 B2, Bit 0 Pixel n Pixel n+1 16 bits 16 bits Look-up table for 65k color data mapping (16 bits to 18 bits) 18 bits Frame memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Note 1: The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green and MSB=Bit 4, LSB=Bit 0 for Red and Blue data. Note 2: 2-times transfer is used to transmit 1 pixel data with the 16-bit color depth information. Note 3: ‘-‘ = Don't care - Can be set to '0' or '1' V0.2 42 2009-08-05 ST7735R 9.8.4 8-bit data bus for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH= “06h” There is 1 pixel (3 sub-pixels) per 3-bytes. RESX IM[2:0] “ 1” ” “ 100” ” CSX D/CX WRX RDX “ 1” ” 8080-series control pins D7 0 R1, Bit 5 G1, Bit 5 B1, Bit 5 R2, Bit 5 D6 0 R1, Bit 4 G1, Bit 4 B1, Bit 4 R2, Bit 4 D5 1 R1, Bit 3 G1, Bit 3 B1, Bit 3 R2, Bit 3 D4 0 R1, Bit 2 G1, Bit 2 B1, Bit 2 R2, Bit 2 D3 1 R1, Bit 1 G1, Bit 1 B1, Bit 1 R2, Bit 1 D2 1 R1, Bit 0 G1, Bit 0 B1, Bit 0 R2, Bit 0 D1 0 - - - - D0 0 - - - - Pixel n Pixel n+1 18 bits 18 bits Frame memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Note 1: The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data. Note 2: 3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3: ‘-‘ = Don't care - Can be set to '0' or '1' V0.2 43 2009-08-05 ST7735R 9.8.5 16-Bit Parallel Interface (IM2,IM1, IM0= “101”) Different display data formats are available for three colors depth supported by listed below. - 4k colors, RGB 4,4,4-bit input - 65k colors, RGB 5,6,5-bit input - 262k colors, RGB 6,6,6-bit input 9.8.6 16-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH= “03h” There is 1 pixel (3 sub-pixels) per 1 byte RESX “1” ” “101” ” IM[2:0] CSX D/CX WRX RDX “1” ” 8080-series control pins D15 - - - - - D14 - - - - - D13 - - - - - D12 - - - - - D11 - R1, Bit 3 R2, Bit 3 R3, Bit 3 R4, Bit 3 D10 - R1, Bit 2 R2, Bit 2 R3, Bit 2 R4, Bit 2 D9 - R1, Bit 1 R2, Bit 1 R3, Bit 1 R4, Bit 1 D8 - R1, Bit 0 R2, Bit 0 R3, Bit 0 R4, Bit 0 D7 0 G1, Bit 3 G2, Bit 3 G3, Bit 3 G4, Bit 3 D6 0 G1, Bit 2 G2, Bit 2 G3, Bit 2 G4, Bit 2 D5 1 G1, Bit 1 G2, Bit 1 G3, Bit 1 G4, Bit 1 D4 0 G1, Bit 0 G2, Bit 0 G3, Bit 0 G4, Bit 0 D3 1 B1, Bit 3 B2, Bit 3 B3, Bit 3 B4, Bit 3 D2 1 B1, Bit 2 B2, Bit 2 B3, Bit 2 B4, Bit 2 D1 0 B1, Bit 1 B2, Bit 1 B3, Bit 1 B4, Bit 1 D0 0 B1, Bit 0 B2, Bit 0 B3, Bit 0 B4, Bit 0 Pixel n Pixel n+1 Pixel n+2 Pixel n+3 12 bits 12 bits Look-up table for 4096 color data mapping (12 bits to 18 bits) 18 bits Frame memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Note 1: The data order is as follows, MSB=D11, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data. Note 2: 1-times transfer (D11 to D0) is used to transmit 1 pixel data with the 12-bit color depth information. V0.2 44 2009-08-05 ST7735R 9.8.7 16-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH= “05h” There is 1 pixel (3 sub-pixels) per 1 byte RESX “ 1” ” “101” ” IM[2:0] CSX D/CX WRX RDX “ 1” ” 8080-series control pins D15 R1, Bit 4 R2, Bit 4 R3, Bit 4 R4, Bit 4 D14 - R1, Bit 3 R2, Bit 3 R3, Bit 3 R4, Bit 3 D13 - R1, Bit 2 R2, Bit 2 R3, Bit 2 R4, Bit 2 D12 - R1, Bit 1 R2, Bit 1 R3, Bit 1 R4, Bit 1 D11 - R1, Bit 0 R2, Bit 0 R3, Bit 0 R4, Bit 0 D10 - G1, Bit 5 G2, Bit 5 G3, Bit 5 G4, Bit 5 D9 - G1, Bit 4 G2, Bit 4 G3, Bit 4 G4, Bit 4 D8 - G1, Bit 3 G2, Bit 3 G3, Bit 3 G4, Bit 3 D7 0 G1, Bit 2 G2, Bit 2 G3, Bit 2 G4, Bit 2 D6 0 G1, Bit 1 G2, Bit 1 G3, Bit 1 G4, Bit 1 D5 1 G1, Bit 0 G2, Bit 0 G3, Bit 0 G4, Bit 0 D4 0 B1, Bit 4 B2, Bit 4 B3, Bit 4 B4, Bit 4 D3 1 B1, Bit 3 B2, Bit 3 B3, Bit 3 B4, Bit 3 D2 1 B1, Bit 2 B2, Bit 2 B3, Bit 2 B4, Bit 2 D1 0 B1, Bit 1 B2, Bit 1 B3, Bit 1 B4, Bit 1 D0 0 B1, Bit 0 B2, Bit 0 B3, Bit 0 B4, Bit 0 Pixel n Pixel n+1 Pixel n+2 Pixel n+3 16 bits 16 bits Look-up table for 65k color data mapping (16 bits to 18 bits) 18 bits Frame memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0 for Red and Blue data. Note 2: 1-times transfer (D15 to D0) is used to transmit 1 pixel data with the 16-bit color depth information. Note 3: ‘-‘ = Don't care - Can be set to '0' or '1' V0.2 45 2009-08-05 ST7735R 9.8.8 16-bit data bus for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH= “06h” There are 2 pixels (6 sub-pixels) per 3 bytes RESX “1” ” “ 101” ” IM[2:0] CSX D/CX WRX RDX “1” ” 8080-series control pins D15 - R1, Bit 5 B1, Bit 5 G2, Bit 5 R3, Bit 5 D14 - R1, Bit 4 B1, Bit 4 G2, Bit 4 R3, Bit 4 D13 - R1, Bit 3 B1, Bit 3 G2, Bit 3 R3, Bit 3 D12 - R1, Bit 2 B1, Bit 2 G2, Bit 2 R3, Bit 2 D11 - R1, Bit 1 B1, Bit 1 G2, Bit 1 R3, Bit 1 D10 - R1, Bit 0 B1, Bit 0 G2, Bit 0 R3, Bit 0 D9 - - - - - D8 - - - - - D7 0 G1, Bit 5 R2, Bit 5 B2, Bit 5 G3, Bit 5 D6 0 G1, Bit 4 R2, Bit 4 B2, Bit 4 G3, Bit 4 D5 1 G1, Bit 3 R2, Bit 3 B2, Bit 3 G3, Bit 3 D4 0 G1, Bit 2 R2, Bit 2 B2, Bit 2 G3, Bit 2 D3 1 G1, Bit 1 R2, Bit 1 B2, Bit 1 G3, Bit 1 D2 1 G1, Bit 0 R2, Bit 0 B2, Bit 0 G3, Bit 0 D1 0 - - - - D0 0 - - - - Pixel n Pixel n+1 18 bits 18 bits Frame memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data. Note 2: 3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3: ‘-‘ = Don't care - Can be set to '0' or '1' V0.2 46 2009-08-05 ST7735R 9.8.9 9-Bit Parallel Interface (IM2, IM1, IM0=“110”) Different display data formats are available for three colors depth supported by listed below. -262k colors, RGB 6,6,6-bit input 9.8.10 Write 9-bit data for RGB 6-6-6-bit input (262k-color) There is 1 pixel (6 sub-pixels) per 3 bytes RESX “1” ” “ 110” ” IM[2:0] CSX D/CX WRX RDX “1” ” 8080-series control pins D8 - R1, Bit 5 G1, Bit 2 R2, Bit 5 G2, Bit 2 D7 0 R1, Bit 4 G1, Bit 1 R2, Bit 4 G2, Bit 1 D6 0 R1, Bit 3 G1, Bit 0 R2, Bit 3 G2, Bit 0 D5 1 R1, Bit 2 B1, Bit 5 R2, Bit 2 B2, Bit 5 D4 0 R1, Bit 1 B1, Bit 4 R2, Bit 1 B2, Bit 4 D3 1 R1, Bit 0 B1, Bit 3 R2, Bit 0 B2, Bit 3 D2 1 G1, Bit 5 B1, Bit 2 G2, Bit 5 B2, Bit 2 D1 0 G1, Bit 4 B1, Bit 1 G2, Bit 4 B2, Bit 1 D0 0 G1, Bit 3 B1, Bit 0 G2, Bit 3 B2, Bit 0 Pixel n Pixel n+1 18 bits 18 bits Frame memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Note 1: The data order is as follows, MSB=D8, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data. Note 2: 3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3: ‘-‘ = Don't care - Can be set to '0' or '1' V0.2 47 2009-08-05 ST7735R 9.8.11 18-Bit Parallel Interface (IM2, IM1, IM0=“111”) Different display data formats are available for three colors depth supported by listed below. - 4k colors, RGB 4,4,4-bit input - 65k colors, RGB 5,6,5-bit input - 262k colors, RGB 6,6,6-bit input. 9.8.12 18-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH=“03h” There is 1 pixel (3 sub-pixels) per 1 byte RESX IM [2:0] “ 1” “ 111 ” C SX D /CX W RX R DX “ 1” 8080-series control pins D17 - - - - - D16 - - - - - D15 - - - - - D14 - - - - - D13 - - - - - D12 - - - - - D11 - R1, Bit 3 R2, Bit 3 R3, Bit 3 R4, Bit 3 D10 - R1, Bit 2 R2, Bit 2 R3, Bit 2 R4, Bit 2 D9 - R1, Bit 1 R2, Bit 1 R3, Bit 1 R4, Bit 1 D8 - R1, Bit 0 R2, Bit 0 R3, Bit 0 R4, Bit 0 D7 0 G1, Bit 3 G2, Bit 3 G3, Bit 3 G4, Bit 3 D6 0 G1, Bit 2 G2, Bit 2 G3, Bit 2 G4, Bit 2 D5 1 G1, Bit 1 G2, Bit 1 G3, Bit 1 G4, Bit 1 D4 0 G1, Bit 0 G2, Bit 0 G3, Bit 0 G4, Bit 0 D3 1 B1, Bit 3 B2, Bit 3 B3, Bit 3 B4, Bit 3 D2 1 B1, Bit 2 B2, Bit 2 B3, Bit 2 B4, Bit 2 D1 0 B1, Bit 1 B2, Bit 1 B3, Bit 1 B4, Bit 1 D0 0 B1, Bit 0 B2, Bit 0 B3, Bit 0 B4, Bit 0 Pixel n Pixel n+1 Pixel n+2 Pixel n+3 12 bits 12 bits Look-Up Table for 4096 Color data m apping (12 bits to 18 bits) 18 bits Fram e m em ory R1 G1 B1 R2 G2 B2 R3 G3 B3 Note 1: The data order is as follows, MSB=D11, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data. Note 2: 1-times transfer is used to transmit 1 pixel data with the 12-bit color depth information. V0.2 48 2009-08-05 ST7735R 9.8.13 18-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH=“05h” There is 1 pixel (3 sub-pixels) per 1 byte RESX “1” ” “111” ” IM[2:0] CSX D/CX WRX RDX “1” ” 8080-series control pins D17 - - - - - D16 - - - - - D15 - R1, Bit 4 R2, Bit 4 R3, Bit 4 R4, Bit 4 D14 - R1, Bit 3 R2, Bit 3 R3, Bit 3 R4, Bit 3 D13 - R1, Bit 2 R2, Bit 2 R3, Bit 2 R4, Bit 2 D12 - R1, Bit 1 R2, Bit 1 R3, Bit 1 R4, Bit 1 D11 - R1, Bit 0 R2, Bit 0 R3, Bit 0 R4, Bit 0 D10 - G1, Bit 5 G2, Bit 5 G3, Bit 5 G4, Bit 5 D9 - G1, Bit 4 G2, Bit 4 G3, Bit 4 G4, Bit 4 D8 - G1, Bit 3 G2, Bit 3 G3, Bit 3 G4, Bit 3 D7 0 G1, Bit 2 G2, Bit 2 G3, Bit 2 G4, Bit 2 D6 0 G1, Bit 1 G2, Bit 1 G3, Bit 1 G4, Bit 1 D5 1 G1, Bit 0 G2, Bit 0 G3, Bit 0 G4, Bit 0 D4 0 B1, Bit 4 B2, Bit 4 B3, Bit 4 B4, Bit 4 D3 1 B1, Bit 3 B2, Bit 3 B3, Bit 3 B4, Bit 3 D2 1 B1, Bit 2 B2, Bit 2 B3, Bit 2 B4, Bit 2 D1 0 B1, Bit 1 B2, Bit 1 B3, Bit 1 B4, Bit 1 D0 0 B1, Bit 0 B2, Bit 0 B3, Bit 0 B4, Bit 0 Pixel n Pixel n+1 Pixel n+2 Pixel n+3 16 bits 16 bits Look-up table for 65k color data mapping (16 bits to 18 bits) 18 bits Frame memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0 for Red and Blue data. Note 2: 1-time transfer is used to transmit 1 pixel data with the 16-bit color depth information. V0.2 49 2009-08-05 ST7735R 9.8.14 18-bit data bus for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH=“06h” There is 1 pixel (3 sub-pixels) per 1 byte RESX “1” ” “ 111” ” IM[2:0] CSX D/CX WRX RDX “1” ” 8080-series control pins D17 - R1, Bit 5 R2, Bit 5 R3, Bit 5 R4, Bit 5 D16 - R1, Bit 4 R2, Bit 4 R3, Bit 4 R4, Bit 4 D15 - R1, Bit 3 R2, Bit 3 R3, Bit 3 R4, Bit 3 D14 - R1, Bit 2 R2, Bit 2 R3, Bit 2 R4, Bit 2 D13 - R1, Bit 1 R2, Bit 1 R3, Bit 1 R4, Bit 1 D12 - R1, Bit 0 R2, Bit 0 R3, Bit 0 R4, Bit 0 D11 - G1, Bit 5 G2, Bit 5 G3, Bit 5 G4, Bit 5 D10 - G1, Bit 4 G2, Bit 4 G3, Bit 4 G4, Bit 4 D9 - G1, Bit 3 G2, Bit 3 G3, Bit 3 G4, Bit 3 D8 - G1, Bit 2 G2, Bit 2 G3, Bit 2 G4, Bit 2 D7 0 G1, Bit 1 G2, Bit 1 G3, Bit 1 G4, Bit 1 D6 0 G1, Bit 0 G2, Bit 0 G3, Bit 0 G4, Bit 0 D5 1 B1, Bit 5 B2, Bit 5 B3, Bit 5 B4, Bit 5 D4 0 B1, Bit 4 B2, Bit 4 B3, Bit 4 B4, Bit 4 D3 1 B1, Bit 3 B2, Bit 3 B3, Bit 3 B4, Bit 3 D2 1 B1, Bit 2 B2, Bit 2 B3, Bit 2 B4, Bit 2 D1 0 B1, Bit 1 B2, Bit 1 B3, Bit 1 B4, Bit 1 D0 0 B1, Bit 0 B2, Bit 0 B3, Bit 0 B4, Bit 0 Pixel n Pixel n+1 Pixel n+2 Pixel n+3 18 bits 18 bits Frame memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Note 1: The data order is as follows, MSB=D17, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Read, Green and Blue data. Note 2: 1-times transfer (D17o D0) is used to transmit 1 pixel data with the 18-bit color depth information. V0.2 50 2009-08-05 ST7735R 9.8.15 3-line serial Interface Different display data formats are available for three colors depth supported by the LCM listed below. 4k colors, RGB 4-4-4-bit input 65k colors, RGB 5-6-5-bit input 262k colors, RGB 6-6-6-bit input 9.8.16 Write data for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH=“03h” Note 1: Pixel data with the 12-bit color depth information Note 2: The most significant bits are: Rx3, Gx3 and Bx3 Note 3: The least significant bits are: Rx0, Gx0 and Bx0 V0.2 51 2009-08-05 ST7735R 9.8.17 Write data for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH=“05h” Note 1: Pixel data with the 16-bit color depth information Note 2: The most significant bits are: Rx4, Gx5 and Bx4 Note 3: The least significant bits are: Rx0, Gx0 and Bx0 V0.2 52 2009-08-05 ST7735R 9.8.18 Write data for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH=“06h” Note 1: Pixel data with the 18-bit color depth information Note 2: The most significant bits are: Rx5, Gx5 and Bx5 Note 3: The least significant bits are: Rx0, Gx0 and Bx0 V0.2 53 2009-08-05 ST7735R 9.8.19 4-line serial Interface Different display data formats are available for three colors depth supported by the LCM listed below. 4k colors, RGB 4-4-4-bit input 65k colors, RGB 5-6-5-bit input 262k colors, RGB 6-6-6-bit input 9.8.20 Write data for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH=“03h” Note 1. pixel data with the 12-bit color depth information Note 2. The most significant bits are: Rx3, Gx3 and Bx3 Note 3. The least significant bits are: Rx0, Gx0 and Bx0 V0.2 54 2009-08-05 ST7735R 9.8.21 Write data for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH=“05h” Note 1. pixel data with the 16-bit color depth information Note 2. The most significant bits are: Rx4, Gx5 and Bx4 Note 3. The least significant bits are: Rx0, Gx0 and Bx0 9.8.22 Write data for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH=“06h” Note 1. pixel data with the 18-bit color depth information Note 2. The most significant bits are: Rx5, Gx5 and Bx5 Note 3. The least significant bits are: Rx0, Gx0 and Bx0 V0.2 55 2009-08-05 ST7735R 9.9 Display Data RAM 9.9.1 Configuration (GM[1:0] = “00”) The display module has an integrated 132x162x18-bit graphic type static RAM. This 384,912-bit memory allows storing on-chip a 132xRGBx162 image with an 18-bpp resolution (262K-color). There will be no abnormal visible effect on the display when there is a simultaneous Panel Read and Interface Read or Write to the same location of the Frame Memory. Figure 9.9.1Display data RAM organization V0.2 56 2009-08-05 ST7735R 9.9.2 Memory to Display Address Mapping 9.9.3 When using 128RGB x 160 resolution (GM[1:0] = “11”, SMX=SMY=SRGB= ‘0’) 2 3 4 5 6 7 8 9 | | | | | 154 155 156 157 158 159 160 161 S12 -------- S385 S386 S387 S388 S389 S390 G0 B0 R1 G1 B1 | | | | | | | | | | | | | | | | | | | | | | | | | 0 127 1 126 RGB Order RGB=1 S11 RGB=0 S10 Pixel 128 RGB=1 RA MY=' 0 ' MY=' 1 ' 0 159 R0 1 158 2 157 3 156 4 155 5 154 6 153 7 152 | | | | | | | | | | | | | | | 152 7 153 6 154 5 155 4 156 3 157 2 158 1 159 0 MX=' 0 ' CA MX=' 1 ' S9 RGB=0 S8 RGB=0 S7 Pixel 127 -------- RGB=1 Source Out RGB=0 Gate Out Pixel 2 RGB=1 Pixel 1 SA ML=' 0 ' ML=' 1 ' -------- R126 G126 B126 R127 G127 B127 0 159 -------1 158 -------2 157 -------3 156 -------4 155 -------5 154 -------6 153 -------7 152 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -------152 7 -------153 6 -------154 5 -------155 4 -------156 3 -------157 2 -------158 1 -------159 0 126 127 -------1 0 -------- Note RA = Row Address, CA = Column Address SA = Scan Address MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command MY = Mirror Y-axis (Row address direction parameter), D7 parameter of MADCTL command ML = Scan direction parameter, D4 parameter of MADCTL command RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command V0.2 57 2009-08-05 ST7735R When using 132RGB x 162 resolution (GM[1:0] = “00”, SMX=SMY=SRGB= ‘0’) 1 2 3 4 5 6 7 8 | | | | | 155 156 157 158 159 160 161 162 S5 S6 -------- S391 S392 S393 S394 S395 S396 RGB Order G0 B0 R1 G1 B1 | | | | | | | | | | | | | | | | | | | | | | | | | 0 131 1 130 RGB=1 S4 RGB=0 RA MY=' 0 ' MY=' 1 ' 0 161 R0 1 160 2 159 3 158 4 157 5 156 6 155 7 154 | | | | | | | | | | | | | | | 154 7 155 6 156 5 157 4 158 3 159 2 160 1 161 0 MX=' 0 ' CA MX=' 1 ' S3 Pixel 132 RGB=1 S2 RGB=0 S1 Pixel 131 -------- RGB=1 Source Out RGB=0 Gate Out Pixel 2 RGB=0 Pixel 1 RGB=1 9.9.4 SA ML=' 0 ' ML=' 1 ' -------- R131 G131 B131 R132 G132 B132 0 161 -------1 160 -------2 159 -------3 158 -------4 157 -------5 156 -------6 155 -------7 154 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -------154 7 -------155 6 -------156 5 -------157 4 -------158 3 -------159 2 -------160 1 -------161 0 130 131 -------1 0 -------- Note RA = Row Address, CA = Column Address SA = Scan Address MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command MY = Mirror Y-axis (Row address direction parameter), D7 parameter of MADCTL command ML = Scan direction parameter, D4 parameter of MADCTL command RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command V0.2 58 2009-08-05 ST7735R 9.9.5 Normal Display On or Partial Mode On 9.9.6 When using 128RGB x 160 resolution (GM[1:0] = “11”) In this mode, the content of the frame memory within an area where column pointer is 00h to 7Fh and page pointer is 00h to 9Fh is displayed. To display a dot on leftmost top corner, store the dot data at (column pointer, row pointer) = (0, 0). 1). Example for Normal Display On (MX=MY=ML=’0’, SMX=SMY=’0’) Scan Order 128 Columns 00h 00 10 20 30 40 50 60 01h ---- ---- 76h 77h ---- 7Fh 83h 01 0Y 0Z 11 1Y 1Z 21 2Y 2Z 31 3Y 3Z 41 4Y 4Z 51 5Y 5Z 6Z 128 x 160 x18bit Fram e RAM X0 X1 X2 XX XY XZ Y0 Y1 Y2 Y3 YW YX YY YZ Z0 Z1 Z2 Z3 ZW ZX ZY ZZ 1 2 3 | | | | | | | | | | 158 159 160 00 10 20 30 40 50 60 01 11 21 31 41 51 02 12 22 32 42 03 13 0W 0X 0Y 1W 1X 1Y 2X 2Y 3X 3Y 4X 4Y 5Y 0Z 1Z 2Z 3Z 4Z 5Z 6Z 128RGB x 160 LCD Panel S0 U0 V0 W0 X0 Y0 Z0 U1 V1 W1 X1 Y1 Z1 V2 W2 X2 Y2 Y3 Z2 Z3 VX WX XX YW YX ZW ZX UY VY WY XY YY ZY SZ UZ VZ WZ XZ YZ ZZ G2 G3 G4 | | | | | | | | | | | | G159 G160 G161 Display area =160 lines 160 Lines 00h 01h 02h | | | | | | | | | | | 9Eh 9Fh A0h A1h 128 Columns 2). Example for Partial Display On (PSL[7:0]=04h,PEL[7:0]=9Bh, MX=MV=ML=’0’ ,SMX=SMY=’0’) Scan Order 128 Columns 160 Lines V0.2 00h 01h 02h | | | | | | | | | | | 9Eh 9Fh A0h A1h 00h 00 10 20 30 40 50 60 01h ---- ---- 76h 77h ---- 7Fh 83h 01 0Y 0Z 11 1Y 1Z 21 2Y 2Z 31 3Y 3Z 41 4Y 4Z 51 5Y 5Z 6Z U0 V0 W0 X0 Y0 Z0 128 x 160 x18bit Fram e RAM U1 V1 VX W1 W2 WX X1 X2 XX Y1 Y2 Y3 YW YX Z1 Z2 Z3 ZW ZX UY VY WY XY YY ZY UZ VZ WZ XZ YZ ZZ 128 Columns 00 10 20 30 40 50 60 1 2 3 | | | | | | | | | | 158 159 160 01 11 21 31 41 51 02 12 22 32 42 03 13 0W 0X 0Y 1W 1X 1Y 2X 2Y 3X 3Y 4X 4Y 5Y 0Z 1Z 2Z 3Z 4Z 5Z 6Z 128RGB x 160 LCD Panel S0 U0 V0 W0 X0 Y0 Z0 59 U1 V1 W1 X1 Y1 Z1 V2 W2 X2 Y2 Y3 Z2 Z3 VX WX XX YW YX ZW ZX UY VY WY XY YY ZY SZ UZ VZ WZ XZ YZ ZZ G2 G3 G4 | | | | | | | | | | | | G159 G160 G161 Non-Display area =4 lines Display area =152 lines Non-Display area =4 lines 2009-08-05 ST7735R 9.9.7 When using 132RGB x 162 resolution (GM[1:0] = “00”) In this mode, contents of the frame memory within an area where column pointer is 00h to 83h and page pointer is 00h to A1h is displayed. To display a dot on leftmost top corner, store the dot data at (column pointer, row pointer) = (0, 0) 1). Example for Normal Display On (MX=MY=ML=’0’, SMX=SMY=’0’) Scan Order 132 Columns 162 Lines 00h 01h 02h | | | | | | | | | | 9Dh 9Eh 9Fh A0h A1h 00h 00 10 20 30 40 50 60 01h 01 11 21 31 41 51 ---- ---- ---- ---- ---- 81h 02 03 0W 0X 0Y 12 13 1W 1X 1Y 22 2X 2Y 32 3X 3Y 42 4X 4Y 5Y 83h 0Z 1Z 2Z 3Z 4Z 5Z 6Z 132 x 162 x18 bit Fram e RAM S0 U0 V0 W0 X0 Y0 Z0 U1 V1 W1 X1 Y1 Z1 V2 W2 X2 Y2 Y3 Z2 Z3 VX WX XX YW YX ZW ZX UY VY WY XY YY ZY SZ UZ VZ WZ XZ YZ ZZ 1 2 3 | | | | | | | | | | | | 160 161 162 132 Columns 00 10 20 30 40 50 60 01 11 21 31 41 51 02 12 22 32 42 03 13 0W 0X 0Y 1W 1X 1Y 2X 2Y 3X 3Y 4X 4Y 5Y 0Z 1Z 2Z 3Z 4Z 5Z 6Z 132RGB x 162 LCD Panel S0 U0 V0 W0 X0 Y0 Z0 U1 V1 W1 X1 Y1 Z1 V2 W2 X2 Y2 Y3 Z2 Z3 VX WX XX YW YX ZW ZX UY VY WY XY YY ZY SZ UZ VZ WZ XZ YZ ZZ G1 G2 G3 | | | | | | | | | | | | G160 G161 G162 Non-Displa y area =4 lines Display area =155 lines Non-Displa y area =4lines 2). Example for Partial Display On (PSL[7:0]=04h,PEL[7:0]=9Dh, MX=MV=ML=’0’ ,SMX=SMY=’0’) Scan Order 132 Columns 00h 00 10 20 30 40 50 60 01h 01 11 21 31 41 51 ---- ---- ---- ---- ---- 81h 02 03 0W 0X 0Y 12 13 1W 1X 1Y 22 2X 2Y 32 3X 3Y 42 4X 4Y 5Y 83h 0Z 1Z 2Z 3Z 4Z 5Z 6Z 132 x 162 x18 bit Fram e RAM S0 U0 V0 W0 X0 Y0 Z0 U1 V1 W1 X1 Y1 Z1 V2 W2 X2 Y2 Y3 Z2 Z3 VX WX XX YW YX ZW ZX UY VY WY XY YY ZY SZ UZ VZ WZ XZ YZ ZZ 00 10 20 30 40 50 60 1 2 3 | | | | | | | | | | | | 160 161 162 01 11 21 31 41 51 02 03 12 13 22 32 42 0W 0X 0Y 1W 1X 1Y 2X 2Y 3X 3Y 4X 4Y 5Y 0Z 1Z 2Z 3Z 4Z 5Z 6Z 132R G B x 162 LCD Panel S0 U0 V0 W0 X0 Y0 Z0 60 U1 V1 W1 X1 Y1 Z1 V2 W2 X2 Y2 Y3 Z2 Z3 VX WX XX YW YX ZW ZX UY VY WY XY YY ZY SZ UZ VZ WZ XZ YZ ZZ G1 G2 G3 | | | | | | | | | | | | G160 G161 G162 Display area =162 lines 162 Lines V0.2 00h 01h 02h | | | | | | | | | | | | 9Fh A0h A1h 132 Columns 2009-08-05 ST7735R 9.10 Address Counter The address counter sets the addresses of the display data RAM for writing and reading. Data is written pixel-wise into the RAM matrix of DRIVER. The data for one pixel or two pixels is collected (RGB 6-6-6-bit), according to the data formats. As soon as this pixel-data information is complete the “Write access” is activated on the RAM. The locations of RAM are addressed by the address pointers. The address ranges are X=0 to X=131 (83h) and Y=0 to Y=161 (A1h). Addresses outside these ranges are not allowed. Before writing to the RAM, a window must be defined that will be written. The window is programmable via the command registers XS, YS designating the start address and XE, YE designating the end address. For example the whole display contents will be written, the window is defined by the following values: XS=0 (0h) YS=0 (0h) and XE=127 (83h), YE=161 (A1h). In vertical addressing mode (MV=1), the Y-address increments after each byte, after the last Y-address (Y=YE), Y wraps around to YS and X increments to address the next column. In horizontal addressing mode (V=0), the X-address increments after each byte, after the last X-address (X=XE), X wraps around to XS and Y increments to address the next row. After the every last address (X=XE and Y=YE) the address pointers wrap around to address (X=XS and Y=YS). For flexibility in handling a wide variety of display architectures, the commands “CASET, RASET and MADCTL” (see section 10 command list), define flags MX and MY, which allows mirroring of the X-address and Y-address. All combinations of flags are allowed. Section 9.10 show the available combinations of writing to the display RAM. When MX, MY and MV will be changed the data bust be rewritten to the display RAM. For each image condition, the controls for the column and row counters apply as section 9.11 below Condition Column Counter Row Counter When RAMWR/RAMRD command is accepted Return to “Start Column (XS)” Return to “Start Row (YS)” Complete Pixel Read / Write action Increment by 1 No change The Column counter value is larger than “End Column (XE)” Return to “Start Column (XS)” Increment by 1 The Column counter value is larger than “End Column (XE)” and the Row counter value is larger than “End Row (YE)” Return to “Start Column (XS)” Return to “Start Row (YS)” V0.2 61 2009-08-05 ST7735R 9.11 Memory Data Write/ Read Direction The data is written in the order illustrated above. The Counter which dictates where in the physical memory the data is to be written is controlled by “Memory Data Access Control” Command, bits B5 (MV), B6 (MX), B7 (MY) as described below. Panel Figure 9.11.1Data streaming order 9.11.1 When 128RGBx160 (GM= “11”) MV MX MY CASET RASET 0 0 0 Direct to Physical Column Pointer Direct to Physical Row Pointer 0 0 1 Direct to Physical Column Pointer Direct to (159-Physical Row Pointer) 0 1 0 Direct to (127-Physical Column Pointer) Direct to Physical Row Pointer 0 1 1 Direct to (127-Physical Column Pointer) Direct to (159-Physical Row Pointer) 1 0 0 Direct to Physical Row Pointer Direct to Physical Column Pointer 1 0 1 Direct to (159-Physical Row Pointer) Direct to Physical Column Pointer 1 1 0 Direct to Physical Row Pointer Direct to (127-Physical Column Pointer) 1 1 1 Direct to (159-Physical Row Pointer) Direct to (127-Physical Column Pointer) 9.11.2 When 132RGBx162 (GM= “00”) MV MX MY CASET RASET 0 0 0 Direct to Physical Column Pointer Direct to Physical Row Pointer 0 0 1 Direct to Physical Column Pointer Direct to (161-Physical Row Pointer) 0 1 0 Direct to (131-Physical Column Pointer) Direct to Physical Row Pointer 0 1 1 Direct to (131-Physical Column Pointer) Direct to (161-Physical Row Pointer) 1 0 0 Direct to Physical Row Pointer Direct to Physical Column Pointer 1 0 1 Direct to (161-Physical Row Pointer) Direct to Physical Column Pointer 1 1 0 Direct to Physical Row Pointer Direct to (131-Physical Column Pointer) 1 1 1 Direct to (161-Physical Row Pointer) Direct to (131-Physical Column Pointer) Note: Data is always written to the Frame Memory in the same order, regardless of the Memory Write Direction set by MADCTL bits B7 (MY), B6 (MX), B5 (MV). The write order for each pixel unit is One pixel unit represents 1 column and 1page counter value on the Frame Memory. V0.2 62 2009-08-05 ST7735R 9.11.3 Frame Data Write Direction According to the MADCTL parameters (MV, MX and MY) Display Data Direction MADCTL Parameter MV MX MY Normal 0 0 0 Y-Mirror 0 0 1 X-Mirror 0 1 0 X-Mirror Y-Mirror 0 1 1 X-Y Exchange 1 0 0 X-Y Exchange Y-Mirror 1 0 1 X-Y Exchange X-Mirror 1 1 0 X-Y Exchange X-Mirror Y-Mirror 1 1 1 V0.2 Image in the Host (MPU) Image in the Driver (DDRAM) 63 2009-08-05 ST7735R 9.12 Tearing Effect Output Line The Tearing Effect output line supplies to the MPU a Panel synchronization signal. This signal can be enabled or disabled by the Tearing Effect Line Off & On commands. The mode of the Tearing Effect signal is defined by the parameter of the Tearing Effect Line On command. The signal can be used by the MPU to synchronize Frame Memory Writing when displaying video images. 9.12.1 Tearing Effect Line Modes Mode 1, the Tearing Effect Output signal consists of V-Blanking Information only: tvdh= The LCD display is not updated from the Frame Memory tvdl= The LCD display is updated from the Frame Memory (except Invisible Line – see above) Mode 2, the Tearing Effect Output signal consists of V-Blanking and H-Blanking Information, there is one V-sync and 162 H-sync pulses per field. thdh= The LCD display is not updated from the Frame Memory thdl= The LCD display is updated from the Frame Memory (except Invisible Line – see above) Note: During Sleep In Mode, the Tearing Output Pin is active Low. V0.2 64 2009-08-05 ST7735R 9.12.2 Tearing Effect Line Timings The Tearing Effect signal is described below: Symbol Parameter min max unit tvdl Vertical Timing Low Duration 13 - ms tvdh Vertical Timing High Duration 1000 - µs thdl Horizontal Timing Low Duration 33 - µs thdh Horizontal Timing Low Duration 25 500 µs description Table 9.12.1 AC characteristics of Tearing Effect Signal Idle Mode Off (Frame Rate = 60 Hz, Ta=25°C) Note: The timings in Table 9.10.1 apply when MADCTL ML=0 and ML=1 The signal’s rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns. The Tearing Effect Output Line is fed back to the MPU and should be used as shown below to avoid Tearing Effect: V0.2 65 2009-08-05 ST7735R 9.12.3 Example 1: MPU Write is faster than panel read Data write to Frame Memory is now synchronized to the Panel Scan. It should be written during the vertical sync pulse of the Tearing Effect Output Line. This ensures that data is always written ahead of the panel scan and each Panel Frame refresh has a complete new image: V0.2 66 2009-08-05 ST7735R 9.12.4 Example 2: MPU write is slower than panel read The MPU to Frame Memory write begins just after Panel Read has commenced i.e. after one horizontal sync pulse of the Tearing Effect Output Line. This allows time for the image to download behind the Panel Read pointer and finishing download during the subsequent Frame before the Read Pointer “catches” the MPU to Frame memory write position. B V0.2 67 2009-08-05 ST7735R 9.13 Power ON/OFF Sequence VDD must be powered on before the VDDI. VDDI must be powered off before the VDD. During power off, if LCD is in the Sleep Out mode, VDD and VDDI must be powered down minimum 120msec after RESX has been released. During power off, if LCD is in the Sleep In mode, VDDI or VDD can be powered down minimum 0msec after RESX has been released. CSX can be applied at any timing or can be permanently grounded. RESX has priority over CSX. Note 1: There will be no damage to the display module if the power sequences are not met. Note 2: There will be no abnormal visible effects on the display panel during the Power On/Off Sequences. Note 3: There will be no abnormal visible effects on the display between end of Power On Sequence and before receiving Sleep Out command. Also between receiving Sleep In command and Power Off Sequence. Note 4: If RESX line is not held stable by host during Power On Sequence as defined in the sequence below, then it will be necessary to apply a Hardware Reset (RESX) after Host Power On Sequence is complete to ensure correct operation. Otherwise function is not guaranteed. The power on/off sequence is illustrated below TrPW 0ns TfPW 0ns VDD VDDI Timing when the latter signal rises up to 90% of its typical value. e.g. When VDD comes later, this timing is defined at the cross point of 90% of 2.75V, not 90% of 2.6V. Timing when the latter signal falls up to 90% of its typical value. e.g. When VDD comes later, this timing is defined at the cross point of 90% of 2.75V, not 90% of 2.6V. TfPW-CSX = +/- no limit TrPW-CSX = +/- no limit CSX H or L TrPW-RESX = + no limit RESX (Power down in sleep-out mode) TfPW-RESX1 = min 120ms 30% TrPW-RESX = + no limit RESX (Power down in sleep-in mode) TfPW-RESX2 = min 0ms 30% TfPW-RESx1 is applied to RESX falling in the Sleep Out Mode. TfPW-RESx2 is applied to RESX falling in the Sleep In Mode. 9.13.1 Uncontrolled Power Off The uncontrolled power-off means a situation which removed a battery without the controlled power off sequence. It will neither damage the module or the host interface. If uncontrolled power-off happened, the display will go blank and there will not any visible effect on the display (blank display) and remains blank until “Power On Sequence” powers it up. V0.2 68 2009-08-05 ST7735R 9.14 Power Level Definition 9.14.1 Power Level 6 level modes are defined they are in order of Maximum Power consumption to Minimum Power Consumption 1. Normal Mode On (full display), Idle Mode Off, Sleep Out. In this mode, the display is able to show maximum 262,144 colors. 2. Partial Mode On, Idle Mode Off, Sleep Out. In this mode part of the display is used with maximum 262,144 colors. 3. Normal Mode On (full display), Idle Mode On, Sleep Out. In this mode, the full display area is used but with 8 colors. 4. Partial Mode On, Idle Mode On, Sleep Out. In this mode, part of the display is used but with 8 colors. 5. Sleep In Mode In this mode, the DC: DC converter, internal oscillator and panel driver circuit are stopped. Only the MCU interface and memory works with VDDI power supply. Contents of the memory are safe. 6. Power Off Mode In this mode, both VDD and VDDI are removed. Note: Transition between modes 1-5 is controllable by MCU commands. Mode 6 is entered only when both Power supplies are removed. V0.2 69 2009-08-05 ST7735R 9.14.2 Power Flow Chart Normal display mode on = NOR ON Partial display mode on = PTL ON Idle mode off = IDM OFF Idle mode on = IDM ON Sleep out = SLP OUT Sleep in = SLP IN NOR ON PTL ON Sleep out Normal display mode on Idle mode off IDM ON Power on sequence HW reset SW reset SLP IN SLP OUT Sleep in Normal display mode on Idle mode off Sleep out Normal display mode on Idle mode on Sleep out Partial display mode on Idle mode off PTL ON NOR ON V0.2 PTL ON IDM OFF IDM ON IDM ON NOR ON SLP IN SLP OUT SLP IN SLP OUT IDM OFF Sleep out Partial display mode on Idle mode on Sleep in Normal display mode on Idle mode on Sleep in Partial display mode on Idle mode off IDM ON SLP IN SLP OUT 70 IDM OFF IDM OFF Sleep in Partial display mode on Idle mode on PTL ON NOR ON 2009-08-05 ST7735R 9.15 Reset Table 9.15.1 Reset Table (Default Value, GM[1:0]=“11”, 128RGB x 160) Item After Power On After H/W Reset After S/W Reset Frame memory Random No Change No Change Sleep In/Out In In In Display On/Off Off Off Off Display mode (normal/partial) Normal Normal Normal Display Inversion On/Off Off Off Off Display Idle Mode On/Off Off Off Off Column: Start Address (XS) 0000h 0000h 0000h Column: End Address (XE) 007Fh 007Fh 007Fh (127d) (when MV=0) 009Fh (159d) (when MV=1) Row: Start Address (YS) 0000h 0000h 0000h 009Fh 009Fh (159d) (when MV=0) 007Fh (127d) (when MV=1) Row: End Address (YE) 009Fh Gamma setting GC0 GC0 GC0 RGB for 4k and 65k Color Mode Random values Random values No Change Partial: Start Address (PSL) 0000h 0000h 0000h Partial: End Address (PEL) 009Fh 009Fh 009Fh Tearing: On/Off Off Off Off Tearing Effect Mode (*1) 0 (Mode1) 0 (Mode1) 0 (Mode1) Memory Data Access Control (MY/MX/MV/ML/RGB) 0/0/0/0/0 0/0/0/0/0 No Change Interface Pixel Color Format 6 (18-Bit/Pixel) 6 (18-Bit/Pixel) No Change RDDPM 08h 08h 08h RDDMADCTL 00h 00h No Change RDDCOLMOD 6 (18-Bit/Pixel) 6 (18-Bit/Pixel) No Change 00h RDDIM 00h 00h RDDSM 00h 00h 00h ID2 NV value NV value NV value ID3 NV value NV value NV value Note: TE Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only V0.2 71 2009-08-05 ST7735R 9.15.2 Reset Table (GM[1:0]= “00”, 132RGB x 162) Item After Power On After H/W Reset After S/W Reset Frame memory Random No Change No Change Sleep In/Out In In In Display On/Off Off Off Off Display mode (normal/partial) Normal Normal Normal Display Inversion On/Off Off Off Off Display Idle Mode On/Off Off Off Off Column: Start Address (XS) 0000h 0000h 0000h 0083h (131d) (when MV=0) 00A1h (161d) (when MV=1) Column: End Address (XE) 0083h 0083h Row: Start Address (YS) 0000h 0000h 0000h 00A1h 00A1h (161d) (when MV=0) 0083h (131d) (when MV=1) Row: End Address (YE) 00A1h Gamma setting GC0 GC0 GC0 RGB for 4k and 65k Color Mode Random values Random values No Change Partial: Start Address (PSL) 0000h 0000h 0000h Partial: End Address (PEL) 00A1h 00A1h 00A1h Tearing: On/Off Off Off Off Tearing Effect Mode (*1) 0 (Mode1) 0 (Mode1) 0 (Mode1) Memory Data Access Control (MY/MX/MV/ML/RGB) 0/0/0/0/0 0/0/0/0/0 No Change Interface Pixel Color Format 6 (18-Bit/Pixel) 6 (18-Bit/Pixel) No Change RDDPM 08h 08h 08h RDDMADCTL 00h 00h No Change RDDCOLMOD 6 (18-Bit/Pixel) 6 (18-Bit/Pixel) No Change RDDIM 00h 00h 00h RDDSM 00h 00h 00h ID2 NV value NV value NV value ID3 NV value NV value NV value Note: TE Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only V0.2 72 2009-08-05 ST7735R 9.16 Module Input/Output Pins 9.16.1 Output or Bi-directional (I/O) Pins Output or Bi-directional pins TE D7 to D0 (Output driver) Input pins RESX CSX D/CX WRX RDX D7 to D0 During Power On Process See 9.14 Input invalid Input invalid Input invalid Input invalid Input invalid After Power On Low High-Z (Inactive) After Power On Input valid Input valid Input valid Input valid Input valid Input valid After Hardware Reset Low High-Z (Inactive) After Hardware Reset Input valid Input valid Input valid Input valid Input valid Input valid After Software Reset Low High-Z (Inactive) After Software Reset Input valid Input valid Input valid Input valid Input valid Input valid During Power Off Process See 9.14 Input invalid Input invalid Input invalid Input invalid Input invalid Note: There will be no output from D7-D0 during Power On/Off sequence, Hardware Reset and Software Reset. V0.2 73 2009-08-05 ST7735R 9.17 Reset Timing Related Pins RESX Symbol tRESW Parameter Reset pulse duration tREST Reset cancel MIN 10 - MAX 5 120 Unit us ms ms Table 9.17.1 Reset timing Notes: 1. The reset cancel includes also required time for loading ID bytes, VCOM setting and other settings from NVM (or similar device) to registers. This loading is done every time when there is HW reset cancel time (tRT) within 5 ms after a rising edge of RESX. 2. Spike due to an electrostatic discharge on RESX line does not cause irregular system reset according to the table below: RESX Pulse Shorter than 5us Longer than 9us Between 5us and 9us Action Reset Rejected Reset Reset starts 3. During the Resetting period, the display will be blanked (The display is entering blanking sequence, which maximum time is 120 ms, when Reset Starts in Sleep Out –mode. The display remains the blank state in Sleep In -mode.) and then return to Default condition for Hardware Reset. 4. Spike Rejection also applies during a valid reset pulse as shown below: 5. When Reset applied during Sleep In Mode. 6. When Reset applied during Sleep Out Mode. 7. It is necessary to wait 5msec after releasing RESX before sending commands. Also Sleep Out command cannot be sent for 120msec. V0.2 74 2009-08-05 ST7735R 9.18 Color Depth Conversion Look Up Tables 9.18.1 65536 Color to 262,144 Color Color Look Up Table Output Frame Memory Data (6-bits) RGBSET Parameter RED R005 R004 R003 R002 R001 R000 R015 R014 R013 R012 R011 R010 R025 R024 R023 R022 R021 R020 R035 R034 R033 R032 R031 R030 R045 R044 R043 R042 R041 R040 R055 R054 R053 R052 R051 R050 R065 R064 R063 R062 R061 R060 R075 R074 R073 R072 R071 R070 R085 R084 R083 R082 R081 R080 R095 R094 R093 R092 R091 R090 R105 R104 R103 R102 R101 R100 R115 R114 R113 R112 R111 R110 R125 R124 R123 R122 R121 R120 R135 R134 R133 R132 R131 R130 R145 R144 R143 R142 R141 R140 R155 R154 R153 R152 R151 R150 R165 R164 R163 R162 R161 R160 R175 R174 R173 R172 R171 R170 R185 R184 R183 R182 R181 R180 R195 R194 R193 R192 R191 R190 R205 R204 R203 R202 R201 R200 R215 R214 R213 R212 R211 R210 R225 R224 R223 R222 R221 R220 R235 R234 R233 R232 R231 R230 R245 R244 R243 R242 R241 R240 R255 R254 R253 R252 R251 R250 R265 R264 R263 R262 R261 R260 R275 R274 R273 R272 R271 R270 R285 R284 R283 R282 R281 R280 R295 R294 R293 R292 R291 R290 R305 R304 R303 R302 R301 R300 R315 R314 R313 R312 R311 R310 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Color Look Up Table Output Frame Memory Data (6-bits) RGBSET Parameter G005 G004 G003 G002 G001 G000 G015 G014 G013 G012 G011 G010 G025 G024 G023 G022 G021 G020 G035 G034 G033 G032 G031 G030 G045 G044 G043 G042 G041 G040 G055 G054 G053 G052 G051 G050 G065 G064 G063 G062 G061 G060 G075 G074 G073 G072 G071 G070 G085 G084 G083 G082 G081 G080 G095 G094 G093 G092 G091 G090 G105 G104 G103 G102 G101 G100 G115 G114 G113 G112 G111 G110 G125 G124 G123 G122 G121 G120 G135 G134 G133 G132 G131 G130 G145 G144 G143 G142 G141 G140 G155 G154 G153 G152 G151 G150 G165 G164 G163 G162 G161 G160 G175 G174 G173 G172 G171 G170 G185 G184 G183 G182 G181 G180 G195 G194 G193 G192 G191 G190 G205 G204 G203 G202 G201 G200 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 GREEN V0.2 75 Look Up Table Input Data 65k Color (5-bits) 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Look Up Table Input Data 65k Color (5-bits) 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 2009-08-05 ST7735R Color BLUE V0.2 G215 G214 G213 G212 G211 G210 G225 G224 G223 G222 G221 G220 G235 G234 G233 G232 G231 G230 G245 G244 G243 G242 G241 G240 G255 G254 G253 G252 G251 G250 G265 G264 G263 G262 G261 G260 G275 G 274 G273 G272 G271 G270 G285 G 284 G283 G282 G281 G280 G295 G 294 G293 G292 G291 G290 G305 G 304 G303 G302 G301 G300 G315 G 314 G313 G312 G311 G310 G325 G324 G323 G322 G321 G320 G335 G334 G333 G332 G331 G330 G345 G344 G343 G342 G341 G340 G355 G354 G353 G352 G351 G350 G365 G364 G363 G362 G361 G360 G375 G374 G373 G372 G371 G370 G385 G384 G383 G382 G381 G380 G395 G394 G393 G392 G391 G390 G405 G404 G403 G402 G401 G400 G415 G414 G413 G412 G411 G410 G425 G424 G423 G422 G421 G420 G435 G434 G433 G432 G431 G430 G445 G444 G443 G442 G441 G440 G455 G454 G453 G452 G451 G450 G465 G464 G463 G462 G461 G460 G475 G474 G473 G472 G471 G470 G485 G484 G483 G482 G481 G480 G495 G494 G493 G492 G491 G490 G505 G504 G503 G502 G501 G500 G515 G514 G513 G512 G511 G510 G525 G524 G523 G522 G521 G520 G535 G534 G533 G532 G531 G530 G545 G544 G543 G542 G541 G540 G555 G554 G553 G552 G551 G550 G565 G564 G563 G562 G561 G560 G575 G574 G573 G572 G571 G570 G585 G584 G583 G582 G581 G580 G595 G594 G593 G592 G591 G590 G605 G604 G603 G602 G601 G600 G615 G614 G613 G612 G611 G610 G625 G624 G623 G622 G621 G620 G635 G634 G633 G632 G631 G630 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 Look Up Table Output Frame Memory Data (6-bits) RGBSET Parameter B005 B004 B003 B002 B001 B000 B015 B014 B013 B012 B011 B010 B025 B024 B023 B022 B021 B020 B035 B034 B033 B032 B031 B030 B045 B044 B043 B042 B041 B040 B055 B054 B053 B052 B051 B050 B065 B064 B063 B062 B061 B060 B075 B074 B073 B072 B071 B070 B085 B084 B083 B082 B081 B080 B095 B094 B093 B092 B091 B090 B105 B104 B103 B102 B101 B100 B115 B114 B113 B112 B111 B110 B125 B124 B123 B122 B121 B120 B135 B134 B133 B132 B131 B130 B145 B144 B143 B142 B141 B140 B155 B154 B153 B152 B151 B150 B165 B164 B163 B162 B161 B160 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 Look Up Table Input Data 65k Color (5-bits) 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 76 2009-08-05 ST7735R B175 B174 B173 B172 B171 B170 B185 B184 B183 B182 B181 B180 B195 B194 B193 B192 B191 B190 B205 B204 B203 B202 B201 B200 B215 B214 B213 B212 B211 B210 B225 B224 B223 B222 B221 B220 B235 B234 B233 B232 B231 B230 B245 B244 B243 B242 B241 B240 B255 B254 B253 B252 B251 B250 B265 B264 B263 B262 B261 B260 B275 B274 B273 B272 B271 B270 B285 B284 B283 B282 B281 B280 B295 B294 B293 B292 B291 B290 B305 B304 B303 B302 B301 B300 B315 B314 B313 B312 B311 B310 V0.2 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 77 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 2009-08-05 ST7735R 9.18.2 4096 Color to 262,144 Color Color RED GREEN BLUE V0.2 Look Up Table Output Frame Memory Data (6-bits) RGBSET Parameter R005 R004 R003 R002 R001 R000 R015 R014 R013 R012 R011 R010 R025 R024 R023 R022 R021 R020 R035 R034 R033 R032 R031 R030 R045 R044 R043 R042 R041 R040 R055 R054 R053 R052 R051 R050 R065 R064 R063 R062 R061 R060 R075 R074 R073 R072 R071 R070 R085 R084 R083 R082 R081 R080 R095 R094 R093 R092 R091 R090 R105 R104 R103 R102 R101 R100 R115 R114 R113 R112 R111 R110 R125 R124 R123 R122 R121 R120 R135 R134 R133 R132 R131 R130 R145 R144 R143 R142 R141 R140 R155 R154 R153 R152 R151 R150 R165 R164 R163 R162 R161 R160 | R315 R314 R313 R312 R311 R310 G005 G004 G003 G002 G001 G000 G015 G014 G013 G012 G011 G010 G025 G024 G023 G022 G021 G020 G035 G034 G033 G032 G031 G030 G045 G044 G043 G042 G041 G040 G055 G054 G053 G052 G051 G050 G065 G064 G063 G062 G061 G060 G075 G074 G073 G072 G071 G070 G085 G084 G083 G082 G081 G080 G095 G094 G093 G092 G091 G090 G105 G104 G103 G102 G101 G100 G115 G114 G113 G112 G111 G110 G125 G124 G123 G122 G121 G120 G135 G134 G133 G132 G131 G130 G145 G144 G143 G142 G141 G140 G155 G154 G153 G152 G151 G150 G165 G164 G163 G162 G161 G160 | G635 G634 G633 G632 G631 G630 B005 B004 B003 B002 B001 B000 B015 B014 B013 B012 B011 B010 B025 B024 B023 B022 B021 B020 B035 B034 B033 B032 B031 B030 B045 B044 B043 B042 B041 B040 B055 B054 B053 B052 B051 B050 B065 B064 B063 B062 B061 B060 B075 B074 B073 B072 B071 B070 B085 B084 B083 B082 B081 B080 B095 B094 B093 B092 B091 B090 B105 B104 B103 B102 B101 B100 B115 B114 B113 B112 B111 B110 B125 B124 B123 B122 B121 B120 B135 B134 B133 B132 B131 B130 B145 B144 B143 B142 B141 B140 B155 B154 B153 B152 B151 B150 B165 B164 B163 B162 B161 B160 | B315 B314 B313 B312 B311 B310 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 | 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 | 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 | 128 78 Look Up Table Input Data 4k Color (4-bits) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Not used 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Not used 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Not used 2009-08-05 ST7735R 10 Command 10.1 System function Command List and Description Table 10.1.1 System Function command List (1) Instruction Refer D/CX WRX RDX D17-8 NOP D7 D6 D5 D4 D3 D2 D1 D0 Function Hex 10.1.1 0 ↑ 1 - 0 0 0 0 0 0 0 0 (00h) No Operation SWRESET 10.1.2 0 ↑ 1 - 0 0 0 0 0 0 0 1 (01h) Software reset 0 ↑ 1 - 0 0 0 0 0 1 0 0 (04h) Read Display ID 1 1 ↑ - - - - - - - - - 1 1 ↑ - ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID1 read 1 1 ↑ - 1 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID2 read 1 1 ↑ - ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 0 ↑ 1 - 0 0 0 0 1 0 0 1 1 1 ↑ - - - - - - - - - 1 1 ↑ - BSTON MY MX MV ML RGB MH ST24 1 1 ↑ - ST23 IFPF2 IFPF1 1 1 ↑ - VSSON ST14 INVON 1 1 ↑ - 0 ↑ 1 - 1 1 ↑ - 1 1 ↑ - 0 ↑ 1 - 0 0 0 0 1 1 1 ↑ - - - - - 1 1 ↑ - MY MX MV 0 ↑ 1 - 0 0 1 1 ↑ - - - 1 1 ↑ - 0 0 ↑ 1 - 0 1 1 ↑ - - - - - - 1 1 ↑ - VSSON D6 INVON - - 0 ↑ 1 - 0 0 0 0 1 1 1 0 (0Eh) Read Display Signal 1 1 ↑ - - - - - - - - - Dummy read 1 1 ↑ - TEON TEM - - - - - - - RDDID 10.1.3 RDDST 10.1.4 RDDPM 10.1.5 RDD 10.1.6 MADCTL RDD 10.1.7 COLMOD RDDIM 10.1.8 RDDSM 10.1.9 GCS1 GCS0 Dummy read ID3 read (09h) Read Display Status Dummy read - IFPF0 IDMON PTLON SLOUT NORON - ST12 ST11 DISON TEON GCS2 - TEM ST4 ST3 ST2 ST1 ST0 - 1 0 (0Ah) Read Display Power Dummy read 0 0 0 0 1 0 - - - - - - - - - - 0 1 1 (0Bh) Read Display - - - - Dummy read ML RGB MH - - - 0 0 1 1 0 0 (0Ch) Read Display Pixel - - - - - - Dummy read 0 0 0 - 0 0 0 1 BSTON IDMON PTLON SLPOUT NORON DISON IFPF2 IFPF1 IFPF0 - - 1 0 1 (0Dh) Read Display Image - - - Dummy read GCS2 GCS1 GCS0 - “-“: Don’t care V0.2 79 2009-08-05 ST7735R Table 10.1.2 System Function command List (2) Instructio Refer D/C D7 D6 D5 D4 D3 D2 D1 D0 SLPIN 10.1.10 0 ↑ 1 - 0 0 0 1 0 0 0 0 (10h) Sleep in & booster off SLPOUT 10.1.11 0 ↑ 1 - 0 0 0 1 0 0 0 1 (11h) Sleep out & booster on PTLON 10.1.12 0 ↑ 1 - 0 0 0 1 0 0 1 0 (12h) Partial mode on NORON 10.1.13 0 ↑ 1 - 0 0 0 1 0 0 1 1 (13h) Partial off (Normal) INVOFF 10.1.14 0 ↑ 1 - 0 0 1 0 0 0 0 0 (20h) Display inversion off INVON 10.1.15 0 ↑ 1 - 0 0 1 0 0 0 0 1 (21h) Display inversion on 0 ↑ 1 - 0 0 1 0 0 1 1 0 (26h) Gamma curve select GAMSET 10.1.16 WR RDX D17- Function Hex 1 ↑ 1 - - - - - DISPOFF 10.1.17 0 ↑ 1 - 0 0 1 0 1 0 0 0 (28h) Display off DISPON 0 ↑ 1 - 0 0 1 0 1 0 0 1 (29h) Display on 0 ↑ 1 - 0 0 1 0 1 0 1 0 (2Ah) Column address set 1 ↑ 1 - XS15 XS14 XS13 XS12 XS11 XS10 XS9 XS8 1 ↑ 1 - XS7 XS1 XS0 1 ↑ 1 - XE15 XE14 XE13 XE12 XE11 XE10 XE9 XE8 1 ↑ 1 - XE7 XE6 XE5 XE4 XE3 XE2 XE1 XE0 0 ↑ 1 - 0 0 1 0 1 0 1 1 1 ↑ 1 - YS15 YS14 YS13 YS12 YS11 YS10 YS9 YS8 1 ↑ 1 - YS7 YS1 YS0 1 ↑ 1 - YE15 YE14 YE13 YE12 YE11 YE10 YE9 YE8 1 ↑ 1 - YE7 YE6 YE5 YE4 YE3 YE2 YE1 YE0 0 ↑ 1 - 0 0 1 0 1 1 0 0 1 ↑ 1 - D7 D6 D5 D4 D3 D2 D1 D0 0 ↑ 1 - 0 0 1 0 1 1 0 1 1 ↑ 1 - - - 1 ↑ 1 - - - : : : : : : 1 ↑ 1 - - - Ra5 Ra4 Ra3 Ra2 Ra1 Ra0 Red tone “a” 1 ↑ 1 - - - G005 G004 G003 G002 G001 G000 Green tone 0 1 ↑ 1 - - - 1 ↑ 1 - - 1 ↑ 1 - - 1 ↑ 1 - - - : : : : : : 1 ↑ 1 - - - Bc5 Bc4 Bc3 Bc2 Bc1 Bc0 0 ↑ 1 - 0 0 1 0 1 1 1 0 (2Eh) Memory read 1 1 ↑ - - - - - - - - - Dummy read 1 1 ↑ - D7 D6 D5 D4 D3 D2 D1 D0 CASET RASET RAMWR 10.1.18 10.1.19 10.1.20 10.1.21 RGBSET 10.1.22 RAMRD 10.1.23 XS6 YS6 XS5 YS5 XS4 YS4 GC3 GC2 GC1 GC0 XS3 YS3 XS2 YS2 R005 R004 R003 R002 R001 R000 : : : : : : - Gb5 Gb4 Gb3 Gb2 Gb1 Gb0 - B005 B004 B003 B002 B001 B000 - X address start: 0≦XS≦X X address end: S≦XE≦X (2Bh) Row address set Y address start: 0≦YS≦Y Y address end:S≦YE≦Y (2Ch) Memory write Write data (2Dh) LUT for 4k,65k,262k color Red tone 0 : : Green tone “b” Blue tone 0 : Blue tone “c” Read data “-“: Don’t care V0.2 80 2009-08-05 ST7735R Table 10.1.3 System Function command List (3) Instruction Refer D/CXWRXRDXD17-8 D7 PTLAR TEOFF TEON 0 ↑ 1 - 0 D6 D5 D4 D3 D2 D1 D0 0 1 1 0 0 0 0 Function Hex (30h) Partial start/end address set 1 ↑ 1 - PSL15 PSL14 PSL13PSL12 PSL11 PSL10 PSL9 PSL8 10.1.24 1 ↑ 1 - PSL7 PSL6 PSL5 PSL4 PSL3 PSL2 PSL1 PSL0 1 ↑ 1 - PEL15 PEL14 PEL13PEL12 PEL11 PEL10 PEL9 PEL8 1 ↑ 1 - PEL7 PEL6 PEL5 PEL4 PEL3 PEL2 PEL1 PEL0 10.1.25 0 ↑ 1 - 0 0 1 1 0 1 0 0 (34h) Tearing effect line off 0 ↑ 1 - 0 0 1 1 0 1 0 1 (35h) Tearing effect mode set & on 1 ↑ 1 - - - - - - - - TEM Partial start address (0,1,2, ..P) Partial end address (0,1,2, .., P) Mode1: TEM=”0” 10.1.26 Mode2: TEM=”1” 0 ↑ 1 - 0 0 1 1 0 1 1 0 1 ↑ 1 - MY MX MV ML RGB MH - - IDMOFF 10.1.28 0 ↑ 1 - 0 0 1 1 1 0 0 0 (38h) Idle mode off IDMON 10.1.29 0 ↑ 1 - 0 0 1 1 1 0 0 1 (39h) Idle mode on 0 ↑ 1 - 0 0 1 1 1 0 1 0 (3Ah) Interface pixel format MADCTL 10.1.27 COLMOD 10.1.30 RDID1 RDID2 RDID3 1 ↑ 1 - - - - - - 0 ↑ 1 - 1 1 0 1 1 0 1 0 10.1.31 1 1 ↑ - - - - - - - - - 1 1 ↑ - IFPF2 IFPF1IFPF0 ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 0 ↑ 1 - 1 1 0 1 1 0 1 1 10.1.32 1 1 ↑ - - - - - - - - - 1 1 ↑ - 1 0 ↑ 1 - 1 1 0 1 1 1 0 0 10.1.33 1 1 ↑ - - - - - - - - - 1 1 ↑ - ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 (36h) Memory data access control - Interface format (DAh) Read ID1 Dummy read Read parameter (DBh) Read ID2 Dummy read Read parameter (DCh) Read ID3 Dummy read Read parameter “-“: Don’t care Note 1: After the H/W reset by RESX pin or S/W reset by SWRESET command, each internal register becomes default state (Refer “RESET TABLE” section) Note 2: Undefined commands are treated as NOP (00 h) command. Note 3: B0 to D9 and DA to F are for factory use of driver supplier. Note 4: Commands 10h, 12h, 13h, 20h, 21h, 26h, 28h, 29h, 30h, 33h, 36h (ML parameter only), 37h, 38h and 39h are updated during V-sync when Module is in Sleep Out Mode to avoid abnormal visual effects. During Sleep In mode, these commands are updated immediately. Read status (09h), Read Display Power Mode (0Ah), Read Display MADCTL (0Bh), Read Display Pixel Format (0Ch), Read Display Image Mode (0Dh), Read Display Signal Mode (0Eh). V0.2 81 2009-08-05 ST7735R 10.1.1 NOP (00h) 00H NOP (No Operation) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX NOP 0 ↑ 1 - 0 0 0 0 0 0 0 0 (00h) Parameter No Parameter Description This command is empty command. - “-“ Don’t care V0.2 82 2009-08-05 ST7735R 10.1.2 SWRESET (01h): Software Reset 01H SWRESET (Software Reset) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX SWRESET 0 ↑ 1 - 0 0 0 0 0 0 0 1 (01h) Parameter No Parameter - “-“ Don’t care -If Software Reset is applied during Sleep In mode, it will be necessary to wait 120msec before sending next command. Description -The display module loads all default values to the registers during 120msec. -If Software Reset is applied during Sleep Out or Display On Mode, it will be necessary to wait 120msec before sending next command. Legend SWRESET Command Parameter Display whole blank screen Display Flow Chart Set Commands to S/W Default Value Action Sleep In Mode Mode Sequential transter V0.2 83 2009-08-05 ST7735R 10.1.3 RDDID (04h): Read Display ID 04H RDDID (Read Display ID) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX RDDID 0 ↑ 1 - 0 0 0 0 0 1 0 0 (04h) 1st parameter 1 1 ↑ - - - - - - - - - - 2nd parameter 1 1 ↑ - ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 3rd parameter 1 1 ↑ - 1 ID26 ID25 ID24 ID23 ID22 ID21 ID20 1 1 ↑ - ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 4th parameter -This read byte returns 24-bit display identification information. -The 1st parameter is dummy data -The 2nd parameter (ID17 to ID10): LCD module’s manufacturer ID. -The 3rd parameter (ID26 to ID20): LCD module/driver version ID Description -The 4th parameter (ID37 to UD30): LCD module/driver ID. -Commands RDID1/2/3(DAh, DBh, DCh) read data correspond to the parameters 2,3,4 of the command 04h, respectively. “-“ Don’t care Default Value Status Default Power On Sequence ID1 ID2 ID3 - NV Value NV Value S/W Reset - NV Value NV Value H/W Reset - NV Value NV Value Serial I/F Mode Parallel I/F Mode Legend Read 04h Read 04h Host Display Dummy Clock Dummy Read Command Parameter Display Flow Chart Send 2nd parameter Send 2nd parameter Action Send 3rd parameter Send 3rd parameter Mode Sequential transter Send 4th parameter V0.2 Send 4th parameter 84 2009-08-05 ST7735R 10.1.4 RDDST (09h): Read Display Status 09H RDDST (Read Display Status) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX RDDST 0 ↑ 1 - 0 0 0 0 1 0 0 1 (09h) 1st parameter 1 1 ↑ - - - - - - - - - - 2nd parameter 1 1 ↑ - BSTON MY MX MV ML RGB MH ST24 3rd parameter 1 1 ↑ - ST23 IFPF2 IFPF1 IFPF0 4th parameter 1 1 ↑ - ST15 ST14 INVON ST12 ST11 DISON TEON GCS2 5th parameter 1 1 ↑ - GCS1 GCS0 TEM ST4 ST3 ST2 ST1 ST0 IDMON PTLON SLOUT NORON This command indicates the current status of the display as described in the table below: Bit Description Value BSTON Booster Voltage Status ‘1’ =Booster on, ‘0’ =Booster off MY Row Address Order (MY) ‘1’ =Decrement, (Bottom to Top, when MADCTL (36h) D7=’1’) ‘0’ =Increment, (Top to Bottom, when MADCTL (36h) D7=’0’) MX Column Address Order (MX) ‘1’ =Decrement, (Right to Left, when MADCTL (36h) D6=’1’) ‘0’ =Increment, (Left to Right, when MADCTL (36h) D6=’1’) MV Row/Column Exchange (MV) ‘1’ = Row/column exchange, (when MADCTL (36h) D5=’1’) ‘0’ = Normal, (when MADCTL (36h) D5=’0’ ML Scan Address Order (ML) ‘0’ =Decrement, (LCD refresh Top to Bottom, when MADCTL (36h) D4=’0’) ‘1’=Increment, (LCD refresh Bottom to Top, when MADCTL (36h) D4=’1’) RGB RGB/ BGR Order (RGB) ‘1’ =BGR, (When MADCTL (36h) D3=’1’) ‘0’ =RGB, (When MADCTL (36h) D3=’0’) Description MH Horizontal Order ‘0’ =Decrement, (LCD refresh Left to Right, when MADCTL (36h) D2=’0’) ‘1’ =Increment, (LCD refresh Right to Left, when MADCTL (36h) D2=’1’) ST24 For Future Use ST23 For Future Use ‘0’ ‘0’ IFPF2 “011” = 12-bit / pixel, Interface Color Pixel Format “101” = 16-bit / pixel, IFPF1 Definition “110” = 18-bit / pixel, others are no define IFPF0 IDMON Idle Mode On/Off ‘1’ = On, “0” = Off PTLON Partial Mode On/Off ‘1’ = On, “0” = Off SLPOUT Sleep In/Out ‘1’ = Out, “0” = In NORON ‘1’ = Normal Display, Display Normal Mode On/Off ‘0’ = Partial Display V0.2 ST15 Vertical Scrolling Status (Not Used) ‘1’ = Scroll on,“0” = Scroll off ST14 Horizontal Scroll Status (Not Used) ‘0’ INVON Inversion Status ‘1’ = On, “0” = Off ST12 All Pixels On (Not Used) ‘0’ ST11 All Pixels Off (Not Used) ‘0’ 85 2009-08-05 ST7735R DISON Display On/Off ‘1’ = On, “0” = Off TEON Tearing effect line on/off ‘1’ = On, “0” = Off GCSEL2 “000” = GC0 GCSEL1 “001” = GC1 Gamma Curve Selection “010” = GC2 “011” = GC3 GCSEL0 ”100” to “111” = Not defined TEM Tearing effect line mode ‘0’ = mode1, ‘1’ = mode2 ST4 For Future Use ‘0’ ST3 For Future Use ‘0’ ST2 For Future Use ‘0’ ST1 For Future Use ‘0’ ST0 For Future Use ‘0’ “-“ Don’t care Status Default Default Value (ST31 to ST0) ST[31-24] ST[23-16] ST[15-8] ST[7-0] Power On Sequence 0000-0000 0110-0001 0000-0000 0000-0000 S/W Reset 0xxx0xx00 0xxx-0001 0000-0000 0000-0000 H/W Reset 0000-0000 0110-0001 0000-0000 0000-0000 Flow Chart V0.2 86 2009-08-05 ST7735R 10.1.5 RDDPM (0Ah): Read Display Power Mode 0AH RDDPM (Read Display Power Mode) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX RDDPM 0 ↑ 1 - 0 0 0 0 1 0 1 0 (0Ah) 1st parameter 1 1 ↑ - - - - - - - - - - 2nd parameter 1 1 ↑ D1 D0 BSTON IDMON PTLON SLPOUT NORON DISON This command indicates the current status of the display as described in the table below: “-“ Don’t care Bit Description BSTON Booster Voltage Status Value ‘1’ =Booster on, ‘0’ =Booster off ‘1’ = Idle Mode On, IDMON Idle Mode On/Off ‘0’ = Idle Mode Off ‘1’ = Partial Mode On, PTLON Partial Mode On/Off ‘0’ = Partial Mode Off Description ‘1’ = Sleep Out, SLPON Sleep In/Out ‘0’ = Sleep In ‘1’ = Normal Display, NORON Display Normal Mode On/Off ‘0’ = Partial Display ‘1’ = Display On, DISON Display On/Off ‘0’ = Display Off D1 Not Used ‘0’ D0 Not Used ‘0’ Status Default Value (D7 to D0) Power On Sequence 0000_1000(08h) S/W Reset 0000_1000(08h) H/W Reset 0000_1000(08h) Default Flow Chart V0.2 87 2009-08-05 ST7735R 10.1.6 RDDMADCTL (0Bh): Read Display MADCTL 0BH RDDMADCTL (Read Display MADCTL) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX RDDMADCTL 0 ↑ 1 - 0 0 0 0 1 0 1 1 (0Bh) - - 1st parameter 1 1 ↑ 2nd parameter 1 1 ↑ - - - - - - - - MY MX MV ML RGB MH D1 D0 This command indicates the current status of the display as described in the table below: “-“ Don’t care Bit Description MX Column Address Order Value ‘1’ = Right to Left (When MADCTL B6=’1’) ‘0’ = Left to Right (When MADCTL B6=’0’) ‘1’ = Bottom to Top (When MADCTL B7=’1’) MY Row Address Order ‘0’ = Top to Bottom (When MADCTL B7=’0’) ‘1’ = Row/column exchange (MV=1) MV Row/Column Order (MV) ‘0’ = Normal (MV=0) Description ‘1’ =LCD Refresh Bottom to Top ML Vertical Refresh Order ‘0’ =LCD Refresh Top to Bottom RGB RGB/BGR Order ‘1’ =BGR, “0”=RGB LCD horizontal refresh direction control MH Horizontal Refresh Order ‘0’ = LCD horizontal refresh Left to right ‘1’ = LCD horizontal refresh right to left D1 Not Used ‘0’ D0 Not Used ‘0’ Status Default Value (D7 to D0) Power On Sequence 0000_0000 (00h) S/W Reset No change H/W Reset 0000_0000 (00h) Default Flow Chart V0.2 88 2009-08-05 ST7735R 10.1.7 RDDCOLMOD (0Ch): Read Display Pixel Format 0CH RDDCOLMOD (Read Display Pixel Format) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX RDDCOLMOD 0 ↑ 1 - 0 0 0 0 1 1 0 0 (0Ch) - 1st parameter 1 1 ↑ - - - - - - - - - 2nd parameter 1 1 ↑ - 0 0 0 0 - IFPF2 IFPF1 IFPF0 This command indicates the current status of the display as described in the table below: IFPF[2:0] MCU Interface Color Format 011 12-bit/pixel 101 16-bit/pixel 110 18-bit/pixel 111 No used Description Others are no define and invalid “-“ Don’t care Status Default Value IFPF[2:0] Default Power On Sequence 0110 (18 bits/pixel) S/W Reset No Change H/W Reset 0110 (18 bits/pixel) Flow Chart V0.2 89 2009-08-05 ST7735R 10.1.8 RDDIM (0Dh): Read Display Image Mode 0DH RDDIM (0Dh): Read Display Image Mode Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX RDDIM 0 ↑ 1 - 0 0 0 0 1 1 0 1 (0Dh) - 1st parameter 1 1 ↑ - - - - - - - - - 2nd parameter 1 1 ↑ - VSSON D6 INVON D4 D3 GCS2 GCS1 GCS0 This command indicates the current status of the display as described in the table below: “-“ Don’t care Bit Description Value VSSON Reversed “0” D6 Reversed “0” INVON Inversion On/Off “1” = Inversion is On, “0” = Inversion is Off Description D4 All Pixels On “0” (Not used) D3 All Pixels Off “0” (Not used) “000” = GC0, GCS2 “001” = GC1, GCS1 Gamma Curve Selection “010” = GC2, GCS0 “011” = GC3, ”100” to “111” = Not defined Status Default Value(D7 to D0) Power On Sequence 0000_0000 (00h) S/W Reset 0000_0000 (00h) H/W Reset 0000_0000 (00h) Default Flow Chart V0.2 90 2009-08-05 ST7735R 10.1.9 RDDSM (0Eh): Read Display Signal Mode 0EH RDDSM (0Eh): Read Display Signal Mode Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX RDDSM 0 ↑ 1 - 0 0 0 0 1 1 1 0 (0Eh) - 1st parameter 1 1 ↑ - - - - - - - - - 2nd parameter 1 1 ↑ - TEON TEM D5 D4 D3 D2 D1 D0 This command indicates the current status of the display as described in the table below: “-“ Don’t care Bit Description Value TEON Tearing Effect Line On/Off “1” = On, “0” = Off TEM Tearing effect line mode “1” = mode2, “0” = mode1 D5 Not Used “1” = On, “0” = Off Description D4 Not Used “1” = On, “0” = Off D3 Not Used “1” = On, “0” = Off D2 Not Used “1” = On, “0” = Off D1 Not Used “1” = On, “0” = Off D0 Not Used “1” = On, “0” = Off Status Default Value(D7~D0) Power On Sequence 0000_0000 (00h) S/W Reset 0000_0000 (00h) H/W Reset 0000_0000 (00h) Default V0.2 91 2009-08-05 ST7735R Flow Chart V0.2 92 2009-08-05 ST7735R 10.1.10 SLPIN (10h): Sleep In 10H SLPIN (Sleep In) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX SLPIN 0 ↑ 1 - 0 0 0 1 0 0 0 0 (10h) Parameter No Parameter - -This command causes the LCD module to enter the minimum power consumption mode. Description -In this mode the DC/DC converter is stopped, Internal display oscillator is stopped, and panel scanning is stopped. -This command has no effect when module is already in Sleep In mode. Sleep In Mode can only be exit by the Sleep Out Command (11h). Restriction -When IC is in Sleep Out or Display On mode, it is necessary to wait 120msec before sending next command because of the stabilization timing for the supply voltages and clock circuits. Status Default Value Power On Sequence Sleep in mode S/W Reset Sleep in mode H/W Reset Sleep in mode Default Legend SLPIN Stop DC-DC Converter Command Parameter Display whole blank screen (Automatic No effect to DISP ON/OFF Commands) Stop Internal Oscillator Display Flow Chart Sleep In Mode Drain Charge From LCD Panel Action Mode Sequential transter V0.2 93 2009-08-05 ST7735R 10.1.11 SLPOUT (11h): Sleep Out 11H SLPOUT (Sleep Out) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX SLPOUT 0 ↑ 1 - 0 0 0 1 0 0 0 1 (11h) Parameter No Parameter - -This command turns off sleep mode. Description -In this mode the DC/DC converter is enabled, Internal display oscillator is started, and panel scanning is started. -This command has no effect when module is already in sleep out mode. Sleep Out Mode can only be exit by the Sleep In Command (10h). -When IC is in Sleep In mode, it is necessary to wait 120msec before sending next command because of the stabilization Restriction timing for the supply voltages and clock circuits. -When IC is in Sleep Out or Display On mode, it is necessary to wait 120msec before sending next command due to the download of default value of registers and the execution of self-diagnostic function. Status Default Value Power On Sequence Sleep in mode S/W Reset Sleep in mode H/W Reset Sleep in mode Default Legend Command SLPOUT Display whole blank screen for 2 firames (Automatic No effect to DISP ON/OFF Commands) Start Internal Oscillator Parameter Display Flow Chart Start up DC:DC Converter Display Memory contents In accordance with the current command table settings Charge Offset voltage for LCD Panel Action Mode Sleep Out mode Sequential transter V0.2 94 2009-08-05 ST7735R 10.1.12 PTLON (12h): Partial Display Mode On 12H PTLON (12h): Partial Display Mode On Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX PTLON 0 ↑ 1 - 0 0 0 1 0 0 1 0 (12h) Parameter No Parameter - -This command turns on Partial mode. The partial mode window is described by the Partial Area command (30h) Description -To leave Partial mode, the Normal Display Mode On command (13h) should be written. “-“ Don’t care Default Flow Chart V0.2 Status Default Value Power On Sequence Normal Mode On S/W Reset Normal Mode On H/W Reset Normal Mode On See Partial Area (30h) 95 2009-08-05 ST7735R 10.1.13 NORON (13h): Normal Display Mode On 13H NORON (Normal Display Mode On) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX NORON 0 ↑ 1 - 0 0 0 1 0 0 1 1 (13h) Parameter No Parameter - -This command returns the display to normal mode. -Normal display mode on means Partial mode off. Description -Exit from NORON by the Partial mode On command (12h) “-“ Don’t care Default Flow Chart V0.2 Status Default Value Power On Sequence Normal Mode On S/W Reset Normal Mode On H/W Reset Normal Mode On See Partial Area Definition Descriptions for details of when to use this command 96 2009-08-05 ST7735R 10.1.14 INVOFF (20h): Display Inversion Off 20H IVNOFF (Normal Display Mode Off) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX INVOFF 0 ↑ 1 - 0 0 1 0 0 0 0 0 (20h) Parameter No Parameter - -This command is used to recover from display inversion mode. (Example) “-“ Don’t care Memory Description Display Top-Left (0,0) Status Default Default Value Power On Sequence Display Inversion off S/W Reset Display Inversion off H/W Reset Display Inversion off Legend Command Display Inversion On Mode Parameter Display Flow Chart INVOFF (20h) Action Display Inversion OFF Mode Mode Sequential transter V0.2 97 2009-08-05 ST7735R 10.1.15 INVON (21h): Display Inversion On 21H IVNOFF (Display Inversion On) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX INVON 0 ↑ 1 - 0 0 1 0 0 0 0 1 (21h) Parameter No Parameter - -This command is used to enter into display inversion mode -To exit from Display Inversion On, the Display Inversion Off command (20h) should be written. (Example) Memory “-“ Don’t care Description Default Display Top-Left (0,0) Status Default Value Power On Sequence Display Inversion off S/W Reset Display Inversion off H/W Reset Display Inversion off Legend Command Display Inversion OFF Mode Parameter Display Flow Chart INVON (21h) Action Display Inversion ON Mode Mode Sequential transter V0.2 98 2009-08-05 ST7735R 10.1.16 GAMSET (26h): Gamma Set 26H GAMSET (Gamma Set) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX GAMSET 0 ↑ 1 - 0 0 1 0 0 1 1 0 (26h) Parameter 1 ↑ 1 - - - - - GC3 GC2 GC1 GC0 -This command is used to select the desired Gamma curve for the current display. A maximum of 4 curves can be selected. The curve is selected by setting the appropriate bit in the parameter as described in the Table. GC [7:0] Description Parameter Curve Selected GS=1 GS=0 01h GC0 Gamma Curve 1 (G2.2) Gamma Curve 1 (G1.0) 02h GC1 Gamma Curve 2 (G1.8) Gamma Curve 2 (G2.5) 04h GC2 Gamma Curve 3 (G2.5) Gamma Curve 3 (G2.2) 08h GC3 Gamma Curve 4 (G1.0) Gamma Curve 4 (G1.8) Note: All other values are undefined. Default Status Default Value Power On Sequence 01h S/W Reset 01h H/W Reset 01h Flow Chart V0.2 99 2009-08-05 ST7735R 10.1.17 DISPOFF (28h): Display Off 28H DISPOFF (Display Off) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX DISPOFF 0 ↑ 1 - 0 0 1 0 1 0 0 0 (28h) Parameter No Parameter - - This command is used to enter into DISPLAY OFF mode. In this mode, the output from Frame Memory is disabled and blank page inserted. - This command makes no change of contents of frame memory. - This command does not change any other status. - There will be no abnormal visible effect on the display. - Exit from this command by Display On (29h) Description (Example) Memory Display Status Default Default Value Power On Sequence Display off S/W Reset Display off H/W Reset Display off Flow Chart V0.2 100 2009-08-05 ST7735R 10.1.18 DISPON (29h): Display On 29H DISPON (Display On) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX DISPON 0 ↑ 1 - 0 0 1 0 1 0 0 1 (29h) Parameter No Parameter - - This command is used to recover from DISPLAY OFF mode. - Output from the Frame Memory is enabled. - This command makes no change of contents of frame memory. - This command does not change any other status. Description (Example) Memory Display Status Default Default Value Power On Sequence Display off S/W Reset Display off H/W Reset Display off Legend Command Display Off Mode Parameter Display Flow Chart DISPON Action Display On Mode Mode Sequential transter V0.2 101 2009-08-05 ST7735R 10.1.19 CASET (2Ah): Column Address Set 2AH CASET(Column Address Set)_ Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX CASET(2Ah) 0 ↑ 1 - 0 0 1 0 1 0 1 0 (2Ah) 1st parameter 1 ↑ 1 - XS15 XS14 XS13 XS12 XS11 XS10 XS9 XS8 2nd parameter 1 ↑ 1 - XS7 XS6 XS5 XS4 XS3 XS2 XS1 XS0 3rd parameter 1 ↑ 1 - XE15 XE14 XE13 XE12 XE11 XE10 XE9 XE8 4th parameter 1 ↑ 1 - XE7 XE6 XE5 XE4 XE3 XE2 XE1 XE0 -The value of XS [7:0] and XE [7:0] are referred when RAMWR command comes. -Each value represents one column line in the Frame Memory. XS[7:0] XE[7:0] Description XS [15:0] always must be equal to or less than XE [15:0] When XS [15:0] or XE [15:0] is greater than maximum address like below, data of out of range will be ignored. 1. 128X160 memory base (GM = ’11’) (Parameter range: 0 < XS [15:0] < XE [15:0] < 127 (007Fh)): MV=”0”) Restriction (Parameter range: 0 < XS [15:0] < XE [15:0] < 159 (009Fh)): MV=”1”) 2. 132X162 memory base (GM = ’00’) (Parameter range: 0 < XS [15:0] < XE [15:0] < 131 (0083h)): MV=”0”) (Parameter range: 0 < XS [15:0] < XE [15:0] < 161 (00A1h)): MV=”1”) Default Status GM=’11’ (128x160 memory base) Power On Sequence 0000h S/W Reset 0000h H/W Reset 0000h 007Fh (127) Power On Sequence 0000h 0083h (131) GM=’00’ (132x162 memory base) V0.2 Default Value GM Status XS [7:0] S/W Reset 0000h H/W Reset 0000h 102 XE [7:0] (MV=’0 ’) XE [7:0] (MV=’1’) 007Fh (127) 007Fh (127) 0083h (131) 009Fh (159) 00A1h (161) 0083h (131) 2009-08-05 ST7735R Flow Chart V0.2 103 2009-08-05 ST7735R 10.1.20 RASET (2Bh): Row Address Set 2BH RASET (Row Address Set) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX RASET (2Bh) 0 ↑ 1 - 0 0 1 0 1 0 1 1 (2Bh) 1st parameter 1 ↑ 1 - YS15 YS14 YS13 YS12 YS11 YS10 YS9 YS8 2nd parameter 1 ↑ 1 - YS7 YS6 YS5 YS4 YS3 YS2 YS1 YS0 3rd parameter 1 ↑ 1 - YE15 YE14 YE13 YE12 YE11 YE10 YE9 YE8 1 ↑ 1 - YE7 YE6 YE5 YE4 YE3 YE2 YE1 YE0 4th parameter The value of YS [7:0] and YE [7:0] are referred when RAMWR command comes. Each value represents one column line in the Frame Memory. YS[7:0] Description YE[7:0] YS [15:0] always must be equal to or less than YE [15:0] When YS [15:0] or YE [15:0] are greater than maximum row address like below, data of out of range will be ignored. 1. 128X160 memory base (GM = ’11’) (Parameter range: 0 < YS [15:0] < YE [15:0] < 159 (009Fh)): MV=”0” Restriction (Parameter range: 0 < YS [15:0] < YE [15:0] < 127 (007Fh)): MV=”1” 2. 132X162 memory base (GM = ’00’) (Parameter range: 0 < YS [15:0] < YE [15:0] < 161 (00A1h)): MV=”0” (Parameter range: 0 < YS [15:0] < YE [15:0] < 131 (0083h)): MV=”1” Default Status GM=’11’ (128x160 memory base) Power On Sequence 0000h GM=’00’ (132x162 memory base) V0.2 Default Value GM status YS [15:0] YE [15:0] (MV=’0 ’) YE [15:0] (MV=’1’) 009Fh (159) S/W Reset 0000h H/W Reset 0000h 009Fh (159) Power On Sequence 0000h 00A1h (161) S/W Reset 0000h H/W Reset 0000h 104 009Fh (159) 00A1h (161) 007Fh (127) 0083h (131) 00A1h (161) 2009-08-05 ST7735R CASET Legend 1st parameter XS[15:0] 2nd parameter XE[15:0] Command Parameter PASET Flow Chart Display 1st parameter YS[15:0] 2nd parameter YE[15:0] Action Mode RAMWR Sequential transter Image Data D1[7:0],D2[7:0] …….Dn[7:0] Any Command V0.2 105 2009-08-05 ST7735R 10.1.21 RAMWR (2Ch): Memory Write 2CH RAMWR (Memory Write) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX RAMWR 0 ↑ 1 - 0 0 1 0 1 1 0 0 (2Ch) 1st parameter 1 ↑ 1 ∣ 1 ↑ 1 D17-8 ∣ D7 ∣ D6 ∣ D5 ∣ D4 ∣ D3 ∣ D2 ∣ D1 ∣ D0 ∣ Nth parameter 1 ↑ 1 D17-8 D7 D6 D5 D4 D3 D2 D1 D0 In all color modes, there is no restriction on length of parameters. 1. 128X160 memory base (GM = ‘11’) 128x160x18-bit memory can be written by this command Description Memory range: (0000h, 0000h) -> (007Fh, 09Fh) 2. 132x162 memory base (GM = ‘00’) 132x162x18-bit memory can be written on this command. Memory range: (0000h, 0000h) -> (0083h, 00A1h) Default Status Default Value Power On Sequence Contents of memory is set randomly S/W Reset Contents of memory is not cleared H/W Reset Contents of memory is not cleared Legend Command RAMWR Parameter Display Flow Chart Image Data D1[7:0],D2[7:0] …….Dn[7:0] Action Mode Any Command V0.2 106 Sequential transter 2009-08-05 ST7735R 10.1.22 RGBSET (2Dh): Color Setting for 4K, 65K and 262K 2DH RGBSET (Color Set for 4K, 65K, 262K and 16.7M) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX RGBSET 0 ↑ 1 - 0 0 1 0 1 1 0 1 (2Dh) 1st parameter 1 ↑ 1 - - - R005 R004 R003 R002 R001 R000 ∣ 1 ↑ 1 - - - Rnn5 Rnn4 Rnn3 Rnn2 Rnn1 Rnn0 ∣ 1 ↑ 1 - - - R315 R314 R313 R312 R311 R310 ∣ 1 ↑ 1 - - - G005 G004 G003 G002 G001 G000 ∣ 1 ↑ 1 - - - Gnn5 Gnn4 Gnn3 Gnn2 Gnn1 Gnn0 ∣ 1 ↑ 1 - - - G635 G634 G633 G632 G631 G630 ∣ 1 ↑ 1 - - - B005 B004 B003 B002 B001 B000 ∣ 1 ↑ 1 - - - Bnn5 Bnn4 Bnn3 Bnn2 Bnn1 Bnn0 1 ↑ 1 - - - B315 B314 B313 B312 B311 B310 128th parameter This command is used to define the LUT for 12bits-to-16bits / 16-bit-to- 18bits color depth conversations. 128-Bytes must be written to the LUT regardless of the color mode. Only the values in Section 9.18 are referred. In this condition, 4K-color (4-4-4) and 65K-color(5-6-5) data input are transferred 6(R)-6(G)-6(B) through RGB LUT Description table. This command has no effect on other commands/parameters and Contents of frame memory. Visible change takes effect next time the Frame Memory is written to. Do not send any command before the last data is sent or LUT is not defined correctly. Default Status Default Value Power On Sequence Random S/W Reset Contents of the look-up table protected H/W Reset Random Flow Chart V0.2 107 2009-08-05 ST7735R 10.1.23 RAMRD (2Eh): Memory Read 2EH RAMHD (Memory Read) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX RAMHD 0 ↑ 1 - 0 0 1 0 1 1 1 0 (2Eh) 1st parameter 1 1 ↑ - - - - - - - - - 2nd parameter 1 1 ↑ ∣ 1 1 ↑ D17-8 ∣ D7 ∣ D6 ∣ D5 ∣ D4 ∣ D3 ∣ D2 ∣ D1 ∣ D0 ∣ 1 1 ↑ D17-8 D7 D6 D5 D4 D3 D2 D1 D0 (N+1)th parameter -This command is used to transfer data from frame memory to MCU. -When this command is accepted, the column register and the row register are reset to the Start Column/Start Row positions. -The Start Column/Start Row positions are different in accordance with MADCTL setting. -Then D[17:0] is read back from the frame memory and the column register and the row register incremented as section 9.10 Description -Frame Read can be cancelled by sending any other command. -The data color coding is fixed to 18-bit in reading function. Please see section 9.8 “Data color coding” for color coding (18-bit cases), when there is used 8, 9, 16 and 18-bit data lines for image data. Note1: The Command 3Ah should be set to 66h when reading pixel data from frame memory. Please check the LUT in chapter 9.17 when using memory read function. Default Status Default Value Power On Sequence Contents of memory is set randomly S/W Reset Contents of memory is not cleared H/W Reset Contents of memory is not cleared Flow Chart V0.2 108 2009-08-05 ST7735R 10.1.24 PTLAR (30h): Partial Area 30H PTLAR (Partial Area) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX PTLAR 0 ↑ 1 - 0 0 1 1 0 0 0 0 (30h) 1st parameter 1 ↑ 1 - PSL15 PSL14 PSL13 PSL12 PSL11 PSL10 PSL9 PSL8 2nd parameter 1 ↑ 1 - PSL7 PSL6 PSL5 PSL4 PSL3 PSL2 PSL1 PSL0 3rd parameter 1 ↑ 1 - PEL15 PEL14 PEL13 PEL12 PEL11 PEL10 PEL9 PEL8 4th parameter 1 ↑ 1 - PEL7 PEL6 PEL5 PEL4 PEL3 PEL2 PEL1 PEL0 -This command defines the partial mode’s display area. -There are 4 parameters associated with this command, the first defines the Start Row (PSL) and the second the End Row (PEL), as illustrated in the figures below. PSL and PEL refer to the Frame Memory row address counter. -If End Row > Start Row, when MADCTL ML=’0’ End row Non-display area PEL [7:0] Partial display area PSL [7:0] Non-display area Start row -If End Row > Start Row, when MADCTL ML=’1’ Start row Non-display area PSL [7:0] Description Partial display area PEL [7:0] Non-display area End row -If End Row < Start Row, when MADCTL ML=’0’ Partial display area End row PEL [7:0] Non-display area PSL [7:0] Start row Partial display area -If End Row = Start Row then the Partial Area will be one row deep. Status Default V0.2 Default Value PSL [15:0] PEL [15:0] GM[1:0] “xx” GM[1:0]=”11” GM[1:0]=”00” Power On Sequence 0000h 009Fh 00A1h S/W Reset 0000h 009Fh 00A1h H/W Reset 0000h 009Fh 00A1h 109 2009-08-05 ST7735R Flow Chart V0.2 110 2009-08-05 ST7735R 10.1.25 TEOFF (34h): Tearing Effect Line OFF 34H TEOFF (Tearing Effect Line OFF) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX TEOFF 0 ↑ 1 - 0 0 1 1 0 1 0 0 (34h) Parameter Description No Parameter - -This command is used to turn OFF (Active Low) the Tearing Effect output signal from the TE signal line. Status Default Default Value Power On Sequence OFF S/W Reset OFF H/W Reset OFF Legend Command TE Line Output ON Parameter TEOFF Display Flow Chart TE Line Output OFF Action Mode Sequential transter V0.2 111 2009-08-05 ST7735R 10.1.26 TEON (35h): Tearing Effect Line ON 35H TEON (Tearing Effect Line ON) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX TEON 0 ↑ 1 - 0 0 1 1 0 1 0 1 (35h) Parameter 1 ↑ 1 - 0 0 0 0 0 0 0 TEM -This command is used to turn ON the Tearing Effect output signal from the TE signal line. -This output is not affected by changing MADCTL bit ML. -The Tearing Effect Line On has one parameter, which describes the mode of the Tearing Effect Output Line: -When TEM =’0’: The Tearing Effect output line consists of V-Blanking information only Tvdl Tvdh Vertical time scale Description -When TEM =’1’: The Tearing Effect output Line consists of both V-Blanking and H-Blanking information Tvdl Tvdh Vertical time scale Note: During Sleep In Mode with Tearing Effect Line On, Tearing Effect Output pin will be active Low. Default Status Default Value Power On Sequence Tearing effect off & TEM=0 S/W Reset Tearing effect off & TEM=0 H/W Reset Tearing effect off & TEM=0 Legend TE Line Output OFF Command Parameter TEON Display Flow Chart TELOM Action TE Line Output ON Mode Sequential transter V0.2 112 2009-08-05 ST7735R 10.1.27 MADCTL (36h): Memory Data Access Control 36H MADCTL (Memory Data Access Control) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX MADCTL 0 ↑ 1 - 0 0 1 1 0 1 1 0 (36h) Parameter 1 ↑ 1 - MY MX MV ML RGB MH - - -This command defines read/ write scanning direction of frame memory. Bit NAME DESCRIPTION MY Row Address Order MX Column Address Order MV Row/Column Exchange ML Vertical Refresh Order LCD vertical refresh direction control ‘0’ = LCD vertical refresh Top to Bottom ‘1’ = LCD vertical refresh Bottom to Top RGB RGB-BGR ORDER Color selector switch control ‘0’ =RGB color filter panel, ‘1’ =BGR color filter panel) MH Horizontal Refresh Order LCD horizontal refresh direction control ‘0’ = LCD horizontal refresh Left to right ‘1’ = LCD horizontal refresh right to left These 3bits controls MCU to memory write/read direction. -Bit Assignment Top-left (0, 0) Top-left (0, 0) Memory Display Send first Send 2nd Send 3rd ML="0" Description Send last Top-left (0, 0) Top-left (0, 0) Memory Display Send last ML="1" Send 3rd Send 2nd Send first R G B R SIG1 RGB="0" RGB="1" Driver IC Driver IC G B R SIG2 SIG1 G B SIG2 G B R SIG1 SIG132 G B R SIG2 SIG1 G B SIG132 SIG2 SIG132 R G B R G B R G B B G R B G R B G R R G B R G B R G B B G R B G R B G R LCD panel V0.2 R SIG132 LCD panel 113 2009-08-05 ST7735R Top-left (0, 0) Top-left (0, 0) Memory Memory ML="0" ML="1" Send first Send 3rd Send 2nd Top-left (0, 0) Display Default Send last Send last Send 3rd Send 2nd Send first Top-left (0, 0) Display Status Default Value Power On Sequence MY=0,MX=0,MV=0,ML=0,RGB=0,MH=0 S/W Reset No Change H/W Reset MY=0,MX=0,MV=0,ML=0,RGB=0,MH=0 Legend Command MADCTL Parameter Display Flow Chart 1st parameter B[7:0] Action Mode Sequential transter V0.2 114 2009-08-05 ST7735R 10.1.28 IDMOFF (38h): Idle Mode Off 38H IDMOFF (Idle Mode Off) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX IDMOFF 0 ↑ 1 - 0 0 1 1 1 0 0 0 (38h) Parameter No Parameter - -This command is used to recover from Idle mode on. -In the idle off mode, Description 1. LCD can display 4096, 65k or 262k colors. 2. Normal frame frequency is applied. Default Status Default Value Power On Sequence Idle Mode Off S/W Reset Idle Mode Off H/W Reset Idle Mode Off Flow Chart V0.2 115 2009-08-05 ST7735R 10.1.29 IDMON (39h): Idle Mode On 39H IDMON (Idle Mode On) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX IDMOFF 0 ↑ 1 - 0 0 1 1 1 0 0 1 (39h) Parameter No Parameter - -This command is used to enter into Idle mode on. -There will be no abnormal visible effect on the display mode change transition. -In the idle on mode, 1. Color expression is reduced. The primary and the secondary colors using MSB of each R,G and B in the Frame Memory, 8 color depth data is displayed. 2. 8-Color mode frame frequency is applied. 3. Exit from IDMON by Idle Mode Off (38h) command (Example) Memory Top-Left (0,0) Display Description Color Register Availability Default V0.2 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B4 B1 B0 Black 0xxxxx 0xxxxx 0xxxxx Blue 0xxxxx 0xxxxx 1xxxxx Red 1xxxxx 0xxxxx 0xxxxx Magenta 1xxxxx 0xxxxx 1xxxxx Green 0xxxxx 1xxxxx 0xxxxx Cyan 0xxxxx 1xxxxx 1xxxxx Yellow 1xxxxx 1xxxxx 0xxxxx White 1xxxxx 1xxxxx 1xxxxx Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out No Partial Mode On, Idle Mode On, Sleep Out No Sleep In Yes Status Default Value Power On Sequence Idle Mode Off S/W Reset Idle Mode Off H/W Reset Idle Mode Off 116 2009-08-05 ST7735R Legend Command Idle off mode Parameter IDMON Display Idle on mode Action Flow Chart Mode Sequential transter V0.2 117 2009-08-05 ST7735R 10.1.30 COLMOD (3Ah): Interface Pixel Format 3AH COLMOD (3Ah): Interface Pixel Format Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX COLMOD 0 ↑ 1 - 0 0 1 1 1 0 1 0 (3Ah) Parameter 1 ↑ 1 - - - - - - IFPF2 IFPF1 IFPF0 This command is used to define the format of RGB picture data, which is to be transferred via the MCU interface. The formats are shown in the table: IFPF[2:0] Description MCU Interface Color Format 011 3 101 5 12-bit/pixel 16-bit/pixel 110 6 18-bit/pixel 111 7 No used Note1: In 12-bit/Pixel, 16-bit/Pixel or 18-bit/Pixel mode, the LUT is applied to transfer data into the Frame Memory. Note2: The Command 3Ah should be set at 55h when writing 16-bit/pixel data into frame memory, but 3Ah should be re-set to 66h when reading pixel data from frame memory. Please check the LUT in chapter 9.17 when using memory read function. Register Availability Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out No Partial Mode On, Idle Mode On, Sleep Out No Sleep In Yes Status Default Power On Sequence Default Value IFPF[2:0] VIPF[3:0] 0110(18-bit/Pixel) 0110(18-bit/Pixel) S/W Reset No Change No Change H/W Reset 0110(18-bit/Pixel) 0110(18-bit/Pixel) Flow Chart V0.2 118 2009-08-05 ST7735R 10.1.31 RDID1 (DAh): Read ID1 Value DAH RDID1 (Read ID1 Value) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX RDID1 0 ↑ 1 - 1 1 0 1 1 0 1 0 (DAh) 1st parameter 1 1 ↑ - - - - - - - - - - 2nd parameter 1 1 ↑ - ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 -This read byte returns 8-bit LCD module’s manufacturer ID -The 1st parameter is dummy data Description -The 2nd parameter (ID17 to ID10): LCD module’s manufacturer ID. NOTE: See command RDDID (04h), 2nd parameter. Register Availability Default Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out No Partial Mode On, Idle Mode On, Sleep Out No Sleep In Yes Status Default Value Power On Sequence - S/W Reset - H/W Reset - Legend Serial I/F Mode Parallel I/F Mode Read ID1 Command Read ID1 Parameter Send 2nd parameter Dummy Read Display Flow Chart Action Send 2nd parameter Mode Sequential transter V0.2 119 2009-08-05 ST7735R 10.1.32 RDID2 (DBh): Read ID2 Value DBH RDID2 (Read ID2 Value) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX RDID2 0 ↑ 1 - 1 1 0 1 1 0 1 1 (DBh) - 1st parameter 1 1 ↑ - - - - - - - - - 2nd parameter 1 1 ↑ - 1 ID26 ID25 ID24 ID23 ID22 ID21 ID20 -This read byte returns 8-bit LCD module/driver version ID -The 1st parameter is dummy data -The 2nd parameter (ID26 to ID20): LCD module/driver version ID -Parameter Range: ID=80h to FFh Description ID26 to ID20 Version Changes 80h 81h 82h 83h NOTE: See command RDDID (04h), 3rd parameter. Register Availability Default Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out No Partial Mode On, Idle Mode On, Sleep Out No Sleep In Yes Status Default Value Power On Sequence NV Value S/W Reset NV Value H/W Reset NV Value Flow Chart V0.2 120 2009-08-05 ST7735R 10.1.33 RDID3 (DCh): Read ID3 Value DCH RDID3 (Read ID2 Value) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX RDID3 0 ↑ 1 - 1 1 0 1 1 1 0 0 (DCh) 1st parameter 1 1 ↑ - - - - - - - - - - 2nd parameter 1 1 ↑ - ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 -This read byte returns 8-bit LCD module/driver ID. -The 1st parameter is dummy data Description -The 2nd parameter (ID37 to ID30): LCD module/driver ID. NOTE: See command RDDID (04h), 4th parameter. Register Availability Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out No Partial Mode On, Idle Mode On, Sleep Out No Sleep In Yes Status Default Value Power On Sequence NV Value Default S/W Reset NV Value H/W Reset NV Value Legend Serial I/F Mode Read ID3 Parallel I/F Mode Command Read ID3 Parameter Host Display Display Flow Chart Send 2nd parameter Dummy Read Action Send 2nd parameter Mode Sequential transter V0.2 121 2009-08-05 ST7735R 10.2 Panel Function Command List and Description Table 10.2.1 Panel Function Command List (1) Instruction Refer D/CX WRX RDX D23-8 D7 FRMCTR1 10.2.1 FRMCTR2 10.2.2 FRMCTR3 10.2.3 INVCTR V0.2 D6 D5 D4 D3 D2 D1 D0 Hex Function 0 1 1 0 0 0 1 (B1h) In normal mode (Full colors) 0 ↑ 1 - 1 ↑ 1 - 1 ↑ 1 - FPA5 FPA4 FPA3 FPA2 FPA1 FPA0 1 ↑ 1 - BPA5 BPA4 BPA3 BPA2 BPA1 BPA0 0 ↑ 1 - 0 1 0 1 ↑ 1 - 1 ↑ 1 - FPB5 FPB4 FPB3 FPB2 FPB1 FPB0 1 ↑ 1 - BPB5 BPB4 BPB3 BPB2 BPB1 BPB0 0 ↑ 1 - 0 1 1 1 ↑ 1 - 1 ↑ 1 - FPC5 FPC4 FPC3 FPC2 FPC1 FPC0 1 ↑ 1 - BPC5 BPC4 BPC3 BPC2 BPC1 BPC0 1 ↑ 1 - 1 ↑ 1 - FPD5 FPD4 FPD3 FPD2 FPD1 FPD0 1 ↑ 1 - BPD5 BPD4 BPD3 BPD2 BPD1 BPD0 0 ↑ 1 - 1 0 1 1 0 1 0 0 1 ↑ 1 - 0 0 0 0 0 NLA NLB NLC 1 RTNA3 RTNA2 RTNA1 RTNA0 1 0 1 1 0 RTNA set 1-line period FPA: front porch BPA: back porch (B2h) RTNB3 RTNB2 RTNB1 RTNB0 1 0 1 1 0 In Idle (8-colors) mode RTNB: set 1-line period FPB: front porch BPB: back porch (B3h) In partial mode + Full colors RTNC3 RTNC2 RTNC1 RTNC0 RTNC,RTND: set 1-line period FPC,FPD: front porch BPC,BPD: back porch RTND3 RTND2 RTND1 RTND0 (B4h) Display control inversion 10.2.4 122 NLA,NLB,NLC set inversion 2009-08-05 ST7735R Table 10.2.2 Panel Function Command List (2) Instruction Refer D/CX WRX RDX D17-8 0 ↑ 1 - 1 ↑ 1 - 1 ↑ 1 - 1 ↑ 1 0 ↑ 1 - 1 ↑ 1 - D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 0 0 0 0 0 0 ↑ 1 PWCTR3 10.2.7 1 0 ↑ ↑ ↑ 0 1 1 VGH2 VGH2 5[1] 5[0] 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 - - 0 0 [1] [0] 1] 0] 0 0 1 0 SAPA SAPA SAPA APA2 APA1 APA0 2 1 0 - DCA7 DCA6 DCA5 DCA4 DCA3 DCA2 DCA1 DCA0 1 1 0 0 0 0 1 1 SAPB SAPB SAPB APB2 APB1 APB0 2 1 0 - DCB9 DCB8 - DCB7 DCB6 DCB5 DCB4 DCB3 DCB2 DCB1 DCB0 1 0 ↑ 1 - 1 ↑ 1 - DCC9 DCC8 1 ↑ 1 - DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1 DCC0 0 ↑ 1 - 1 1 1 ↑ 1 - - - 1 1 PWCTR5 10.2.9 VRH: Set the GVDD voltage 0 0 0 1 0 0 SAPC SAPC SAPC APC2 APC1 APC0 2 1 0 0 0 (C1h) Power control setting BT: set voltage VGLSEL VGLSEL VGHBT[ VGHBT[ DCA9 DCA8 - (C0h) Power control setting VRHN VRHN VRHN VRHN VRHN 4 3 2 1 0 1 PWCTR4 10.2.8 1 0 MODE MODE [1] [0] - Function AVDD[ AVDD[ AVDD VRHP VRHP VRHP VRHP VRHP 2] 1] [0] 4 3 2 1 0 PWCTR1 10.2.5 PWCTR2 10.2.6 Hex 0 1 0 1 (C2h) VGH/ VGL In normal mode (Full colors) APA: adjust the operational amplifier DCA: adjust the booster Voltage (C3h) In Idle mode (8-colors) APB: adjust the operational amplifier DCB: adjust the booster Voltage (C4h) In partial mode + Full colors APC: adjust the operational amplifier DCC: adjust the booster circuit for Idle mode (C5h) VCOM control 1 VMCTR1 10.2.10 VCOMS VCOMS VCOMS VCOMS VCOMS VCOMS 5 4 3 2 1 0 0 0 1 1 1 0 ↑ 1 - 1 1 0 1 ↑ 1 - - - - 0 ↑ 1 - 1 1 0 1 ↑ 1 - - VCOM voltage control (C7h) Set VCOM offset control VMOFCTR 10.2.11 WRID2 VMF4 VMF3 VMF2 VMF1 VMF0 1 0 0 0 1 (D1h) Set LCM version code 10.2.12 ID2[6] ID2[5] ID2[4] ID2[3] ID2[2] ID2[1] ID2[0] “-“: Don’t care Note 1: C0h to C7h are fixed for about power controller V0.2 123 2009-08-05 ST7735R Table 10.2.3 Panel Function Command List (3) Instruction Refer D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 Hex 1 1 0 1 0 0 1 0 (D2h) Function Customer Project 0 ↑ 1 - code WRID3 10.2.13 Set the project code 1 ↑ 1 - ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 at ID3 0 ↑ 1 - 1 1 0 1 1 0 0 1 1 ↑ 1 - 0 VMF _EN ID2 _EN 0 0 0 0 EXT_ R 0 ↑ 1 - 1 1 0 1 1 1 1 0 1 ↑ 1 - 1 0 1 0 0 1 0 1 0 ↑ 1 - 1 1 0 1 1 1 1 1 1 ↑ 1 - NVM_ NVM _ NVM _ NVM _ NVM _ NVM _ NVM _ NVM _ IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 1 ↑ 1 - NVM _ NVM _ NVM _ NVM _ NVM _ NVM _ NVM _ NVM _ CMD7 CMD6 CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 1 ↑ 1 - NVCTR1 10.2.14 (D9) NVM control status (DEh) NVM Read Command NVCTR2 10.2.15 NVCTR3 10.2.16 1 0 1 0 0 1 0 1 A5 Action code (DFh) NVM Write Command A5 “-“: Don’t care Note 1: The D1h to D3h registers are fixed for about ID code setting. Note 2: The D9h, DEh and DFh registers are used for NV Memory function controller. (Ex: write, clear, etc.) V0.2 124 2009-08-05 ST7735R Table 10.2.4 Panel Function Command List (4) Instruction Refer D/CX WRX RDX D17-8 D7 GAMCTRP1 10.2.17 GAMCTRN1 10.2.18 Hex Function D6 D5 D4 D3 D2 D1 D0 0 ↑ 1 - 1 1 1 0 0 0 0 0 1 ↑ 1 - --- --- VRFP[5] VRFP[4] VRFP[3] VRFP[2] VRFP[1] VRF0P[0] 1 ↑ 1 - --- --- VOS0P[5] VOS0P[4] VOS0P[3] VOS0P[2] VOS0P[1] VOS0P[0] 1 ↑ 1 - --- --- PKP0[5] PKP0[4] PKP0[3] PKP0[2] PKP0[1] PKP0[0] 1 ↑ 1 - --- --- PKP1[5] PKP1[4] PKP1[3] PKP1[2] PKP1[1] PKP1[0] 1 ↑ 1 - --- --- PKP2[5] PKP2[4] PKP2[3] PKP2[2] PKP2[1] PKP2[0] 1 ↑ 1 - --- --- PKP3[5] PKP3[4] PKP3[3] PKP3[2] PKP3[1] PKP3[0] 1 ↑ 1 - --- --- PKP4[5] PKP4[4] PKP4[3] PKP4[2] PKP4[1] PKP4[0] 1 ↑ 1 - --- --- PKP5[5] PKP5[4] PKP5[3] PKP5[2] PKP5[1] PKP5[0] 1 ↑ 1 - --- --- PKP6[5] PKP6[4] PKP6[3] PKP6[2] PKP6[1] PKP6[0] 1 ↑ 1 - --- --- PKP7[5] PKP7[4] PKP7[3] PKP7[2] PKP7[1] PKP7[0] 1 ↑ 1 - --- --- PKP8[5] PKP8[4] PKP8[3] PKP8[2] PKP8[1] PKP8[0] 1 ↑ 1 --- --- PKP9[5] PKP9[4] PKP9[3] PKP9[2] PKP9[1] PKP9[0] 1 ↑ 1 - --- --- SELV0P[5] SELV0P[4] SELV0P[3] SELV0P[2] SELV0P[1] SELV0P[0] 1 ↑ 1 - --- --- SELV1P[5] SELV1P[4] SELV1P[3] SELV1P[2] SELV1P[1] SELV1P[0] 1 ↑ 1 --- --- SELV62P[5] SELV62P[4] SELV62P[3] SELV62P[2] SELV62P[1] SELV62P[0] 1 ↑ 1 - --- --- SELV63P[5] SELV63P[4] SELV63P[3] SELV63P[2] SELV63P[1] SELV63P[0] 0 ↑ 1 - 1 1 0 0 0 1 1 ↑ 1 - --- --- VRF0N[5] VRF0N[4] VRF0N[3] VRF0N[2] VRF0N[1] VRF0N[0] 1 ↑ 1 - --- --- VOS0N[5] VOS0N[4] VOS0N[3] VOS0N[2] VOS0N[1] VOS0N[0] 1 ↑ 1 - --- --- PKN0[5] PKN0[4] PKN0[3] PKN0[2] PKN0[1] PKN0[0] 1 ↑ 1 - --- --- PKN1[5] PKN1[4] PKN1[3] PKN1[2] PKN1[1] PKN1[0] 1 ↑ 1 - --- --- PKN2[5] PKN2[4] PKN2[3] PKN2[2] PKN2[1] PKN2[0] 1 ↑ 1 - --- --- PKN3[5] PKN3[4] PKN3[3] PKN3[2] PKN3[1] PKN3[0] 1 ↑ 1 - --- --- PKN4[5] PKN4[4] PKN4[3] PKN4[2] PKN4[1] PKN4[0] 1 ↑ 1 - --- --- PKN5[5] PKN5[4] PKN5[3] PKN5[2] PKN5[1] PKN5[0] 1 ↑ 1 - --- --- PKN6[5] PKN6[4] PKN6[3] PKN6[2] PKN6[1] PKN6[0] 1 ↑ 1 - --- --- PKN7[5] PKN7[4] PKN7[3] PKN7[2] PKN7[1] PKN7[0] 1 ↑ 1 - --- --- PKN8[5] PKN8[4] PKN8[3] PKN8[2] PKN8[1] PKN8[0] 1 ↑ 1 - --- --- PKN9[5] PKN9[4] PKN9[3] PKN9[2] PKN9[1] PKN9[0] 1 ↑ 1 - --- --- SELV0N[5] SELV0N[4] SELV0N[3] SELV0N[2] SELV0N[1] SELV0N[0] 1 ↑ 1 - --- --- SELV1N[5] SELV1N[4] SELV1N[3] SELV1N[2] SELV1N[1] SELV1N[0] 1 ↑ 1 - --- --- SELV62N[5] SELV62N[4] SELV62N[3] SELV62N[2] SELV62N[1] SELV62N[0] 1 ↑ 1 - --- --- SELV63N[5] SELV63N[4] SELV63N[3] SELV63N[2] SELV63N[1] SELV63N[0] 1 0 (E0h) Set Gamma adjustment (+ polarity) (E1h) Set Gamma adjustment (- polarity) “-“: Don’t care Note 1: E0-E1 registers are fixed for adjusting Gamma V0.2 125 2009-08-05 ST7735R 10.2.1 FRMCTR1 (B1h): Frame Rate Control (In normal mode/ Full colors) B1H Inst / Para FRMCTR1 (Frame Rate Control) D/CX WRX RDX D17-8 D7 D6 D5 D4 FRMCTR1 D3 D2 D1 D0 HEX 0 ↑ 1 - 1 0 1 1 0 0 1st parameter 1 ↑ 1 - - - - - RTNA3 RTNA2 0 1 (B1h) RTNA1 RTNA0 2nd parameter 1 ↑ 1 - - - FPA5 FPA4 FPA3 FPA2 FPA1 FPA0 3rd parameter 1 ↑ 1 - - - BPA5 BPA4 BPA3 BPA2 BPA1 BPA0 -Set the frame frequency of the full colors normal mode. Description - Frame rate=fosc/((RTNA x 2 + 40) x (LINE + FPA + BPA)) -fosc = 625kHz Status Default Default Value GM[1:0] = “00” GM[1:0] = “11” Power On Sequence 01h/2Ch/2Dh 01h/2Ch/2Bh S/W Reset 01h/2Ch/2Dh 01h/2Ch/2Bh H/W Reset 01h/2Ch/2Dh 01h/2Ch/2Bh Flow Chart V0.2 126 2009-08-05 ST7735R 10.2.2 FRMCTR2 (B2h): Frame Rate Control (In Idle mode/ 8-colors) B2H Inst / Para FRMCTR2 (Frame Rate Control) D/CX WRX RDX FRMCTR2 D17-8 D7 D6 D5 D4 0 ↑ 1st parameter 1 ↑ 2nd parameter 1 3rd parameter 1 D3 D2 D1 D0 HEX 1 - 1 0 1 1 0 0 1 - - - - - RTNB3 RTNB2 1 0 (B2h) RTNB1 RTNB0 ↑ 1 - - - FPB5 FPB4 FPB3 FPB2 FPB1 FPB0 ↑ 1 - - - BPB5 BPB4 BPB3 BPB2 BPB1 BPB0 -Set the frame frequency of the Idle mode. Description - Frame rate=fosc/((RTNB x 2 + 40) x (LINE + FPB + BPB)) -fosc = 625kHz Status Default Default Value GM[1:0] = “00” GM[1:0] = “11” Power On Sequence 01h/2Ch/2Dh 01h/2Ch/2Bh S/W Reset 01h/2Ch/2Dh 01h/2Ch/2Bh H/W Reset 01h/2Ch/2Dh 01h/2Ch/2Bh Flow Chart V0.2 127 2009-08-05 ST7735R 10.2.3 FRMCTR3 (B3h): Frame Rate Control (In Partial mode/ full colors) B3H FRMCTR3 (Frame Rate Control) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HE FRMCTR3 0 ↑ 1 - 1 0 1 1 0 0 1 1 (B3 1st parameter 1 ↑ 1 - - - - - RTNC RTNC RTNC RTNC 2 parameter 1 ↑ 1 - - - FPC5 FPC4 FPC3 FPC2 FPC1 FPC0 3rd parameter 1 ↑ 1 - - - BPC5 BPC4 BPC3 BPC2 BPC1 BPC0 4th parameter nd 1 ↑ 1 - - - - - RTND RTND RTND RTND th 1 ↑ 1 - - - FPD5 FPD4 FPD3 FPD2 FPD1 FPD0 th 1 ↑ 1 - - - BPD5 BPD4 BPD3 BPD2 BPD1 BPD0 5 parameter 6 parameter -Set the frame frequency of the Partial mode/ full colors. - 1st parameter to 3rd parameter are used in dot inversion mode. Description - 4th parameter to 6th parameter are used in line inversion mode. - Frame rate=fosc/((RTNC x 2 + 40) x (LINE + FPC + BPC)) -fosc = 625kHz Status Default Default Value GM[1:0] = “00” GM[1:0] = “11” Power On Sequence 01h/2Ch/2Dh/01h/2Ch/2Dh 01h/2Ch/2Bh/01h/2Ch/2Bh S/W Reset 01h/2Ch/2Dh/01h/2Ch/2Dh 01h/2Ch/2Bh/01h/2Ch/2Bh H/W Reset 01h/2Ch/2Dh/01h/2Ch/2Dh 01h/2Ch/2Bh/01h/2Ch/2Bh Flow Chart V0.2 128 2009-08-05 ST7735R 10.2.4 INVCTR (B4h): Display Inversion Control B4H INVCTR (Display Inversion Control) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX INVCTR 0 ↑ 1 - 1 0 1 1 0 1 0 0 (B4h) Parameter 1 ↑ 1 - 0 0 0 0 0 NLA NLB NLC -Display Inversion mode control -NLA: Inversion setting in full colors normal mode (Normal mode on) NLA Inversion setting in full Colors normal mode 0 Dot Inversion 1 Line Inversion -NLB: Inversion setting in Idle mode (Idle mode on) Description NLB Inversion setting in Idle mode 0 Dot Inversion 1 Line Inversion -NLC: Inversion setting in full colors partial mode (Partial mode on / Idle mode off) NLC Inversion setting in full Colors partial mode 0 Dot Inversion 1 Line Inversion Status Default Value B4h Default Power On Sequence 03h S/W Reset 03h H/W Reset 03h Flow Chart V0.2 129 2009-08-05 ST7735R 10.2.5 PWCTR1 (C0h): Power Control 1 C0H Inst / Para PWCTR1 (Power Control 1) D/CX WRX RDX D17-8 PWCTR1 0 ↑ 1 - 1st parameter 1 ↑ 1 - 2nd parameter 1 ↑ 1 - 1 ↑ 1 - rd 3 parameter V0.2 D6 D5 D4 D3 D2 D1 D0 HEX 1 1 0 0 0 0 0 0 (C0h) AVDD[2] AVDD[1] AVDD[0] VRHP4 VRHP3 VRHP2 VRHP1 VRHP0 0 0 0 MODE[1] MODE[0] 0 VRHN4 VRHN3 VRHN2 VRHN1 VRHN0 0 0 1 0 AVDD[2:0] AVDD MODE[1:0] FUNCTION 000 4.5 00 2X 001 4.6 01 3X 010 4.7 10 AUTO 011 4.8 11 3X 100 4.9 101 5 110 5.1 Don’t use this setting, reserve for testing. 111 Description D7 VRHP[4:0] 00000 GVDD 4.7 VRHN[4:0] 00000 GVCL -4.7 00001 00010 4.65 4.6 00001 00010 -4.65 -4.6 00011 00100 4.55 4.5 00011 00100 -4.55 -4.5 00101 00110 4.45 4.4 00101 00110 -4.45 -4.4 00111 01000 4.35 4.3 00111 01000 -4.35 -4.3 01001 01010 4.25 4.2 01001 01010 -4.25 -4.2 01011 01100 4.15 4.1 01011 01100 -4.15 -4.1 01101 01110 4.05 4 01101 01110 -4.05 -4 01111 10000 3.95 3.9 01111 10000 -3.95 -3.9 10001 10010 3.85 3.8 10001 10010 -3.85 -3.8 10011 10100 3.75 3.7 10011 10100 -3.75 -3.7 10101 10110 3.65 3.6 10101 10110 -3.65 -3.6 10111 11000 3.55 3.5 10111 11000 -3.55 -3.5 11001 11010 3.45 3.4 11001 11010 -3.45 -3.4 11011 11100 3.35 3.3 11011 11100 -3.35 -3.3 11101 11110 3.25 3.2 11101 11110 -3.25 -3.2 11111 3.15 11111 -3.15 130 0 2009-08-05 ST7735R Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Default Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value C0h 82h/02h/84h 82h/02h/84h 82h/02h/84h Flow Chart V0.2 131 2009-08-05 ST7735R 10.2.6 PWCTR2 (C1h): Power Control 2 C1H Inst / Para PWCTR2 (Power Control 2) D/CX WRX RDX D17-8 PWCTR2 0 ↑ 1 1st parameter 1 ↑ 1 - D7 D6 D5 D4 1 1 0 0 - - VGH25[1] VGH25[0] D3 D2 D1 D0 HEX 0 0 0 1 (C1h) VGLSEL[1] VGLSEL[0] VGHBT[1] VGHBT[0] -Set the VGH and VGL supply power level Description Restriction Register Availability V0.2 V25 00 2.1 01 2.2 10 2.3 11 2.4 VGHBT[1:0] VGH 00 2*AVDD+VGH25 01 3*AVDD 10 3*AVDD+VGH25 11 Don’t use this setting, reserve for testing. VGLSEL[1:0] VGL 00 -7.5 01 -10 10 -12.5 11 -13 -The deviation value of VGH/ VGL between with Measurement and Specification: Max <= 1V -VGH-VGL <= 32V Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Default VGH25[1:0] Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value C1h C5h C5h C5h 132 2009-08-05 ST7735R Flow Chart V0.2 133 2009-08-05 ST7735R 10.2.7 PWCTR3 (C2h): Power Control 3 (in Normal mode/ Full colors) C2H Inst / Para PWCTR3 (Power Control 3) D/CX WRX RDX D17-8 PWCTR3 0 ↑ 1 - 1 1 0 1st parameter 1 ↑ 1 - DCA9 DCA8 SAPA2 SAPA1 SAPA0 APA2 1 ↑ 1 - DCA7 DCA6 DCA5 DCA2 DCA1 DCA0 2nd parameter D7 D6 D5 D4 D3 0 0 0 DCA4 DCA3 D2 D1 D0 HEX 1 0 (C2h) APA1 APA0 -Set the amount of current in Operational amplifier in normal mode/full colors. -Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver. AP[2:0] Amount of Current in Operational Amplifier Operation of the operational amplifier stops 000 Description 001 Small 010 011 Medium Low Medium 100 101 Medium High Large 110 111 Reserved Reserved SAP[2:0] 000 Amount of Current in Operational Amplifier Operation of the operational amplifier stops 001 010 Small Medium Low 011 100 Medium Medium High 101 110 Large Reserved 111 Reserved -Set the Booster circuit Step-up cycle in Normal mode/ full colors. DCA[9:8] DCA[7:6] DCA[5:4] DCA[3:2] DCA[1:0] 00 BCLK/1 BCLK/1 BCLK/1 BCLK/1 BCLK/1 01 BCLK/1.5 BCLK/1.5 BCLK/1.5 BCLK/1.5 BCLK/1.5 10 BCLK/2 BCLK/2 BCLK/2 BCLK/2 BCLK/2 11 BCLK/4 BCLK/4 BCLK/4 BCLK/4 BCLK/4 Note: BCLK is Clock frequency for Booster circuit Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Default V0.2 Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value C2h 0Ah/00h 0A h/00h 0A h/00h 134 2009-08-05 ST7735R Flow Chart V0.2 135 2009-08-05 ST7735R 10.2.8 PWCTR4 (C3h): Power Control 4 (in Idle mode/ 8-colors) C3H Inst / Para PWCTR4 (Power Control 4) D/CX WRX RDX D17-8 PWCTR4 0 ↑ 1 - 1 1 0 1st parameter 1 ↑ 1 - DCB9 DCB8 SAPB2 SAPB1 SAPB0 APB2 1 ↑ 1 - DCB7 DCB6 DCB5 DCB2 DCB1 DCB0 2nd parameter D7 D6 D5 D4 D3 0 0 0 DCB4 DCB3 D2 D1 D0 HEX 1 1 (C3h) APB1 APB0 -Set the amount of current in Operational amplifier in Idle mode/8 colors. -Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver. AP[2:0] Amount of Current in Operational Amplifier Operation of the operational amplifier stops 000 Description 001 Small 010 011 Medium Low Medium 100 101 Medium High Large 110 111 Reserved Reserved SAP[2:0] 000 Amount of Current in Operational Amplifier Operation of the operational amplifier stops 001 010 Small Medium Low 011 100 Medium Medium High 101 110 Large Reserved 111 Reserved -Set the Booster circuit Step-up cycle in Idle mode/8 colors. DCB[9:8] DCB[7:6] DCB[5:4] DCB[3:2] DCB[1:0] 00 01 BCLK/1 BCLK/1.5 BCLK/1 BCLK/1.5 BCLK/1 BCLK/1.5 BCLK/1 BCLK/1.5 BCLK/1 BCLK/1.5 10 11 BCLK/2 BCLK/4 BCLK/2 BCLK/4 BCLK/2 BCLK/4 BCLK/2 BCLK/4 BCLK/2 BCLK/4 Note: BCLK is Clock frequency for Booster circuit Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Default V0.2 Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value C3h 8Ah/2Eh 8Ah/2Eh 8Ah/2Eh 136 2009-08-05 ST7735R Flow Chart V0.2 137 2009-08-05 ST7735R 10.2.9 PWCTR5 (C4h): Power Control 5 (in Partial mode/ full-colors) C4H Inst / Para PWCTR5 (Power Control 5) D/CX WRX RDX D17-8 PWCTR5 0 ↑ 1 - 1 1 1 1st parameter 1 ↑ 1 - DCC9 DCC8 SAPC2 SAPC1 SAPC0 APC2 1 ↑ 1 - DCC7 DCC6 DCC5 DCC2 DCC1 DCC0 2nd parameter D7 D6 D5 D4 D3 0 0 0 DCC4 DCC3 D2 D1 D0 HEX 0 0 (C4h) APC1 APC0 -Set the amount of current in Operational amplifier in Partial mode/ full-colors. -Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver. AP[2:0] Amount of Current in Operational Amplifier Operation of the operational amplifier stops 000 Description 001 Small 010 011 Medium Low Medium 100 101 Medium High Large 110 111 Reserved Reserved SAP[2:0] 000 Amount of Current in Operational Amplifier Operation of the operational amplifier stops 001 010 Small Medium Low 011 100 Medium Medium High 101 110 Large Reserved 111 Reserved -Set the Booster circuit Step-up cycle in Partial mode/ full-colors. DCC[9:8] DCC[7:6] DCC[5:4] DCC[3:2] DCC[1:0] 00 BCLK/1 BCLK/1 BCLK/1 BCLK/1 BCLK/1 01 10 BCLK/1.5 BCLK/2 BCLK/1.5 BCLK/2 BCLK/1.5 BCLK/2 BCLK/1.5 BCLK/2 BCLK/1.5 BCLK/2 11 BCLK/4 BCLK/4 BCLK/4 BCLK/4 BCLK/4 Note: BCLK is Clock frequency for Booster circuit Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Default V0.2 Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value C4h 8Ah/AAh 8Ah/AAh 8Ah/AAh 138 2009-08-05 ST7735R Legend Command Parameter PWCTR5 Display Flow Chart 1st Parameter 2nd parameter Action Mode Sequential transter V0.2 139 2009-08-05 ST7735R 10.2.10 VMCTR1 (C5h): VCOM Control 1 C5H VMCTR1 (VCOM Control 1) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX VMCTR1 0 ↑ 1 - 1 1 0 0 0 1 0 1 (C5h) 1st parameter 1 ↑ 1 - - - VCOMS5 VCOMS 4 VCOMS 3 VCOMS 2 VCOMS 1 VCOMS 0 VCOM voltage setting. Description Register Availability VCOMS [5:0] VCOM VCOMS [5:0] VCOM VCOMS [5:0] VCOM VCOMS [5:0] VCOM 0 000000 -0.425 16 010000 -0.825 32 100000 -1.225 48 110000 -1.625 1 000001 -0.45 17 010001 -0.85 33 100001 -1.25 49 110001 -1.65 2 000010 -0.475 18 010010 -0.875 34 100010 -1.275 50 110010 -1.675 3 000011 -0.5 19 010011 -0.9 35 100011 -1.3 51 110011 -1.7 4 000100 -0.525 20 010100 -0.925 36 100100 -1.325 52 110100 -1.725 5 000101 -0.55 21 010101 -0.95 37 100101 -1.35 53 110101 -1.75 6 000110 -0.575 22 010110 -0.975 38 100110 -1.375 54 110110 -1.775 7 000111 -0.6 23 010111 -1 39 100111 -1.4 55 110111 -1.8 8 001000 -0.625 24 011000 -1.025 40 101000 -1.425 56 111000 -1.825 9 001001 -0.65 25 011001 -1.05 41 101001 -1.45 57 111001 -1.85 10 001010 -0.675 26 011010 -1.075 42 101010 -1.475 58 111010 -1.875 11 001011 -0.7 27 011011 -1.1 43 101011 -1.5 59 111011 -1.9 12 001100 -0.725 28 011100 -1.125 44 101100 -1.525 60 111100 -1.925 13 001101 -0.75 29 011101 -1.15 45 101101 -1.55 61 111101 -1.95 14 001110 -0.775 30 011110 -1.175 46 101110 -1.575 62 111110 -1.975 15 001111 -0.8 31 011111 -1.2 47 101111 -1.6 63 111111 -2 Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Default V0.2 Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value C5h 04h 04h 04h 140 2009-08-05 ST7735R Flow Chart V0.2 141 2009-08-05 ST7735R 10.2.11 VMOFCTR (C7h): VCOM Offset Control C7H VMOFCTR (VCOM Offset Control) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 VMOFCTR 0 ↑ 1 - 1 1 0 0 0 1 Parameter 1 ↑ 1 - - - - VMF4 VMF3 VMF2 D4 D3 D2 D1 D0 HEX 1 1 (C7h) VMF1 VMF0 -Set VCOM Voltage level for reduce the flicker issue -Before use command 0xC7, the bit VMF_EN of command 0xD9 must be enabled (set to 1). Description VMF[4] VMF[3:0] VCOM Output Level 0 0000 “VCOMS”-16d 0 0001 “VCOMS”-15d 0 | | 0 1110 “VCOMS”-2d 0 1111 “VCOMS”-1d 1 0000 “VCOMS” 1 0001 “VCOMS”+1d 1 0010 “VCOMS”+2d 1 | | 1 1110 “VCOMS”+14d 1 1111 “VCOMS”+15d - 1d=25mV, 2d=50mV 3d=75mv.... Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Default Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value C7h 10h 10h 10h Flow Chart V0.2 142 2009-08-05 ST7735R 10.2.12 WRID2 (D1h): Write ID2 Value D1H Inst / Para WRID2 (Write ID2 Value) D/CX WRX WRID2 0 ↑ Parameter 1 ↑ RDX D17-8 D7 D6 D5 D4 D3 D2 1 - 1 1 0 1 0 0 1 - - ID26 ID25 ID24 ID23 ID22 D1 D0 HEX 0 1 (D1h) ID21 ID20 - -Write 7-bit data of LCD module version to save it to NVM. Description -The parameter ID2[6:0] is LCD Module version ID. Flow Chart V0.2 143 2009-08-05 ST7735R 10.2.13 WRID3 (D2h): Write ID3 Value D2H WRID3 (Write ID3 Value) Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX WRID3 0 ↑ 1 - 1 1 0 1 0 0 1 0 (D2h) Parameter 1 ↑ 1 - ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 - Description -Write 8-bit data of project code module to save it to NVM. -The parameter ID3[7:0] is product project ID. Flow Chart V0.2 144 2009-08-05 ST7735R 10.2.14 NVFCTR1 (D9h): NVM Control Status D9H NVFCTR1 (NV Memory Function Controller 1) Inst / Para D/CX NVFCTR1 parameter WRX RDX D17-8 D7 0 ↑ 1 - 1 1 1 ↑ - 0 D6 D5 1 0 VMF_EN ID2_EN D4 D3 D2 D1 D0 HEX (D9h) 0 1 0 0 1 0 0 0 0 EXT_R -NVM control status Description Bit Value VMF_EN “1” = Command C7h enable ; “0” = Command C7h disable ID2_EN “1” = Command D1h enable ; “0” = Command D1h disable EXT_R Read: extension command status, “1” for enable, “0” for disable. Write: Don’t care Status Default Value D9h Default Power On Sequence 00h S/W Reset 00h H/W Reset 00h Flow Chart V0.2 145 2009-08-05 ST7735R 10.2.15 NVFCTR2 (DEh): NVM Read Command DEH Inst / Para NVFCTR1 (NV Memory Function Controller 2) D/CX WRX RDX D17-8 NVFCTR2 0 ↑ 1 - 1 1 0 1 1 1 1st parameter 1 ↑ 1 1 1 1 1 0 1 1 ↑ 1 1 0 1 0 0 1 0 nd 2 parameter D7 D6 D5 D4 D3 D2 D1 D0 HEX 1 0 (DEh) 0 1 F5 1 A5 NVM Read Command Description NOTE: “-“ Don’t care Flow Chart V0.2 146 2009-08-05 ST7735R 10.2.16 NVFCTR3 (DFh): NVM Write Command DFH Inst / Para NVFCTR1 (NV Memory Function Controller 3 D/CX WRX RDX D17-8 NVFCTR1 0 ↑ 1 1st parameter 1 ↑ 1 1 ↑ 1 2nd parameter D7 D6 D5 D4 D3 D2 1 1 0 1 1 1 - NVM_CMD7 NVM_CMD6 NVM_CMD5 NVM_CMD4 NVM_CMD3 NVM_CMD2 1 0 1 0 0 1 D1 D0 HEX (DFh) 1 1 NVM_CMD1 NVM_CMD0 0 1 A5 -NVM Write Command Description -NVM_CMD[7:0] : Select to Program/Erase ; Program command : 3Ah ; Erase command : C5h NOTE: “-“ Don’t care NVM Program Flow Legend Wait 20ms Modify CMD register (C7h/D1h/D2h) Command Program CMD DFh 1st Para 3Ah 2nd Para A5h Parameter Display Flow Chart Enable NVM : EXTC = “1” CMD F1h, 44h External VPP = 7.5V ON Wait 20ms Erase CMD DFh 1st Para C5h 2nd Para A5h V0.2 Disable NVM : EXTC = “0” CMD F1h, 04h External VPP = 7.5V OFF 147 Action Mode Sequential transter 2009-08-05 ST7735R 10.2.17 GMCTRP1 (E0h): Gamma (‘+’polarity) Correction Characteristics Setting E0H Inst / Para GMCTRP0 (Gamma ‘+’polarity Correction Characteristics Setting) D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 0 (E0h) VRF0P[1] VRF0P[0] GMCTRP1 0 ↑ 1 - 1 1 1 0 0 0 1st parameter 1 ↑ 1 - - - VRF0P[5] VRF0P[4] VF0P[3] VRF0P[2] 2nd parameter 1 ↑ 1 - - - VOS0P[5] VOS0P[4] VOS0P[3] VOS0P[2] VOS0P[1] VOS0P[0] 3rd parameter 1 ↑ 1 - - - PK0P[5] PK0P[4] PK0P[3] PK0P[2] PK0P[1] PK0P[0] 4 parameter 1 ↑ 1 - - - PK1P[5] PK1P[4] PK1P[3] PK1P[2] PK1P[1] PK1P[0] 5th parameter 1 ↑ 1 - - - PK2P[5] PK2P[4] PK2P[3] PK2P[2] PK2P[1] PK2P[0] 6 parameter 1 ↑ 1 - - - PK3P[5] PK3P[4] PK3P[3] PK3P[2] PK3P[1] PK3P[0] 7th parameter 1 ↑ 1 - - - PK4P[5] PK4P[4] PK4P[3] PK4P[2] PK4P[1] PK4P[0] 8 parameter 1 ↑ 1 - - - PK5P[5] PK5P[4] PK5P[3] PK5P[2] PK5P[1] PK5P[0] 9th parameter 1 ↑ 1 - - - PK6P[5] PK6P[4] PK6P[3] PK6P[2] PK6P[1] PK6P[0] 10th parameter 1 ↑ 1 - - - PK7P[5] PK7P[4] PK7P[3] PK7P[2] PK7P[1] PK7P[0] 11 parameter 1 ↑ 1 - - - PK8P[5] PK8P[4] PK8P[3] PK8P[2] PK8P[1] PK8P[0] 12th parameter 1 ↑ 1 - - - PK9P[5] PK9P[4] PK9P[3] PK9P[2] PK9P[1] PK9P[0] 13 parameter 1 ↑ 1 - - - SELV0P[5] SELV0P[4] SELV0P[3] SELV0P[2] SELV0P[1] SELV0P[0] 14th parameter 1 ↑ 1 - - - SELV1P[5] SELV1P[4] SELV1P[3] SELV1P[2] SELV1P[1] SELV1P[0] 15 parameter 1 ↑ 1 - - - SELV62P[5] SELV62P[4] SELV62P[3] SELV62P[2] SELV62P[1] SELV62P[0] 16th parameter 1 ↑ 1 - - - SELV63P[5] SELV63P[4] SELV63P[3] SELV63P[2] SELV63P[1] SELV63P[0] th th th th th th Description Register Group Positive Polarity Set-up Contents High level adjustment VRF0P[5:0] Variable resistor VRHP SELV0P[5:0] The voltage of V0 grayscale is selected by the 64 to 1 selector SELV1P[5:0] The voltage of V1 grayscale is selected by the 64 to 1 selector PK0P[5:0] The voltage of V3 grayscale is selected by the 64 to 1 selector PK1P[5:0] The voltage of V4 grayscale is selected by the 64 to 1 selector PK2P[5:0] The voltage of V12 grayscale is selected by the 64 to 1 selector PK3P[5:0] The voltage of V20 grayscale is selected by the 64 to 1 selector PK4P[5:0] The voltage of V28 grayscale is selected by the 64 to 1 selector PK5P[5:0] The voltage of V36 grayscale is selected by the 64 to 1 selector PK6P[5:0] The voltage of V44 grayscale is selected by the 64 to 1 selector PK7P[5:0] The voltage of V52 grayscale is selected by the 64 to 1 selector PK8P[5:0] The voltage of V56 grayscale is selected by the 64 to 1 selector PK9P[5:0] The voltage of V60 grayscale is selected by the 64 to 1 selector SELV62P[5:0] The voltage of V62 grayscale is selected by the 64 to 1 selector SELV63P[5:0] The voltage of V63 grayscale is selected by the 64 to 1 selector VOS0P[5:0] Variable resistor VRLP Mid level adjustment Low level adjustment V0.2 148 2009-08-05 ST7735R Flow Chart V0.2 149 2009-08-05 ST7735R 10.2.18 GMCTRN1 (E1h): Gamma ‘-’polarity Correction Characteristics Setting E1H Inst / Para GMCTRP0 (Gamma ‘+’polarity Correction Characteristics Setting) D/CX WRX RDX D17-8 D7 D6 - 1 1 1 0 0 0 - - - VRF0N[5] VRF0N[4] VF0N[3] VRF0N[2] 1 - - - VOS0N[5] VOS0N[4] VOS0N[3] VOS0N[2] VOS0N[1] VOS0N[0] 1 - - - PK0N[5] PK0N[4] PK0N[3] PK0N[2] PK0N[1] PK0N[0] ↑ 1 - - - PK1N[5] PK1N[4] PK1N[3] PK1N[2] PK1N[1] PK1N[0] ↑ 1 - - - PK2N[5] PK2N[4] PK2N[3] PK2N[2] PK2N[1] PK2N[0] 1 ↑ 1 - - - PK3N[5] PK3N[4] PK3N[3] PK3N[2] PK3N[1] PK3N[0] 1 ↑ 1 - - - PK4N[5] PK4N[4] PK4N[3] PK4N[2] PK4N[1] PK4N[0] 8 parameter 1 ↑ 1 - - - PK5N[5] PK5N[4] PK5N[3] PK5N[2] PK5N[1] PK5N[0] 9th parameter 1 ↑ 1 - - - PK6N[5] PK6N[4] PK6N[3] PK6N[2] PK6N[1] PK6N[0] 10th parameter 1 ↑ 1 - - - PK7N[5] PK7N[4] PK7N[3] PK7N[2] PK7N[1] PK7N[0] 11 parameter 1 ↑ 1 - - - PK8N[5] PK8N[4] PK8N[3] PK8N[2] PK8N[1] PK8N[0] 12th parameter 1 ↑ 1 - - - PK9[5] PK9N[4] PK9N[3] PK9N[2] PK9N[1] PK9N[0] 13 parameter 1 ↑ 1 - - - SELV0N[5] SELV0N[4] SELV0N[3] SELV0N[2] SELV0N[1] SELV0N[0] 14th parameter 1 ↑ 1 - - - SELV1N[5] SELV1N[4] SELV1N[3] SELV1N[2] SELV1N[1] SELV1N[0] 15 parameter 1 ↑ 1 - - - SELV62N[5] SELV62N[4] SELV62N[3] SELV62N[2] SELV62N[1] SELV62N[0] 16th parameter 1 ↑ 1 - - - SELV63N[5] SELV63N[4] SELV63N[3] SELV63N[2] SELV63N[1] SELV63N[0] GMCTRP1 0 ↑ 1 1st parameter 1 ↑ 1 2nd parameter 1 ↑ 3rd parameter 1 ↑ 4 parameter 1 5th parameter 1 6 parameter 7th parameter th th th th th th Description D4 D3 D2 D1 D0 HEX 0 1 (E1h) VRF0N[1] VRF0N[0] Register Group Negative Polarity Set-up Contents High level adjustment VRF0N[5:0] Variable resistor VRHN SELV0N[5:0] The voltage of V0 grayscale is selected by the 64 to 1 selector SELV1N[5:0] The voltage of V1 grayscale is selected by the 64 to 1 selector PK0N[5:0] The voltage of V3 grayscale is selected by the 64 to 1 selector PK1N[5:0] The voltage of V4 grayscale is selected by the 64 to 1 selector PK2N[5:0] The voltage of V12 grayscale is selected by the 64 to 1 selector PK3N[5:0] The voltage of V20 grayscale is selected by the 64 to 1 selector PK4N[5:0] The voltage of V28 grayscale is selected by the 64 to 1 selector PK5N[5:0] The voltage of V36 grayscale is selected by the 64 to 1 selector PK6N[5:0] The voltage of V44 grayscale is selected by the 64 to 1 selector PK7N[5:0] The voltage of V52 grayscale is selected by the 64 to 1 selector PK8N[5:0] The voltage of V56 grayscale is selected by the 64 to 1 selector PK9N[5:0] The voltage of V60 grayscale is selected by the 64 to 1 selector SELV62N[5:0] The voltage of V62 grayscale is selected by the 64 to 1 selector SELV63N[5:0] The voltage of V63 grayscale is selected by the 64 to 1 selector VOS0N[5:0] Variable resistor VRLN Mid level adjustment Low level adjustment V0.2 D5 150 2009-08-05 ST7735R Legend Command Parameter GMCTRN1 Display Flow Chart 1st Parameter 2nd Parameter | Action Mode Sequential transter V0.2 151 2009-08-05 ST7735R 11 Power Structure 11.1 Driver IC Operating Voltage Specification Fig 11.1.1 Power Booster Level V0.2 152 2009-08-05 ST7735R 11.2 Power Booster Circuit Source Output Circuit Block VDD S1 | S 396 REGP Reference Voltage generator AVDD Gray reference Circuit Block ( Gamma ) Vci1 AVDD REGP GVDD REGP AGND AGND AVCL VDD REGP Charge Pump 1 VCOM AVDD C AVDD AGND Vci1 Charge Pump 2 VGH VDD Gate Driver VGL G1 | G 162 Charge Pump 4 AVCL Reference Voltage generator CVCL V0.2 153 VDDI 2009-08-05 ST7735R 11.2.1 EXTERNAL COMPONENTS CONNECTION Pad Name V0.2 Rated (Min) Typical Voltage capacitance value Connection AVDD Connect to Capacitor: AVDD -------||-------- GND 6.3V 1.0 uF AVCL Connect to Capacitor: AVCL -------||-------- GND 6.3V 1.0 uF 154 2009-08-05 ST7735R 12 Gamma structure 12.1 TRUCTURE OF GRAYSCALE AMPLIFIER 16 voltage levels (VIN0-VIN15) between GVDD and VSS are determined by the high/ mid/ low level adjustment registers. Each mid-adjustment level is split into 64 levels again by the internal ladder resistor network. As a result, grayscale amplifier generates 64 voltage levels ranging from V0 to V63 and outputs one of 64 levels. 12.2 Gamma Voltage Formula (Positive/ Negative Polarity) V0.2 Gray Level Voltage Formula (Positive) Voltage Formula (Negative) 0 VINP0 VINP0 1 VINP1 VINP1 2 VINP2 VINP2 3 VINP3 VINP3 4 VINP4 VINP4 5 V4-(V4-V12)*(4/32) V4-(V4-V12)*(4/32) 6 V4-(V4-V12)*(8/32) V4-(V4-V12)*(8/32) 7 V4-(V4-V12)*(12/32) V4-(V4-V12)*(12/32) 8 V4-(V4-V12)*(16/32) V4-(V4-V12)*(16/32) 9 V4-(V4-V12)*(20/32) V4-(V4-V12)*(20/32) 10 V4-(V4-V12)*(24/32) V4-(V4-V12)*(24/32) 11 V4-(V4-V12)*(28/32) V4-(V4-V12)*(28/32) 12 VINP5 VINP5 13 V12-(V12-V20)*(4/32) V12-(V12-V20)*(4/32) 14 V12-(V12-V20)*(8/32) V12-(V12-V20)*(8/32) 15 V12-(V12-V20)*(12/32) V12-(V12-V20)*(12/32) 16 V12-(V12-V20)*(16/32) V12-(V12-V20)*(16/32) 17 V12-(V12-V20)*(20/32) V12-(V12-V20)*(20/32) 18 V12-(V12-V20)*(24/32) V12-(V12-V20)*(24/32) 19 V12-(V12-V20)*(28/32) V12-(V12-V20)*(28/32) 20 VINP6 VINP6 21 V20-(V20-V28)*(4/32) V20-(V20-V28)*(4/32) 22 V20-(V20-V28)*(8/32) V20-(V20-V28)*(8/32) 23 V20-(V20-V28)*(12/32) V20-(V20-V28)*(12/32) 24 V20-(V20-V28)*(16/32) V20-(V20-V28)*(16/32) 25 V20-(V20-V28)*(20/32) V20-(V20-V28)*(20/32) 26 V20-(V20-V28)*(24/32) V20-(V20-V28)*(24/32) 27 V20-(V20-V28)*(28/32) V20-(V20-V28)*(28/32) 28 VINP7 VINP7 29 V28-(V28-V36)* (4/32) V28-(V28-V36)* (4/32) 30 V28-(V28-V36)* (8/32) V28-(V28-V36)* (8/32) 31 V28-(V28-V36)* (12/32) V28-(V28-V36)* (12/32) 32 V28-(V28-V36)* (16/32) V28-(V28-V36)* (16/32) 33 V28-(V28-V36)* (20/32) V28-(V28-V36)* (20/32) 34 V28-(V28-V36)* (24/32) V28-(V28-V36)* (24/32) 35 V28-(V28-V36)* (28/32) V28-(V28-V36)* (28/32) 155 2009-08-05 ST7735R V0.2 36 VINP8 VINP8 37 V36-(V36-V44)*(4/32) V36-(V36-V44)*(4/32) 38 V36-(V36-V44)*(8/32) V36-(V36-V44)*(8/32) 39 V36-(V36-V44)*(12/32) V36-(V36-V44)*(12/32) 40 V36-(V36-V44)*(16/32) V36-(V36-V44)*(16/32) 41 V36-(V36-V44)*(20/32) V36-(V36-V44)*(20/32) 42 V36-(V36-V44)*(24/32) V36-(V36-V44)*(24/32) 43 V36-(V36-V44)*(28/32) V36-(V36-V44)*(28/32) 44 VINP9 VINP9 45 V44-(V44-V52)*(4/32) V44-(V44-V52)*(4/32) 46 V44-(V44-V52)*(8/32) V44-(V44-V52)*(8/32) 47 V44-(V44-V52)*(12/32) V44-(V44-V52)*(12/32) 48 V44-(V44-V52)*(16/32) V44-(V44-V52)*(16/32) 49 V44-(V44-V52)*(20/32) V44-(V44-V52)*(20/32) 50 V44-(V44-V52)*(24/32) V44-(V44-V52)*(24/32) 51 V44-(V44-V52)*(28/32) V44-(V44-V52)*(28/32) 52 VINP10 VINP10 53 V52-(V52-V56)*(1/4) V52-(V52-V56)*(1/4) 54 V52-(V52-V56)*(2/4) V52-(V52-V56)*(2/4) 55 V52-(V52-V56)*(3/4) V52-(V52-V56)*(3/4) 56 VINP11 VINP11 57 V56-(V56-V60)*(1/4) V56-(V56-V60)*(1/4) 58 V56-(V56-V60)*(2/4) V56-(V56-V60)*(2/4) 59 V56-(V56-V60)*(3/4) V56-(V56-V60)*(3/4) 60 VINP12 VINP12 61 VINP13 VINP13 62 VINP14 VINP14 63 VINP15 VINP15 156 2009-08-05 ST7735R 13 Example Connection with Panel direction and Different Resolution 13.1 Application of connection with panel direction Case 1: (This is default case) st - 1 Pixel is at Left Top of the panel - RGB filter order = RGB 1st pixel IC (Bump down) LCD Front side CF Glass TFT Glass Case 2: st - 1 Pixel is at Left Top of the panel - RGB filter order = BGR 1st pixel IC (Bump down) LCD Front side CF Glass TFT Glass V0.2 157 2009-08-05 ST7735R Case 3: st - 1 Pixel is at Right Bottom of the panel - RGB filter order = RGB IC (Bump down) LCD Front side CF Glass 1st pixel TFT Glass Case 4: st - 1 Pixel is at Right Bottom of the panel - RGB filter order = BGR IC (Bump down) LCD Front side CF Glass 1st pixel TFT Glass V0.2 158 2009-08-05 ST7735R 13.2 Application of connection with Different resolution Case1 of Resolution (128RGB x 160) (GM[1:0] = “11”) RAM size=128 x 160 x 18-bit (Used) Display size = 128RGB x 160 1). Example for SMX=SMY=’0’ Driver IC G161 00h 01h 02h 7Eh 7Fh 83h G3 P1 P2 S7 P3 (bump down) S390 G2 G160 P126 P127 P128 00h G1 01h G2 02h G3 G4 G157 G158 G159 9Fh G160 A1h - Display direction control (S/W) - X-Mirror control by MX - Y-Mirror control by MY - XY-Exchange control by MV - Direction default setting (H/W) SMX = '0' SMY = '0' SRGB = '0' 2). Example for SMX=SMY=’1’ Driver IC G161 00h 01h 02h 7Eh 7Fh 83h G3 P1 P2 S7 P3 (bump down) S390 P126 G2 P127 00h G160 P128 G1 01h G2 02h G3 G4 G157 G158 G159 9Fh G160 A1h - Display direction control (S/W) - X-Mirror control by MX - Y-Mirror control by MY - XY-Exchange control by MV V0.2 - Direction default setting (H/W) SMX = '1' SMY = ' 1' SRGB = '0' 159 2009-08-05 ST7735R Case2 of Resolution (132RGB x 162) (GM[1:0] = “00”) RAM size=132 x 162 x 18-bit (Used) Display size = 132RGB x 162 1). Example for SMX=SMY=’0’ 2). Example for SMX=SMY=’1’ V0.2 160 2009-08-05 ST7735R 13.3 Microprocessor Interface applications 13.3.1 8080-Series MCU Interface for 8-bit data bus (P68=0, IM2, IM1, IM0=”100”) 80 Serial MPU 8-Bit Bus VDDI GND MPU RESX CSX D/CX RDX WRX D7 to D0 GND ST7735R SPI4W IM2 IM1 IM0 RESX CSX D/CX (SCL) RDX (E) WRX (R/WX) D7 to D0 D17 to D8 P68 13.3.2 8080-Series MCU Interface for 16-bit data bus (P68=0, IM2, IM1, IM0=”101”) 80 Serial MPU 16-Bit Bus VDDI GND MPU RESX CSX D/CX RDX WRX D15 to D0 GND ST7735R SPI4W IM2 IM1 IM0 RESX CSX D/CX (SCL) RDX (E) WRX (R/WX) D15 to D0 D17 to D16 P68 13.3.3 8080-Series MCU Interface for 9-bit data bus (P68=0, IM2, IM1, IM0=”110”) 80 Serial MPU 9-Bit Bus VDDI MPU GND RESX CSX D/CX RDX WRX D8 to D0 GND V0.2 ST7735R SPI4W IM2 IM1 IM0 RESX CSX D/CX (SCL) RDX (E) WRX (R/WX) D9 to D0 D17 to D9 P68 161 2009-08-05 ST7735R 13.3.4 8080-Series MCU Interface for 18-bit data bus (P68=0, IM2, IM1, IM0=”111”) 80 Serial MPU 18-Bit Bus VDDI ST7735R GND MPU SPI4W IM2 IM1 IM0 RESX CSX D/CX (SCL) RDX (E) WRX (R/WX) D17 to D0 RESX CSX D/CX RDX WRX D17 to D0 P68 GND 13.3.5 6800-Series MCU Interface for 8-bit data bus (P68=1, IM2, IM1, IM0=”100”) 68 Serial MPU 8-Bit Bus VDDI GND MPU ST7735R SPI4W IM2 IM1 IM0 RESX CSX D/CX (SCL) RDX (E) WRX (R/WX) D7 to D0 D17 to D8 RESX CSX D/CX E R/WX D7 to D0 GND VDDI P68 13.3.6 6800-Series MCU Interface for 16-bit data bus (P68=1, IM2, IM1, IM0=”101”) 68 Serial MPU 16-Bit Bus VDDI GND MPU RESX CSX D/CX E R/WX D15 to D0 GND VDDI V0.2 ST7735R SPI4W IM2 IM1 IM0 RESX CSX D/CX (SCL) RDX (E) WRX (R/WX) D15 to D0 D17 to D16 P68 162 2009-08-05 ST7735R 13.3.7 6800-Series MCU Interface for 9-bit data bus (P68=1, IM2, IM1, IM0=”110”) 68 Serial MPU 9-Bit Bus VDDI MPU ST7735R GND SPI4W IM2 IM1 IM0 RESX CSX D/CX (SCL) RDX (E) WRX (R/WX) D7 to D0 D17 to D9 RESX CSX D/CX E R/WX D8 to D0 GND VDDI P68 13.3.8 6800-Series MCU Interface for 18-bit data bus (P68=1, IM2, IM1, IM0=”111”) 68 Serial MPU 18-Bit Bus VDDI MPU GND RESX CSX D/CX E R/WX D17 to D0 ST7735R SPI4W IM2 IM1 IM0 RESX CSX D/CX (SCL) RDX (E) WRX (R/WX) D17 to D0 P68 VDDI 13.3.9 3-Line serial MCU Interface (IM2, IM1, IM0=”000”, SPI4W=0) 3-Pin Serial Mode ST7735R GND MPU RESX CSX GND SCL SDA SPI4W IM2 IM1 IM0 RESX CSX RDX,WRX D/CX (SCL) SDA(D0) D17 to D1 GND 13.3.10 4-Line serial MCU Interface (IM2, IM1, IM0=”000”, SPI4W=1) 4-Pin Serial Mode VDDI GND MPU RESX CSX GND D/CX SCL SDA GND V0.2 163 ST7735R SPI4W IM2 IM1 IM0 RESX CSX RDX WRX(D/CX) D/CX (SCL) SDA(D0) D17 to D1 2009-08-05 ST7735R 14 Revision History ST7735R Specification Revision History Version Date V0.1 2009/07/10 First issue. 2009/08/05 Modify VGH, VGL PAD location (P7) Add TESEL pin description. (P16) Modify command DFh (P147) Modify AVDD range 4.5~5.1 (P152) V0.2 V0.2 Description 164 2009-08-05