STMICROELECTRONICS STS8C5H30L_0707

STS8C5H30L
N-channel 30V - 0.018 Ω - 8A/p-channel 30V - 0.045 Ω - 5A - SO-8
Low gate charge STripFET™ III MOSFET
Features
Type
VDSS
RDS(on)
ID
STS8C5H30L(N-channel)
30V
<0.022
8A
STS8C5H30L(P-channel)
30V
<0.056
5A
■
Conduction losses reduced
■
Switching losses reduced
■
Low threshold drive
■
Standard outline for easy automated surface
mount assembly
S0-8
SO-8
Description
This Power MOSFET is the latest development of
STMicroelectronics unique "Single Feature
Size™" strip-based process. The resulting
transistor shows extremely high packing density
for low on-resistance, rugged avalanche
characteristics and less critical alignment steps
therefore a remarkable manufacturing
reproducibility.
Figure 1.
Internal schematic diagram
Application
■
Switching application
Table 1.
Device summary
Part number
Marking
Package
Packaging
STS8C5H30L
S8C5H30L
SO-8
Tape & reel
Note:
July 2007
For the P-channel MOSFET actual polarity of voltages and current has to be reversed
Rev 4
1/14
www.st.com
14
Contents
STS8C5H30L
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................ 6
3
Test circuit
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2/14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
STS8C5H30L
1
Electrical ratings
Electrical ratings
Table 2.
Absolute maximum ratings
Value
Symbol
Parameter
Unit
N-channel
VDS
Drain-source voltage (vgs = 0)
VGS
Gate- source voltage
P-channel
30
V
±16
±16
V
ID
Drain current (continuos) at TC = 25°C
single operating
8
4.2
A
ID
Drain current (continuos) at TC = 100°C
single operating
6.4
3.1
A
IDM (1)
Drain current (pulsed)
32
16.8
A
PTOT
Total dissipation at TC = 25°C dual operating
Total dissipation at TC = 25°C single operating
Tstg
Storage temperature
Tj
1.6
2
W
W
-55 to 150
°C
150
°C
Thermal resistance junction-ambient single
operating
Thermal resistance junction-ambient dual
operating
62.5
°C/W
78
°C/W
Maximum lead temperature for soldering purpose
300
°C
Operating junction temperature
1. Pulse width limited by safe operating area
Table 3.
Rthj-a
Tl
Note:
Thermal data
For the P-channel MOSFET actual polarity of voltages and current has to be reversed
3/14
Electrical characteristics
2
STS8C5H30L
Electrical characteristics
(TCASE=25°C unless otherwise specified)
Table 4.
On/off states
Symbol
Parameter
Test conditions
Min.
V(BR)DSS
Drain-source
Breakdown voltage
ID = 250 µA, VGS = 0
n-ch
p-ch
VDS = Max rating
n-ch
1
µA
VDS=Max rating,
TC=125°C
p-ch
10
µA
±100
±100
nA
nA
1.6
2.5
V
V
0.018
0.045
0.020
0.070
0.022
0.055
0.025
0.075
Ω
Ω
Ω
Ω
Typ.
Max.
Unit
IDSS
Zero gate voltage
Drain current (VGS = 0)
IGSS
Gate-body leakage
current (VDS = 0)
VGS = ±16V
VGS = ±16V
n-ch
p-ch
Gate threshold voltage
VDS = VGS, ID = 250µA
n-ch
p-ch
Static drain-source on
resistance
VGS = 10V, ID = 4A
VGS = 10V, ID = 2.5A
VGS = 4.5V, ID = 4A
VGS = 4.5V, ID = 2.5A
n-ch
p-ch
n-ch
p-ch
VGS(th)
RDS(on)
Table 5.
Typ.
Max.
30
30
1
1
Unit
V
V
Dynamic
Symbol
Parameter
gfs (1)
Forward transconductance
Ciss
Input capacitance
Coss
Output capacitance
Crss
Reverse transfer
capacitance
Qg
Total gate charge
Qgs
Gate-source charge
Qgd
Gate-drain charge
Test conditions
VDS = 15V, ID= 4A
VDS = 15V, ID= 2.5A
VDS = 25V, f = 1 MHz,
VGS = 0
N-channel
VDD=24V ID=8A
VGS=5V
P-channel
VDD = 24V ID = 4A
VGS= 5V
(see Figure 27)
Min.
n-ch
p-ch
8.5
10
S
S
n-ch
p-ch
857
1350
pF
pF
n-ch
p-ch
147
490
pF
pF
n-ch
p-ch
20
130
pF
pF
n-ch
p-ch
7
12.5
n-ch
p-ch
2.5
5
nC
nC
n-ch
p-ch
2.3
3
nC
nC
10
16
nC
nC
1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5.
Note:
4/14
For the P-channel MOSFET actual polarity of voltages and current has to be
reversed
STS8C5H30L
Electrical characteristics
Table 6.
Symbol
td(on)
tr
td(off)
tf
Table 7.
Symbol
Switching times
Parameter
Test conditions
Turn-on delay time
Rise time
N-channel
VDD = 15V, ID = 4A
RG=4.7 Ω, VGS = 4.5V
P-channel
VDD = 15V, ID = 2A
RG=4.7 Ω, VGS = 4.5V
(see Figure 26)
Turn-off delay time
Fall time
N-channel
VDD = 15V, ID = 4A
RG=4.7 Ω, VGS = 4.5V
P-channel
VDD = 15V, ID = 2A
RG=4.7 Ω, VGS = 4.5V
(see Figure 26)
Min.
Typ.
Max.
Unit
n-ch
p-ch
12
25
ns
ns
n-ch
p-ch
14.5
35
ns
ns
n-ch
p-ch
23
125
ns
ns
n-ch
p-ch
8
35
ns
ns
Source drain diode
Parameter
Test conditions
Min
Typ.
Max
Unit
ISD
Source-drain current
n-ch
p-ch
8
5
A
A
ISDM (1)
Source-drain current
(pulsed)
n-ch
p-ch
32
20
A
A
VSD (2)
Forward on voltage
ISD = 8A, VGS = 0
ISD = 5A, VGS = 0
n-ch
p-ch
1.5
1.2
V
V
Reverse recovery time
Reverse recovery charge
Reverse recovery current
N-channel
ISD = 8A, di/dt = 100A/µs
VDD=15 V,Tj =150 oC
P-channel
ISD = 5 A, di/dt = 100A/µs
VDD=15 V, Tj =150 oC
(see Figure 28)
n-ch
p-ch
n-ch
p-ch
n-ch
p-ch
trr
Qrr
IRRM
15
45
5.7
36
0.76
1.6
ns
ns
nC
nC
A
A
1. Pulse width limited by safe operating area.
2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%
5/14
Electrical characteristics
STS8C5H30L
2.1
Electrical characteristics (curves)
Figure 2.
Safe operating area n-ch
Figure 3.
Thermal impedance n-ch
Figure 4.
Output characteristics n-ch
Figure 5.
Transfer characteristics n-ch
Figure 6.
Transconductance n-ch
Figure 7.
Static drain-source on resistance nch
6/14
STS8C5H30L
Figure 8.
Electrical characteristics
Gate charge vs. gate-source voltage Figure 9.
n-ch
Capacitance variations n-ch
Figure 10. Normalized gate threshold voltage
vs. temperature n-ch
Figure 11. Normalized on resistance vs.
temperature n-ch
Figure 12. Source-drain diode forward
characteristics n-ch
Figure 13. Normalized breakdown voltage vs.
temperature n-ch
7/14
Electrical characteristics
STS8C5H30L
Figure 14. Safe operating area p-ch
Figure 15. Thermal impedance p-ch
Figure 16. Output characteristics p-ch
Figure 17. Transfer characteristics p-ch
Figure 18. Transconductance p-ch
Figure 19. Static drain-source on resistance pch
8/14
STS8C5H30L
Electrical characteristics
Figure 20. Gate charge vs. gate-source voltage Figure 21. Capacitance variations p-ch
p-ch
Figure 22. Normalized gate threshold voltage
vs. temperature p-ch
Figure 23. Normalized on resistance vs.
temperature p-ch
Figure 24. Source-drain diode forward
characteristics p-ch
Figure 25. Normalized breakdown voltage vs.
temperature p-ch
9/14
Test circuit
3
STS8C5H30L
Test circuit
Figure 26. Switching times test circuit for
resistive load
Figure 27. Gate charge test circuit
Figure 28. Test circuit for inductive load
Figure 29. Unclamped Inductive load test
switching and diode recovery times
circuit
Figure 30. Unclamped inductive waveform
10/14
Figure 31. Switching time waveform
STS8C5H30L
4
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
11/14
Package mechanical data
STS8C5H30L
SO-8 MECHANICAL DATA
DIM.
mm.
MIN.
TYP
A
a1
inch
MAX.
TYP.
1.75
0.1
MAX.
0.068
0.25
a2
0.003
0.009
1.65
0.064
a3
0.65
0.85
0.025
0.033
b
0.35
0.48
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.25
0.5
0.010
0.019
D
4.8
5.0
0.188
0.196
E
5.8
6.2
0.228
c1
45 (typ.)
1.27
e
e3
3.81
0.150
3.8
4.0
0.14
L
0.4
1.27
0.015
S
0.244
0.050
F
M
12/14
MIN.
0.6
0.157
0.050
0.023
8 (max.)
STS8C5H30L
5
Revision history
Revision history
Table 8.
Revision history
Date
Revision
Changes
17-Sep-2004
1
First revision
31-Oct-2006
2
The document has been reformatted
30-Jan-2007
3
typo mistake on Table 2.
23-Jul-2007
4
Figure 14 has been updated
13/14
STS8C5H30L
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