STS4C3F30L N-channel 30V - 0.044Ω - 5A - SO-8 STripFET™ Power MOSFET General features Type VDSS RDS(on) ID STS4C3F30L (n-ch) 30V <0.055Ω 5A STS4C3F30L (p-ch) 30V <0.165Ω 3A ■ Low threshold drive ■ Standard outline for easy automated surface mount assembly SO-8 Description This application specific MOSFET is the second generation of STMicroelectronics unique “Single Feature Size™” strip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. Internal schematic diagram Applications ■ Switching application Order codes Part number Marking Package Packaging STS4C3F30L S4C3F30L SO-8 Tape & reel May 2006 Rev 1 1/14 www.st.com 14 Contents STS4C3F30L Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) .......................... 6 3 Test circuit 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2/14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 STS4C3F30L 1 Electrical ratings Electrical ratings Table 1. Absolute maximum ratings Value Symbol Parameter Unit N-channel VDS VDGR VGS P-channel Drain-source voltage (VGS = 0) 30 V Drain-gate voltage (RGS = 20 kΩ) 30 V ± 16 V Gate- source voltage ID Drain current (continuos) at TC = 25°C S.O. 5 2.7 A ID Drain current (continuos) at TC = 100°C S.O. 3.2 1.7 A Drain current (pulsed) 20 11 A IDM (1) PTOT Total dissipation at TC = 25°C D.O. Total dissipation at TC = 25°C S.O. Tstg Storage temperature Tj Max. operating junction temperature 1.6 2 W W -60 to 150 W/°C 150 °C 1. Pulse width limited by safe operating area Note: For the P-channel MOSFET actual polarity of voltages and current has to be reversed Table 2. Symbol Rthj-case Tl Thermal data Parameter Value Unit Thermal resistance junction-case S.O. 62.5 °C/W Thermal resistance junction-case D.O. 78.0 °C/W Maximum lead temperature for soldering purpose 300 °C 3/14 Electrical characteristics 2 STS4C3F30L Electrical characteristics (TCASE=25°C unless otherwise specified) Table 3. Symbol On/off states Parameter Test condictions Drain-source breakdown voltage ID = 250µA, VGS = 0 IDSS Zero gate voltage drain current (VGS = 0) VDS = Max rating n-ch VDS = Max rating,@125°C p-ch IGSS Gate-body leakage current (VDS = 0) VGS = ± 20V n-ch p-ch VGS(th) Gate threshold voltage VDS = VGS, ID = 250µA n-ch p-ch RDS(on) Static drain-source on resistance VGS = 10V, ID = 2A VGS = 10V, ID = 1.5A VGS = 4.5V, ID = 2A VGS = 4.5V, ID = 1.5A n-ch p-ch n-ch p-ch V(BR)DSS Table 4. Symbol gfs (1) Ciss Coss n-ch p-ch Typ. Max. 30 30 1 1 Unit V V 1.6 1.6 1 1 µA µA ±100 ±100 nA nA 2.5 2.5 V V 0.044 0.055 0.145 0.165 0.051 0.065 0.160 0.20 Ω Ω Ω Ω Dynamic Parameter Forward transconductance Test condictions Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Typ. Max. Unit n-ch p-ch 6 4 S S VDS = 25V, f = 1 MHz, VGS = 0 n-ch p-ch n-ch p-ch n-ch p-ch 220 420 115 95 23 30 pF pF pF pF pF pF Input capacitance Output capacitance Min. VDS >ID(on)xRDS(on)max, ID=3.5A VDS >ID(on)xRDS(on)max, ID=2A N-channel VDD = 24V, ID = 5 A VGS = 10V P-channel VDD =15V, ID = 3 A VGS = 4.5V (see Figure 24) 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 4/14 Min. n-ch p-ch n-ch p-ch n-ch p-ch 9.5 4.8 2.25 1.7 1.7 2 2 7 nC nC nC nC nC nC STS4C3F30L Electrical characteristics Table 5. Symbol td(on) tr td(off) tf Table 6. Symbol ISD Switching times Parameter Turn-on delay time Rise time Turn-off-delay time Fall time Parameter VSD (2) Forward on voltage IRRM n-ch p-ch n-ch p-ch n-ch p-ch n-ch p-ch Test condictions Source-drain current Source-drain current (pulsed) Qrr N-channel VDD = 15V, ID = 2.5 A RG = 4.7Ω, VGS = 10V P-channel VDD = 15V, ID = 1.5 A RG = 4.7Ω, VGS = 4.5V (see Figure 26) Min. Typ. Max 13 15 27 37 10 90 3 23 Unit ns ns ns ns ns ns ns ns Source drain diode ISDM (1) trr Test condictions ISD = 4 A, VGS = 0 N-channel ISD = 3.5A, di/dt=100A/µs VDD = 15V, Tj = 150°C P-channel Reverse recovery charge ISD = 3A, di/dt=100 A/µs VDD = 15V, Tj = 150°C Reverse recovery current (see Figure 28) Reverse recovery time 1. Pulse width limited by safe operating area. 2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. Min Typ. Max Unit n-ch p-ch n-ch p-ch 5 3 20 12 A A A A n-ch p-ch 1.2 1.2 V V n-ch p-ch 28 35 ns ns n-ch p-ch n-ch p-ch 18 25 1.3 1.5 nC nC A A 5/14 Electrical characteristics STS4C3F30L 2.1 Electrical characteristics (curves) Figure 1. Safe operating area n-ch Figure 2. Thermal impedance n-ch Figure 3. Output characterisics n-ch Figure 4. Transfer characteristics n-ch Figure 5. Transconductance n-ch Figure 6. Static drain-source on resistance n-ch 6/14 STS4C3F30L Electrical characteristics Figure 7. Gate charge vs gate-source voltage Figure 8. n-ch Figure 9. Normalized gate threshold voltage vs temperature n-ch Capacitance variations n-ch Figure 10. Normalized on resistance vs temperature n-ch Figure 11. Source-drain diode forward characteristics n-ch 7/14 Electrical characteristics STS4C3F30L Figure 12. Safe operating area p-ch Figure 13. Thermal impedance p-ch Figure 14. Output characterisics p-ch Figure 15. Transfer characteristicsp-ch Figure 16. Transconductance p-ch Figure 17. Static drain-source on resistance p-ch 8/14 STS4C3F30L Electrical characteristics Figure 18. Gate charge vs gate-source voltage Figure 19. Capacitance variations p-ch p-ch Figure 20. Normalized gate threshold voltage vs temperature p-ch Figure 21. Normalized on resistance vs temperature p-ch Figure 22. Source-drain diode forward characteristics p-ch 9/14 Test circuit 3 STS4C3F30L Test circuit Figure 23. Switching times test circuit for resistive load Figure 24. Gate charge test circuit Figure 25. Test circuit for inductive load Figure 26. Unclamped Inductive load test switching and diode recovery times circuit Figure 27. Unclamped inductive waveform 10/14 Figure 28. Switching time waveform STS4C3F30L 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 11/14 Package mechanical data STS4C3F30L SO-8 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. TYP. 1.75 0.1 MAX. 0.068 0.25 a2 0.003 0.009 1.65 0.064 a3 0.65 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.019 D 4.8 5.0 0.188 0.196 E 5.8 6.2 0.228 c1 45 (typ.) 1.27 e e3 3.81 0.150 3.8 4.0 0.14 L 0.4 1.27 0.015 S 0.244 0.050 F M 12/14 MIN. 0.6 0.157 0.050 0.023 8 (max.) STS4C3F30L 5 Revision history Revision history Table 7. Revision history Date Revision 12-May-2006 1 Changes First release 13/14 STS4C3F30L Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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