STP120NF04 N-channel 40V - 0.0047Ω - 120A TO-220 STripFET™ II MOSFET General features Type VDSS RDS(on) ID Pw STP120NF04 40V <0.0050Ω 120A 300W ■ Standard threshold drive ■ 100% avalanche tested 3 1 Description This MOSFET is the latest development of STMicroelectronics unique “Single Feature Size™” strip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. 2 TO-220 Internal schematic diagram Applications ■ Switching application Order codes Part number Marking Package Packaging STP120NF04 P120NF04 TO-220 Tube October 2006 Rev 2 1/14 www.st.com 14 Contents STP120NF04 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 3 Test circuit 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2/14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 STP120NF04 1 Electrical ratings Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit 40 V VDS Drain-source voltage (VGS = 0) VGS Gate-source voltage ± 20 V Drain current (continuous) at TC = 25°C 120 A ID (1) ID Drain current (continuous) at TC = 100°C 120 A IDM(2) Drain current (pulsed) 480 A PTOT Total dissipation at TC = 25°C 300 W Derating factor 2 W/°C dv/dt(3) Peak diode recovery voltage slope 6 V/ns EAS(4) Single pulse avalanche energy 1.2 J TJ Tstg Operating junction temperature Storage temperature -55 to 175 °C 0.5 °C/W see Figure 14. on page 8 °C/W Thermal resistance junction-ambient (free air) Max 62.5 °C/W Maximum lead temperature for soldering purpose 300 °C 1. Current Limited by Package 2. Pulse width limited by safe operating area 3. ISD ≤120A, di/dt ≤300A/µs, VDD ≤V(BR)DSS, Tj ≤TJMAX. 4. Starting Tj = 25°C, Id = 60A, VDD=30 V Table 2. Thermal data Rthj-case Thermal resistance junction-case Max Rthj-pcb Thermal resistance junction-pcb Max Rthj-a Tl 3/14 Electrical characteristics 2 STP120NF04 Electrical characteristics (TCASE=25°C unless otherwise specified) Table 3. Symbol On/off states Parameter Test conditions Drain-source breakdown voltage ID = 250 µA, VGS = 0 IDSS Zero gate voltage drain current (VGS = 0) VDS = Max Rating VDS = Max Rating, TC = 125 °C IGSS Gate body leakage current (VDS = 0) VGS = ± 20V VGS(th) Gate threshold voltage VDS = VGS, ID = 250µA RDS(on) Static drain-source on resistance VGS = 10V, ID = 50 A V(BR)DSS Table 4. Symbol (1) Typ. Max. 40 Unit V 2.8 1 10 µA µA ±100 nA 4.5 V 0.0047 0.0050 Ω Dynamic Parameter Test conditions Min. Typ. Max. Unit Forward transconductance VDS =15V, ID = 50A 150 S Ciss Coss Crss Input capacitance Output capacitance Reverse transfer capacitance VDS =25V, f=1 MHz, VGS=0 5100 1300 160 pF pF pF td(on) tr Turn-on delay time rise time VDD = 20 V, ID = 60 A, RG = 4.7 Ω, VGS = 10 V (see Figure 18) 35 220 ns ns td(off) tf Turn-off delay time fall time VDD = 20 V, ID = 60 A, RG = 4.7 Ω, VGS = 10 V (see Figure 18) 80 50 ns ns Qg Qgs Qgd Total gate charge Gate-source charge Gate-drain charge VDD=32V, ID = 120A VGS =10V (see Figure 19) 110 35 35 gfs 1. Pulsed: pulse duration=300µs, duty cycle 1.5% 4/14 Min. 150 nC nC nC STP120NF04 Electrical characteristics Table 5. Symbol Source drain diode Max Unit Source-drain current 120 A ISDM(1) Source-drain current (pulsed) 480 A VSD(2) Forward on voltage 1.3 V ISD trr Qrr IRRM Parameter Reverse recovery time Reverse recovery charge Reverse recovery current Test conditions Min Typ. ISD=120A, VGS=0 ISD=120A, di/dt = 100A/µs, VDD=20V, Tj=150°C (see Figure 20) 75 185 5 ns nC A 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration=300µs, duty cycle 1.5% 5/14 Electrical characteristics STP120NF04 2.1 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characterisics Figure 4. Transfer characteristics Figure 5. Transconductance Figure 6. Static drain-source on resistance 6/14 STP120NF04 Electrical characteristics Figure 7. Gate charge vs gate-source voltage Figure 8. Figure 9. Normalized gate threshold voltage vs temperature Figure 11. Normalized on resistance vs temperature Capacitance variation Figure 10. Normalized BVDSS vs temperature Figure 12. Source-drain diode forward characteristics 7/14 Electrical characteristics STP120NF04 Figure 13. Power derating vs Tc Figure 14. Thermal resistance Rthj-a vs PCB copper area Figure 15. Max id current vs Tc Figure 16. Max power dissipation vs PCB copper area 8/14 STP120NF04 Electrical characteristics Figure 17. Allowable Iav vs time in avalanche The previous curve gives the safe operating area for unclamped inductive loads, single pulse or repetitive, under the following conditions: PD(AVE) =0.5*(1.3*BVDSS *IAV ) EAS(AR) =PD(AVE) *tAV Where: IAV is the allowable current in avalanche PD(AVE) is the average power dissipation in avalanche (single pulse) tAV is the time in avalanche To derate above 25 °C, at fixed IAV, the following equation must be applied: IAV = 2 * (Tjmax - TCASE) / (1.3 * BVDSS * Zth) Where: Zth = K * Rth is the value coming from Normalized Thermal Response at fixed pulse width equal to TAV. 9/14 Test circuit 3 STP120NF04 Test circuit Figure 18. Switching times test circuit for resistive load Figure 19. Gate charge test circuit Figure 20. Test circuit for inductive load Figure 21. Unclamped Inductive load test switching and diode recovery times circuit Figure 22. Unclamped inductive waveform 10/14 Figure 23. Switching time waveform STP120NF04 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 11/14 Package mechanical data STP120NF04 TO-220 MECHANICAL DATA DIM. mm. MIN. inch MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 b 0.61 0.88 0.024 0.034 b1 1.15 1.70 0.045 0.066 c 0.49 0.70 0.019 0.027 D 15.25 15.75 0.60 0.620 E 10 10.40 0.393 0.409 e 2.40 2.70 0.094 0.106 e1 4.95 5.15 0.194 0.202 F 1.23 1.32 0.048 0.052 H1 6.20 6.60 0.244 0.256 J1 2.40 2.72 0.094 0.107 0.551 L 13 14 0.511 L1 3.50 3.93 0.137 L20 16.40 L30 12/14 TYP 0.154 0.645 28.90 1.137 øP 3.75 3.85 0.147 0.151 Q 2.65 2.95 0.104 0.116 STP120NF04 5 Revision history Revision history Table 6. Revision history Date Revision Changes 28-Feb-2005 1 First release. 02-Oct-2006 2 New template, no content change 13/14 STP120NF04 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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