AMIS-39100
Octal High Side Driver with
Protection
General Description
Features
PIN ASSIGNMENT
TEST1
1
28
GND6
CLK
2
27
VDDN
WR
3
26
PDB
OUT1
4
25
OUT8
VB1
5
24
VB4
OUT2
6
23
OUT7
GND1
7
22
GND5
GND2
8
21
GND4
20
OUT6
VB2
10
19
VB3
OUT4
11
18
OUT5
DIN
12
17
CAPA1
DOUT
13
16
TEST
TEST2
14
15
GND3
OUT3
9
(Top View)
PC20070110.1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
Typical Applications
• Eight HS drivers
• Up to 830 mA Continuous Current Per Driver Pair
•
•
•
•
•
•
•
•
•
•
•
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AMIS−39100
The AMIS−39100 is a general purpose IC with eight integrated high
side (HS) output drivers. The device is designed to control the power
of virtually any type of load in a 12 V automotive environment, such
as transistor gates, relays, LEDs etc.
Each of the output drivers of the AMIS−39100 is able to drive up to
275 mA continuously when connected to an inductive load of
300 mH. Even higher driver output currents can be obtained as long as
the total current of the device is limited. The integrated charge−pump
of the AMIS−39100, which uses only one low cost external capacitor,
avoids thermal runaways even if the battery voltage is low. The HS
drivers withstand short to ground (even when AMIS−39100 has lost its
ground connection), short to the battery and has overcurrent
limitation. In case of a potential hazardous situation, the drivers are
switched off and the diagnostic state of the HS drivers can be read out
via serial peripheral interface (SPI). In case of a short to ground, the
output driver is deactivated after a de−bounce time.
The AMIS−39100 can be connected to a 3.3 V or 5 V
microcontroller by means of a SPI interface. This SPI interface is used
to control each of the output drivers individually (on or off) and to read
the status of each individual output driver (read−back of possible error
conditions). This allows the detection of error situations for each
driver individually. Furthermore, the SPI interface can be used to
read−back the status of the built−in thermal shutdown protection. The
AMIS−39100 has a low−power mode and excellent handling and
system ESD characteristics.
•
•
•
•
•
•
(Resistive Load)
Charge Pump with One External Capacitor
Serial peripheral interface (SPI)
Short−Circuit Protection
Diagnostic Features
Powerdown Mode
Internal Thermal Shutdown
3.3 V and 5 V Microcontroller Compliant
Excellent System ESD
Automotive Compliant
SOIC 28 Package with Low Rthja
This is a Pb−Free Device*
Automotive Dashboard
Automotive Load Management
Actuator Control
LED Driver Applications
Relays and Solenoids
Industrial Process Control
*For additional information on our Pb−Free strategy and
soldering
details,
please
download
the
ON Semiconductor
Soldering
and
Mounting
Techniques Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2009
January, 2009 − Rev. 2
1
Publication Order Number:
AMIS−39100/D
AMIS−39100
VDDN
27
5
Power on
Reset
4
OUT1
Thermal
shutdown
VB1
OUT1
6
OUT2
OUT2
10
DIN
DOUT
CLK
WR
VB2
12
13
2
9
OUT3
SPI
interface
OUT3
3
LOGIC
Control
Diagnostic
11
OUT4
OUT4
19
VB3
18
OUT5
OUT5
Oscillator
20
OUT6
CAPA1
17
24
Charge−
pump
23
OUT7
OUT6
VB4
OUT7
Bandgap
25
OUT8
OUT8
AMIS−39100
26
1
14
16
TEST2
PDB
TEST1
TEST
7
8
21 22
28
GND3
GND5
GND1
GND4
GND6
GND2
Figure 1. Block Diagram
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2
15
PC20070110.4
AMIS−39100
Table 1. PIN DESCRIPTION
Pin
Name
1
TEST1
Description
2
CLK
Schmitt Trigger SPI CLK Input
3
WR
Schmitt Trigger SPI Write Enable Input
4
OUT1
5
VB1
Connect to GND
HS Driver Output
Battery Supply
6
OUT2
HS Driver Output
7
GND1
Power Ground and Thermal Dissipation Path Junction−to−PCB
8
GND2
Power Ground and Thermal Dissipation Path Junction−to−PCB
9
OUT3
HS Driver Output
10
VB2
11
OUT4
Battery Supply
HS Driver Output
12
DIN
13
DOUT
SPI Input Pin (Schmitt trigger or CMOS inverter)
Digital Three State Output for SPI
14
TEST2
Connect to GND
15
GND3
Power Ground and Thermal Dissipation Path Junction−to−PCB
16
TEST
Connect to GND
17
CAPA1
Charge Pump Capacitor Pin
18
OUT5
HS Driver Output
19
VB3
20
OUT6
HS Driver Output
21
GND4
Power Ground and Thermal Dissipation Path Junction−to−PCB
22
GND5
Power Ground and Thermal Dissipation Path Junction−to−PCB
23
OUT7
HS Driver Output
Battery Supply
24
VB4
25
OUT8
Battery Supply
26
PDB
27
VDDN
Digital Supply
28
GND6
Power Ground and Thermal Dissipation Path Junction−to−PCB
HS Driver Output
Schmitt Trigger Powerdown Input
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AMIS−39100
Table 2. ABSOLUTE MAXIMUM RATINGS
Min
Max
Unit
VDDN
Symbol
Power Supply Voltage
Description
GND − 0.3
6
V
VB
DC Battery Supply on Pins VB1 to VB4 Load Dump, Pulse 5b 400 ms
GND − 0.3
35
V
Iout_ON
Maximum Output Current OUTx Pins (Note 1)
The HS Driver is Switched On
−3000
350
mA
Iout_OFF
Maximum Output Current OUTx Pins (Note 1)
The HS Driver is Switched Off
−350
350
mA
I_OUT_VB
Maximum Output Current VB1, 2, 3, 4 Pins
−700
3750
mA
Vcapa1
DC Voltage on Pins capa1
0
VB + 16.5
V
Vdig_in
Voltage on Digital Inputs CLK, PDB, WR, DIN
−0.3
VDDN + 0.3
V
VESD
Pins that Connect the Application (Pins VB1 − 8 and Out1 − 8) (Note 2)
All Other Pins (Note 2)
−4
−2
+4
+2
kV
VESD
ESD According Charged Device Model (Note 3)
−750
+750
V
TJ
Junction Temperature (T < 100 hours)
−40
175
°C
Tmr
Ambient Temperature Under Bias
−40
105
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The power dissipation of the chip must be limited not to exceed the maximum junction temperature Tj.
2. According to Human Body Model (HBM) standard MIL−STD−883 method 3015.7
3. According to norm EOS/ESD−STM5.3.1−1999 robotic mode
Table 3. THERMAL CHARACTERISTICS OF THE PACKAGE
Symbol
Rth(vj−a)
Description
Thermal Resistance from Junction−to−Ambient in Power SOIC 28 Package
Conditions
Value
Unit
In Free Air
145
K/W
Table 4. THERMAL CHARACTERISTICS OF THE AMIS−39100 ON A PCB
Conductivity Top and Bottom Layer
Rthja
(Note 4)
Unit
Two Layer (35 mm)
Copper Planes According Figure 3 to +25% Popper for the Remaining Areas
24
K/W
Two Layer (35 mm)
Copper Planes According to Figure 3 0% Popper for the Remaining Areas
53
K/W
Four Layer JEDEC:
EIA/JESD51−7
25% Copper Coverage
25
K/W
One Layer JEDEC:
EIA/JESD51−3
25% Copper Coverage
46
K/W
PCB Design
4. These values are informative only.
Rthja = Thermal Resistance from Junction−to−Ambient
Table 5. OPERATING RANGES
Symbol
Description
Min
Max
Unit
VDDN
Digital Power Supply Voltage
3.1
5.5
V
Vdig_in
Voltage on Digital Inputs CLK, PDB, WR, DIN
−0.3
VDDN
V
VB
(Note 5)
DC Battery Supply on Pins VB1 to VB4
3.5
16
V
TA
Ambient Temperature
−40
105
°C
5. The power dissipation of the chip must be limited not to exceed maximum junction temperature TJ of 130°C.
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AMIS−39100
TYPICAL APPLICATION DIAGRAM
5V−reg
VDDN
VCC
27
Micro−
controller
CVB
CVDDN
CVCC
CCP
CAPA
VBAT
17
5
VB1..4
10
19 24
DIN 12
DOUT 13
CLK 2
WR 3
AMIS−39100
PDB 26
1 14 16
28 22 21 15
4
Lload1
OUT1
Cout1
6
9
11
18
20
23
25
8 7
OUT8
Lload8
Cout8
GND
Rload1
Rload8
GND1..6
TEST1..2
PC20070110.2
Figure 2. Typical Application Diagram
External Components
It is important to properly decouple the power supplies of the chip with external capacitors that have good high frequency
properties.
The VB1, VB2, VB3, and VB4 pins are shorted on the PCB level. Also GND1, GND2, GND3, GND4, GND5, GND6, TEST,
TEST1, and TEST2 are shorted on the PCB level.
Table 6. EXTERNAL COMPONENTS
Component
Function
Min
Value
Max
Tol [%]
Unit
$20
nF
CVB
Decoupling Capacitor; X7R
100
Ccharge_pump
Charge Pump Capacitor (Note 6)
0.47
Cout (Note 7)
EMC Capacitor on Connector
1
Cout (Note 7)
Decoupling Capacitors on OUT 1 to 8; 50 V
22
$20
nF
CVDD
Decoupling Capacitors; 50 V
22
$20
nF
RLoad
Load Resistance
65
LLoad
Load Inductance at Maximum Current
300
6. The capacitor must be placed close to the AMIS−39100 pins on the PCB.
7. Both capacitors are optional and depend on the final application and board layout.
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5
47
nF
nF
$10
350
W
mH
AMIS−39100
Bottom PCB view
Top PCB view
5 mm
5 mm
5 mm
114.3
114.3
5 mm
GND copper
Ground plane GND copper
25 % filled by GND copper
76.2
76.2
Figure 3. Layout Recommendation for Thermal Characteristics
ELECTRICAL AND ENVIRONMENTAL RATINGS
ELECTRICAL PARAMETERS
Operation outside the operating ranges for extended periods may affect device reliability. Total cumulative dwell time above
the maximum operating rating for the power supply or temperature must be less than 100 hours.
The parameters below are independent from load type (see Section “Load Specific Parameters”).
Table 7. ELECTRICAL CHARACTERISTICS
Symbol
Description
Min
Max
Unit
I_VB_norm (Note 8)
Consumption on VB Without Load Currents
In Normal Mode of Operation PDB = High
3.5
mA
I_PDB_3.3 (Notes 8 and 9)
Sum of VB and VDDN Consumption in Powerdown Mode of Operation
PDB = Low, VDDN 3.3 V, VB = 12 V, 23°C Ambient
CLK and WR are at VDDN Voltage
25
mA
I_PDB_5 (Notes 8 and 9)
Sum of VB and VDDN Consumption in Powerdown Mode of Operation
PDB = low, VDDN 5 V, VB = 24 V, 23°C Ambient
CLK and WR are at VDDN Voltage
40
mA
I_PDB_MAX_VB
VB Consumption in Powerdown Mode of Operation PDB = Low, VB = 16 V
10
mA
I_VDDN_norm (Note 8)
Consumption on VDDN
In Normal Mode of Operation PDB = High
CLK is 500 kHz, VDDN = 5.5 V, VB = 16 V
1.6
mA
R_on_1 − 8
On Resistance of the Output Drivers 1 through 8
Vb= 16 V (Normal Battery Conditions and TA = 25°C)
Vb = 4.6 V (Worst Case Battery Condition and TA = 25°C)
I_OUT_lim_x (Note 8)
Internal Overcurrent Limitation of HS Driver Outputs
0.65
T_shortGND_HSdoff
The Time from Short of HS Driver OUTx Pin to GND and the Driver
Deactivation; Driver is Off; Detection Works from VB Minimum of 7 V;
VDDN Minimum is 3 V
5.4
TSD_H (Note 8)
High TSD Threshold for Junction Temperature (Temperature Rising)
130
170
°C
TSD_HYST
TSD Hysteresis for Junction Temperature
9
18
°C
8. The power dissipation of the chip must be limited not to exceed maximum junction temperature TJ.
9. The cumulative operation time mentioned above may cause permanent device failure.
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6
1
3
2
W
A
ms
AMIS−39100
LOAD SPECIFIC PARAMETERS
HS driver parameters for specific loads are specified in following categories:
A. Parameters for inductive loads till 350 mH and TA till 105°C
B. Parameters for inductive loads till 300 mH and TA till 105°C
C. Parameters for resistive loads and TA till 85°C
Table 8. LOAD SPECIFIC CHARACTERISTICS
Symbol
Description
Min
Max
Unit
240
mA
275
mA
Maximum output per HS driver, all eight drivers might be active simultaneously
350
mA
Maximum output per one HS driver, only one can be active
650
mA
Maximum output per HS driver, only two HS drivers from a different pair
can be active simultaneously
500
mA
Maximum output per one HS driver pair
830
mA
A. INDUCTIVE LOAD TILL 350 mH AND TA TILL 1055C
I_OUT_ON_max
Maximum output per HS driver, all eight drivers might be active simultaneously
B. INDUCTIVE LOAD TILL 300 mH AND TA TILL 1055C
I_OUT_ON_max
Maximum output per HS driver, all eight drivers might be active
simultaneously
C. RESISTIVE LOAD AND TA TILL 855C
I_OUT_ON_max
10. The parameters above are not tested in production but are guaranteed by design. The overall current capability limitations need to be
respected at all times.
The maximum current specified in cannot always be
obtained. The practically obtainable maximum drive current
heavily depends on the thermal design of the application
PCB (see Section “Thermal Characteristics”).
The available power in the package is: (TSD_H − TA) /
Rthja
With TSD_H = 130°C and Rthja according to Table 4.
result in the diagnostic register which is then latched in the
output register at the rising edge of the WR−pin. Each driver
has its corresponding diagnostic bit DIAG_x. By comparing
the actual output status (DIAG_x) with the requested driver
status (CMD_x) you can diagnose the correct operation of
the application according to .
CHARGE PUMP
In case of TSD activation, all bits DIAG 1 to DIAG 8 in
the SPI output register are set into the fault state and all
drivers will be switched off (see ).
The TSD error condition is active until it is reset by the
next correct communication on SPI interface (i.e. number of
clock pulses during WR=0 is divisible by 8), provided that
the device has cooled down under the TSD trip point.
Thermal Shutdown (TSD) Diagnostic
The HS drivers use floating NDMOS transistors as power
devices. To provide the gate voltages for the NDMOS of the
HS drivers, a charge pump is integrated. The storage
capacitor is an external one. The charge pump oscillator has
typical frequency of 4 MHz.
DIAGNOSTICS
Short−Circuit Diagnostics
The diagnostic circuit in the AMIS−39100 monitors the
actual output status at the pins of the device and stores the
Table 9. OUT DIAGNOSTICS
Requested driver status
CMD_x
Actual output status
DIAG_x
Diagnosis
On
1
High
1
Normal State
On
1
Low
0
Short−to−Ground or TSD (Note 12)
Off
0
High
1
Short−to−VB or Missing Load (Note 11) or TSD
(Note 12)
Off
0
Low
0
Normal State (Note 11)
11. The correct diagnostic information is available after T_diagnostic_OFF time.
12. All 8 diagnostic bits DIAG_x must be in the fault condition to conclude a TSD diagnostic.
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7
AMIS−39100
Ground Loss
Due to its design, the AMIS−39100 is protected for
withstanding module ground loss and driver output shorted
to ground at the same time.
Table 10. POWER LOSS
VDDN
VB
Possible Case
Action
0
0
System stopped
Nothing
0
1
Start case or sleeping mode with missing VDDN
Eight switches in the off−state
Power down consumption on VB
1
0
Missing VB supply
VDDN normally present
Eight switches in the off−state
Normal consumption on VDDN
1
1
System functional
Nominal functionality
SPI INTERFACE
The serial peripheral interface (SPI) is used to allow an
external microcontroller (MCU) to communicate with the
device. The AMIS−39100 acts always as a slave and it can’t
initiate any transmission.
The diagram in Figure 6 represents the SPI timing
diagram for 8−bit communication.
Communication starts with a falling edge on the WR−pin
which latches the status of the diagnostic register into the
SPI output register. Subsequently, the CMD_x bits –
representing the newly requested driver status – are shifted
into the input register and simultaneously, the DIAG_x bits
– representing the actual output status – are shifted out. The
bits are shifted with x = 1 first and ending with x = 8.
At the rising edge of the WR−pin, the data in the input
register is latched into the command register and all drivers
are simultaneously switching to the newly requested status.
SPI communication is ended.
In case the SPI master does only support 16−bit
communication, then the master must first send 8 clock
pulses with dummy DIN data and ignoring the DOUT data.
For the next 8 clock pulses the above description can be
applied.
The required timing for serial to peripheral interface is
shown in Table 11.
SPI Transfer Format and Pin Signals
The SPI block diagram and timing characteristics are
shown in and Figures 5 and 6.
During an SPI transfer, data is simultaneously sent to and
received from the device. A serial clock line (CLK)
synchronizes shifting and sampling of the information on
the two serial data lines (DIN and DOUT). DOUT signal is
the output from the AMIS−39100 to the external MCU and
DIN signal is the input from the MCU to the AMIS−39100.
The WR−pin selects the AMIS−39100 for communication
and can also be used as a chip select (CS) in a multiple−slave
system. The WR−pin is active low. If AMIS−39100 is not
selected, DOUT is in high impedance state and it does not
interfere with SPI bus activities. Since AMIS−39100 always
shifts data out on the rising edge and samples the input data
also on the rising edge of the CLK signal, the MCU SPI port
must be configured to match this operation. SPI clock idles
high between the transferred bytes.
Table 11. DIGITAL CHARACTERISTICS
Symbol
Description
Min
Max
Unit
500
kHz
2
ms
T_CLK
Maximum applied clock frequency on CLK input
T_DATA_ready
Time between falling edge on WR and first bit of data ready on DOUT
output (driver going from HZ state to output of first diagnostic bit)
T_CLK_first
First clock edge from falling edge on WR
3
ms
T_setup (Note 13)
Setup time on DIN
20
ns
T_hold (Note 13)
Hold time on DIN
20
ns
T_DATA_next
Time between rising edge on CLK and next bit ready on DOUT (capa on
DOUT is 30 pF max.)
T_SPI_END
Time between last CLK edge and WR rising edge
1
T_risefall
Rise and fall time of all applied signals (maximum loading capacitance is
30 pF)
5
T_WR
Time between two rising edge on WR (repetition of the same command)
300
13. Guaranteed by design.
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8
100
ns
ms
20
ns
ms
AMIS−39100
Normal Mode Verification:
• The command is the set of eight bits loaded via SPI, which drives the eight HS drivers on or off.
• The command is activated with rising edge on WR pin.
Table 12. DIGITAL CHARACTERISTICS
Symbol
Description
Min
Max
Unit
T_command_L_max
(Note 14)
Minimum time between two opposite commands for inductive loads and
maximum HS driver current of 275 mA
1
s
T_command_R (Note 14)
Minimum time between two opposite commands for resistive loads and
maximum HS driver current of 350 mA
2
ms
T_PDB_recov
The time between the rising edge on the PDB input and 90 percent of
VB−1V on all HS driver outputs. (all drivers are activated, pure resistive
load 35 mA on all outputs)
1
14. Guaranteed by design.
PD
50%
t_PD_recov
VOUTi
90% {VBi − 1V}
t
PC20070110.7
Figure 4. Timing for Powerdown Recovery
DOUT
OUTPUT REGISTER
INP UT REGISTER
DIN
CMD8
CMD DRIVER
COMMAND
CMD8
DIAG
CMD1
8
MEMORY
REGISTER
MEMO CMD
DIAG
CMD1
8
CMDx
High Side
STATE DIAG
DIAGx
Driver
OUTx
Figure 5. SPI Block Diagram
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9
DIAG
1
DIAG
MEMO DIAG
DIAG
1
ms
AMIS−39100
Transfer from input registers to
the command registers
(Rising edge on WR)
Transfer data from diagnostic registers
to the output registers
Falling edge on WR
WR
CLK
1
2
3
4
5
6
7
8
CMD CMD CMD CMD CMD CMD CMD CMD
5
6
7
3
4
1
2
8
DIN
OUT
DIN : DRIVER COMMAND
DOUT
DIAG DIAG DIAG DIAG DIAG DIAG DIAG DIAG
5
6
7
2
3
4
1
8
High Z
High Z
IN
DOUT: OUTPUTs THE STATE OF DIAGNOSTICs
OUT1 to 8
Figure 6. Timing Diagram
DEVICE ORDERING INFORMATION
Temperature Range
Package Type
Shipping†
AMIS39100PNPB3G
−40°C to 105°C
SOIC 28 W
(Pb−Free)
26 Units / Rail
AMIS39100PNPB3RG
−40°C to 105°C
SOIC 28 W
(Pb−Free)
1500 / Tape & Reel
Part Number
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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AMIS−39100
PACKAGE DIMENSIONS
SOIC 28 W
CASE 751AR−01
ISSUE O
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AMIS−39100
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent
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AMIS−39100/D