AMIS-30523 Product Preview CAN Micro-Stepping Motor Driver Introduction The AMIS−30523 is a micro−stepping stepper motor driver for bipolar stepper motors with an embedded CAN transceiver. The motor driver is connected through I/O pins and a SPI interface with an external microcontroller. It has an on−chip voltage regulator, reset−output and watchdog reset, able to supply peripheral devices. It contains a current−translation table and takes the next micro−step depending on the clock signal on the “NXT” input pin and the status of the “DIR” (=direction) register or input pin. The CAN transceiver is the interface between a (CAN) protocol controller and the physical bus. It provides differential transmit capability to the bus and differential receive capability to the CAN controller. To cope with the long bus delay the communication speed needs to be low. The integrated transceiver allows low transmit data rates down 10 kbit/s or lower. The AMIS−30523 is ideally suited for general−purpose stepper motor applications in the automotive, industrial, medical, and marine environment. With the on−chip voltage regulator and embedded CAN transceiver it further reduces the BOM for mechatronic stepper applications. Key Features Motor Driver • Dual H−Bridge for 2−Phase Stepper Motors • Programmable Peak−Current up to 1.2 A Continuous (1.6 A for a http://onsemi.com 1 52 QFN52, 8x8 CASE 485M MARKING DIAGRAM 1 AMIS30523 0C523−001 XXXXYZZ 0C523−001 = Specific Device Code XXXX = Date Code Short Time)* WL = Wafer Lot • On−Chip Current Translator Y = Assembly Location ZZ = Traceability Code • SPI Interface • Seven Step Modes from Full Step up to 32 Micro−Steps • PWM Current Control with Automatic Selection of Fast and Slow ORDERING INFORMATION Decay and Fully Integrated Current−Sense See detailed ordering and shipping information in the package • Full Output Protection and Diagnosis dimensions section on page 34 of this data sheet. • Thermal Warning and Shutdown • Integrated 5 V Regulator to Supply External • Low EME: Common−Mode Choke is No Longer Microcontroller Required • Differential Receiver with Wide common−mode range CAN Transceiver ($35 V) • Compatible with the ISO 11898 Standard • Voltage Source via VSPLIT Pin for Stabilizing the • Wide Range of Bus Communication Speed (0 up to 1 Recessive Bus Level Mbit/s) • No Disturbance of the Bus Lines with an Un−Powered • Allows Low Transmit Data Rate in Networks Node Exceeding 1 km • Logic Level Inputs Compatible with 3.3 V Devices • Extremely Low Current Standby Mode with Wake−up • These are Pb−Free Devices via the Bus *Output Current Level May be Limited by Ambient Temperature and Heat Sinking This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. © Semiconductor Components Industries, LLC, 2010 November, 2010 − Rev. P0 1 Publication Order Number: AMIS−30523/D AMIS−30523 BLOCK DIAGRAM VDD DI DO NXT DIR SLA POR /WD CLR ERR TxD 22 Chargepump POR 24 8 Vreg 21 10 Logic & Registers P W M T R A N S L A T O R 45 17 Load Angle 19 27, 28 EMC P W M RxD GND 31,32 I−sense MOTXP MOTXN MOTYP MOTYN 23 4 18 Band− gap VCC POR VSPLIT 52 Thermal shutdown Mode & wake −up control 51 Wake−up Filter COMP 47 COMP 1, 2 29,30 36, 37 GND AMIS−30523 Figure 1. Block Diagram AMIS−30523 http://onsemi.com 2 7 49 Driver control 6 VCC 48 VCC STB 34, 35 I−sense Temp. Sense 42 38, 39 EMC OTP SPI 25, 26 CS Timebase 20 VBB 40,41 CLK 46 9 CPN CPP VCP V SPLIT CANH CANL 40 41 42 44 45 46 47 48 49 50 51 52 VBB VBB VCC RxD VSPLIT DI CLK NXT POR/WD TSTO DO VDD GND CANH CANL STB TxD GND GND 43 AMIS−30523 1 39 2 38 3 37 4 36 5 35 6 34 AMIS−30523 7 8 33 32 9 31 MOTYN MOTYN GND GND MOTYP MOTYP 26 25 24 23 22 21 20 19 27 18 28 13 17 29 12 16 30 15 10 11 14 MOTXP MOTXP GND GND MOTXN MOTXN VBB VBB CS CLR VCP CPP CPN SLA ERR DIR Figure 2. Pin Out AMIS−30523 Table 1. PIN DESCRIPTION Name Pin Description Type GND 1, 2 / 3 No function (to be left open in normal operation) VCC 4 CAN Supply voltage Ground Equivalent Schematic Supply Supply / 5 No function (to be left open in normal operation) RXD 6 CAN Receive data output; dominant transmitter ³ low output VSPLIT 7 CAN common−mode stabilization output DI 8 SPI Data In Digital Input Type 2 CLK 9 SPI Clock Input Digital Input Type 2 NXT 10 Next micro−step input Digital Input Type 2 Digital Input Type 2 Digital Output Supply / 11 .. 16 DIR 17 No function (to be left open in normal operation) Direction input ERRB 18 Error output (open drain) Digital Output Type 4 SLA 19 Speed load angle output Analog Output Type 5 CPN 20 Negative connection of charge pump capacitor High Voltage CPP 21 Positive connection of charge pump capacitor High Voltage VCP 22 Charge pump filter−capacitor High Voltage CLR 23 “Clear” = chip reset input Digital Input Type 1 CSB 24 SPI chip select input Digital Input Type 2 VBB 25, 26 High voltage supply Input Supply Type 3 MOTYP 27, 28 Negative end of phase Y coil output GND 29, 30 Ground, heat sink Driver Output Supply http://onsemi.com 3 AMIS−30523 Table 1. PIN DESCRIPTION Name Pin MOTYN 31, 32 Description / 33 MOTXN 34, 35 Positive end of phase X coil output GND 36, 37 Ground, heat sink MOTXP 38, 39 Negative end of phase X coil output High voltage supply input Type Positive end of phase Y coil output Equivalent Schematic Driver Output No function (to be left open in normal operation) Driver Output Supply Driver Output VBB 40, 41 PORB/WD 42 Power−on−reset and watchdog reset output (open drain) TST0 43 Test pin input (to be tied to ground in normal operation) / 44 No function (to be left open in normal operation) DO 45 SPI data output (open drain) VDD 46 GND Supply Type 3 Digital Output Type 2 Digital Input Digital Output Type 4 5V Logic Supply Output (needs external decoupling capacitor) Supply Type 6 47 Ground Supply CANH 48 High−level CAN bus line (high in dominant mode) Analog Output CANL 49 Low−level CAN bus line (low in dominant mode) Analog Output / 50 No function (to be left open in normal operation) STB 51 CAN stand−by mode control input Digital Input TXD 52 CAN transmit data input; low input ³ dominant driver; internal pull−up current Digital Input Table 2. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Min Max Unit VBB Analog DC supply voltage (Note 1) −0.3 +40 V VCC CAN Supply voltage −0.3 +7 V VCANH, VCANL, VSPLIT DC voltage CANH ,CANL and VSPLIT (Note 2) −50 +50 V VTRANS Transient voltage CANH, CANL and VSPLIT (Note 3) −300 +300 V Storage temperature −55 +150 °C Junction Temperature under bias (Note 4) −40 +170 °C VESD Electrostatic discharges on component level, All pins (Note 5) −2 +2 kV VESD Electrostatic discharges on component level, All pins (Note 7) −500 +500 V VESD Electrostatic discharges on CANH, CANL and VSPLIT (Note 6) −6 +6 kV VESD Electrostatic discharges on CANH and CANL (Note 7) −500 +500 V VESD Electrostatic discharges on component level, HiV pins (Note 6) −6 +6 kV 100 mA TST TJ Latch−up Static latch−up at all pins Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. For limited time < 0.5 s. 2. For 0 < VCC < 5.25 V unlimited time 3. Applied transient waveforms in accordance with ISO 7637 part 3, test pulses 1, 2, 3a, and 3b. 4. Circuit functionality not guaranteed. 5. Standardized Human body model (100 pF via 1.5 kW, according to JEDEC EIA−JESD22−A114−B). 6. Standardized human body model electrostatic discharge (ESD) pulses (100 pF via 1.5 kW) stressed pin to ground. 7. Standardized charged device model ESD pulses when tested according to ESD STM5.3.1−1999. http://onsemi.com 4 AMIS−30523 Table 3. THERMAL RESISTANCE Thermal Resistance Junction−to−Ambient (RthJ−A) Package Junction−to−Exposed Pad (RthJ−EP) 1S0P Board 2S2P Board Unit QFN−52 0.95 60 30 K/W EQUIVALENT SCHEMATICS Following figure gives the equivalent schematics of the user relevant inputs and outputs. The diagrams are simplified representations of the circuits used. 4k IN OUT Rpd TYPE 1: CLR Input IN TYPE 4: DO and ERR Open Drain Outputs 4k Rout SLA TYPE 2: CLK, DI, CS, NXT, DIR Inputs VDD VDD TYPE 5: SLA Analog Output VBB VBB TYPE 3: VDD and VBB Power Supply Figure 3. In− and Output Equivalent Diagrams PACKAGE THERMAL CHARACTERISTICS The AMIS−30523 is available in a QFN−52 package. For cooling optimizations, the QFN has an exposed thermal pad which has to be soldered to the PCB ground plane. The ground plane needs thermal vias to conduct the heat to the bottom layer. Figure 4 gives an example for good power distribution solutions. For precise thermal cooling calculations the major thermal resistances of the device are given. The thermal media to which the power of the devices has to be given are: • Static environmental air (via the case) • PCB board copper area (via the exposed pad) The thermal resistances are presented in Table 5: DC Parameters Motor Driver. The major thermal resistances of the device are the Rth from the junction to the ambient (RthJ−A) and the overall Rth from the junction to exposed pad (RthJ−EP). In Table 3 one can find the values for the RthJ−A and RthJ−EP, simulated according to JESD−51: The RthJ−A for 2S2P is simulated conform JEDEC JESD−51 as follows: • A 4−layer printed circuit board with inner power planes and outer (top and bottom) signal layers is used • Board thickness is 1.46 mm (FR4 PCB material) • The 2 signal layers: 70 mm thick copper with an area of 5500 mm2 copper and 20% conductivity http://onsemi.com 5 AMIS−30523 • The 2 power internal planes: 36 mm thick copper with • Board thickness is 1.46 mm (FR4 PCB material) • The layer has a thickness of 70 mm copper with an area an area of 5500 mm2 copper and 90% conductivity The RthJ−A for 1S0P is simulated conform JEDEC JESD−51 as follows: • A 1−layer printed circuit board with a single power and signal layer of 5500 mm2 copper and 20% conductivity 40 41 42 43 44 45 46 47 48 50 51 52 30 11 29 12 28 13 27 14 MOTXP MOTXP GND GND MOTXN MOTXN MOTYN MOTYN GND GND MOTYP MOTYP 26 10 25 31 24 32 9 23 33 8 22 34 7 21 35 6 20 36 5 19 37 4 18 3 17 38 16 39 2 15 1 VCC RxD VSPLIT DI CLK NXT 49 DO VDD GND CANH CANL STB TxD GND GND VBB VBB POR/WD TSTO ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ VBB VBB CS CLR VCP CPP CPN SLA ERR DIR Figure 4. Example of QFN−52 PCB Ground Plane Layout in Top View (preferred layout at top and bottom) ELECTRICAL SPECIFICATION Recommend Operation Conditions ranges is not guaranteed. Operating outside the recommended operating ranges for extended periods of time may affect device reliability. Operating ranges define the limits for functional operation and parametric characteristics of the device. Note that the functionality of the chip outside these operating Table 4. OPERATING RANGES Symbol Parameter Min Max Unit VBB Motor Driver Analog DC supply 6 30 V VCC CAN transceiver DC supply 4.75 5.25 V Junction temperature (Note 8) −40 +172 °C TJ 8. No more than 100 cumulative hours in life time above Ttw. http://onsemi.com 6 AMIS−30523 Table 5. DC PARAMETERS MOTOR DRIVER (The DC Parameters are Given for VBB and Temperature in Their Operating Ranges Unless Otherwise Specified) Convention: Currents Flowing in the Circuit are Defined as Positive. Symbol Pin(s) Remark/ Test Conditions Parameter Min Typ Max Unit 30 V SUPPLY AND VOLTAGE REGULATOR VBB IBB Nominal operating supply range 6 Total internal current consumption Unloaded outputs 8 mA IBBS Sleep current in VBB (Note 9) Unloaded outputs 100 mA VDD Regulated Output Voltage 5.50 V IINT Internal load current 8 mA ILOAD VBB VDD IDDLIM 4.50 Unloaded outputs Max. Output Current (external and internal loads) Current limitation ILOAD_PD 5 6 V v VBB < 8 V 15 mA 8 V v VBB v 30 V 40 mA Pin shorted to ground Output current in Power Down 200 1 mA mA POWER ON RESET (POR) VDDH VDDL VDD VDDHYS Internal POR comparator threshold VDD rising Internal POR comparator threshold VDD falling Hysteresis between VDDH and VDDL 3.9 4.15 4.4 3.80 0.1 0.35 V V 0.6 V MOTORDRIVER IMDmax,Peak Max current through motor coil in normal operation 1600 mA IMdmax,RMS Max RMS current through coil in normal operation 800 mA IMdabs Absolute error on coil current −10 10 % IMdrel Error on current ratio Icoilx / Icoily −7 7 % ISET_TC1 Temperature coefficient of coil current set−level, CUR[4:0] = 0 ... 27 (Note 10) −40 °C v TJ v 160°C −240 ppm/K ISET_TC2 Temperature coefficient of coil current set−level, CUR[4:0] = 28 ... 31 (Note 10) −40 °C v TJ v 160°C −490 ppm/K VBB = 12 V, TJ = 27°C 0.45 0.56 W VBB = 12 V, TJ = 160°C 0.94 1.25 W VBB = 12 V, TJ = 27°C 0.45 0.56 W VBB = 12 V, TJ = 160°C 0.94 1.25 W VBB = 12 V, TJ = 27°C 0.90 1.2 W VBB = 12 V, TJ = 160°C 1.9 2.5 W VBB = 12 V, TJ = 27°C 1.8 2.3 W VBB = 12 V, TJ = 160°C 3.8 5.0 W RHS RLS3 RLS2 RLS1 RLS0 IMpd MOTXP On−resistance high−side driver, MOTXN CUR[4:0] = 0 ... 31 MOTYP MOTYN On−resistance low−side driver, CUR[4:0] = 23 ... 31 On−resistance low−side driver, CUR[4:0] = 16 ... 22 On−resistance low−side driver, CUR[4:0] = 9 ... 15 On−resistance low−side driver, CUR[4:0] = 0 ... 8 Pull down current motor pins VBB = 12 V, TJ = 27°C 3.6 4.5 W VBB = 12 V, TJ = 160°C 7.5 10 W HiZ mode 1 9. Characterization Data Only, not tested in production 10. The coil current at a given junction temperature is calculated as: Icoil @ TJ = Icoil [1 + (TJ − 125) x ISET_TCi x 10−6]. See also paragraph Programmable Peak Current. 11. Not valid for pins with internal Pull Down resistor. 12. No more than 100 cumulated hours in life time above Ttw. 13. Thermal shutdown is derived from Thermal Warning. http://onsemi.com 7 mA AMIS−30523 Table 5. DC PARAMETERS MOTOR DRIVER (The DC Parameters are Given for VBB and Temperature in Their Operating Ranges Unless Otherwise Specified) Convention: Currents Flowing in the Circuit are Defined as Positive. Symbol Pin(s) Remark/ Test Conditions Parameter Min Typ Max Unit 1 mA 0 0.65 V 2.20 VDD V DIGITAL INPUTS Ileak VIL VIH DI, CLK Input Leakage (Note 11) NXT, Logic Low Threshold DIR CLR, Logic High Threshold CSB TJ = 160°C Rpd_CLR CLR Internal Pull Down Resistor 120 300 kW Rpd_TST TST0 Internal Pull Down Resistor 3 9 kW 0.3 V 152 °C DIGITAL OUTPUTS VOL DO, ERRB, PORB/ WD Logic Low level open drain IOL = 5 mA THERMAL WARNING & SHUTDOWN Ttw Thermal Warning 138 Ttsd Thermal shutdown (Notes 12 and 13) 145 Ttw + 20 °C 2 * VBB –2 V CHARGE PUMP VopCP Output voltage 6 V< VBB < 15 V VCP 15 V < VBB < 30 V VBB + 9 VBB + 11.5 VBB + 16 V PACKAGE THERMAL RESISTANCE VALUE Thermal Resistance Junction−to−Ambient RthJ−A RthJ−EP QFN package Simulated Conform JEDEC JESD−51, (2S2P) Thermal Resistance Junction−to−Exposed Pad 30 K/W 0.95 K/W SPEED AND LOAD ANGLE OUTPUT Vout Output Voltage Range 0.2 VDD − 0.2 V Voff Output Offset SLA pin −50 50 mV 1 kW 50 pF Gsla SLA Gain of SLA Pin = VBEMF / VCOIL SLAG = 0 0.5 SLAG = 1 0.25 Rout Output Resistance SLA pin (Note 9) 0.23 Cload Load Capacitance SLA pin (Note 9) 9. Characterization Data Only, not tested in production 10. The coil current at a given junction temperature is calculated as: Icoil @ TJ = Icoil [1 + (TJ − 125) x ISET_TCi x 10−6]. See also paragraph Programmable Peak Current. 11. Not valid for pins with internal Pull Down resistor. 12. No more than 100 cumulated hours in life time above Ttw. 13. Thermal shutdown is derived from Thermal Warning. http://onsemi.com 8 AMIS−30523 Table 6. AC PARAMETERS MOTOR DRIVER (The AC Parameters are Given for VBB and Temperature in Their Operating Ranges) Symbol Pin(s) Remark/ Test Conditions Parameter Min Typ Max Unit 3.6 4 4.4 MHz 20.8 22.8 24.8 kHz 41.6 45.6 49.6 kHz INTERNAL OSCILLATOR Frequency of internal oscillator fosc MOTOR DRIVER fPWM Frequency depends only on internal oscillator PWM frequency MOTxx fd Double PWM frequency PWM jitter Depth (Note 14) tbrise Turn−on voltage slope, 10% to 90% MOTxx tbfall Turn−off voltage slope, 90% to 10% MOTxx 10 % fPWM EMC[1:0] = 00 150 V/ms EMC[1:0] = 01 100 V/ms EMC[1:0] = 10 50 V/ms EMC[1:0] = 11 25 V/ms EMC[1:0] = 00 150 V/ms EMC[1:0] = 01 100 V/ms EMC[1:0] = 10 50 V/ms EMC[1:0] = 11 25 V/ms DIGITAL OUTPUTS tH2L DO ERRB Capacitive load 400 pF and pull−up resistor of 1.5 kW Output fall−time from VinH to VinL (Note 14) 50 ns CHARGE PUMP fCP tCPU CPN CPP MOTxx Charge pump frequency 250 Start−up time of charge pump (Note 14) Spec external components See Table 10 kHz 5 ms CLR FUNCTION tCLR CLR Hard reset duration time 100 ms POWER−UP tPU tPOR PORB/ WD tRF Power−up time VBB = 12 V, ILOAD = 50 mA, CLOAD = 220 nF 110 ms Reset duration See Figure 22 100 ms Reset filter time See Figure 22 1 Watchdog time out interval See Figure 23 32 Prohibited watchdog acknowledge delay See Figure 23 NXT Minimum, High Pulse Width See Figure 5 2 ms NXT Minimum, Low Pulse Width See Figure 5 2 ms NXT Hold Time, Following Change of DIR See Figure 5 2 ms NXT Hold Time, Before Change of DIR See Figure 5 2 ms ms WATCHDOG tWDTO tWDPR PORB/ WD 512 2 ms ms NXT FUNCTION tNXT_HI tNXT_HI tDIR_SET tDIR_HOLD NXT 14. Characterization Data Only, not tested in production. http://onsemi.com 9 AMIS−30523 tNXT_HI tNXT_LO 0.5 VCC NXT tDIR_SET ÌÌÌ ÌÌÌ ÌÌÌ DIR tDIR_HOLD VALID ÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌ Figure 5. NXT−Input Timing Diagram Table 7. SPI TIMING PARAMETERS Symbol Parameter tCLK SPI clock period tCLK_HIGH Min Typ Max Unit 1 ms SPI clock high time 100 ns tCLK_LOW SPI clock low time 100 ns tSET_DI DI set up time, valid data before rising edge of CLK 50 ns tHOLD_DI DI hold time, hold data after rising edge of CLK 50 ns tCSB_HIGH CSB high time 2.5 ms tSET_CSB CSB set up time, CSB low before rising edge of CLK 100 ns tSET_CLK CLK set up time, CLK low before rising edge of CSB 100 ns CS 0.2 VCC tSET_CSB 0.2 VCC tCLK tSET_CLK 0.8 VCC CLK 0.2 VCC 0.2 VCC tCLK_HI DI ÌÌ ÌÌ ÌÌ ÌÌ tSET_DI tHOLD_DI 0.8 VCC VALID tCLK_LO ÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌ Figure 6. SPI Timing http://onsemi.com 10 AMIS−30523 Table 8. DC PARAMETERS CAN TRANSCEIVER (The DC parameters are given for VCC and temperature in its operating range; TJ = −40 to +150°C; RLT = 60 W unless otherwise specified) Convention: currents flowing in the circuit are defined as positive. Symbol Pin(s) Remark / Test Conditions Parameter Min Typ Max Unit SUPPLY ICC VCC ICCS Supply current Dominant; VTxD = 0 V Recessive; VTxD = VCC 45 65 mA Supply current in standby mode TJ,max = 100°C 4 8 mA TRANSMITTER DATA INPUT ViH High−level input voltage CAN bus output recessive 2.0 − VCC + 0.3 V ViL Low−level input voltage CAN bus output dominant −0.3 − +0.8 V High−level input current VTxD = VCC −5 0 +5 mA IiL Low−level input current VTxD = 0 V −75 −200 −350 mA Ci Input capacitance (Note 15) − 5 10 pF IiH TXD TRANSMITTER MODE SELECT High−level input voltage Standby mode 2.0 − VCC + 0.3 V Low−level input voltage Normal mode −0.3 − +0.8 V High−level input current VSTB = VCC −5 0 +5 mA IiL Low−level input current VSTB = 0 V −1 −4 −10 mA Ci Input capacitance (Note 15) − 5 10 pF 0.75 x VCC V 0.25 0.45 V ViH ViL IiH TXD RECEIVER DATA OUTPUT High−level output voltage IRXD = −10 mA Low−level output voltage IRXD = 5 mA High−level output current Vo = 0.7 x VCC −5 −10 −15 mA Iol Low−level output current Vo = 0.3 x VCC 5 10 15 mA Ci Input capacitance (Note 15) − 5 10 pF VOH VOL Ioh RXD 15. Characterization Data Only, not tested in production. http://onsemi.com 11 0.6 x VCC AMIS−30523 Table 8. DC PARAMETERS CAN TRANSCEIVER (The DC parameters are given for VCC and temperature in its operating range; TJ = −40 to +150°C; RLT = 60 W unless otherwise specified) Convention: currents flowing in the circuit are defined as positive. Symbol Pin(s) Remark / Test Conditions Parameter Min Typ Max Unit BUS LINES Vo(reces) Recessive bus voltage VTxD = VCC; no load normal mode 2.0 2.5 3.0 V Recessive bus voltage VTxD = VCC; no load standby mode −100 0 100 mV Recessive output current at pin CANH −35 V < VCANH< +35 V; 0 V < VCC < 5.25 V −2.5 − +2.5 mA Recessive output current at pin CANL −35 V <VCANL < +35 V; 0 V <VCC < 5.25 V −2.5 − +2.5 mA Dominant output voltage at pin CANH VTxD = 0 V 3.0 3.6 4.25 V Dominant output voltage at pin CANL VTxD = 0 V 0. 5 1.4 1.75 V Differential bus output voltage (VCANH − VCANL) VTxD = 0 V; dominant; 42.5 W < RLT < 60 W 1.5 2.25 3.0 V Differential bus output voltage (VCANH − VCANL) VTxD = VCC; recessive; no load −120 0 +50 mV Short circuit output current at pin CANH VCANH = 0 V; VTxD = 0 V −45 −70 −120 mA Short circuit output current at pin CANL VCANL = 36 V; VTxD = 0V 45 70 120 mA Differential receiver threshold voltage (see Figure 8) −5 V < VCANL < +12 V; −5 V < VCANH < +12 V; 0.5 0.7 0.9 V Differential receiver threshold voltage for high common−mode (see Figure 8)) −35 V < VCANL < +35 V; −35 V < VCANH < +35 V; 0.40 0.7 1.00 V Differential receiver input voltage hysteresis (see Figure 8) −35 V < VCANL < +35 V; −35 V < VCANH < +35 V; 50 70 100 mV (norm) Vo(reces) (stby) Io(reces) (CANH) Io(reces) (CANL) Vo(dom) (CANH) Vo(dom) (CANL) Vo(dif) (bus_dom) Vo(dif) (bus_rec) Io(sc) (CANH) CANH CANL Io(sc) (CANL) Vi(dif) (th) Vihcm(dif) (th) Vi(dif) (hys) Ri(cm) (CANH) Common−mode input resistance at pin CANH 15 26 37 kW Ri(cm) (CANL) Common−mode input resistance at pin CANL 15 26 37 kW −3 0 +3 % 25 50 75 kW Ri(cm) (m) Matching between pin CANH and pin CANL common mode input resistance Ri(dif) Differential input resistance Ci(CANH) Ci(CANL) VCANH = VCANL CANH CANL Ci(dif) Input capacitance at pin CANH VTxD = VCC; (Note 15) 7.5 20 pF Input capacitance at pin CANL VTxD = VCC; (Note 15) 7.5 20 pF Differential input capacitance VTxD = VCC; (Note 15) 3.75 10 pF − 0.7 x VCC COMMON−MODE STABILIZATION VSPLIT ISPLIT(i) ISPLIT(lim) VSPLIT Reference output voltage at pin VSPLIT Normal mode; −500 mA < ISPLIT < 500 mA 0.3 x VCC VSPLIT leakage current Stand−by mode −5 +5 mA VSPLIT limitation current Normal mode −3 +3 mA CANH, CANL, Vref in tri−state below POR level 2.2 4.7 V POWER ON RESET (POR) PORL POR level 15. Characterization Data Only, not tested in production. http://onsemi.com 12 3.5 AMIS−30523 Table 9. AC PARAMETER CAN TRANSCEIVER The AC parameters are given for VCC and temperature in its operating range; TJ = −40 to +150°C; RLT = 60 W unless otherwise specified Symbol Pin(s) Remark / Test Conditions Parameter Min Typ Max Unit TIMING CHARACTERISTICS td(TxD−BUSon) Delay TXD to bus active Cl = 100 pF between CANH to CANL 40 85 105 ns td(TxD−BUSoff) Delay TXD to bus inactive Cl = 100 pF between CANH to CANL 30 60 105 ns td(BUSon−RXD) Delay bus active to RXD Crxd = 15 pF 25 55 105 ns td(BUSoff−RXD) Delay bus inactive to RXD Crxd = 15 pF 40 100 105 ns tpd(rec−dom) Propagation delay TXD to RXD from recessive to dominant Cl = 100 pF between CANH to CANL 90 230 ns td(dom−rec) Propagation delay TXD to RXD from dominant to recessive Cl = 100 pF between CANH to CANL 90 245 ns td(stb−nm) Delay standby mode to normal mode tdbus Dominant time for wake−up via bus 5 7.5 10 ms 0.75 2.5 5 ms 16. Characterization Data Only, not tested in production +5 V 100 nF VCC 4 TxD 1 nF 52 AMIS− 30523 RxD 6 7 49 51 20 pF CANH 48 STB 2 VSPLIT Transient Generator 1 nF CANL GND Figure 7. Test Circuit for Transients VRxD High Low Hysteresis 0.9 0.5 Figure 8. Hysteresis of the Receiver http://onsemi.com 13 Vi(dif)(hys) AMIS−30523 +5 V 100 nF VCC 4 TxD 52 AMIS− 30523 RxD CANH 48 6 7 RLT VSPLIT 20 pF CANL 2 STB 100 pF 60 W 49 51 CLT GND Figure 9. Test Circuit for Timing Characteristics TxD 50% 50% VO(dom)CANH VCANH VO(reces) VCANL VO(dom)CANL Vi(dif) = VCANH-VCANL 0.9V Vi(dif)dom 0.5V td(BUSon-RxD) Vi(dif)rec td(TxD-BUSoff) td(BUSoff-RxD) 0.7VCC RxD td(TxD-BUSon) 0.3VCC td(dom-rec) td(rec-dom) PC20101012.1 Figure 10. Timing Diagram for AC Characteristics +5 V 100 nF VCC 4 TxD 48 AMIS−49 30523 6 7 51 20 pF 10 nF 52 Generator RxD 6.2 kW CANH STB 2 Active Probe CANL 6.2 kW 30 W VSPLIT 30 W 47 nF GND Figure 11. Basic Test Set−up for EME http://onsemi.com 14 Spectrum Anayzer AMIS−30523 Figure 12. EME Measurements http://onsemi.com 15 AMIS−30523 R3 VDD CPN R2 VCC POR/WD RESET 220 nF SPI interface ERR 18 DO 45 DI 8 CLK 9 CS 24 20 CPP 21 100 nF 100 nF VCP 22 C3 VBB POSITION feedback TXD 38, 39 34, 35 27, 28 31, 32 AMIS−30523 48 MOTXP MOTXN 7 MOTYN CANH VSPLIT R6 49 51 23 CLR 19 1 2 29 30 36 37 SLA CANL C9 1 D1 CAN −bus 3 47 nF 2 43 TSTO GND R1 M MOTYP R5 10 6 STB 100 mF VBB 52 RXD C2 C1 25, 26 40, 41 17 NXT CAN controller 46 C4 42 DIR MOTOR positioner 6 220 nF 100 nF C5 56 W DRIVER diagnostic C6 R4 VBB 56 W mC 10 kW 10 kW 1 kW C7 100 nF TYPICAL APPLICATION SCHEMATIC PC20100126.1 100 W 10 nF C8 Figure 13. Typical Application Schematic AMIS−30523 Table 10. EXTERNAL COMPONENTS LIST AND DESCRIPTION Component Function Typ Value Tolerance Unit C1 VBB buffer capacitor (Note 17) 100 −20 +80% mF C2, C3 VBB decoupling block capacitor 100 −20 +80% nF C4 Charge−pump pumping capacitor 220 $20% nF C5 Charge−pump buffer capacitor 220 $20% nF C6, C7 VDD buffer capacitor 100 $20 % nF C8 Low pass filter SLA 10 $20% nF C9 VSPLIT decoupling capacitor 47 $20% nF R1 Low pass filter SLA 100 $1% W R2 Pull up resistor open drain DO output 1 $1% kW R3, R4 Pull up resistor open drain output 10 $1% kW R5, R6 CAN termination resistors 56 $1% W D1 CAN protection diode NUP2105 17. Low ESR < 1 W. http://onsemi.com 16 AMIS−30523 FUNCTIONAL DESCRIPTION MOTOR DRIVER Introduction The power transistors are equipped with so−called “active diodes”: when a current is forced trough the transistor switch in the reverse direction, i.e. from source to drain, then the transistor is switched on. This ensures that most of the current flows through the channel of the transistor instead of through the inherent parasitic drain−bulk diode of the transistor. Depending on the desired current range and the micro−step position at hand, the RDS(on) of the low−side transistors will be adapted such that excellent current−sense accuracy is maintained. The RDS(on) of the high−side transistors remain unchanged; see Table 5 DC Parameters Motor driver, for more details. The AMIS−30523 is a micro−stepping stepper motor driver for bipolar stepper motors embedded with an integrated CAN transceiver. The motor driver is connected through I/O pins and a SPI interface with an external microcontroller. It has an on−chip voltage regulator, reset−output and watchdog reset, able to supply peripheral devices. It contains a current−translation table and takes the next micro−step depending on the clock signal on the “NXT” input pin and the status of the “DIR” (=direction) register or input pin. A proprietary PWM algorithm is used for reliable current control. The motor driver provides a so−called “speed and load angle” output. This allows the creation of stall detection algorithms and control loops based on load−angle to adjust torque and speed. PWM Current Control A PWM comparator compares continuously the actual winding current with the requested current and feeds back the information to a digital regulation loop. This loop then generates a PWM signal, which turns on/off the H−bridge switches. The switching points of the PWM duty−cycle are synchronized to the on−chip PWM clock. The frequency of the PWM controller can be doubled and an artificial jitter can be added (see Table 15 SPI Control Parameter Overview PWMJ). The PWM frequency will not vary with changes in the supply voltage. Also variations in motor−speed or load−conditions of the motor have no effect. There are no external components required to adjust the PWM frequency. H−Bridge Drivers A full H−bridge is integrated for each of the two stator windings. Each H−bridge consists of two low−side and two high−side N−type MOSFET switches. Writing logic ‘0’ in bit <MOTEN> disables all drivers (high−impedance). Writing logic ‘1’ in this bit enables both bridges and current can flow in the motor stator windings. In order to avoid large currents through the H−bridge switches, it is guaranteed that the top− and bottom−switches of the same half−bridge are never conductive simultaneously (interlock delay). A two−stage protection against shorts on motor lines is implemented. In a first stage, the current in the driver is limited. Secondly, when excessive voltage is sensed across the transistor, the transistor is switched off. In order to reduce the radiated/conducted emission, voltage slope control is implemented in the output switches. The output slope is defined by the gate−drain capacitance of output transistor and the (limited) current that drives the gate. There are two trimming bits for slope control (see Table 15 SPI Control Parameter Overview EMC[1:0]). Automatic Forward and Slow−Fast Decay The PWM generation is in steady−state using a combination of forward and slow−decay. The absence of fast−decay in this mode, guarantees the lowest possible current−ripple “by design”. For transients to lower current levels, fast−decay is automatically activated to allow high−speed response. The selection of fast or slow decay is completely transparent for the user and no additional parameters are required for operation. Icoil Set value Actual value t 0 TPWM Forward & Slow Decay Forward & Slow Decay Fast Decay & Forward Figure 14. Forward and Slow/Fast Decay PWM http://onsemi.com 17 AMIS−30523 Automatic Duty Cycle Adaptation process is completely automatic and requires no additional parameters for operation. The over−all current−ripple is divided by two if PWM frequency is doubled (see Table 15 SPI Control Parameter Overview PWMF) In case the supply voltage is lower than 2 * Bemf, then the duty cycle of the PWM is adapted automatically to >50% to maintain the requested average current in the coils. This Icoil Duty Cycle < 50% Duty Cycle < 50% Duty Cycle >50% Actual value Set value t TPWM Figure 15. Automatic Duty Cycle Adaption Step Translator and Step Mode corresponding stepping mode. When remaining in the same step mode, subsequent translator positions are all in the same column and increased or decreased with 1. Table 12 lists the output current vs. the translator position. As shown in Figure 16 the output current−pairs can be projected approximately on a circle in the (Ix,Iy) plane. There are, however, two exceptions: uncompensated half step and full step. In these step modes the currents are not regulated to a fraction of Imax but are in all intermediate steps regulated at 100%. In the (Ix,Iy) plane the current−pairs are projected on a square. Table 11 lists the output current vs. the translator position for these cases. The step translator provides the control of the motor by means of SPI register Stepmode: SM[2:0], SPI register DIRCNTRL and input pins DIR and NXT. It is translating consecutive steps in corresponding currents in both motor coils for a given step mode. One out of seven possible stepping modes can be selected through SPI−bits SM[2:0] (see Table 15 SPI Control Parameter Overview ) After power−on or hard reset, the coil−current translator is set to the default 1/32 micro−stepping at position ‘0’. Upon changing the step mode, the translator jumps to position 0* of the http://onsemi.com 18 AMIS−30523 Table 11. SQUARE TRANSLATOR TABLE FOR FULL STEP AND UNCOMPENSATED HALF STEP Stepmode ( SM[2:0] ) % of Imax 101 110 MSP[6:0] Uncompensated Half−Step Full Step Coil x Coil y 000 0000 0 − 0 100 001 0000 1 1 100 100 010 0000 2 − 100 0 011 0000 3 2 100 −100 100 0000 4 − 0 −100 101 0000 5 3 −100 −100 110 0000 6 − −100 0 111 0000 7 0 −100 100 IY Start = 0 IY Step 1 Step 2 Step 1 Start = 0 Step 3 IY Step 1 Step 2 I X IX Step 3 1/4th Micro Step SM[2:0] = 011 Start = 0 IX Step 3 Uncompensated Half Step SM[2:0] = 101 Figure 16. Translator Table: Circular and Square http://onsemi.com 19 Step 2 Full Step SM[2:0] = 110 AMIS−30523 Table 12. CIRCULAR TRANSLATOR TABLE Stepmode (SM[2:0]) MSP[6:0] 000 0000 000 0001 000 0010 000 0011 000 0100 000 0101 000 0110 000 0111 000 1000 000 1001 000 1010 000 1011 000 1100 000 1101 000 1110 000 1111 001 0000 001 0001 001 0010 001 0011 001 0100 001 0101 001 0110 001 0111 001 1000 001 1001 001 1010 001 1011 001 1100 001 1101 001 1110 001 1111 010 0000 010 0001 010 0010 010 0011 010 0100 010 0101 010 0110 010 0111 010 1000 010 1001 010 1010 010 1011 010 1100 010 1101 010 1110 010 1111 011 0000 011 0001 011 0010 011 0011 011 0100 011 0101 011 0110 011 0111 011 1000 011 1001 011 1010 011 1011 011 1100 011 1101 011 1110 011 1111 % of Imax 000 001 010 011 100 1/32 1/16 1/8 1/4 1/2 ‘0’ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 0* − 1 − 2 − 3 − 4 − 5 − 6 − 7 − 8 − 9 − 10 − 11 − 12 − 13 − 14 − 15 − 16 − 17 − 18 − 19 − 20 − 21 − 22 − 23 − 24 − 25 − 26 − 27 − 28 − 29 − 30 − 31 − 0* − − − 1 − − − 2 − − − 3 − − − 4 − − − 5 − − − 6 − − − 7 − − − 8 − − − 9 − − − 10 − − − 11 − − − 12 − − − 13 − − − 14 − − − 15 − − − 0* − − − − − − − 1 − − − − − − − 2 − − − − − − − 3 − − − − − − − 4 − − − − − − − 5 − − − − − − − 6 − − − − − − − 7 − − − − − − − 0* − − − − − − − − − − − − − − − 1 − − − − − − − − − − − − − − − 2 − − − − − − − − − − − − − − − 3 − − − − − − − − − − − − − − − http://onsemi.com 20 Coil x 0 3.5 8.1 12.7 17.4 22.1 26.7 31.4 34.9 38.3 43 46.5 50 54.6 58.1 61.6 65.1 68.6 72.1 75.5 79 82.6 84.9 87.2 89.5 91.8 93 94.1 95.3 96.5 97.7 98.8 100 98.8 97.7 96.5 95.3 94.1 93 91.8 89.5 87.2 84.9 82.6 79 75.5 72.1 68.6 65.1 61.6 58.1 54.6 50 46.5 43 38.3 34.9 31.4 26.7 22.1 17.4 12.7 8.1 3.5 Coil y 100 98.8 97.7 96.5 95.3 94.1 93 91.8 89.5 87.2 84.9 82.6 79 75.5 72.1 68.6 65.1 61.6 58.1 54.6 50 46.5 43 38.3 34.9 31.4 26.7 22.1 17.4 12.7 8.1 3.5 0 −3.5 −8.1 −12.7 −17.4 −22.1 −26.7 −31.4 −34.9 −38.3 −43 −46.5 −50 −54.6 −58.1 −61.6 −65.1 −68.6 −72.1 −75.5 −79 −82.6 −84.9 −87.2 −89.5 −91.8 −93 −94.1 −95.3 −96.5 −97.7 −98.8 AMIS−30523 Table 12. CIRCULAR TRANSLATOR TABLE Stepmode ( SM[2:0] ) % of Imax 000 001 010 011 100 MSP[6:0] 1/32 1/16 1/8 1/4 1/2 Coil x Coil y 100 0000 100 0001 100 0010 100 0011 100 0100 100 0101 100 0110 100 0111 100 1000 100 1001 100 1010 100 1011 100 1100 100 1101 100 1110 100 1111 101 0000 101 0001 101 0010 101 0011 101 0100 101 0101 101 0110 101 0111 101 1000 101 1001 101 1010 101 1011 101 1100 101 1101 101 1110 101 1111 110 0000 110 0001 110 0010 110 0011 110 0100 110 0101 110 0110 110 0111 110 1000 110 1001 110 1010 110 1011 110 1100 110 1101 110 1110 110 1111 111 0000 111 0001 111 0010 111 0011 111 0100 111 0101 111 0110 111 0111 111 1000 111 1001 111 1010 111 1011 111 1100 111 1101 111 1110 111 1111 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 32 − 33 − 34 − 35 − 36 − 37 − 38 − 39 − 40 − 41 − 42 − 43 − 44 − 45 − 46 − 47 − 48 − 49 − 50 − 51 − 52 − 53 − 54 − 55 − 56 − 57 − 58 − 59 − 60 − 61 − 62 − 63 − 16 − − − 17 − − − 18 − − − 19 − − − 20 − − − 21 − − − 22 − − − 23 − − − 24 − − − 25 − − − 26 − − − 27 − − − 28 − − − 29 − − − 30 − − − 31 − − − 8 − − − − − − − 9 − − − − − − − 10 − − − − − − − 11 − − − − − − − 12 − − − − − − − 13 − − − − − − − 14 − − − − − − − 15 − − − − − − − 4 − − − − − − − − − − − − − − − 5 − − − − − − − − − − − − − − − 6 − − − − − − − − − − − − − − − 7 − − − − − − − − − − − − − − − 0 −3.5 −8.1 −12.7 −17.4 −22.1 −26.7 −31.4 −34.9 −38.3 −43 −46.5 −50 −54.6 −58.1 −61.6 −65.1 −68.6 −72.1 −75.5 −79 −82.6 −84.9 −87.2 −89.5 −91.8 −93 −94.1 −95.3 −96.5 −97.7 −98.8 −100 −98.8 −97.7 −96.5 −95.3 −94.1 −93 −91.8 −89.5 −87.2 −84.9 −82.6 −79 −75.5 −72.1 −68.6 −65.1 −61.6 −58.1 −54.6 −50 −46.5 −43 −38.3 −34.9 −31.4 −26.7 −22.1 −17.4 −12.7 −8.1 −3.5 −100 −98.8 −97.7 −96.5 −95.3 −94.1 −93 −91.8 −89.5 −87.2 −84.9 −82.6 −79 −75.5 −72.1 −68.6 −65.1 −61.6 −58.1 −54.6 −50 −46.5 −43 −38.3 −34.9 −31.4 −26.7 −22.1 −17.4 −12.7 −8.1 −3.5 0 3.5 8.1 12.7 17.4 22.1 26.7 31.4 34.9 38.3 43 46.5 50 54.6 58.1 61.6 65.1 68.6 72.1 75.5 79 82.6 84.9 87.2 89.5 91.8 93 94.1 95.3 96.5 97.7 98.8 http://onsemi.com 21 AMIS−30523 Direction Synchronization of Step Mode and NXT Input The direction of rotation is selected by means of following combination of the DIR input pin and the SPI−controlled direction bit <DIRCTRL>. (see Table 15 SPI Control Parameter Overview) When step mode is re−programmed to another resolution (Figure 18), then this is put in effect immediately upon the first arriving “NXT” input. If the micro−stepping resolution is increased, the coil currents will be regulated to the nearest micro−step, according to the fixed grid of the increased resolution. If however the micro−stepping resolution is decreased, then it is possible to introduce an offset (or phase shift) in the micro−step translator table. If the step resolution is decreased at a translator table position that is shared both by the old and new resolution setting, then the offset is zero and micro−stepping is proceeds according to the translator table. If the translator position is not shared both by the old and new resolution setting, then the micro−stepping proceeds with an offset relative to the translator table (See Figure 18 right hand side). More information can be found in application note AND8399/D. NXT input Changes on the NXT input will move the motor current one step up/down in the translator table (even when the motor is disabled). Depending on the NXT−polarity bit <NXTP> (see Table 15 SPI Control Parameter Overview), the next step is initiated either on the rising edge or the falling edge of the NXT input. Translator Position The translator position MSP[6:0] can be read in SPI Status Register 3 (See Table 18 SPI Status Registers). This is a 7−bit number equivalent to the 1/32th micro−step from Table 12 “Circular Translator Table”. The translator position is updated immediately following a NXT trigger. NXT Update Translator Position Update Translator Position Figure 17. Translator Position Timing Diagram Change from lower to higher resolution IY IY DIR endpos Change from higher to lower resolution NXT2 NXT3 NXT4 NXT1 IX Halfstep IY DIR endpos IY DIR startpos NXT1 startpos DIR NXT2 IX IX 1/4th Step 1/8th Step IX NXT3 Halfstep Figure 18. NXT−Step−Mode Synchronization Left: change from lower to higher resolution. The left−hand side depicts the ending half−step position during which a new step mode resolution was programmed. The right−hand side diagram shows the effect of subsequent NXT commands on the micro−step position. Right: change from higher to lower resolution. The left−hand side depicts the ending micro−step position during which a new step mode resolution was programmed. The right−hand side diagram shows the effect of subsequent NXT commands on the half−step position. NOTE: It is advised to reduce the micro−stepping resolution only at micro−step positions that overlap with desired micro−step positions of the new resolution. Programmable Peak−Current Overview). Whenever this parameter is changed, the coil−currents will be updated immediately at the next PWM period. Figure 19 presents the Peak−Current and Current Ratings in conjunction to the Current setting CUR[4:0]. The amplitude of the current waveform in the motor coils (coil peak current = Imax) is adjusted by means of an SPI parameter “CUR[4:0]” (see Table 15 SPI Control Parameter http://onsemi.com 22 AMIS−30523 Peak Current 1.48 A Current Range 3 CUR[4:0] = 23 −> 31 630 mA Current Range 2 CUR[4:0] = 16 −> 22 325 mA Current Range 1 CUR[4:0] = 9 −> 15 166 mA Current Range 0 CUR[4:0] = 0 −> 8 0 8 15 22 31 CUR[4:0] Figure 19. Programmable Peak−Current Overview Speed and Load Angle Output current zero crossings”. Per coil, two zero−current positions exist per electrical period, yielding in total four zero−current observation points per electrical period. The SLA−pin provides an output voltage that indicates the level of the Back−e.m.f. voltage of the motor. This Back−e.m.f. voltage is sampled during every so−called ”coil VBEMF ICOIL t ZOOM Previous Micro−Step ICOIL Coil Current Zero Crossing Next Micro−Step Current Decay Zero Current t VCOIL Voltage Transient VBB |VBEMF| t Figure 20. Principle of Bemf Measurement http://onsemi.com 23 AMIS−30523 generates smoother Back e.m.f. input for post−processing, e.g. by software. In order to bring the sampled Back e.m.f. to a descent output level (0 to 5 V), the sampled coil voltage VCOIL is divided by 2 or by 4. This divider is set through an SPI bit <SLAG> (see Table 15 SPI Control Parameter Overview). The following drawing illustrates the operation of the SLA−pin and the transparency−bit. “PWMsh” and “Icoil = 0” are internal signals that define together with SLAT the sampling and hold moments of the coil voltage. More information can be found in application note AND8399/D. Because of the relatively high recirculation currents in the coil during current decay, the coil voltage VCOIL shows a transient behavior. As this transient is not always desired in application software, two operating modes can be selected by means of the bit <SLAT> (see “SLA−transparency” in Table 15 SPI Control Parameter Overview). The SLA pin shows in “transparent mode” full visibility of the voltage transient behavior. This allows a sanity−check of the speed−setting versus motor operation and characteristics and supply voltage levels. If the bit “SLAT” is cleared, then only the voltage samples at the end of each coil current zero crossing are visible on the SLA−pin. Because the transient behavior of the coil voltage is not visible anymore, this mode VCOIL div2 div4 Ssh Sh buf SLA−Pin Ch Csh Icoil=0 PWMsh SLAT NOT (Icoil=0) PWMsh Icoil=0 SLAT VCOIL t SLA−Pin last sample is retained VBEMF previous output is kept at SLA pin retain last sample t SLAT = 0 => SLA−pin is not “transparent” during VBEMF sampling @ Coil Current Zero Crossing. SLA−pin is updated when leaving current−less state. SLAT = 1 => SLA−pin is “transparent” during VBEMF sampling @ Coil Current Zero Crossing. SLA−pin is updated “real−time”. Figure 21. Timing Diagram of SLA−Pin Warning, Error Detection and Diagnostics Feedback Over−Current Detection The over−current detection circuit monitors the load current in each activated output stage. If the load current exceeds the over−current detection threshold, then the over−current flag is set and the drivers are switched off to reduce the power dissipation and to protect the integrated circuit. Each driver transistor has an individual detection bit in (see Table 17 SPI Status registers Address SR1 and SR2: <OVCXij> and <OVCYij>). Error condition is latched and the microcontroller needs to clear the status bits (by reading Status Register 1 or 2) to reactivate the drivers. Thermal Warning and Shutdown When junction temperature rises above TTW, the thermal warning bit <TW> is set (Table 17 SPI Status registers Address SR0). If junction temperature increases above thermal shutdown level, then the circuit goes in “Thermal Shutdown” mode (<TSD>) and all driver transistors are disabled (high impedance) (see Table 17 SPI Status registers Address SR2). The conditions to reset flag <TSD> is to be at a temperature lower than TTW and to clear the <TSD> flag reading out Status Register 2. http://onsemi.com 24 AMIS−30523 Note: Successive reading the SPI StatusRegisters 1 and 2 in case of a short circuit condition, may lead to damage to the drivers the required threshold. During that time tCPU <CPFAIL> will be set to “1”. Error Output This is a digital output to flag a problem to the external microcontroller. The signal on this output is active low and the logic combination of: NOT(ERRB) = <TW> OR <TSD> OR <OVCXij> OR < OVCYij> OR <OPENi> OR <CPFAIL> This open drain output can be wired OR−ed with error outputs other motor drivers. Open Coil/Current Not Reached Detection Open coil detection is based on the observation of 100% duty cycle of the PWM regulator. If in a coil 100% duty cycle is detected for longer than 200 ms then the related driver transistors are disabled (high−impedance) and an appropriate bit in the SPI status register is set (<OPENX> or <OPENY>). (Table 17 SPI Status Register Address SR0) When the resistance of a motor coil is very large and the supply voltage is low, it can happen that the motor driver is not able to deliver the requested current to the motor. Under these conditions the PWM controller duty cycle will be 100% and after 200 ms the error pin and <OPENX>, <OPENY> will flag this situation (motor current is kept alive). This feature can be used to test if the operating conditions (supply voltage, motor coil resistance) still allow reaching the requested coil−current or else the coil current should be reduced. Logic Supply Regulator AMIS−30523 has an on−chip 5 V low−drop regulator with external capacitor to supply the digital part of the chip, some low−voltage analog blocks and external circuitry. The voltage level is derived from an internal bandgap reference. To calculate the available drive−current for external circuitry, the specified Iload should be reduced with the consumption of internal circuitry (unloaded outputs) and the loads connected to logic outputs. See Table 5 DC parameters Motor Driver. Charge Pump Failure The charge pump is an important circuit that guarantees low RDS(on) for all drivers, especially for low supply voltages. If supply voltage is too low or external components are not properly connected to guarantee RDS(on) of the drivers, then the bit <CPFAIL> is set in Table 17. Also after POR the charge pump voltage will need some time to exceed Power−On Reset (POR) Function The open drain output pin PORB/WD provides an “active low” reset for external purposes. At power−up of AMIS−30523, this pin will be kept low for some time to reset for example an external microcontroller. A small analogue filter avoids resetting due to spikes or noise on the VDD supply. VBB t tPU VDD tPD VDDH VDDL t < tRF POR/WD pin tPOR tRF Figure 22. Power−on−Reset Timing Diagram http://onsemi.com 25 AMIS−30523 Watchdog Function the timer is activated and WDEN is acknowledged too early (before tWDPR) or not within the interval (after tWDTO), then a reset of the microcontroller will occur through PORB/WD pin. In addition, a warm/cold boot bit <WD> is available in Table 17 for further processing when the external microcontroller is alive again. See Figure 23. The watchdog function is enabled/disabled through <WDEN> bit (See Table 15 SPI Control Registers address 00h). Once this bit has been set to “1” (watchdog enable), the microcontroller needs to re−write this bit to clear an internal timer before the watchdog timeout interval expires. In case VBB t tPU VDD VDDH t tPOR POR/WD pin tWDRD tDSPI tPOR Enable WD = tWDPR or = tWDTO > tWDPR and < tWDTO Acknowledge WD t tWDTO WD timer t Figure 23. Watchdog Timing Diagram NOTE: tDSPI is the time needed by the external microcontroller to shift−in the <WDEN> bit after a power−up. The duration of the watchdog timeout interval is programmable through the WDT[3:0] bits (See Table 14 SPI Control Registers address 00h). The timing is given in Table 13 below. http://onsemi.com 26 AMIS−30523 digital, charge pump remains active. Logic 0 on CLR pin resumes normal operation again. The voltage regulator remains functional during and after the reset and the PORB/WD pin is not activated. Watchdog function is reset completely. Table 13. WATCHDOG TIMEOUT INTERVAL AS FUNCTION OF WDT[3.0] Index WDT[3:0] tWDTO (ms) 0 0 0 0 0 32 1 0 0 0 1 64 2 0 0 1 0 96 3 0 0 1 1 128 4 0 1 0 0 160 5 0 1 0 1 192 6 0 1 1 0 224 7 0 1 1 1 256 8 1 0 0 0 288 9 1 0 0 1 320 A 1 0 1 0 352 B 1 0 1 1 384 C 1 1 0 0 416 D 1 1 0 1 448 E 1 1 1 0 480 F 1 1 1 1 512 Sleep Mode The bit <SLP> in SPI Control Register 2 (See Table 14 SPI Control Registers address 03h) is provided to enter a so−called “sleep mode”. This mode allows reduction of current−consumption when the motor is not in operation. The effect of sleep mode is as follows: • The drivers are put in HiZ • All analog circuits are disabled and in low−power mode • All internal registers are maintaining their logic content • NXT and DIR inputs are forbidden • SPI communication remains possible (slight current increase during SPI communication) • Oscillator and digital clocks are silent, except during SPI communication The voltage regulator remains active but with reduced current−output capability (ILOADSLP). The watchdog timer stops running and it’s value is kept in the counter. Upon leaving sleep mode, this timer continues from the value it had before entering sleep mode. Normal operation is resumed after writing logic ‘0’ to bit <SLP>. A start−up time is needed for the charge pump to stabilize. After this time, (tcpu) NXT commands can be issued. CLR Pin (= Hard Reset) Logic 0 on CLR pin allows normal operation of the chip. To reset the complete digital inside AMIS−30523, the input CLR needs to be pulled to logic 1 during minimum time given by tCLR. (See Table 6 AC Parameters Motor Driver). This reset function clears all internal registers without the need of a power−cycle, except in sleep mode. The operation of all analog circuits is depending on the reset state of the http://onsemi.com 27 AMIS−30523 SPI INTERFACE DO signal is the output from the Slave (AMIS−30523), and DI signal is the output from the Master. A chip select line (CSB) allows individual selection of a Slave SPI device in a multiple−slave system. The CSB line is active low. If AMIS−30523 is not selected, DO is pulled up with the external pull up resistor. Since AMIS−30523 operates as a Slave in MODE 0 (CPOL = 0; CPHA = 0) it always clocks data out on the falling edge and samples data in on rising edge of clock. The Master SPI port must be configured in MODE 0 too, to match this operation. The SPI clock idles low between the transferred bytes. The diagram below is both a Master and a Slave timing diagram since CLK, DO and DI pins are directly connected between the Master and the Slave. The serial peripheral interface (SPI) allows an external microcontroller (Master) to communicate with AMIS−30523. The implemented SPI block is designed to interface directly with numerous micro−controllers from several manufacturers. AMIS−30523 acts always as a Slave and can’t initiate any transmission. The operation of the device is configured and controlled by means of SPI registers which are observable for read and/or write from the Master. SPI Transfer Format and Pin Signals During a SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line (CLK) synchronizes shifting and sampling of the information on the two serial data lines (DO and DI). #CLK Cycle 1 2 3 4 5 6 7 8 CS CLK ÌÌÌÌ ÌÌÌÌ ÌÌÌ ÌÌÌ DI MSB 6 5 4 3 2 1 LSB DO MSB 6 5 4 3 2 1 LSB Figure 24. Timing Diagram of a SPI Transfer NOTE: At the falling edge of the eighth clock pulse the data−out shift register is updated with the content of the addressed internal SPI register. The internal SPI registers are updated at the first rising edge of the AMIS−30523 system clock when CS = High. Transfer Packet: Serial data transfer is assumed to follow MSB first rule. The transfer packet contains one or more bytes. BYTE 1 BYTE 2 Command and SPI Register Address Data MSB LSB MSB D7 CMD2 CMD1 CMD0 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 Command LSB D6 D5 D4 D3 D2 D1 D0 SPI Register Address Figure 25. SPI Transfer Packet Two command types can be distinguished in the communication between master and AMIS−30523: • READ from SPI Register with address ADDR[4:0]: CMD2 = “0” Byte 1 contains the Command and the SPI Register Address and indicates to AMIS−30523 the chosen type of operation and addressed register. Byte 2 contains data, or sent from the Master in a WRITE operation, or received from AMIS−30523 in a READ operation. http://onsemi.com 28 AMIS−30523 • WRITE to SPI Register with address ADDR[4:0]: address of the SPI register to be read out. At the falling edge of the eight clock pulse the data−out shift register is updated with the content of the corresponding internal SPI register. In the next 8−bit clock pulse train this data is shifted out via DO pin. At the same time the data shifted in from DI (Master) should be interpreted as the following successive command or dummy data. CMD2 = “1” READ Operation If the Master wants to read data from Status or Control Registers, it initiates the communication by sending a READ command. This READ command contains the Registers are updated with the internal status at the rising edge of the internal AMIS−30523 clock when CS = 1 CS COMMAND DI DATA from previous command or NOT VALID after POR or RESET DO READ DATA from ADDR1 COMMAND or DUMMY DATA DATA OLD DATA or NOT VALID DATA from ADDR1 Figure 26. Single READ Operation where DATA from SPI Register with Address 1 is Read by the Master immediately after the READ operation. For the same reason it is recommended to keep the CSB line high always when the SPI bus is idle. All 4 Status Registers (see Table 17 SPI Registers) contain 7 data bits and a parity check bit The most significant bit (D7) represents a parity of D[6:0]. If the number of logical ones in D[6:0] is odd, the parity bit D7 equals “1”. If the number of logical ones in D[6:0] is even then the parity bit D7 equals “0”. This simple mechanism protects against noise and increases the consistency of the transmitted data. If a parity check error occurs it is recommended to initiate an additional READ command to obtain the status again. Also the Control Registers can be read out following the same routine. Control Registers don’t have a parity check. The CSB line is active low and may remain low between successive READ commands as illustrated in Figure 28. There is however one exception. In case an error condition is latched in one of Status Registers (see Table 17 SPI Registers) the ERRB pin is activated. (See the Error Output section). This signal flags a problem to the external microcontroller. By reading the Status Registers information about the root cause of the problem can be determined. After this READ operation the Status Registers are cleared. Because the Status Registers and ERRB pin (see SPI Registers) are only updated by the internal system clock when the CSB line is high, the Master should force CSB high WRITE Operation If the Master wants to write data to a Control Register it initiates the communication by sending a WRITE command. This contains the address of the SPI register to write to. The command is followed with a data byte. This incoming data will be stored in the corresponding Control Register after CSB goes from low to high! AMIS−30523 responds on every incoming byte by shifting out via DO the data stored in the last received address. It is important that the writing action (command − address and data) to the Control Register is exactly 16 bits long. If more or less bits are transmitted the complete transfer packet is ignored (with the exception of preceding read commands (see Figure 28)). A WRITE command executed for a read−only register (e.g. Status Registers) will not affect the addressed register and the device operation. Because after a power−on−reset the initial address is unknown the data shifted out via DO is not valid. http://onsemi.com 29 AMIS−30523 The NEW DATA is written into the corresponding internal register at the rising edge of CS CS DI COMMAND DATA WRITE DATA to ADDR3 NEW DATA for ADDR3 DATA DATA OLD DATA or NOT VALID OLD DATA from ADDR3 DATA from previous command or NOT VALID after POR or RESET DO Figure 27. Single WRITE Operation where DATA from the Master is Written in SPI Register with Address 3 Examples of Combined READ and WRITE Operations by writing a control byte in Control Register at ADDR2. Note that during the write command the old data of the pointed register is returned at the moment the new data is shifted in In the following examples successive READ and WRITE operations are combined. In Figure 28 the Master first reads the status from Register at ADDR4 and at ADDR5 followed Registers are updated with the internal status at the rising edge of the internal 523 clock when CS = 1 The NEW DATA is written into the corresponding internal register at the rising edge of CS CS DI DATA from previous command or NOT VALID after POR or RESET DO COMMAND READ DATA from ADDR4 COMMAND READ DATA from ADDR5 COMMAND WRITE DATA to ADDR2 DATA NEW DATA for ADDR2 DATA OLD DATA or NOT VALID DATA DATA from ADDR4 DATA DATA from ADDR5 DATA OLD DATA from ADDR2 Figure 28. Two Successive READ Commands Followed by a WRITE Command transmitted. This rule also applies when the master device wants to initiate an SPI transfer to read the Status Registers. Because the internal system clock updates the Status Registers only when CSB line is high, the first read out byte might represent old status information. After the write operation the Master could initiate a read back command in order to verify the data correctly written as illustrated in Figure 29. During reception of the READ command the old data is returned for a second time. Only after receiving the READ command the new data is Registers are Updated with the Internal Status at the Rising Edge of the Internal 523 Clock when CS = 1 Registers are Updated with the Internal Status at the Rising Edge of CS CS DI DATA from previous command or NOT VALID after POR or RESET DO COMMAND DATA WRITE DATA to ADDR2 NEW DATA for ADDR2 COMMAND READ DATA from ADDR2 DATA DATA DATA OLD DATA or NOT VALID OLD DATA from ADDR2 OLD DATA from ADDR2 COMMAND or DUMMY DATA NEW DATA from ADDR2 Figure 29. A WRITE Operation where DATA from the Master is Written in SPI Register with Address 2 Followed by a READ Back Operation to Verify a Correct WRITE Operation NOTE: The internal data−out shift buffer of the AMIS−30523 is updated with the content of the selected SPI register only at the last (every eighth) falling edge of the CLK signal (see SPI Transfer Format and Pin Signals). As a result, new data for transmission cannot be written to the shift buffer at the beginning of the transfer packet and the first byte shifted out might represent old data. http://onsemi.com 30 AMIS−30523 Table 14. SPI CONTROL REGISTERS (All SPI control registers have Read/Write Access and default to ”0” after power−on or hard reset.) Structure Content Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Address Reset 0 0 0 0 0 0 0 0 WR (00h) Data WDEN − − − CR0 (01h) Data CR1 (02h) Data DIRCTRL NXTP − − PWMF PWMJ CR2 (03h) Data MOTEN SLP SLAG SLAT − − Where: R/W Reset: WDT[3:0] SM[2:0] CUR[4:0] EMC[1:0] − − Read and Write access Status after power−On or hard reset Table 15. SPI CONTROL PARAMETER OVERVIEW Symbol Description Status <DIR> = 0 DIRCTRL NXTP EMC[1:0] SLAT SLAG Controls the direction of rotation (in combination with logic level on input DIR) Selects if NXT triggers on rising or falling edge Speed load angle transparency bit Speed load angle gain setting Enables doubling of the PWM frequency (Note 18) PWMJ Enables jittery PWM Enables sleep mode MOTEN Activates the motor driver outputs <DIRCTRL> = 1 CCW motion <DIRCTRL> = 0 CCW motion <DIRCTRL> = 1 CW motion Trigger on rising edge <NXTP> = 1 Trigger on falling edge 00 Very Fast 01 Fast 10 Slow 11 Very Slow <SLAT> = 0 SLA is transparent <SLAT> = 1 SLA is NOT transparent <SLAG> = 0 Gain = 0.5 <SLAG> = 1 Gain = 0.25 <PWMF> = 0 Default Frequency <PWMF> = 1 Double Frequency <PWMJ> = 0 Jitter disabled <PWMJ> = 1 Jitter enabled 000 1/32 Micro − Step 001 1/16 Micro − Step 010 1/8 Micro − Step 011 1/4 Micro − Step 100 Compensated Half Step 101 Uncompensated Half Step 110 Full Step 111 n.a. <SLP> = 0 Active mode <SLP> = 1 Sleep mode <MOTEN> = 0 Drivers disabled <MOTEN> = 1 Drivers enabled Stepmode SLP CW motion <NXTP> = 0 Turn On – Turn−off Slopes of motor driver (Note 18) PWMF SM[2:0] <DIR> = 1 Value <DIRCTRL> = 0 18. The typical values can be found in Table 5: DC Parameters Motor Driver and in Table 6: AC parameters Motor Driver http://onsemi.com 31 AMIS−30523 CUR[4:0] Selects IMCmax peak. This is the peak or amplitude of the regulated current waveform in the motor coils. Table 16. SPI CONTROL PARAMETER OVERVIEW CUR[4:0] Current Range (Note 20) 0 1 Index CUR[4:0] Current (mA) (Note 19) 0 00000 Current Range (Note 20) Index CUR[4:0] Current (mA) (Note 19) 33 16 10000 365 1 00001 64 17 10001 400 2 00010 95 18 10010 440 3 00011 104 19 10011 485 4 00100 115 20 10100 530 5 00101 126 21 10101 585 6 00110 138 22 10110 630 7 00111 153 23 10111 750 8 01000 166 24 11000 825 2 3 9 01001 190 25 11001 895 10 01010 205 26 11010 975 11 01011 230 27 11011 1065 12 01100 250 28 11100 1155 13 01101 275 29 11101 1245 14 01110 300 30 11110 1365 15 01111 325 31 11111 1480 19. Typical current amplitude at TJ = 125°C 20. Reducing the current over different current ranges might trigger overcurrent detection. See application note AND8372/D for solutions. SPI Status Register Description All 4 SPI status registers have Read Access and are default to “0” after power−on or hard reset. Table 17. SPI STATUS REGISTERS Structure Content Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R R R R R R R R Address Reset 0 0 0 0 0 0 0 0 SR0 (04h) Data is not latched PAR TW CPfail WD OPENX OPENY − − SR1 (05h) Data is latched PAR OVCXPT OVCXPB OVCXNT OVCXNB − − − SR2 (06h) Data is latched PAR OVCYPT OVCYPB OVCYYNT OVCYNB TSD − − SR3 (07h) Data is not latched PAR Where: R Reset PAR MSP[6:0] Read only mode access Status after power−on or hard reset Parity check http://onsemi.com 32 AMIS−30523 Table 18. SPI STATUS FLAGS OVERVIEW Mnemonic Flag Length (bit) Related SPI Register CPFail Charge pump failure 1 Status Register 0 ‘0’ = no failure ‘1’ = failure: indicates that the charge pump does not reach the required voltage level. MSP[6:0] Micro−step position 7 Status Register 3 Translator micro step position OPENX OPEN Coil X 1 Status Register 0 ‘1’ = Open coil detected ‘0’ OPENY OPEN Coil Y 1 Status Register 0 ‘1’ = Open coil detected ‘0’ OVCXNB OVer Current on X H−bridge; MOTXN terminal; Bottom tran. 1 Status Register 1 ‘0’ = no failure ‘1’ = failure: indicates that over current is detected at bottom transistor XN−terminal ‘0’ OVCXNT OVer Current on X H−bridge; MOTXN terminal; Top transist. 1 Status Register 1 ‘0’ = no failure ‘1’ = failure: indicates that over current is detected at top transistor XN−terminal ‘0’ OVCXPB OVer Current on X H−bridge; MOTXP terminal; Bottom transist. 1 Status Register 1 ‘0’ = no failure ‘1’ = failure: indicates that over current is detected at bottom transistor XP−terminal ‘0’ OVCXPT OVer Current on X H−bridge; MOTXP terminal; Top transist. 1 Status Register 1 ‘0’ = no failure ‘1’ = failure: indicates that over current is detected at top transistor XP−terminal ‘0’ OVCYNB OVer Current on Y H−bridge; MOTYN terminal; Bottom transist. 1 Status Register 2 ‘0’ = no failure ‘1’ = failure: indicates that over current is detected at bottom transistor YN−terminal ‘0’ OVCYNT OVer Current on Y H−bridge; MOTYN terminal; Top transist. 1 Status Register 2 ‘0’ = no failure ‘1’ = failure: indicates that over current is detected at top transistor YN−terminal ‘0’ OVCYPB OVer Current on Y H−bridge; MOTYP terminal; Bottom transist. 1 Status Register 2 ‘0’ = no failure ‘1’ = failure: indicates that over current is detected at bottom transistor YP−terminal ‘0’ OVCYPT OVer Current on Y H−bridge; MOTYP terminal; Top transist. 1 Status Register 2 ‘0’ = no failure ‘1’ = failure: indicates that over current is detected at top transistor YP−terminal ‘0’ TSD Thermal shutdown 1 Status Register 2 ‘0’ TW Thermal warning 1 Status Register 0 ‘0’ WD Watchdog event (Note 21) 1 Status Register 0 Comment ‘1’ = watchdog reset after time−out Reset State ‘0’ ‘0000000’ ‘0’ 21. WD – This bit indicates that the watchdog timer has not been cleared properly. If the master reads that WD is set to “1” after reset, it means that a watchdog reset occurred (warm boot) instead of POR (cold boot). WD bit will be cleared only when the master writes “0” to WDEN bit. http://onsemi.com 33 AMIS−30523 FUNCTIONAL DESCRIPTION CAN TRANSCEIVER Introduction a time period of tBUS, the RxD pin is driven low by the transceiver to inform the controller of the wake−up request. The CAN transceiver is the interface between a (CAN) protocol controller and the physical bus. It provides differential transmit capability to the bus and differential receive capability to the CAN controller. Due to the wide common−mode voltage range of the receiver inputs, it is able to reach outstanding levels of electro−magnetic susceptibility (EMS). Similarly, extremely low electromagnetic emission (EME) is achieved by the excellent matching of the output signals. Additional features are the ideal passive behavior when the supply voltage is removed; a wake−up over bus and the extreme low current in stand−by mode. To cope with the long bus delay the communication speed needs to be low. The integrated transceiver allows low transmit data rates down 10 kbit/s or lower. Split Circuit The VSPLIT pin is operational only in normal mode. In standby mode this pin is floating. The VSPLIT is connected as shown in Figure 13 and its purpose is to provide a stabilized DC voltage of 0.5 x VCC to the bus avoiding possible steps in the common−mode signal therefore reducing EME. These unwanted steps could be caused by an un−powered node on the network with excessive leakage current from the bus that shifts the recessive voltage from its nominal 0.5 x VCC voltage. Wake−up Once a valid wake−up (dominant state longer than tBUS) has been received during the standby mode the RxD pin is driven low Operating Modes The CAN transceiver provides two modes of operation as illustrated in Table 19. These modes are selectable through pin STB Over−Temperature Detection A thermal protection circuit protects the IC from damage by switching off the transmitter if the junction temperature exceeds a value of approximately 160°C. Because the transmitter dissipates most of the power, the power dissipation and temperature of the IC is reduced. All other IC functions continue to operate. The transmitter off−state resets when pin TxD goes high. The thermal protection circuit is particularly needed when a bus line short circuits. Table 19. OPERATING MODES RXD Mode STB Low High Normal Low Bus dominant Bus recessive Standby High Wake−up request detected No wake−up request detected High Communication Speed Range The transceiver is primarily intended for industrial applications. It allows very low baud rates needed for long bus length applications. But also high speed communication is possible up to 1 Mbit/s. In the normal mode, the transceiver is able to communicate via the bus lines. The signals are transmitted and received to the CAN controller via the pins TxD and RxD. The slopes on the bus lines outputs are optimized to give extremely low EME. In stand−by mode both the transmitter and receiver are disabled and a very low−power differential receiver monitors the bus lines for CAN bus activity. The bus lines are terminated to ground and supply current is reduced to a minimum, typically 10 mA. When a wake−up request is detected by the low−power differential receiver, the signal is first filtered and then verified as a valid wake signal after Fail Safe Features A current−limiting circuit protects the transmitter output stage from damage caused by accidental short circuit to either positive or negative supply voltage, although power dissipation increases during this fault condition. The pins CANH and CANL are protected from automotive electrical transients (according to ISO 7637; see Figure 7). Pins TxD and STB are pulled high internally should the input become disconnected. Pins TxD, STB and RxD will be floating, preventing reverse supply should the VCC supply be removed. DEVICE ORDERING INFORMATION Temperature Range Peak Current AMIS30523C5231RG −40°C – 125°C AMIS30523C5231G −40°C – 125°C Part Number Package Type Shipping† 1600 mA QFN−52 (Pb−Free) Tape & Reel 1600 mA QFN−52 (Pb−Free) Tube †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 34 AMIS−30523 PACKAGE DIMENSIONS QFN52 8x8, 0.5P CASE 485M−01 ISSUE C D B ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ PIN ONE REFERENCE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A DIM A A1 A2 A3 b D D2 E E2 e K L E 2X 0.15 C 2X 0.15 C A2 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.60 0.80 0.20 REF 0.18 0.30 8.00 BSC 6.50 6.80 8.00 BSC 6.50 6.80 0.50 BSC 0.20 --0.30 0.50 0.10 C RECOMMENDED SOLDERING FOOTPRINT A 0.08 C SEATING PLANE A3 A1 REF 8.30 C 14 52 X L 52X 0.62 6.75 D2 26 27 13 6.75 E2 39 1 52 X K 8.30 52 40 e 52 X b PKG OUTLINE NOTE 3 0.50 PITCH 0.10 C A B 0.05 C 52X 0.30 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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